Methods for semiconductor substrate processing by densifying a dielectric layer

Abstract

A method of processing a single crystal semiconductor substrate including providing the single crystal semiconductor substrate, where the single crystal semiconductor substrate includes two major, generally parallel surfaces, one of which is a front surface of the single crystal semiconductor substrate and the other of which is a back surface of the single crystal semiconductor substrate, a circumferential edge joining the front and back surfaces, and a bulk region between the front and back surfaces. The method further includes applying a densification agent to a dielectric layer in interfacial contact with the front surface of the single crystal semiconductor substrate, where applying the densification agent densifies the dielectric layer.

Description

METHODS FOR SEMICONDUCTOR SUBSTRATE PROCESSING BY DENSIFYING A DIELECTRIC LAYERCROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims priority to U.S. Provisional Patent Application No. 63 / 670,009, filed July 11, 2024, the disclosure of which is hereby incorporated by reference in its entirety.BACKGROUND

[0002] As demand for smaller transistor device size in the semiconductor industry increases, wafer surface defects become increasingly critical for processes below 5 nm, even for the backside of the wafer. Forming wafers using epitaxial processes is one way to provide suitable wafer surfaces for device makers. But auto-doping may be a concern during such epitaxial processes. For example, epitaxial processes are high temperature thermal processes. During these processes, highly doped (p+) silicon substrates diffuse out dopant atoms through the backside of the wafer substrate, leading to an over doping effect on the wafer frontside. Growing a low temperature oxide (LTO) layer by plasma enhanced chemical vapor deposition (PECVD) on the wafer backside can reduce auto-doping in epitaxial processes.

[0003] An exemplary PECVD reactor is described and depicted in U.S. Patent No. 10,832,938, the entire contents of which are hereby incorporated by reference herein. In some PECVD LTO processes, which may be used in tandem with a relative chamber configuration tool, the wafer is placed frontside down and on the heater within the PECVD reactor for growing a silicon dioxide layer. In such processes, wafer support pins and the heater are in direct contact with the wafer frontside during wafer loading and unloading from the reactor.

[0004] The surface contact position (also referred to as a dimple) is installed as a wafer support on the heater and the number of dimples can be designed on a case-by-case basis. The number of dimples can be significantly large (e.g., up to33) in commercial heaters, and depends in part on how the wafer is handled and loaded and unloaded from the reactor.

[0005] The PECVD heater is typically made of high purity quartz or silicon carbide or some other ceramic material for strength, thermal stability, and thermal conductivity considerations. The wafer surface can be damaged due to direct contact with the heater (e.g., micro scratches, pits or silicon base particles bonded on the wafer). Each contact position (dimple) may create one or more defects on the frontside of the wafer. For sub-5 nm process, lithography is sensitive, and frontside contact point defects will impact the device yield. Accordingly, in some processes, the frontside of the wafer is polished and a significant amount of material (e.g., 1.3 pm or more) is removed to eliminate or reduce heat mark defects.

[0006] Thus, there is a need for improved processes to reduce marks on wafer frontsides.BRIEF DESCRIPTION

[0007] In one aspect, described herein is a method of processing a single crystal semiconductor substrate. The method includes providing the single crystal semiconductor substrate, the single crystal semiconductor substrate including two major, generally parallel surfaces, one of which is a front surface of the single crystal semiconductor substrate and the other of which is a back surface of the single crystal semiconductor substrate, a circumferential edge joining the front and back surfaces, and a bulk region between the front and back surfaces; and applying a densification agent to a dielectric layer in interfacial contact with the front surface of the single crystal semiconductor substrate, where applying the densification agent densifies the dielectric layer.

[0008] In another aspect, described herein is a method of processing a single crystal semiconductor substrate. The method includes providing the single crystal semiconductor substrate, the single crystal semiconductor substrate comprising two major, generally parallel surfaces, one of which is a front surface of the single crystal semiconductor substrate and the other of which is a back surface of the singlecrystal semiconductor substrate, a circumferential edge joining the front and back surfaces, and a bulk region between the front and back surfaces; applying a densification agent to a dielectric layer in interfacial contact with the front surface of the single crystal semiconductor substrate, wherein applying the densification agent densifies the dielectric layer; subsequent to applying the densification agent to the dielectric layer, positioning the single crystal semiconductor substrate on a heater of a plasma-enhanced chemical vapor deposition system such that the dielectric layer is in contact with the heater; growing a low temperature oxide (LTO) layer on the back surface of the single crystal semiconductor substrate with the plasma-enhanced chemical vapor deposition system; and polishing the front surface of the single crystal semiconductor substrate.BRIEF DESCRIPTION OF THE DRAWINGS

[0009] These and other features, aspects, and advantages of the present disclosure will become better understood when the following detailed description is read with reference to the accompanying drawings in which like characters represent like parts throughout the drawings, wherein:

[0010] FIG. 1 is a cross-section of an example semiconductor substrate suitable for use in methods of processing single crystal semiconductor substrates in accordance with the present disclosure.

[0011] FIG. 2 depicts an exemplary process flow for a backside LTO process suitable for use in methods of processing single crystal semiconductor substrates in accordance with the present disclosure.

[0012] FIG. 3 depicts an oxide thickness curve for different lengths of time that an O3 solution was applied to a front surface of a semiconductor substrate in accordance with aspects of the present disclosure.

[0013] FIG. 4A depicts dimple marks on an unprocessed silicon wafer with no fine polishing (FPOL,) removal.

[0014] FIG. 4B depicts dimple marks on a silicon wafer with a 0.3 pm FPOL removal condition suitable for use in methods of processing single crystal semiconductor substrates in accordance with the present disclosure.

[0015] FIG. 4C depicts dimple marks on a silicon wafer with a 0.9 pm FPOL removal condition suitable for use in methods of processing single crystal semiconductor substrates in accordance with the present disclosure.

[0016] FIG. 4D depicts dimple marks on a silicon wafer with a 1.3 pm FPOL removal condition suitable for use in methods of processing single crystal semiconductor substrates in accordance with the present disclosure.

[0017] FIG. 4E depicts dimple marks on a silicon wafer with surface protection via an LTO 300 A deposit on the wafer backside at a 0.9 pm FPOL removal condition suitable for use in methods of processing single crystal semiconductor substrates in accordance with the present disclosure.

[0018] FIG. 4F depicts dimple marks on a silicon wafer with surface protection via a 20 ppm O3 solution treatment for 150 seconds at a 0.3 pm FPOL removal condition suitable for use in methods of processing single crystal semiconductor substrates in accordance with the present disclosure.

[0019] FIG. 4G depicts dimple marks on a silicon wafer with surface protection via a 20 ppm O3 solution treatment for 150 seconds at a 0.9 pm FPOL removal condition suitable for use in methods of processing single crystal semiconductor substrates in accordance with the present disclosure.

[0020] FIG. 4H depicts dimple marks on a silicon wafer with surface protection via a 550 standard cubic centimeters per minute (seem) N2O gas treatment for 300 seconds at a 0.9 pm FPOL removal condition suitable for use in methods of processing single crystal semiconductor substrates in accordance with the present disclosure.

[0021] FIG. 5 depicts dimple mark defect fail rates in a design of experiments (DOE) split test, which demonstrates that increasing time of treatment ofa front surface of a single crystal semiconductor substrate with O3 water decreases fail rate in methods of processing single crystal semiconductor substrates in accordance with the present disclosure.

[0022] FIG. 6 depicts a comparative dimple mark detection between a baseline wafer and a wafer treated for a relatively long time (e.g., greater than 60 seconds) with O3 water in a processing step suitable for use in methods of processing single crystal semiconductor substrates in accordance with the present disclosure.

[0023] Unless otherwise indicated, the drawings provided herein are meant to illustrate features of embodiments of the disclosure. These features are believed to be applicable in a wide variety of systems comprising one or more embodiments of the disclosure. As such, the drawings are not meant to include all conventional features known by those of ordinary skill in the art to be required for the practice of the embodiments disclosed herein.DETAILED DESCRIPTION

[0024] Methods for processing semiconductor substrates are described herein. The methods are especially useful for reducing total removal from polishing and defects induced by PECVD heater contact marks on the wafer. In the methods, a densification agent is used to densify a dielectric (e.g., oxide) layer of a wafer surface. The methods minimize polishing removal thickness and defects on the wafer frontside during PECVD LTO processes.

[0025] Referring now to FIG. 1, an example single crystal semiconductor substrate 1 has a front surface 3, a back surface 5, an imaginary central plane 7 between the front and back surfaces, and a wafer bulk 9 comprising the wafer volume between the front and back surfaces. The single crystal semiconductor substrate 1 may also be referred to as a wafer. Further, while the single crystal semiconductor substrate 1 is described throughout the present disclosure as a silicon substrate, the single crystal semiconductor substrate 1 may include other semiconductor substrates, materials, or layers, including, for example and without limitation, silicon, germanium, gallium arsenide, aluminum nitride, silicongermanium, gallium nitride, indium gallium arsenide, silicon carbide, sapphire, and combinations thereof.

[0026] The single crystal semiconductor substrate 1 may be a single crystal silicon wafer sliced from a single crystal ingot grown in accordance with Czochralski (CZ) or float zone growing methods. Such methods, as well as standard silicon slicing, lapping, etching, and polishing techniques are disclosed, for example, in F. Shimura, Semiconductor Silicon Crystal Technology, Academic Press, 1989, and Silicon Chemical Etching, (J. Grabmaier ed.) Springer-Verlag, N.Y., 1982 (incorporated herein by reference).

[0027] Single crystal silicon wafers may be obtained from commercial suppliers, such as GlobalWafers Co., Ltd., Taiwan. The wafers may be sliced from an ingot using any suitable technique (e.g., a wire saw operation). In various embodiments, the single crystal semiconductor substrate 1 is sliced substantially on-axis from a single crystal silicon ingot. The phrase “substantially on- axis” as used herein to describe semiconductor substrates sliced from a single crystal silicon ingot means that the slicing angle at which the semiconductor substrates are sliced has minimal on-axis deviation (e.g., less than + / -0.10, preferably less than + / -0.070, in an x-axis direction and in a y-axis direction) from the crystal direction that is normal to the crystallographic orientation of the ingot (i.e., along a central longitudinal axis of the ingot). Although single crystal silicon wafers having any crystallographic orientation (e.g., {100}, {110} or {111}) may be used as the single crystal semiconductor substrate 1, {100} silicon wafers will be described to illustrate a semiconductor substrate that is sliced substantially on-axis from the ingot in accordance with the present disclosure. The {100} silicon wafers may, in some implementations, be sliced from a {100} silicon ingot at an angle that deviates from the direction (e.g., at an angle between about 0. 1° to about 0.5° off the central longitudinal axis of the ingot in an x-axis and / or y-axis direction). These {100} silicon wafers sliced at an angle that deviates from the direction in the x-axis and / or the y-axis direction may have less haze after being annealed than wafers sliced substantially along (e.g., deviating less than + / -0.1 ° in the x-axis direction and in the y-axis direction from) the direction. However, post-anneal, nanometer-sized recessesthat affect surface roughness may be absent from silicon device layers derived from epitaxial silicon layers formed on single crystal semiconductor substrate 1 that have been sliced substantially on-axis from the ingot. These post-anneal, nanometer-sized recesses may otherwise exist where the silicon device layer is derived from a single crystal semiconductor substrate 1 that has been sliced off-axis from an ingot. Accordingly, the single crystal semiconductor substrate 1 is, in some embodiments, sliced substantially on-axis from a single crystal silicon ingot. In these embodiments, the on-axis deviation of the slicing angle (i.e., the deviation of the slicing angle from the central longitudinal axis of the ingot in the x-axis direction and in the y-axis direction) at which the single crystal semiconductor substrate 1 is sliced from a single crystal silicon ingot is preferably less than + / -0.1°, and more preferably less than + / -0.070. In some embodiments, the single crystal semiconductor substrate 1 is sliced precisely along (i.e., at an angle that does not deviate in either the x-axis direction or the y-axis direction from) the crystal direction that is normal to the crystallographic orientation of the ingot. For example, {100} silicon wafers used for the single crystal semiconductor substrate 1 may be sliced from a {100} silicon ingot precisely along the direction.

[0028] Referring now to FIG. 2, an example process flow 11 for processing a semiconductor substrate, such as the single crystal semiconductor substrate 1 shown in FIG. 1, is shown. The process flow includes a pre-cleaning step 13, a densification treatment step 15, a growth step 17, an edge strip step 19, a polishing step 21, and a defect inspection step 23. This exemplary process flow is illustrative and does not limit the depicted process steps or the order of these steps, nor does it exclude other process steps. For example, the methods of the present disclosure may be used with other backside treatment process, such as one or more of rapid thermal annealing (RTA), epitaxy (EPI), chemical vapor deposition (CVD), physical vapor deposition (PVD), dry etching, furnace processing, and cleaning. Relevant process steps are described in more detail, for example, in US Patent No. 10,832,938, US Patent No. 11,798,802, US Patent Publication No. 2024 / 0258156, US Patent Publication No. 2025 / 0069945, US Patent Publication No. 2024 / 0258155, andUS Patent Publication No. 2022 / 0359195, the entire contents of which are hereby incorporated by reference herein.

[0029] The pre-cleaning step 13 prepares the single crystal semiconductor substrate for treatment. This pre-cleaning step 13 may include any suitable cleaning step known in the art that facilitates the method described herein. In some embodiments, the wafers are polished and cleaned by standard methods known to those skilled in the art. See, for example, W. C. O'Mara et al., Handbook of Semiconductor Silicon Technology, Noyes Publications. If desired, the wafers can be cleaned, for example, in a conventional Standard Clean 1 (SCI) / Standard Clean 2 (SC2) solution. In some embodiments, pre-cleaning step 13 comprises treating a surface of the single crystal semiconductor substrate to remove contaminants (e.g., organic compound contaminants and other contaminant particles deposited on the wafer during an implantation process). Treating the surface may include washing with a solvent, exposing the surface to a reducing agent, exposing the surface to an etching agent, or a combination thereof.

[0030] The densification treatment step 15 provides a denser surface on a single side of the semiconductor substrate and simplifies the process flow. The densification treatment step 15 in the exemplary process flow 11 is performed between the pre-cleaning step 13 and the growth step 17. However, this densification treatment step 15 may be performed at any stage in the process flow 11, including before the final polishing step 21, after the final polishing step 21, or both before and after the final polishing step 21 . Regardless of when the densification treatment step 15 occurs in the process flow 11, the density of the oxide layer may be increased through this treatment step. The densification treatment step 15 is described in more detail below.

[0031] The growth step 17 grows a dielectric layer (e.g., an LTO layer or an oxide layer) on the semiconductor substrate. The growth step 17 may be conducted with any suitable technique known in the art that facilitates the method described herein. In some embodiments, the growth step is achieved via metalorganic chemical vapor deposition (MOCVD), physical vapor deposition (PVD), chemicalvapor deposition (CVD), low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), or molecular beam epitaxy (MBE).

[0032] The dielectric layer may be any electrically insulating material suitable for use that facilitates the method described herein. Generally, the dielectric layer includes an oxide. Exemplary dielectric materials include S1O2, SEN4, aluminum oxide, amorphous silicon, and magnesium oxide.

[0033] The edge strip step 19 strips the edge of the material layer grown in the growth step 17. This step removes unwanted materials from a periphery of the semiconductor substrate. This step avoids defect-free edges.

[0034] The polishing step 21 smooths the front surface of the semiconductor substrate and reduces defects. The polishing step 21 may be a final polishing step or a non-final polishing step. For example, the semiconductor substrate may be subjected to a chemical mechanical polishing (CMP) operation such that a front surface, and optionally a back surface, of the semiconductor substrate are smoothed to a targeted shape and flatness. After polishing, the semiconductor substrate may have a mirror-polished surface finish that is free from surface defects, such as scratches and large particles.

[0035] The defect inspection step 23 analyzes the semiconductor substrate for surface defects (e.g., scratches and large particles) and dimples. The defect inspection step 23 may be conducted with any suitable metrology technique known in the art that facilitates the method described herein.

[0036] The example process flow 11 may include further steps not depicted, including pre-processing steps and post-processing steps.

[0037] For example, the example process flow 11 may further include growing an epitaxial layer on the front surface of the single crystal semiconductor substrate. A grown epitaxial layer may comprise substantially the same electrical characteristics as the underlying single crystal semiconductor substrate. Alternatively, the epitaxial layer may comprise different electricalcharacteristics as the underlying single crystal semiconductor substrate. An epitaxial layer may comprise a material selected from the group consisting of silicon, silicon carbide, silicon germanium, gallium arsenide, gallium nitride, indium phosphide, indium gallium arsenide, germanium, and combinations thereof. Depending upon the desired properties of the final device, the epitaxial layer may comprise electrically active dopants, such as boron (p type), gallium (p type), aluminum (p type), indium (p type), phosphorus (n type), antimony (n type), and arsenic (n type). The resistivity of the epitaxial layer may range from 1 to 50 Ohm-cm, typically, from 5 to 25 Ohm-cm. In some embodiments, the epitaxial layer may have a thickness between about 20 nanometers and about 3 micrometers, such as between about 20 nanometers and about 2 micrometers, such as between about 20 nanometers and about 1.5 micrometers or between about 1.5 micrometers and about 3 micrometers.

[0038] In many embodiments, a method of processing a single crystal semiconductor substrate is disclosed. The method includes providing the single crystal semiconductor substrate, the single crystal semiconductor substrate including two major, generally parallel surfaces, one of which is a front surface of the single crystal semiconductor substrate and the other of which is a back surface of the single crystal semiconductor substrate, a circumferential edge joining the front and back surfaces, and a bulk region between the front and back surfaces; and applying a densification agent to a dielectric layer in interfacial contact with the front surface of the single crystal semiconductor substrate, where applying the densification agent densifies the dielectric layer.

[0039] In some embodiments, the semiconductor substrate comprises a material selected from the group consisting of silicon, germanium, gallium arsenide, aluminum nitride, silicon germanium, gallium nitride, indium gallium arsenide, silicon carbide, sapphire, and combinations thereof.

[0040] In some embodiments, the semiconductor substrate comprises silicon. In some embodiments, the semiconductor substrate is a silicon semiconductor substrate. In some embodiments, the semiconductor substrate is a single crystal silicon substrate.

[0041] The semiconductor substrate may be any diameter suitable for use by those of skill in the art including, for example, about 200 mm, about 300 mm, greater than about 300 mm or even about 450 mm diameter substrates.

[0042] Generally, the densification agent may be applied to the dielectric layer at any suitable temperature known in the art that facilitates the method described herein.

[0043] In some embodiments, the densification agent is applied in the absence of a thermal treatment. In these embodiments, it is understood that heat is not applied to the semiconductor substrate during application of the densification agent.

[0044] In some embodiments, the densification agent is produced in a step of the process. In some embodiments, for example, the densification agent includes ozone produced by electric generation, ultraviolet (UV) light, or a combination thereof.

[0045] In some embodiments, the densification agent is applied to the dielectric layer in an environment at a temperature in a range of from about 100 °C to about 1000 °C. In some embodiments, the densification agent is applied to the dielectric layer in an environment at a temperature in a range of from about 300 °C to about 600 °C. In these embodiments, it is understood that the heat is applied to the semiconductor substrate.

[0046] Generally, the densification agent is applied to the dielectric layer via any suitable technique known in the art that facilitates the method described herein. In some embodiments, applying the densification agent to the dielectric layer comprises one or more of spraying the densification agent onto the dielectric layer, dipping the single crystal semiconductor substrate into the densification agent, and combinations thereof.

[0047] In some embodiments, the densification agent is applied to the dielectric layer at least twice. In these embodiments, the densification agent isapplied to the dielectric layer in at least two consecutive steps or at least two non- consecutive steps. When the densification agent is applied to the dielectric layer in at least two non-consecutive steps, it is understood that the method includes ceasing application of the densification agent to the dielectric layer, and subsequently, applying the densification agent to the dielectric layer a second time.

[0048] In some embodiments, the densification agent is applied to the dielectric layer only before a polishing process. In some embodiments, the densification agent is applied to the dielectric layer only after a polishing process. In some embodiments, the densification agent is applied to the dielectric layer both before and after a polishing process.

[0049] In some embodiments, application of the densification agent increases oxide thickness of the dielectric layer by at least about 50%, at least about 60%, at least about 70%, at least about 80%, at least about 90%, or at least about 100%.

[0050] In some embodiments, application of the densification agent increases oxide thickness of the dielectric layer by at most about 60%, at most about 70%, at most about 80%, at most about 90%, at most about 100%, or at most about 150%.

[0051] In some embodiments, a thickness of the dielectric layer subsequent to the application of the densification agent is at least about 8.0 A, at least about 8.2 A, at least about 8.4 A, at least about 8.6 A, at least about 8.8 A, at least about 9.0 A, at least about 9.2 A, at least about 9.4 A, at least about 9.6 A, at least about 9.8 A, at least about 10.0 A, at least about 10.2 A, at least about 10.4 A, at least about 10.6 A, at least about 10.8 A, at least about 11.0 A, at least about 11.2 A, at least about 11.4 A, at least about 11.6 A, or at least about 11.8 A.

[0052] In some embodiments, a thickness of the dielectric layer subsequent to the application of the densification agent is at most about 8.2 A, at most about 8.4 A, at most about 8.6 A, at most about 8.8 A, at most about 9.0 A, at most about 9.2 A, at most about 9.4 A, at most about 9.6 A, at most about 9.8 A, at mostabout 10.0 A, at most about 10.2 A, at most about 10.4 A, at most about 10.6 A, at most about 10.8 A, at most about 11 .0 A, at most about 11.2 A, at most about 11 .4 A, at most about 11.6 A, at most about 11.8 A, or at most about 12.0 A.

[0053] The single crystal semiconductor substrate may have any resistivity obtainable by the CZ or float zone methods. The resistivity of the substrate may vary based on the requirements of the end use / application of the semiconductor substrate. The resistivity may vary from milliohm or less to megaohm or more. “High resistivity” substrates have a minimum bulk resistivity of at least 500 Ohm-cm, such as between 500 Ohm-cm to 100,000 Ohm-cm. “Low resistivity” substrates have a minimum bulk resistivity of below (less than or equal to) 500 Ohm-cm, such as between 1 Ohm-cm to 100 Ohm-cm. Methods for preparing wafers of varying resistivities are known in the art, and wafers having a desired resistivity may be obtained from commercial suppliers, such as GlobalWafers Co., Ltd., Taiwan.

[0054] In some embodiments, the substrate has a minimum bulk resistivity of at least 500 Ohm-cm, at least 1000 Ohm-cm, or at least 3000 Ohm-cm, such as between 500 Ohm-cm and 100,000 Ohm-cm. In some embodiments, the single crystal semiconductor substrate has a minimum bulk region resistivity in a range of from about 0.8 milliOhm-cm to about 15,000 Ohm-cm. In some embodiments, the single crystal semiconductor substrate has a minimum bulk region resistivity of at least about 0.8 mOhm-cm.

[0055] In some embodiments, the densification agent is selected from the group consisting of liquid densification agents, ozone (O3) solutions, O3 water, gaseous densification agents, N2O, O2, O3, and combinations thereof.

[0056] In some embodiments, the densification agent is in a form selected from the group consisting of solutions, liquids, gases, and combinations thereof. In some embodiments, the densification agent is in the form of a liquid. In some embodiments, the densification agent is in the form of a gas. In some embodiments, the densification agent is in the form of a solution comprising a gaseous solute dissolved in a liquid solvent.

[0057] In gas phase treatments, having oxide formation on both sides of a semiconductor substrate may be undesirable for certain processes. Gas phase treatments therefore may require an additional etching process to remove the single side of dielectric layer. On the contrary, liquid phase-based densification agents (e.g., O3 water) do not exhibit backside oxide formation.

[0058] Generally, the ozone solution may include any suitable solvent in the art that facilitates the method described herein. In some embodiments, the solvent is selected from the group consisting of water, aqueous solvents, nonaqueous solvents, and combinations thereof.

[0059] Generally, the ozone solution may include ozone in any suitable concentration known in the art that facilitates the method described herein. In some embodiments, the ozone solution comprises ozone in an amount of from about 0.01 ppm to about 100 ppm. In some embodiments, the ozone solution comprises ozone in an amount of from about 10 ppm to about 50 ppm. In some embodiments, the ozone solution comprises ozone in an amount of from about 10 ppm to about 20 ppm.

[0060] In some embodiments, the ozone solution comprises ozone in an amount of at least about 10 ppm. In some embodiments, the ozone solution comprises ozone in an amount of at least about 20 ppm.

[0061] If the O3 concentration is too low, no differences may be detected after the treatment step and the protection layer may fail.

[0062] Generally, the gaseous densification agent may be applied in any suitable flow rate known in the art that facilitates the method described herein. In some embodiments, the gaseous densification agent is applied at a flow rate in a range of from about 100 seem to about 15000 seem.

[0063] In some embodiments, the gaseous densification agent is applied concurrent with application of radiofrequency (RF) power. In some embodiments, the RF power is in a range of from about 75 W to about 1300 W.

[0064] Generally, the densification agent may be applied for any suitable time in the art that facilitates the method described herein. In some embodiments, the densification agent is applied for a time in a range of from about 1 second to about 10 hours. In some embodiments, the densification agent is applied for a time in a range of from about 30 seconds to about 1 hour. In some embodiments, the densification agent is applied for a time in a range of from about 30 seconds to about 10 minutes.

[0065] In some embodiments, the densification agent is applied for a time of at least about 5 seconds, at least about 10 seconds, at least about 15 seconds, at least about 20 seconds, at least about 25 seconds, at least about 30 seconds, at least about 35 seconds, at least about 40 seconds, at least about 45 seconds, at least about 50 seconds, at least about 55 seconds, at least about 60 seconds, at least about 90 seconds, at least about 120 seconds, at least about 150 seconds, at least about 180 seconds, at least about 210 seconds, at least about 240 seconds, or at least about 270 seconds.

[0066] In some embodiments, the densification agent is applied for a time of at most about 10 seconds, at most about 15 seconds, at most about 20 seconds, at most about 25 seconds, at most about 30 seconds, at most about 35 seconds, at most about 40 seconds, at most about 45 seconds, at most about 50 seconds, at most about 55 seconds, at most about 60 seconds, at most about 90 seconds, at most about 120 seconds, at most about 150 seconds, at most about 180 seconds, at most about 210 seconds, at most about 240 seconds, at most about 270 seconds, or at most about 300 seconds.

[0067] In some embodiments, the method increases flatness of the semiconductor substrate. In these embodiments, it is understood that the semiconductor substrate is flatter than a semiconductor substrate that is not treated according to the method.

[0068] Generally, the method may further include any suitable method steps known in the art that facilitates the method described herein.

[0069] In some embodiments, the method further includes, subsequent to applying the densification agent to the dielectric layer, positioning the single crystal semiconductor substrate on a heater of a plasma-enhanced chemical vapor deposition system such that the dielectric layer is in contact with the heater, growing a low temperature oxide (LTO) layer on the back surface of the single crystal semiconductor substrate with the plasma-enhanced chemical vapor deposition system, and polishing the front surface of the single crystal semiconductor substrate. In these embodiments, it is understood that the polishing occurs subsequent to the growing.

[0070] In some embodiments, polishing the front surface of the single crystal semiconductor substrate removes at least one heat mark defect on the front surface of the single crystal semiconductor substrate resulting from the heater.

[0071] In some embodiments, polishing the front surface of the single crystal semiconductor substrate removes material from the front surface of the single crystal semiconductor substrate.

[0072] Generally, there is a correlation between higher flatness (which indicates worse quality) and increased removal. The removal is therefore preferably controlled in a range of from about 0.2 pm to about 0.7 pm to provide the desired flatness.

[0073] In some embodiments, less than about 1.5 pm, less than about 1.4 pm, less than about 1.3 pm, less than about 1.2 pm, less than about 1.1 pm, less than about 1.0 pm, less than about 0.9 pm, less than about 0.8 pm, less than about 0.7 pm, less than about 0.6 pm, less than about 0.5 pm, less than about 0.4 pm, less than about 0.3 pm, or less than about 0.2 pm of material is removed from the front surface of the single crystal semiconductor substrate.

[0074] In some embodiments, more than about 1.4 pm, more than about 1.3 pm, more than about 1.2 pm, more than about 1.1 pm, more than about 1.0 pm, more than about 0.9 pm, more than about 0.8 pm, more than about 0.7 pm, more than about 0.6 pm, more than about 0.5 pm, more than about 0.4 pm, more than about0.3 pm, more than about 0.2 m, or more than about 0. 1 pm of material is removed from the front surface of the single crystal semiconductor substrate.

[0075] In some embodiments, the method further includes growing an epitaxial layer on the front surface of the single crystal semiconductor substrate. In some embodiments, the method further includes growing an epitaxial layer on the front surface of the single crystal semiconductor substrate with the plasma-enhanced chemical vapor deposition system. In these embodiments, it is understood that the polishing occurs subsequent to the growing.EXAMPLES

[0076] Without further elaboration, it is believed that one skilled in the art using the preceding description can utilize the present invention to its fullest extent. The following Examples are, therefore, to be construed as merely illustrative, and not limiting of the disclosure in any way whatsoever. The starting material for the following Examples may not have necessarily been prepared by a particular preparative run whose procedure is described in other Examples. It also is understood that any numerical range recited herein includes all values from the lower value to the upper value. For example, if a range is stated as 10-50, it is intended that values such as 12-30, 20-40, or 30-50, etc., are expressly enumerated in this specification. These are only examples of what is specifically intended, and all possible combinations of numerical values between and including the lowest value and the highest value enumerated are to be considered to be expressly stated in this application.

[0077] Example 1. Densification with ozone (O3) water.

[0078] O3 water was used to densify the frontside surface oxide layer of a bare silicon semiconductor substrate. This densification created a clean and hydrophilic oxide layer on the bare silicon semiconductor substrate without any thermal treatment.

[0079] The O3 water can be sprayed on a semiconductor substrate surface or applied by dipping the semiconductor substrate in the tank, so denser oxide layers may be achieved by simple and non-thermal processes.

[0080] In addition, or in the alternative, a gas phase treatment using N2O, O2, and / or O3 at temperature range 300~600°C may also be applied for a duration of 30 seconds to 1 hour to achieve a densified oxide layer on the surface. In gas phase methods, double side densification may occur. That is, a dense layer may form on both sides of the semiconductor substrate, which is undesirable for certain applications or processes. When undesirable, the frontside oxide should be removed.

[0081] FIG. 3 shows a curve representing the thickness of the oxide layer at different durations of O3 water spraying. At the beginning, oxidation occurs immediately when silicon contacts the oxygen radical (~7.5 A after 1 sec of O3 water spray). After 20 seconds of O3 water spraying, the growth of the oxide thickness slows down.

[0082] The O3 water also provides oxygen radicals. Without being bound to any particular theory, it is believed that the O3 water reacts with a silicon (Si) atom in two ways. One way is by directly penetrating through the oxide layer and reacting with the silicon atom on the semiconductor substrate surface. The other way is through diffusion and reacting with partially oxidized silicon dangling bonds within the oxide layer. In any case, a gradual increase in thickness and density is observed over time.

[0083] Example 2. Dimple mark test.

[0084] FIGS. 4A-4H depict dimple mark test results, which show surface contact marks and different defect sizes in a PECVD process for different FPOL removal and densification procedures. The circles aid in visualizing contact marks.

[0085] As shown in FIGS. 4A-4D, without an oxide densifying treatment, the dimple marks will come out with some pits defects. To remove thesemarks, an FPOL process may be used with approximately 1.3 pm removed from the surface. However, this removal amount could result in poor surface flatness.

[0086] As shown in FIGS. 4E-4H, the oxidized surface exhibits varying degrees of scratch resistance from the FPOL 0.9 pm condition. The LTO 300 A, despite being the thickest, has poor density and provides minimal surface protection. Furthermore, both the O3 solution and N2O gas treatment demonstrate exceptional surface protection. Moreover, even at FPOL 0.3 pm, good protection is present in FIG. 4F.

[0087] Example 3. Further densification.

[0088] After final polishing and post polishing cleaning process, a semiconductor substrate may be moved to a new and additional oxide densification treatment. The treatment may involve spraying 20 ppm O3 solution / deionized water (DIW) / N2 for all semiconductor substrate processing steps and DIW and N2 for rinsing and drying steps, respectively. The O3 solution treatment time is approximately 30 to 180 seconds. PECVD may then be used for different thickness (low temperature oxide) LTO growths. An edge stripping process is used for edge oxide stripping. Final polishing is used for front side defect reduction. Surface defects are analyzed and the front side is observed to determine the presence of semiconductor substrate contact points.

[0089] FIG. 5 shows that the different O3 solution spraying durations affect the post polishing dimple mark defect performance. When the spray time increased, the fail rate of dimple mark defect was reduced.

[0090] Example 4. Comparative dimple mark detection.

[0091] FIG. 6 shows a comparative dimple mark detection between a baseline semiconductor substrate and a semiconductor substrate treated for a relatively long time (e.g., greater than 60 seconds) with O3 water. The O3 water- treated semiconductor substrate is free or significantly free of dimples, in contrast to the untreated baseline semiconductor substrate.

[0092] Summary.

[0093] Described herein are semiconductor substrate processing methods. The methods minimize polishing removal thickness and defects on the semiconductor substrate frontside during PECVD LTO processes.

[0094] The methods may add approximately 4 minutes of tool time per semiconductor substrate for the single-semiconductor substrate cleaning process as part of the oxidation treatment function and can reduce the amount of FPOL removal required to eliminate the dimple mark. They may improve the semiconductor substrate flatness of site flatness, frontside, least squares range (SFQR) from 55 nm to 15 nm. Additionally, they may save over 50% of the FPOL process time per semiconductor substrate.

[0095] The methods of the present disclosure may be used with semiconductor substrate backside protection layers such as silicon on insulator (SOI) backside polycrystalline silicon (poly) / LTO, or any other backside treatment process, such as one or more of rapid thermal annealing (RTA), epitaxy (EPI), chemical vapor deposition (CVD), physical vapor deposition (PVD), dry etching, furnace processing, and cleaning.

[0096] Examples of such treatment processes and related configurations are described in more detail, for example, in US Patent No. 10,832,938, the entire contents of which are hereby incorporated by reference herein.

[0097] Definitions.

[0098] As used herein, the term “densify” means to increase thickness, to increase density, or to increase both thickness and density.

[0099] As used herein, references to “example embodiment” or “one embodiment” or “some embodiments” of the present disclosure are not intended to be interpreted as excluding the existence of additional embodiments that also incorporate the recited features.

[0100] As used herein, the terms “about,” “substantially,” “essentially” and “approximately” when used in conjunction with ranges of dimensions, concentrations, temperatures or other physical or chemical properties or characteristics is meant to cover variations that may exist in the upper and / or lower limits of the ranges of the properties or characteristics, including, for example, variations resulting from rounding, measurement methodology or other statistical variation.

[0101] When introducing elements of the present disclosure or the embodiment(s) thereof, the articles “a,” “an,” “the,” and “said” are intended to mean that there are one or more of the elements. The terms “comprising,” “including,” “containing,” and “having” are intended to be inclusive and mean that there may be additional elements other than the listed elements. The use of terms indicating a particular orientation (e.g., “top,” “bottom,” “side,” etc.) is for convenience of description and does not require any particular orientation of the item described.

[0102] As various changes could be made in the above constructions and methods without departing from the scope of the disclosure, it is intended that all matter contained in the above description and shown in the accompanying drawing[s] shall be interpreted as illustrative and not in a limiting sense.

[0103] This written description uses examples to disclose the invention, including the best mode, and also to enable any person skilled in the art to practice the invention, including making and using any devices or systems and performing any incorporated methods. The patentable scope of the invention is defined by the claims, and may include other examples that occur to those skilled in the art. Such other examples are intended to be within the scope of the claims if they have structural elements that do not differ from the literal language of the claims, or if they include equivalent structural elements with insubstantial differences from the literal languages of the claims.

[0104] Exemplary Embodiments.

[0105] 1. A method of processing a single crystal semiconductor substrate, the method comprising: providing the single crystal semiconductor substrate, the single crystal semiconductor substrate comprising two major, generally parallel surfaces, one of which is a front surface of the single crystal semiconductor substrate and the other of which is a back surface of the single crystal semiconductor substrate, a circumferential edge joining the front and back surfaces, and a bulk region between the front and back surfaces; and applying a densification agent to a dielectric layer in interfacial contact with the front surface of the single crystal semiconductor substrate, wherein applying the densification agent densifies the dielectric layer.

[0106] 2. The method of the preceding clause, wherein the densification agent is applied in the absence of a thermal treatment.

[0107] 3. The method of any preceding clause, wherein the densification agent is applied to the dielectric layer in an environment at a temperature in a range of from about 100 °C to about 1000 °C.

[0108] 4. The method of any preceding clause, wherein applying the densification agent to the dielectric layer comprises one or more of spraying the densification agent onto the dielectric layer, dipping the single crystal semiconductor substrate into the densification agent, and combinations thereof.

[0109] 5. The method of any preceding clause, further comprising: ceasing application of the densification agent to the dielectric layer; and subsequently, applying the densification agent to the dielectric layer a second time.

[0110] 6. The method of any preceding clause, further comprising polishing the front surface of the single crystal semiconductor substrate subsequent to the densification agent being applied to the dielectric layer.

[0111] 7. The method of any preceding clause, further comprising polishing the front surface of the single crystal semiconductor substrate prior to the densification agent being applied to the dielectric layer.

[0112] 8. The method of any preceding clause, further comprising polishing the front surface of the single crystal semiconductor substrate both prior to and subsequent to the densification agent being applied to the dielectric layer.

[0113] 9. The method of any preceding clause, wherein applying the densification agent to the dielectric layer increases a thickness of the dielectric layer by at least about 50%.

[0114] 10. The method of any preceding clause, wherein a thickness of the dielectric layer subsequent to the application of the densification agent is at least about 8 A.

[0115] 11. The method of any preceding clause, wherein the single crystal semiconductor substrate has a minimum bulk region resistivity of at least about 0.8 mOhm-cm.

[0116] 12. The method of any preceding clause, wherein the densification agent is in a form selected from the group consisting of solutions, liquids, gases, and combinations thereof.

[0117] 13. The method of any preceding clause, wherein the densification agent is selected from the group consisting of liquid densification agents, ozone (O3) solutions, O3 water, gaseous densification agents, N2O, O2, O3, and combinations thereof.

[0118] 14. The method of any preceding clause, wherein the densification agent comprises an O3 solution.

[0119] 15. The method of the preceding clause, wherein the O3 is present in a concentration of from about 0.01 ppm to about 100 ppm.

[0120] 16. The method of any preceding clause, wherein the O3 is present in a concentration of at least about 20 ppm.

[0121] 17. The method of any preceding clause, wherein the densification agent is applied for a time in a range of from about 1 second to about 10 hours.

[0122] 18. The method of any preceding clause, wherein the densification agent is applied for a time in a range of from about 10 seconds to about 300 seconds.

[0123] 19. The method of any preceding clause, wherein the single crystal semiconductor substrate is a single crystal silicon substrate.

[0124] 20. The method of any preceding clause, further comprising: subsequent to applying the densification agent to the dielectric layer, positioning the single crystal semiconductor substrate on a heater of a plasma- enhanced chemical vapor deposition system such that the dielectric layer is in contact with the heater; growing a low temperature oxide (LTO) layer on the back surface of the single crystal semiconductor substrate with the plasma-enhanced chemical vapor deposition system; and polishing the front surface of the single crystal semiconductor substrate.

[0125] 21. The method of the preceding clause, wherein polishing the front surface of the single crystal semiconductor substrate removes at least one heat mark defect on the front surface of the single crystal semiconductor substrate resulting from the heater.

[0126] 22. The method of any preceding clause, wherein polishing the front surface of the single crystal semiconductor substrate removes less than about 1.5 pm of material from the front surface of the single crystal semiconductor substrate.

[0127] 23. The method of any preceding clause, wherein polishing the front surface of the single crystal semiconductor substrate removes less than about 1.0 pm of material from the front surface of the single crystal semiconductor substrate.

[0128] 24. The method of any preceding clause, wherein polishing the front surface of the single crystal semiconductor substrate removes less than about 0.5 pm of material from the front surface of the single crystal semiconductor substrate.

[0129] 25. The method of any preceding clause, further comprising: growing an epitaxial layer on the front surface of the single crystal semiconductor substrate.

[0130] 26. A method of processing a single crystal semiconductor substrate, the method comprising: providing the single crystal semiconductor substrate, the single crystal semiconductor substrate comprising two major, generally parallel surfaces, one of which is a front surface of the single crystal semiconductor substrate and the other of which is a back surface of the single crystal semiconductor substrate, a circumferential edge joining the front and back surfaces, and a bulk region between the front and back surfaces; applying a densification agent to a dielectric layer in interfacial contact with the front surface of the single crystal semiconductor substrate, wherein applying the densification agent densifies the dielectric layer;subsequent to applying the densification agent to the dielectric layer, positioning the single crystal semiconductor substrate on a heater of a plasma- enhanced chemical vapor deposition system such that the dielectric layer is in contact with the heater; growing a low temperature oxide (LTO) layer on the back surface of the single crystal semiconductor substrate with the plasma-enhanced chemical vapor deposition system; and polishing the front surface of the single crystal semiconductor substrate.

[0131] The individual aspects of the present disclosure may be combined in any combination or permutation. Select exemplary embodiments are set forth in the following clauses. These embodiments are non-limiting.

Claims

WHAT IS CLAIMED IS:

1. A method of processing a single crystal semiconductor substrate, the method comprising: providing the single crystal semiconductor substrate, the single crystal semiconductor substrate comprising two major, generally parallel surfaces, one of which is a front surface of the single crystal semiconductor substrate and the other of which is a back surface of the single crystal semiconductor substrate, a circumferential edge joining the front and back surfaces, and a bulk region between the front and back surfaces; and applying a densification agent to a dielectric layer in interfacial contact with the front surface of the single crystal semiconductor substrate, wherein applying the densification agent densifies the dielectric layer.

2. The method of claim 1, wherein the densification agent is applied in the absence of a thermal treatment.

3. The method of claim 1, wherein the densification agent is applied to the dielectric layer in an environment at a temperature in a range of from about 100 °C to about 1000 °C.

4. The method of claim 1, wherein applying the densification agent to the dielectric layer comprises one or more of spraying the densification agent onto the dielectric layer, dipping the single crystal semiconductor substrate into the densification agent, and combinations thereof.

5. The method of claim 1, further comprising: ceasing application of the densification agent to the dielectric layer; and subsequently, applying the densification agent to the dielectric layer a second time.

6. The method of claim 1, further comprising polishing the front surface of the single crystal semiconductor substrate subsequent to the densification agent being applied to the dielectric layer.

7. The method of claim 1, further comprising polishing the front surface of the single crystal semiconductor substrate prior to the densification agent being applied to the dielectric layer.

8. The method of claim 1, further comprising polishing the front surface of the single crystal semiconductor substrate both prior to and subsequent to the densification agent being applied to the dielectric layer.

9. The method of claim 1, wherein applying the densification agent to the dielectric layer increases a thickness of the dielectric layer by at least about 50%.

10. The method of claim 1, wherein a thickness of the dielectric layer subsequent to the application of the densification agent is at least about 8 A.

11. The method of claim 1 , wherein the single crystal semiconductor substrate has a minimum bulk region resistivity of at least about 0.8 mOhm-cm.

12. The method of claim 1, wherein the densification agent is in a form selected from the group consisting of solutions, liquids, gases, and combinations thereof.

13. The method of claim 1, wherein the densification agent is selected from the group consisting of liquid densification agents, ozone (O3) solutions, O3 water, gaseous densification agents, N2O, O2, O3, and combinations thereof.

14. The method of claim 1, wherein the densification agent comprises an O3 solution.

15. The method of claim 14, wherein the O3 is present in a concentration of from about 0.01 ppm to about 100 ppm.

16. The method of claim 14, wherein the O3 is present in a concentration of at least about 20 ppm.

17. The method of claim 1, wherein the densification agent is applied for a time in a range of from about 1 second to about 10 hours.

18. The method of claim 1, wherein the densification agent is applied for a time in a range of from about 10 seconds to about 300 seconds.

19. The method of claim 1, wherein the single crystal semiconductor substrate is a single crystal silicon substrate.

20. The method of claim 1, further comprising: subsequent to applying the densification agent to the dielectric layer, positioning the single crystal semiconductor substrate on a heater of a plasma- enhanced chemical vapor deposition system such that the dielectric layer is in contact with the heater; growing a low temperature oxide (LTO) layer on the back surface of the single crystal semiconductor substrate with the plasma-enhanced chemical vapor deposition system; and polishing the front surface of the single crystal semiconductor substrate.

21. The method of claim 20, wherein polishing the front surface of the single crystal semiconductor substrate removes at least one heat mark defect on the front surface of the single crystal semiconductor substrate resulting from the heater.

22. The method of claim 20, wherein polishing the front surface of the single crystal semiconductor substrate removes less than about 1 .5 pm of material from the front surface of the single crystal semiconductor substrate.

23. The method of claim 20, wherein polishing the front surface of the single crystal semiconductor substrate removes less than about 1 .0 pm of material from the front surface of the single crystal semiconductor substrate.

24. The method of claim 20, wherein polishing the front surface of the single crystal semiconductor substrate removes less than about 0.5 pm of material from the front surface of the single crystal semiconductor substrate.

25. The method of claim 20, further comprising: growing an epitaxial layer on the front surface of the single crystal semiconductor substrate.

26. A method of processing a single crystal semiconductor substrate, the method comprising: providing the single crystal semiconductor substrate, the single crystal semiconductor substrate comprising two major, generally parallel surfaces, one of which is a front surface of the single crystal semiconductor substrate and the other of which is a back surface of the single crystal semiconductor substrate, a circumferential edge joining the front and back surfaces, and a bulk region between the front and back surfaces; applying a densification agent to a dielectric layer in interfacial contact with the front surface of the single crystal semiconductor substrate, wherein applying the densification agent densifies the dielectric layer; subsequent to applying the densification agent to the dielectric layer, positioning the single crystal semiconductor substrate on a heater of a plasma- enhanced chemical vapor deposition system such that the dielectric layer is in contact with the heater; growing a low temperature oxide (LTO) layer on the back surface of the single crystal semiconductor substrate with the plasma-enhanced chemical vapor deposition system; andpolishing the front surface of the single crystal semiconductor substrate.

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