Ring oscillator and communication apparatus

Abstract

The embodiments of the present application relate to the technical field of electronics. Provided are a ring oscillator and a communication apparatus, which can realize low power consumption and low phase noise. The ring oscillator comprises a first delay cell array, a second delay cell array, a first current source, a second current source, a first switch, and a second switch, wherein current in the first current source is less than current in the second current source. An output end of the first current source is coupled to a power supply end of the first delay cell array by means of the first switch, and an output end of the second current source is coupled to a power supply end of the second delay cell array by means of the second switch; when the second switch is turned on and the first switch is turned off, the second delay cell array operates; and when the second switch is turned off and the first switch is turned on, the first delay cell array operates.

Description

A ring oscillator and a communication device

[0001] The present application claims priority from the Chinese patent application No. 202410973415.0 filed on July 17, 2024, and entitled "A ring oscillator and a communication device", the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0002] The present application relates to the field of electronic technology, and in particular to a ring oscillator and a communication device. BACKGROUND

[0003] Oscillators are widely used in various fields as an important unit of electronic systems. For example, oscillators can be used in clock circuits of microprocessors to generate stable clock signals. Oscillators can also be used in phase-locked loops of wireless transceivers to provide stable local carrier signals for wireless transceivers to ensure the communication performance of the transceivers.

[0004] Among them, the ring oscillator can be implemented by using a complementary metal oxide semiconductor (CMOS) process, without the need for inductors and capacitors and other components. Due to its simple structure, low cost, small area, and wide tuning range, the ring oscillator is widely used in communication devices. The power consumption and phase noise of the ring oscillator are the main parameters for measuring the performance of the ring oscillator. It is usually desired to achieve low phase noise performance under low power consumption conditions. Therefore, a ring oscillator with low power consumption and low phase noise has been a long-term research topic. SUMMARY

[0005] The embodiments of the present application provide a ring oscillator and a communication device, which can achieve low power consumption and low phase noise.

[0006] To achieve the above-mentioned purpose, the embodiments of the present application adopt the following technical solutions:

[0007] In a first aspect, an annular oscillator is provided, comprising: a first delay cell array, a second delay cell array, a first current source, a second current source, a first switch and a second switch; wherein a current in the first current source is less than a current in the second current source. An output terminal of the first current source is coupled with a power supply terminal of the first delay cell array through the first switch, an output terminal of the second current source is coupled with a power supply terminal of the second delay cell array through the second switch, and a voltage terminal of the first delay cell array and a voltage terminal of the second delay cell array are both coupled with a ground terminal. An input terminal of the first delay cell array and an output terminal of the first delay cell array are coupled, an input terminal of the second delay cell array and an output terminal of the second delay cell array are coupled, and the output terminal of the first delay cell array is coupled with the output terminal of the second delay cell array. When the second switch is closed and the first switch is opened, the second delay cell array works; and when the second switch is opened and the first switch is closed, the first delay cell array works.

[0008] In the above technical solution, by turning on and turning off different switches, the annular oscillator works at different power consumptions, achieving the purpose of power consumption switching. For example, in a low power consumption scenario, the first switch is closed and the second switch is opened, so that the first delay cell array works. Since the current in the first current source is less than the current in the second current source, the power consumption of the first delay cell array is lower than that of the second delay cell array, thereby reducing the power consumption of the annular oscillator. In a low phase noise (i.e. high performance) scenario, the second switch is closed and the first switch is opened, so that the second delay cell array works, meeting the requirement of low phase noise, achieving low power consumption and low phase noise, and meeting the requirement of different scenarios.

[0009] In a possible implementation manner of the first aspect, each of the first delay cell arrays comprises at least two first differential delay cells coupled in series, and each of the second delay cell arrays comprises at least two second differential delay cells coupled in series. In the above possible implementation manner, different numbers of differential delay cells can be designed according to the requirements of speed, power consumption and phase noise of the annular oscillator in the design stage, thereby improving the flexibility of design.

[0010] In a possible implementation manner of the first aspect, the first delay cell array and the second delay cell array are different in at least one of the following: the number of the at least two first differential delay cells and the number of the at least two second differential delay cells are different, and the size of the at least two first differential delay cells and the size of the at least two second differential delay cells are different. In the above possible implementation manner, the frequency of the first delay cell array and the second delay cell array is ensured to be the same, and the purpose of frequency-invariant power consumption switching can be achieved by switching different switches.

[0011] In a possible implementation of the first aspect, the first differential delay unit has a power consumption less than that of the second differential delay unit, and the first differential delay unit has a phase noise greater than that of the second differential delay unit. In the possible implementation, the different differential delay units in the different delay unit arrays are enabled to switch the ring oscillator to have different power consumptions while keeping the frequency unchanged, thereby meeting more scene requirements.

[0012] In a possible implementation of the first aspect, the ring oscillator further includes a third switch coupled between the output terminal of the first current source and the output terminal of the second current source. In the possible implementation, when the third switch and the second switch are closed, the output terminal of the first current source and the output terminal of the second current source are coupled to the power terminal of the second delay unit array through the third switch and the second switch respectively to supply power to the second delay unit array, the second delay unit array is multiplexed with the first current source, the utilization of the first current source is improved, and the size of the current in the second current source can be reduced in the design stage, thereby reducing the area of the current source.

[0013] In a possible implementation of the first aspect, for any delay unit array of the first delay unit array or the second delay unit array, the input terminal of the delay unit array includes differential first and second input terminals, the output terminal of the delay unit array includes differential first and second output terminals, and the ring oscillator further includes fourth, fifth, sixth, and seventh switches corresponding to the delay unit array. The fourth switch is coupled between the first input terminal of the delay unit array and a first node, the fifth switch is coupled between the second input terminal of the delay unit array and a second node, the sixth switch is coupled between the second output terminal of the delay unit array and the first node, and the seventh switch is coupled between the first output terminal of the delay unit array and the second node. The first and second nodes are nodes between the input and output terminals of the delay unit array. In the possible implementation, different delay unit arrays are enabled by turning on and off different switches, and the unenabled delay unit arrays are shielded by the switches, thereby reducing interference.

[0014] In a possible implementation of the first aspect, when the first switch is closed and the second switch and the third switch are opened, the fourth switch, the fifth switch, the sixth switch and the seventh switch corresponding to the first delay cell array are closed, the fourth switch, the fifth switch, the sixth switch and the seventh switch corresponding to the second delay cell array are opened, and the first delay cell array works. When the first switch is opened and the second switch and the third switch are closed, the fourth switch, the fifth switch, the sixth switch and the seventh switch corresponding to the first delay cell array are opened, the fourth switch, the fifth switch, the sixth switch and the seventh switch corresponding to the second delay cell array are closed, and the second delay cell array works. In the possible implementation, different delay cell arrays work by turning on and off different switches, and the non-working delay cell arrays are shielded by the switches, thereby reducing interference.

[0015] In a possible implementation of the first aspect, when the first delay cell array includes a plurality of first delay cell arrays, the output terminal of the first current source is coupled to the power supply terminal of each of the plurality of first delay cell arrays through the first switch; and / or when the second delay cell array includes a plurality of second delay cell arrays, the output terminal of the first current source and the output terminal of the second current source are coupled to the power supply terminal of each of the plurality of second delay cell arrays through the second switch and the third switch, respectively. In the possible implementation, different numbers of delay cell arrays can be designed according to the requirements of the speed, power consumption and phase noise of the ring oscillator in the design stage, thereby improving the flexibility of design.

[0016] In a possible implementation of the first aspect, the ring oscillator further includes a frequency tuning circuit, which is coupled between the input terminal of the first delay cell array and the output terminal of the first delay cell. In the possible implementation, the frequency tuning circuit is used to adjust the frequency in the ring oscillator, so that the ring oscillator can meet different frequency requirements, thereby improving the utilization rate.

[0017] In a second aspect, a phase-locked loop circuit is provided, which includes a phase detector, a filter and a ring oscillator. The ring oscillator is as described in the first aspect or any possible implementation of the first aspect. The phase detector is configured to obtain a phase difference signal and convert the phase difference signal into a voltage signal. The filter is configured to filter the voltage signal. The ring oscillator is configured to output a local carrier signal according to the filtered voltage signal.

[0018] In a third aspect, a communication device is provided, which includes a processor and a phase-locked loop circuit. The phase-locked loop circuit is as described in the second aspect. The processor is configured to process the local carrier signal output by the phase-locked loop circuit.

[0019] In a possible implementation form of the third aspect, the communication apparatus further comprises a radio frequency transceiver, and the phase-locked loop circuit is integrated in the radio frequency transceiver and configured to provide a local carrier signal for the radio frequency transceiver.

[0020] It can be understood that any one of the above provided phase-locked loop circuit and communication apparatus comprises all features of the above ring oscillator, and the beneficial effects achieved thereby can correspond to the beneficial effects of the ring oscillator provided above, which will not be repeated here. BRIEF DESCRIPTION OF DRAWINGS

[0021] Fig. 1 is a structural schematic diagram of a ring oscillator provided by an embodiment of the present application;

[0022] Fig. 2 is a structural schematic diagram of a communication apparatus provided by an embodiment of the present application;

[0023] Fig. 3 is a structural schematic diagram of a phase-locked loop circuit provided by an embodiment of the present application;

[0024] Fig. 4 is a structural schematic diagram of another ring oscillator provided by an embodiment of the present application;

[0025] Fig. 5 is a structural schematic diagram of still another ring oscillator provided by an embodiment of the present application;

[0026] Fig. 6 is a structural schematic diagram of another ring oscillator provided by an embodiment of the present application;

[0027] Fig. 7 is a structural schematic diagram of still another ring oscillator provided by an embodiment of the present application;

[0028] Fig. 8 is a structural schematic diagram of another ring oscillator provided by an embodiment of the present application;

[0029] Fig. 9 is a structural schematic diagram of still another ring oscillator provided by an embodiment of the present application;

[0030] Fig. 10 is a structural schematic diagram of another ring oscillator provided by an embodiment of the present application;

[0031] Fig. 11 is a simulation schematic diagram of a ring oscillator provided by an embodiment of the present application;

[0032] Fig. 12 is a layout of a ring oscillator provided by an embodiment of the present application. DETAILED DESCRIPTION

[0033] In the present application, "one or more" refers to one or more than one, and "multiple" refers to two or more than two. The "and / or" describes the association relationship of the associated objects, which means that there can be three kinds of relationships, for example, A and / or B can represent the following three cases: A exists alone, A and B exist together, and B exists alone, where A and B can be singular or plural. The character " / " generally represents an "or" relationship between the front and rear associated objects. "At least one of the following" or similar expressions means any combination of these items, including any combination of single or multiple items. For example, at least one of a, b, or c can represent a, b, c, a-b, a-c, b-c, or a-b-c, where a, b, and c can be single or multiple. In addition, the present application embodiments use "first", "second", and the like to distinguish the same items or similar items with basically the same function and effect. For example, the first threshold and the second threshold are only used to distinguish different thresholds, and do not limit the order. Those skilled in the art can understand that "first", "second", and the like do not limit the quantity and execution order.

[0034] It should be noted that in the present application, the words "exemplary" or "for example" are used to mean serving as an example, instance, or illustration. Any embodiment or design solution described as "exemplary" or "for example" in the present application should not be interpreted as being more preferred or advantageous than other embodiments or design solutions. Rather, the use of "exemplary" or "for example" is intended to present relevant concepts in a concrete manner.

[0035] Before introducing the embodiments of the present application, the related knowledge of the oscillator is first introduced and described.

[0036] The oscillator is one of the important units of the electronic system, and has a very wide range of applications. For example, the oscillator can be applied to the clock circuit of the microprocessor for generating a stable clock signal; the oscillator can also be applied to the phase-locked loop of the wireless transceiver for providing a stable local carrier signal for the wireless transceiver to ensure the communication performance of the transceiver.

[0037] Among them, the ring oscillator can be realized by using a complementary metal oxide semiconductor (CMOS) process, without the need for inductors and capacitors and other elements. Due to its simple structure, low cost, small area, and wide tuning range, the ring oscillator is widely used in communication devices. The power consumption and phase noise of the ring oscillator are the main parameters for measuring the performance of the ring oscillator, and it is usually desired to achieve low phase noise performance under low power consumption conditions. Therefore, the ring oscillator with low power consumption and low phase noise has been a long-term research topic.

[0038] For example, FIG. 1 is a schematic diagram of a ring oscillator 10, which includes three differential delay cells, a current source 104 and a frequency modulation circuit 105. The three differential delay cells are denoted as 101-103, respectively. The frequency modulation circuit 105 includes two transistors and is denoted as M11 and M12, respectively.

[0039] The differential delay cells 101-103 are coupled in a ring. Each differential delay cell includes a differential first input terminal Vi+ and a differential second input terminal Vi-, and a differential first output terminal Vo+ and a differential second output terminal Vo-. The first output terminal Vo+ and the second output terminal Vo- of each differential delay cell are coupled to the first input terminal Vi+ and the second input terminal Vi- of the next differential delay cell, respectively. Two adjacent differential delay cells among the three differential delay cells are coupled in phase, and the rest of the differential delay cells are coupled in anti-phase. For example, the first output terminal Vo+ and the second output terminal Vo- of the differential delay cell 101 are coupled to the second input terminal Vi- and the first input terminal Vi+ of the differential delay cell 102, respectively. The first output terminal Vo+ and the second output terminal Vo- of the differential delay cell 102 are coupled to the second input terminal Vi- and the first input terminal Vi+ of the differential delay cell 103, respectively. The first output terminal Vo+ and the second output terminal Vo- of the differential delay cell 103 are coupled to the first input terminal Vi+ and the second input terminal Vi- of the differential delay cell 101, respectively. The differential delay cell 103 is coupled in phase with the differential delay cell 101, and the rest of the differential delay cells are coupled in anti-phase.

[0040] The output terminal of the current source 104 is coupled to the power supply terminal of each differential delay cell 101-103. The current source 104 is configured to supply power to each differential delay cell. The input terminal of the current source 104 is configured to receive a power supply voltage VDD. The voltage terminal of each differential delay cell 101-103 is coupled to a ground terminal (GND). The second input terminal Vi- of the differential delay cell 101 is coupled to the gate terminal G of the transistor M11. The source terminal S and the drain terminal D of the transistor M11 are coupled to a node P0. The first output terminal Vo+ of the differential delay cell 103 is coupled to the gate terminal G of the transistor M12. The source terminal S and the drain terminal D of the transistor M12 are coupled to the node P0. The node P0 is configured to receive the power supply voltage. In FIG. 1, the first input terminal and the first output terminal of each differential delay cell are positive, and the second input terminal and the second output terminal are negative. The power supply terminal and the voltage terminal are not shown in FIG. 1.

[0041] In the working process, it is assumed that at a moment T0, the first input end and the second input end of the differential delay unit 101 are a positive differential signal (i.e., a high level), the first output end and the second output end of the differential delay unit 101 become a negative differential signal (i.e., a low level) after a delay time ΔT (T=T0+ΔT), the first output end and the second output end of the differential delay unit 102 become a positive differential signal after a delay time ΔT (T=T0+2ΔT), and so on. After 6ΔT, the first output end and the second output end of the differential delay unit 101 become a positive differential signal again, and the ring oscillator completes a period of oscillation. The current source 104 can be used to supply power to each differential delay unit. When the size of the differential delay unit is determined, the oscillation frequency of the ring oscillator is related to the size of the current in the current source 104. The frequency adjustment circuit 105 can be used to adjust the frequency of the ring oscillator based on the received power supply voltage.

[0042] In actual applications, the differential delay unit can also be referred to as a differential inverting amplifier. The number of differential delay units in the ring oscillator can be greater than or equal to 2. The specific number of differential delay units can be selected according to the requirements of the application on the speed, power consumption, and noise performance of the ring oscillator. In FIG. 1, three differential delay units are taken as an example to illustrate the ring oscillator.

[0043] However, when the size of the differential delay unit in the ring oscillator is fixed, the size of the current in the current source determines the oscillation frequency of the ring oscillator. For a ring oscillator with a fixed oscillation frequency, the size of the current in the current source is also fixed, and the purpose of adjusting the power consumption cannot be achieved by adjusting the size of the current in the current source. For example, in a low-power consumption scenario, the power consumption of the oscillator cannot be reduced by adjusting the size of the current in the current source.

[0044] Therefore, the embodiments of the present application provide a ring oscillator. By switching different switches, the ring oscillator can work at the same frequency and different power consumptions, achieving the purpose of frequency-invariant power consumption switching and adapting to more scene requirements.

[0045] The ring oscillator provided by the embodiments of the present application can be applied to a communication device. The structure of the communication device is introduced and described below.

[0046] FIG. 2 is a structural schematic diagram of a communication apparatus provided by an embodiment of the present application, which can include a radio frequency transceiver 001 and multiple groups of radio frequency circuits 002, and the radio frequency transceiver 001 and the multiple groups of radio frequency circuits 002 share some devices. The radio frequency transceiver 001 can include a phase locked loop (PLL) circuit 100, a local oscillator generator (LO) 110, a digital base band (DBB) circuit 120, a transmit analog base band (TX ABB) circuit 130 (schematically shown as TX ABB in the figure) and a mixer 140. Optionally, the communication apparatus can further include a power amplifier (PA) 150 and an antenna 160. Each group of radio frequency circuits 002 can include the TX ABB circuit 130, the mixer 140, the PA 150 and the antenna 160.

[0047] The PLL circuit 100 can include a ring oscillator provided by an embodiment of the present application. In a possible design, the DBB circuit 120 and the TX ABB circuit 130 are collectively referred to as a base band circuit.

[0048] First, the connection relationship of the above-mentioned devices is described.

[0049] The output end of the PLL circuit 100 is connected to the input end of the LO 110. For each group of radio frequency circuits 002, the output end of the LO 110 is connected to the first input end of the mixer 140. On the transmit link of each group of radio frequency circuits 002, the DBB circuit 120 is connected to the input end of the TX ABB circuit 130, the output end of the TX ABB circuit 130 is connected to the second input end of the mixer 140, the output end of the mixer 140 is connected to the input end of the PA 150, and the output end of the PA 150 is connected to the antenna 160.

[0050] The functions of the above-mentioned devices are described as follows.

[0051] The PLL circuit 100 is configured to output a first oscillation signal with a fixed clock frequency for each channel to the LO 110, which can also be referred to as a local carrier signal.

[0052] The LO 110 is configured to process the first oscillation signal and output a plurality of transmit oscillation signals with local oscillator frequencies to the mixer 140.

[0053] The DBB circuit 120 is configured to send a digital signal to the transmit link of the radio frequency circuit 130.

[0054] The TX ABB circuit 130 is configured to filter and amplify the digital signal from the DBB circuit 120.

[0055] The mixer 140 is configured to mix the transmit oscillation signal and the signal output by the TX ABB circuit 130, and output the mixed signal to the PA 150.

[0056] The PA 150 is configured to amplify the signal after mixing.

[0057] The antenna 160 is configured to transmit the signal amplified by the PA 150.

[0058] The specific structure of the phase-locked loop will be described in detail below based on FIG. 3. FIG. 3 is a structural schematic diagram of a phase-locked loop circuit, which can be the phase-locked loop circuit shown in FIG. 2. The phase-locked loop circuit includes a phase detector 301, a filter 302, a ring oscillator 303, and a frequency divider 304. The phase detector 301 is configured to compare a reference signal and a local carrier signal fed back by the frequency divider 304 to obtain a phase difference signal, and convert the phase difference signal into a voltage signal output. The reference signal can be a signal provided by a reference frequency source. The filter 302 filters the voltage signal. The ring oscillator 303 is configured to output a local carrier signal according to the filtered voltage signal, and the local carrier signal can be fed back to the phase detector 301 through the frequency divider 304 to form a closed-loop feedback circuit.

[0059] The specific structure of the ring oscillator will be described below based on FIG. 4. FIG. 4 is a structural schematic diagram of a ring oscillator provided in an embodiment of the present application, which can be the ring oscillator provided in FIG. 3. The ring oscillator can include:

[0060] The first delay unit array 401, the second delay unit array 402, the first current source A1, the second current source A2, the first switch S1, and the second switch S2. The output terminal of the first current source A1 is coupled to the power supply terminal of the first delay unit array 401 through the first switch S1, the output terminal of the second current source A2 is coupled to the power supply terminal of the second delay unit array 402 through the second switch S2, and the voltage terminal of the first delay unit array 401 and the voltage terminal of the second delay unit array 402 are both coupled to the ground terminal.

[0061] The current in the first current source A1 is less than the current in the second current source A2, for example, the current in the first current source A1 is I0, the current in the second current source A2 is I1, I0 is less than I1, and the specific values of I0 and I1 can be set according to the speed, power consumption and noise performance requirements of the ring oscillator. Since I0 is less than I1, the power consumption of the first delay cell array 401 when working is less than the power consumption of the second delay cell array 402 when working. The first delay cell array can also be referred to as a low-power delay cell array, the second delay cell array can also be referred to as a high-performance delay cell array, and the phase noise of the second delay cell array 402 is less than the phase noise of the first delay cell array 401.

[0062] In addition, the input end of the first current source A1 and the input end of the second current source A2 are used to receive a power supply voltage VDD. The first current source A1 can be used to provide a power supply current for the first delay cell array 401 through the first switch S1, and the second current source A2 can be used to provide a power supply current for the second delay cell array 402 through the second switch S2.

[0063] Secondly, the ring oscillator can include one first delay cell array 401, or can include a plurality of first delay cell arrays 401, and similarly, the ring oscillator can include one second delay cell array 402, or can include a plurality of second delay cell arrays 402, and the application does not make specific limitations on the comparison.

[0064] The connection relationship between the different numbers of delay cell arrays and the current sources (including the first current source A1 and the second current source A2) and the switches (including the first switch S1 and the second switch S2) when the ring oscillator includes different numbers of delay cell arrays will be described below.

[0065] In one possible embodiment, the ring oscillator includes one first delay cell array 401 and one second delay cell array 402, the output end of the first current source A1 is coupled with the power supply end of the first delay cell array 401 through the first switch S1, the output end of the second current source A2 is coupled with the power supply end of the second delay cell array 402 through the second switch S2, and the voltage end of the first delay cell array 401 and the voltage end of the second delay cell array 402 are both coupled with the ground end (GND).

[0066] In this embodiment, the first delay cell array 401 corresponds to the first current source A1 and the first switch S1, and the second delay cell array 402 corresponds to the second current source A2 and the second switch S2. When the first switch S1 is closed and the second switch S2 is opened, the first current source A1 provides a power supply current I0 for the first delay cell array 401; when the first switch S1 is opened and the second switch S2 is closed, the second current source A2 provides a power supply current I1 for the second delay cell array 402.

[0067] In one possible embodiment, the ring oscillator comprises a plurality of first delay cell arrays 401 and a plurality of second delay cell arrays 402, the output terminal of the first current source A1 is coupled to the power terminal of each of the plurality of first delay cell arrays 401 through the first switch S1, i.e. the plurality of first delay cell arrays 401 correspond to the first current source A1 and the first switch S1. The output terminal of the second current source A2 is coupled to the power terminal of each of the plurality of second delay cell arrays 402 through the second switch S2, i.e. the plurality of second delay cell arrays 402 correspond to the second current source A2 and the second switch S2.

[0068] In this embodiment, the plurality of first delay cell arrays 401 correspond to the first current source A1 and the first switch S1, and the plurality of second delay cell arrays 402 correspond to the second current source A2 and the second switch S2. When the first switch S1 is closed and the second switch S2 is opened, the first current source A1 provides a power supply current for each of the plurality of first delay cell arrays 401, and the sum of the currents in the plurality of first delay cell arrays 401 is I0. When the first switch S1 is opened and the second switch S2 is closed, the second current source A2 provides a power supply current for each of the plurality of second delay cell arrays 402, and the sum of the currents in the plurality of second delay cell arrays 402 is I1.

[0069] Optionally, the plurality of first delay cell arrays 401 correspond to the first current source A1 and a plurality of first switches S1, each of the plurality of first delay cell arrays 401 corresponds to one of the plurality of first switches S1, and the plurality of second delay cell arrays 402 correspond to the second current source A2 and a plurality of second switches S2, each of the plurality of second delay cell arrays 402 corresponds to one of the plurality of second switches S2. The present application does not make specific limitations thereto.

[0070] For example, in FIG. 4, it is illustrated that the first delay cell array 401 comprises one first delay cell array 401, and the second delay cell array 402 comprises one second delay cell array 402.

[0071] The coupling relationship between the first delay cell array 401 and the second delay cell array 402 will be described below.

[0072] In addition, the input terminal of the first delay cell array 401 is coupled to the output terminal of the first delay cell array 401, the input terminal of the second delay cell array 402 is coupled to the output terminal of the second delay cell array 402, and the output terminal of the first delay cell array 401 is coupled to the output terminal of the second delay cell array 402.

[0073] The input end of each delay cell array includes a differential first input end and a second input end, and a differential first output end and a second output end. One of the two input ends of each delay cell array (including the differential first input end and the second input end) is positive, and the other is negative, for example, the first input end is positive, and the second input end is negative, or the first input end is negative, and the second input end is positive; similarly, one of the two output ends of each delay cell array (including the differential first output end and the second output end) is positive, and the other is negative, for example, the first output end is positive, and the second output end is negative, or the first output end is negative, and the second output end is positive. In this application, the first input end is Vi+ (positive), the second input end is Vi- (negative), the first output end is Vo+ (positive), and the second output end is Vo- (negative) are taken as examples for illustration.

[0074] In addition, the positive or negative of the input end (including the differential first input end and the second input end) and the output end (including the differential first output end and the second output end) of each delay cell array is in terms of electric potential. In terms of phase, it is a same-phase end or an opposite end. The same-phase end means that the polarity of the two ports (including any two of the differential first input end, the second input end, the differential first output end, and the second output end) is the same, and it can also be understood that the signals corresponding to the two ports are in phase, that is, both are 0 or 180 degrees. The opposite end means that the polarity of the two ports is opposite, and it can also be understood that the signals corresponding to the two ports are opposite, that is, one is 0 and the other is 180 degrees. The positive and the negative represent 0 and 180 degrees respectively, for example, the positive can represent 0, and the negative can represent 180 degrees. Therefore, the positive and the negative are opposite.

[0075] Optionally, the two delay cell arrays can be coupled in phase or in opposite phase, for example, the first output end Vo+ and the second output end Vo- of the first delay cell array 401 can be coupled to the first input end Vi+ and the second input end Vi- of the second delay cell array 402 respectively, or the first output end Vo+ and the second output end Vo- of the first delay cell array 401 can be coupled to the second input end Vi- and the first input end Vi+ of the second delay cell array 402 respectively, and the application does not make specific limitations in comparison. In FIG. 4, the first delay cell array 401 and the second delay cell array 402 are coupled in phase as an example.

[0076] Optionally, the input and output of any one delay cell array can be in-phase coupling or anti-phase coupling. For example, the first input Vi+ and the second input Vi- of the first delay cell array 401 are coupled to the first output Vo+ and the second output Vo- of the first delay cell array 401 respectively, and the first input Vi+ and the second input Vi- of the second delay cell array 402 are coupled to the first output Vo+ and the second output Vo- of the second delay cell array 402 respectively. The application does not make specific limitations on the comparison. In FIG. 4, the input and output of the first delay cell array 401 and the input and output of the second delay cell array 402 are in-phase coupling. In actual application, the direct coupling between the input and the output can also be referred to as ring coupling.

[0077] In the working process, when the second switch S2 is closed and the first switch S1 is opened, the second current source A2 provides the power supply current I1 for the second delay cell array 402, the first delay cell array 401 does not work, and the second delay cell array 402 works; when the second switch S2 is opened and the first switch S1 is closed, the first current source A1 provides the power supply current I0 for the first delay cell array 401, the first delay cell array 401 works, and the second delay cell array 402 does not work. Since I0 is less than I1, the power consumption of the first delay cell array 401 when it works is less than the power consumption of the second delay cell array 402 when it works.

[0078] In this embodiment, by turning on and off different switches, the ring oscillator works at different power consumptions, achieving the purpose of power consumption switching. For example, in a low-power consumption scenario, the first switch S1 is closed and the second switch S2 is opened, so that the first delay cell array 401 works, reducing the power consumption of the ring oscillator; in a high-performance scenario, the second switch S2 is closed and the first switch S1 is opened, so that the second delay cell array 402 works. The performance of the second delay cell array 402 is higher than that of the first delay cell array 401, that is, the phase noise of the second delay cell array 402 is lower than that of the first delay cell array 401, meeting the demand of the high-performance scenario, so that the ring oscillator meets the demand of different scenarios.

[0079] In a possible embodiment, in combination with FIG. 4, as shown in FIG. 5, the ring oscillator further includes: a third switch S3, the third switch S3 being coupled between the output of the first current source A1 and the output of the second current source A2.

[0080] The output of the first current source A1 and the output of the second current source A2 provide the power supply current for the second delay cell array 402 through the third switch S3 and the second switch S2 respectively.

[0081] The following will be described respectively the connection relationship between the different number of delay cell arrays and the current sources (including the first current source A1 and the second current source A2) and the switches (including the first switch S1, the second switch S2 and the third switch S3) when the ring oscillator includes different number of delay cell arrays.

[0082] In a possible embodiment, the ring oscillator includes a first delay cell array 401 and a second delay cell array 402, the output terminal of the first current source A1 is coupled with the power supply terminal of the first delay cell array 401 through the first switch S1, the output terminal of the first current source A1 and the output terminal of the second current source A2 are respectively coupled with the power supply terminal of the second delay cell array 402 through the third switch S3 and the second switch S2, and the voltage terminal of the first delay cell array 401 and the voltage terminal of the second delay cell array 402 are both coupled with the ground terminal (GND).

[0083] In this embodiment, the first delay cell array 401 corresponds to the first current source A1 and the first switch S1, and the second delay cell array 402 corresponds to the second current source A2, the second switch S2 and the third switch S3. When the first switch S1 is closed and the second switch S2 and the third switch S3 are opened, the first current source A1 provides the power supply current I0 for the first delay cell array 401; when the first switch S1 is opened and the second switch S2 and the third switch S3 are closed, the first current source A1 and the second current source A2 provide the power supply current I0+I1 for the second delay cell array 402.

[0084] In a possible embodiment, the ring oscillator includes a plurality of first delay cell arrays 401 and a plurality of second delay cell arrays 402, the output terminal of the first current source A1 is coupled with the power supply terminal of each of the plurality of first delay cell arrays 401 through the first switch S1, that is, the plurality of first delay cell arrays 401 correspond to the first current source A1 and the first switch S1. The output terminal of the first current source A1 and the output terminal of the second current source A2 are respectively coupled with the power supply terminal of each of the plurality of second delay cell arrays 402 through the third switch S3 and the second switch S2, that is, the plurality of second delay cell arrays 402 correspond to the second current source A2, the second switch S2 and the third switch S3.

[0085] In this embodiment, the plurality of first delay unit arrays 401 correspond to the first current source A1 and the first switch S1, the plurality of second delay unit arrays 402 correspond to the second current source A2, the second switch S2 and the third switch S3, when the first switch S1 is closed and the second switch S2 and the third switch S3 are opened, the first current source A1 provides a power supply current for each of the plurality of first delay unit arrays 401, and the sum of the currents in the plurality of first delay unit arrays 401 is I0; when the first switch S1 is opened and the second switch S2 and the third switch S3 are closed, the first current source A1 and the second current source A2 provide a power supply current for each of the plurality of second delay unit arrays 402, and the sum of the currents in the plurality of second delay unit arrays 402 is I0+I1.

[0086] Optionally, the plurality of first delay unit arrays 401 correspond to the first current source A1 and the plurality of first switches S1, each of the plurality of first delay unit arrays 401 corresponds to one of the plurality of first switches S1, the plurality of second delay unit arrays 402 correspond to the second current source A2, the plurality of second switches S2 and the plurality of third switches S3, each of the plurality of second delay unit arrays 402 corresponds to one of the plurality of second switches S2 and one of the plurality of third switches S3. The present application does not make specific limitations thereto.

[0087] For example, in FIG. 5 and the following embodiments, it is taken for example that the first delay unit array 401 includes one first delay unit array 401 and the second delay unit array 402 includes one second delay unit array 402.

[0088] In the working process, when the second switch S2 and the third switch S3 are closed and the first switch S1 is opened, the first delay unit array 401 does not work, the second delay unit array 402 works, and the first current source A1 and the second current source A2 provide a power supply current I0+I1 for the second delay unit array 402; when the second switch S2 and the third switch S3 are opened and the first switch S1 is closed, the first current source A1 provides a power supply current I0 for the first delay unit array 401, the first delay unit array 401 works, and the second delay unit array 402 does not work, and since I0 is less than I1, the power consumption of the first delay unit array 401 when working is less than that of the second delay unit array 402 when working.

[0089] In this embodiment, the first current source A1 and the second current source A2 provide a power supply current for the second delay unit array 402, that is, the second delay unit array 402 multiplexes the first current source A1, thereby improving the utilization rate of the first current source, and in the design stage, the size of the current in the second current source can be reduced, thereby reducing the area of the current source.

[0090] In a possible embodiment, the first delay cell array 401 includes at least two first differential delay cells coupled in series; and the second delay cell array 402 includes at least two second differential delay cells coupled in series. Similarly, each differential delay cell includes a first input end Vi+ and a second input end Vi- in differential, and a first output end Vo+ and a second output end Vo- in differential. The power consumption of the first differential delay cell is less than that of the second differential delay cell, and the phase noise of the first differential delay cell is greater than that of the second differential delay cell.

[0091] Among the at least two first differential delay cells or the at least two second differential delay cells, two adjacent differential delay cells can be coupled in phase, and the remaining differential delay cells are coupled in anti-phase; or two adjacent differential delay cells can be coupled in anti-phase, and the remaining differential delay cells are coupled in phase. The application does not make specific limitations on the comparison.

[0092] Since the frequency of the first delay cell array and the frequency of the second delay cell array can be the same or different, the following cases are introduced and explained.

[0093] In a possible embodiment, the frequency of the first delay cell array and the frequency of the second delay cell array are different.

[0094] At this time, the number of the at least two first differential delay cells in the first delay cell array and the number of the at least two second differential delay cells are the same, and the size of the at least two first differential delay cells in the first delay cell array and the size of the at least two second differential delay cells are the same. In this embodiment, by switching different switches, the ring oscillator works at different power consumptions, and the switching of different power consumptions is realized.

[0095] In a possible embodiment, the frequency of the first delay cell array and the frequency of the second delay cell array are the same.

[0096] At this time, the first delay cell array and the second delay cell array are different in at least one of the following: the number of the at least two first differential delay cells and the number of the at least two second differential delay cells, the size of the at least two first differential delay cells and the size of the at least two second differential delay cells. For example, the number of the at least two first differential delay cells and the number of the at least two second differential delay cells are different, and the size of the at least two first differential delay cells is the same as the size of the at least two second differential delay cells; or the number of the at least two first differential delay cells and the number of the at least two second differential delay cells are different, and the size of the at least two first differential delay cells is different from the size of the at least two second differential delay cells. Or, the number of the at least two first differential delay cells and the number of the at least two second differential delay cells are the same, and the size of the at least two first differential delay cells is different from the size of the at least two second differential delay cells.

[0097] In the above embodiment, when the first delay cell array and the second delay cell array have different power consumptions, at least one of the number and the size of the delay cells in the different delay cell arrays is different, so that the first delay cell array and the second delay cell array have the same frequency, and the switching of the same frequency and different power consumptions is realized.

[0098] In the following embodiments, the number of the at least two first differential delay cells and the number of the at least two second differential delay cells are the same, and the size of the at least two first differential delay cells is different from the size of the at least two second differential delay cells.

[0099] The specific structures of the first delay cell array 401 and the second delay cell array 402 will be described below in combination with FIGS. 6 and 7. In FIG. 6, the first delay cell array 401 and the second delay cell array 402 each include two differential delay cells as an example.

[0100] For example, as shown in FIG. 6, the first delay cell array 401 includes the first differential delay cell 11 and the first differential delay cell 12 coupled in series, the first input end Vi+ and the second input end Vi- of the first differential delay cell 11 are the first input end Vi+ and the second input end Vi- of the first delay cell array 401, the first output end Vo+ and the second output end Vo- of the first differential delay cell 12 are the first output end Vo+ and the second output end Vo- of the first delay cell array 401, the first output end Vo+ and the second output end Vo- of the first differential delay cell 11 are coupled to the second input end Vi- and the first input end Vi+ of the first differential delay cell 12 respectively, the first output end Vo+ and the second output end Vo- of the first differential delay cell 12 are coupled to the first input end Vi+ and the second input end Vi- of the first differential delay cell 11 respectively, the power supply end of the first differential delay cell 11 and the power supply end of the first differential delay cell 12 are coupled to the power supply end of the first delay cell array 401 respectively, and the voltage end of the first differential delay cell 11 and the voltage end of the first differential delay cell 12 are coupled to the voltage end of the first delay cell array 401 respectively, i.e., the voltage end of the first differential delay cell 11 and the voltage end of the first differential delay cell 12 are coupled to GND respectively.

[0101] In the example shown in FIG. 6, the first differential delay cell 11 and the first differential delay cell 12 are coupled in opposite phase.

[0102] In the example shown in FIG. 6, the first differential delay cell 11 and the first differential delay cell 12 are coupled in opposite phase.

[0103] In addition, the number of differential delay cells included in the first delay cell array 401 can be selected according to the requirements of the speed, power consumption and noise performance of the ring oscillator, and the embodiments of the present application do not make specific limitations.

[0104] Please continue to refer to FIG. 6, the second delay cell array 402 includes a second differential delay cell 21 and a second differential delay cell 22, the first input end Vi+ and the second input end Vi- of the second differential delay cell 21 as the first input end Vi+ and the second input end Vi- of the second delay cell array 402, the first output end Vo+ and the second output end Vo- of the second differential delay cell 22 as the first output end Vo+ and the second output end Vo- of the second delay cell array 402, the first output end Vo+ and the second output end Vo- of the second differential delay cell 21 are coupled with the second input end Vi- and the first input end Vi+ of the second differential delay cell 22 respectively, the first output end Vo+ and the second output end Vo- of the second differential delay cell 22 are coupled with the first input end Vi+ and the second input end Vi- of the second differential delay cell 21 respectively, the power supply end of the second differential delay cell 21 and the power supply end of the second differential delay cell 22 are coupled with the power supply end of the second delay cell array 402 respectively, the voltage end of the second differential delay cell 21 and the voltage end of the second differential delay cell 22 are coupled with the voltage end of the second delay cell array 402 respectively, that is, the voltage end of the second differential delay cell 21 and the voltage end of the second differential delay cell 22 are coupled with GND respectively,

[0105] Wherein, the second differential delay cell 21 and the second differential delay cell 22 are both high-performance delay cells. In FIG. 6, the second differential delay cell 21 and the second differential delay cell 22 are coupled in opposite phase, and the second differential delay cell 22 and the second differential delay cell 21 are coupled in the same phase as an example.

[0106] Furthermore, the structure of any two differential delay cells included in the second delay cell array 402 is the same, for example, the structure of the second differential delay cell 22 and the second differential delay cell 21 is the same.

[0107] In addition, the specific number of differential delay cells included in the second delay cell array 402 can be selected according to the requirements of the application on the speed, power consumption and noise performance of the ring oscillator, and the embodiments of the present application do not make specific limitations.

[0108] In practical application, the ring oscillator shown in Fig. 6 works as follows. Assuming that at a certain time T0, the first input end Vi+ and the second input end Vi- of the first differential delay unit 11 are positive differential signals (also referred to as high level), the first output end Vo+ and the second output end Vo- of the first differential delay unit 11 become negative differential signals (also referred to as low level) after a delay time ΔT (T = T0 + ΔT), the first output end Vo+ and the second output end Vo- of the first differential delay unit 12 become positive differential signals after a delay time ΔT (T = T0 + 2ΔT), and so on. After 4ΔT, the first output end Vo+ and the second output end Vo- of the first differential delay unit 11 become positive differential signals again, and the ring oscillator completes a cycle of oscillation.

[0109] wherein the positive differential signal refers to a voltage on the positive signal line (the first input end Vi+ or the first output end Vo+) being greater than a voltage on the negative signal line (the second input end Vi- or the second output end Vo-), and the negative differential signal refers to a voltage on the positive signal line being less than a voltage on the negative signal line (the second input end Vi-).

[0110] wherein the delay time of the differential delay unit with the same structure is the same for a signal. For example, the delay time of the first differential delay unit 11 and the first differential delay unit 12 is the same for a same signal, and the delay time of the second differential delay unit 21 and the second differential delay unit 22 is the same for a same signal.

[0111] Optionally, the differential delay unit can also be referred to as a differential inverter or an inverter. For example, assuming that the input differential signal of any differential delay unit is Vi+ and Vi-, the output differential signal Vo+ and Vo- of the differential delay unit can be represented as follows: Vo+ = Av(Vi+ - Vi-), Vo- = -Av(Vi+ - Vi-), wherein Av represents an amplification gain. Thus, when the gain Av of the differential delay unit is equal to 1, the differential delay unit can be regarded as an inverter without amplification function, and in this case, the differential delay unit can also be referred to as a differential inverter or an inverter.

[0112] In this embodiment, in the low-power consumption scenario, the first switch S1 is closed, the second switch S2 and the third switch S3 are opened, each differential delay unit (including the first differential delay unit 11 and the first differential delay unit 12) included in the first delay unit array 401 works, so that the first delay unit array 401 is in the working state, and the power consumption of the ring oscillator is reduced; in the high-performance scenario, the second switch S2 and the third switch S3 are closed, the first switch S1 is opened, each differential delay unit (including the second differential delay unit 21 and the second differential delay unit 22) included in the second delay unit array 402 works, so that the second delay unit array 402 is in the working state, the oscillation frequency of the ring oscillator is kept unchanged, the demand of the high-performance scenario is met, and the ring oscillator meets the demand of different scenarios.

[0113] In a possible embodiment, in combination with the above-mentioned FIG. 6, as shown in FIG. 7, the first delay unit array 401 further includes a first differential delay unit 13, which is coupled between the first differential delay unit 11 and the first differential delay unit 12. Specifically, the first output end Vo+ and the second output end Vo- of the first differential delay unit 11 are coupled with the second input end Vi- and the first input end Vi+ of the first differential delay unit 13 respectively, the first output end Vo+ and the second output end Vo- of the first differential delay unit 13 are coupled with the second input end Vi- and the first input end Vi+ of the first differential delay unit 12 respectively, the power supply end of the first differential delay unit 13 is coupled with the power supply end of the first delay unit array 401, and the voltage end of the first differential delay unit 13 is coupled with GND. The first differential delay unit 13 is a low-power consumption delay unit.

[0114] In the above embodiment, the first differential delay unit 13 is a low-power consumption delay unit. In a possible embodiment, the first differential delay unit 13 is a high-performance delay unit. In this embodiment, the structure of the first differential delay unit 13 is the same as that of the first differential delay unit 11. In FIG. 7, the first delay unit array 401 includes three first differential delay units, the first differential delay unit 12 and the first differential delay unit 11 are in-phase coupled, and the other first differential delay units are in anti-phase coupled.

[0115] Please continue to refer to FIG. 7, the second delay cell array 402 further comprises a second differential delay cell 23 coupled between the second differential delay cell 21 and the second differential delay cell 22. Specifically, the first output terminal Vo+ and the second output terminal Vo- of the second differential delay cell 21 are coupled with the second input terminal Vi- and the second input terminal Vi+ of the second differential delay cell 23 respectively, the first output terminal Vo+ and the second output terminal Vo- of the second differential delay cell 23 are coupled with the second input terminal Vi- and the first input terminal Vi+ of the second differential delay cell 22 respectively, the power terminal of the second differential delay cell 23 is coupled with the power terminal of the second delay cell array 402, the voltage terminal of the second differential delay cell 23 is coupled with GND, and the second differential delay cell 23 is a high-performance delay cell. Wherein, the structure of the second differential delay cell 23 is the same as that of the second differential delay cell 21.

[0116] For example, in FIG. 7, the first differential delay cell 12 and the first differential delay cell 11 are in-phase coupling, the rest of the differential delay cells are in anti-phase coupling, the second differential delay cell 22 and the second differential delay cell 21 are in-phase coupling, the rest of the differential delay cells are in anti-phase coupling, and the first delay cell array 401 and the second delay cell array 402 are in-phase coupling.

[0117] Optionally, among the at least two differential delay cells, one adjacent differential delay cell pair is in anti-phase coupling, and the rest of the differential delay cells are in-phase coupling.

[0118] For example, in combination with FIG. 7 described above, as shown in FIG. 8, the first delay cell array 401 comprises the first differential delay cell 11, the first differential delay cell 12 and the first differential delay cell 13 coupled in series, and the second delay cell array 402 comprises the second differential delay cell 21, the second differential delay cell 22 and the second differential delay cell 23 coupled in series. Wherein, the first differential delay cell 12 and the first differential delay cell 11 are in anti-phase coupling, the rest of the differential delay cells are in-phase coupling, the second differential delay cell 22 and the second differential delay cell 21 are in anti-phase coupling, the rest of the differential delay cells are in-phase coupling, and the first delay cell array 401 and the second delay cell array 402 are in anti-phase coupling.

[0119] In a possible embodiment, for any one of the first delay cell array 401 or the second delay cell array 402, the ring oscillator further comprises a fourth switch, a fifth switch, a sixth switch and a seventh switch corresponding to the delay cell array. The fourth switch is coupled between the first input end of the delay cell array and the first node P1, the fifth switch is coupled between the second input end of the delay cell array and the second node P2, the sixth switch is coupled between the second output end of the delay cell array and the first node P1, and the seventh switch is coupled between the first output end of the delay cell array and the second node P2; wherein the first node P1 and the second node P2 are nodes between the input end and the output end of the delay cell array.

[0120] Wherein each delay array has a corresponding fourth switch to seventh switch, for the convenience of understanding, the first delay cell array 401 corresponds to the fourth switch S14, the fifth switch S15, the sixth switch S16 and the seventh switch S17, and the second delay cell array 402 corresponds to the fourth switch S24, the fifth switch S25, the sixth switch S26 and the seventh switch S27.

[0121] In addition, when the delay cell arrays are coupled in phase, the first node P1 is any one of the nodes between the first input end and the first output end of the delay cell array, and the second node P2 is any one of the nodes between the second input end and the second output end of the delay cell array. When the delay cell arrays are coupled in anti-phase, the first node P1 is any one of the nodes between the first input end and the second output end of the delay cell array, and the second node P2 is any one of the nodes between the second input end and the first output end of the delay cell array. The present application does not make specific limitations thereon, and the following is described by taking the delay cell arrays coupled in phase as an example.

[0122] In a possible embodiment, in combination with FIG. 7, as shown in FIG. 9, the first delay cell array 401 further comprises a fourth switch S14, a fifth switch S15, a sixth switch S16 and a seventh switch S17.

[0123] The fourth switch S14 is coupled between the first input terminal Vi+ of the first delay cell array 401 and the first node P1, the fifth switch S15 is coupled between the second input terminal Vi- of the first delay cell array 401 and the second node P2, the sixth switch S16 is coupled between the second output terminal Vo- of the first delay cell array 401 and the second node P2, and the seventh switch S17 is coupled between the first output terminal Vo+ of the first delay cell array 401 and the first node P1. The first input terminal Vi+ and the second input terminal Vi- of the first differential delay cell 11 are coupled to the first input terminal Vi+ and the second input terminal Vi- of the first delay cell array 401 respectively, and the first output terminal Vo+ and the second output terminal Vo- of the first differential delay cell 12 are coupled to the first output terminal Vo+ and the second output terminal Vo- of the first delay cell array 401 respectively.

[0124] Please continue to refer to FIG. 9, the second delay cell array 402 further comprises a fourth switch S24, a fifth switch S25, a sixth switch S26 and a seventh switch S27.

[0125] The fourth switch S24 is coupled between the first input terminal Vi+ of the second delay cell array 402 and the first node P1, the fifth switch S25 is coupled between the second input terminal Vi- of the second delay cell array 402 and the second node P2, the sixth switch S26 is coupled between the second output terminal Vo- of the second delay cell array 402 and the first node P1, and the seventh switch S27 is coupled between the first output terminal Vo+ of the second delay cell array 402 and the second node P2. The first input terminal Vi+ and the second input terminal Vi- of the second differential delay cell 21 are coupled to the first input terminal Vi+ and the second input terminal Vi- of the second delay cell array 402 respectively, and the first output terminal Vo+ and the second output terminal Vo- of the second differential delay cell 22 are coupled to the first output terminal Vo+ and the second output terminal Vo- of the second delay cell array 402 respectively.

[0126] In the working process, when the first switch S1, the fourth switch S14, the fifth switch S15, the sixth switch S16 and the seventh switch S17 are closed, the second switch S2, the third switch S3, the fourth switch S24, the fifth switch S25, the sixth switch S26 and the seventh switch S27 are opened, the first delay cell array 401 is in the working state, and the second delay cell array 402 is not working. Alternatively, when the first switch S1, the fourth switch S14, the fifth switch S15, the sixth switch S16 and the seventh switch S17 are opened, the second switch S2, the third switch S3, the fourth switch S24, the fifth switch S25, the sixth switch S26 and the seventh switch S27 are closed, the second delay cell array 402 is in the working state, and the first delay cell array 401 is not working.

[0127] In this embodiment, by closing and opening different switches, the ring oscillator works at the same frequency with different power consumptions, so as to realize the frequency-invariant power consumption switching and meet the requirements of different scenarios.

[0128] In a possible embodiment, as shown in FIG. 10, the ring oscillator further includes a frequency tuning circuit 403 coupled between the input end of the first delay cell array 401 and the output end 402 of the first delay cell, in combination with FIG. 9. Specifically, the frequency tuning circuit 403 is coupled between the first node P1 and the second node P2.

[0129] The frequency tuning circuit 403 includes a first transistor M1 and a second transistor M2, the gate of the first transistor M1 and the gate of the second transistor are coupled with the second node P2 and the first node P1 respectively, one pole (such as the source) of the first transistor M1, the other pole (such as the drain) of the first transistor M1, the source of the second transistor M2 and the drain of the second transistor M2 are coupled with a third node P3 for receiving a power supply voltage. Each transistor can include a varactor diode.

[0130] In this embodiment, the frequency tuning circuit 403 adjusts the frequency of the ring oscillator based on the power supply voltage received by the third node P3, so that the ring oscillator meets different frequency requirements and improves the utilization rate of the ring oscillator.

[0131] FIG. 11 is a simulation circuit diagram of the first delay cell array 401 and the second delay cell array 402 in the ring oscillator shown in FIGS. 6 and 10, the first delay cell array 401 includes three first differential delay cells, which can be represented as 11 to 13 respectively, and the second delay cell array 402 includes three differential delay cells, which can be represented as 21 to 23 respectively. The first differential delay cell 11 and the first differential delay cell 12 are in-phase coupled, and the second differential delay cell 21 and the second differential delay cell 22 are in-phase coupled, and the rest of the differential delay cells are in anti-phase coupled, for example. The power supply end of each delay cell array is used to receive a current source supply current, and the power supply end is used to be coupled with GND.

[0132] The circuit shown in FIG. 11 is simulated, in the low-power mode, the first delay cell array 401 works and the second delay cell array 402 does not work, in the high-performance mode, the second delay cell array 402 works and the first delay cell array 401 does not work, and the simulation results are shown in Table 1:

[0133] Table 1

[0134] Wherein, the frequency is the oscillation frequency of the ring oscillator, the current is the power supply current provided by the first current source A1 and / or the second current source A2 for each delay cell array, the voltage is the power supply voltage received by the first current source A1 and the second current source A2, and PN@10K to PN@100M represent the power when measuring the phase noise of the ring oscillator.

[0135] As shown in Table 1, in the high performance mode, the first current source A1 and the second current source A2 provide the power supply current for the second delay cell array 402, the first current source A1 and the second current source A2 provide 1.8mA of power supply current for the second delay cell array 402, that is, the sum of the currents of the first current source A1 and the second current source A2 is 1.8mA, the first current source A1 and the second current source A2 respectively receive 1.52V of power supply voltage, and the phase noise of the ring oscillator measured at different measurement powers is different, and the greater the measurement power, the greater the phase noise of the ring oscillator. In the low power consumption mode, the first current source A1 provides the power supply current for the first delay cell array 401, the first current source A1 provides 0.8mA of power supply current for the first delay cell array 401, the first current source A1 receives 1.51V of power supply voltage, and the phase noise of the ring oscillator measured at different measurement powers is different, and the greater the measurement power, the greater the phase noise of the ring oscillator. However, under the same measurement power, the phase noise of the ring oscillator in the high performance mode is less than the phase noise of the ring oscillator in the low power consumption mode.

[0136] For example, FIG. 12 is a layout of a ring oscillator provided by an embodiment of the present application, which is located on a circuit board, and the ring oscillator includes a first delay cell array 401, a second delay cell array 402, a first current source A1, a second current source A2, and a frequency modulation circuit 403. The first delay cell array 401 and the second delay cell array 402 are placed side by side, wherein the first current source A1 and the second current source A2 are located at the upper end of the first delay cell array 401 and the second delay cell array 402, and the frequency modulation circuit 403 is located at the lower end of the first delay cell array 401 and the second delay cell array 402. The frequency modulation circuit 403 can include a varactor, which can also be referred to as a diode.

[0137] The ring oscillator provided in the embodiments of the present application comprises: a first delay unit array, a second delay unit array, a first current source, a second current source, a first switch and a second switch; wherein the frequency of the first delay unit array is the same as the frequency of the second delay unit array, and the current in the first current source is smaller than the current in the second current source. The output end of the first current source is coupled with the power supply end of the first delay unit array through the first switch, and the output end of the second current source is coupled with the power supply end of the second delay unit array through the second switch and the third switch. The input end of the first delay unit array and the output end of the first delay unit array are coupled, the input end of the second delay unit array and the output end of the second delay unit array are coupled, and the output end of the first delay unit array and the output end of the second delay unit array are coupled. When the second switch is closed and the first switch is opened, the second delay unit array works; when the second switch is opened and the first switch is closed, the first delay unit array works. The ring oscillator can switch different power consumptions by switching different switches, for example, in a low-power consumption scenario, the first switch is closed and the second switch is opened, so that the first delay unit array works, thereby reducing the power consumption of the ring oscillator; in a high-performance scenario, the second switch is closed and the first switch is opened, so that the second delay unit array works. Since the current in the first current source is smaller than the current in the second current source, the power consumption of the first delay unit array when working is smaller than the power consumption of the second delay unit array when working, and the phase noise of the first delay unit array is higher than the phase noise of the second delay unit array. While keeping the oscillation frequency of the ring oscillator unchanged, the demand of the high-performance (i.e. low phase noise) scenario is met, so that the ring oscillator meets the demand of different scenarios.

[0138] The embodiments of the present application also provide a phase-locked loop circuit, which can comprise a phase detector, a filter and a ring oscillator. The ring oscillator can be the ring oscillator provided in FIGS. 4 to 10. The embodiments of the present application also provide a communication device, which can comprise a phase-locked loop circuit. The phase-locked loop circuit can comprise a ring oscillator. The ring oscillator can be the ring oscillator provided in FIGS. 4 to 10.

[0139] In a possible embodiment, the communication device can comprise a radio frequency transceiver. The phase-locked loop circuit is integrated in the radio frequency transceiver, and the phase-locked loop circuit is used to provide a local carrier signal for the radio frequency transceiver. It should be noted that the related description of the ring oscillator can be referred to the related description of the ring oscillator provided above, and the embodiments of the present application will not be described herein again.

[0140] Finally, it should be noted that the above only describes specific embodiments of the present application, but the protection scope of the present application is not limited thereto, and any changes or replacements within the technical scope disclosed by the present application should be covered in the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A ring oscillator, characterized by, The ring oscillator comprises: a first delay cell array, a second delay cell array, a first current source, a second current source, a first switch and a second switch; wherein the current in the first current source is less than the current in the second current source; an output end of the first current source is coupled with a power supply end of the first delay cell array through the first switch, and an output end of the second current source is coupled with a power supply end of the second delay cell array through the second switch; an input end of the first delay cell array is coupled with an output end of the first delay cell array, and an input end of the second delay cell array is coupled with an output end of the second delay cell array; and the output end of the first delay cell array is coupled with the output end of the second delay cell array.

2. The ring oscillator of claim 1, wherein, The first delay cell array comprises at least two first differential delay cells coupled in series; and the second delay cell array comprises at least two second differential delay cells coupled in series.

3. The ring oscillator of claim 2, wherein, The first delay cell array and the second delay cell array are different in at least one of the following aspects: the number of the at least two first differential delay cells and the number of the at least two second differential delay cells are different, and the size of the at least two first differential delay cells and the size of the at least two second differential delay cells are different.

4. A ring oscillator according to claim 2 or 3, characterised in that, The power consumption of the first differential delay cell is less than the power consumption of the second differential delay cell, and the phase noise of the first differential delay cell is greater than the phase noise of the second differential delay cell.

5. The ring oscillator of any of claims 1-4, wherein, The ring oscillator further comprises: a third switch coupled between the output end of the first current source and the output end of the second current source.

6. The ring oscillator of any of claims 1-5, wherein, For any one of the first delay cell array or the second delay cell array, the input end of the delay cell array comprises differential first and second input ends, the output end of the delay cell array comprises differential first and second output ends, and the ring oscillator further comprises fourth, fifth, sixth and seventh switches corresponding to the delay cell array; the fourth switch is coupled between the first input end of the delay cell array and a first node, the fifth switch is coupled between the second input end of the delay cell array and a second node, the sixth switch is coupled between the second output end of the delay cell array and the first node, and the seventh switch is coupled between the first output end of the delay cell array and the second node; wherein the first node and the second node are nodes between the input end and the output end of the delay cell array.

7. The ring oscillator of any of claims 1-6, wherein, The ring oscillator comprises a plurality of the first delay cell arrays coupled in series, and the output end of the first current source is coupled with a power supply end of each of the plurality of the first delay cell arrays through the first switch. And / or, the ring oscillator comprises a plurality of the second delay cell arrays coupled in series, and an output terminal of the first current source and an output terminal of the second current source are coupled with a power terminal of each of the plurality of the second delay cell arrays through the second switch and the third switch, respectively.

8. The ring oscillator of any of claims 1-7, wherein, The ring oscillator further comprises a frequency modulation circuit coupled between an input terminal of the first delay cell array and an output terminal of the first delay cell.

9. A phase-locked loop circuit, characterized by comprising: The phase-locked loop circuit comprises a phase detector, a filter and a ring oscillator, the ring oscillator is the ring oscillator as claimed in any one of claims 1-8, the phase detector is used to obtain a phase difference signal and convert the phase difference signal into a voltage signal, the filter is used to filter the voltage signal, and the ring oscillator is used to output a local carrier signal according to the filtered voltage signal.

10. A communications device, characterized by The communication device comprises a processor and a phase-locked loop circuit, the phase-locked loop circuit is the phase-locked loop circuit as claimed in claim 9, and the processor is used to process the local carrier signal output by the phase-locked loop circuit.

11. The communication apparatus according to claim 10, wherein The communication device further comprises a radio frequency transceiver, and the phase-locked loop circuit is integrated in the radio frequency transceiver, and the phase-locked loop circuit is used to provide the radio frequency transceiver with a local carrier signal.

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