Co-packaging optics structures and manufacturing methods therefor

Abstract

The present invention relates to two co-packaging optics structures and manufacturing methods therefor. One structure comprises: a first redistribution layer; metal pillars arranged on a first surface of the first redistribution layer; a photonic integrated circuit arranged on a first surface of the metal pillars; a second redistribution layer arranged on the first surface of the first redistribution layer, the second redistribution layer being electrically connected to the first redistribution layer, and the height difference between a first surface of the second redistribution layer and the first surface of the metal pillars being equal to the thickness of the photonic integrated circuit; an electronic integrated circuit electrically connected to the photonic integrated circuit and the second redistribution layer; a first underfill filling the bottom of the photonic integrated circuit; a second underfill filling the bottom of the electronic integrated circuit; and solder balls electrically connected to the first redistribution layer. According to the co-packaging optics structures provided in the present invention, the second redistribution layer enables precise control of vertical height, thereby ensuring high-quality and high-density soldering between the photonic integrated circuit and the electronic integrated circuit.

Description

Photovoltaic sealing structure and its manufacturing method Technical Field

[0001] This invention relates to the field of semiconductor packaging technology, and in particular to optoelectronic encapsulation structures and their manufacturing methods. Background Technology

[0002] With the development of information technology, increasingly higher requirements have been placed on the transmission rate, latency, and energy efficiency of optical modules. As a result, the chip package optimization (CPO) structure, which encapsulates the photonic integrated circuit (PIC) and the electronic integrated circuit (EIC) in the same package, has been increasingly widely used.

[0003] Existing optoelectronic packaging solutions include Chip on Board (COB) integration and Through Silicon Via (TSV) integration. COB integration involves assembling discrete electrical and optical chips onto a substrate using wire bonding or flip-chip bonding, with interconnection achieved through substrate circuitry. This solution is inexpensive but suffers from poor high-speed interconnection performance between electrical and optical chips. TSV integration, on the other hand, involves creating through silicon vias within the optical or electrical chips and filling them with conductive material to achieve three-dimensional stacked packaging of the two chips. This results in high interconnection speeds but also drawbacks such as high cost and low yield.

[0004] Chinese patent CN115588618A discloses a three-dimensional stacked optoelectronic packaging structure and its fabrication method. Electrical interconnection between the optical chip and the substrate is achieved through a redistribution layer and bumps beneath the electrical chip, while the height difference of the bumps beneath the electrical chip overcomes the height difference between the upper surface of the optical chip and the substrate. However, growing bumps of different heights on the redistribution layer is technically challenging, and controlling the collapse of bumps of different heights during reflow is difficult to achieve at the same horizontal plane, thus posing significant difficulties for the bump bonding between the optical chip and the electrical chip.

[0005] Chinese patent CN219831453U discloses a chip system packaging structure. It addresses the height difference issue caused by optical chips by creating grooves on the substrate to accommodate them. However, the dimensional tolerances of the grooves on the substrate are large, and the optical chips exhibit vertical tilt during mounting. Furthermore, the mounting equipment struggles to accurately position the optical chips vertically, making it difficult to achieve flush mounting of the upper surface of the optical chip with the upper surface of the substrate. Summary of the Invention

[0006] To address some or all of the problems in the prior art, this invention provides two optoelectronic encapsulation structures and their manufacturing methods, respectively targeting thin and thick optical chips, ensuring that the first surface of the optical chip is flush with the first surface of the second redistribution layer or the second metal pillar, facilitating the subsequent bonding of electrical chips.

[0007] A first aspect of the present invention provides a first optoelectronic sealing structure, the structure comprising:

[0008] First wiring layer;

[0009] Metal pillars are arranged on the first surface of the first rewiring layer;

[0010] An optical chip is disposed on the first surface of the metal pillar;

[0011] A second wiring layer is disposed on the first surface of the first wiring layer. The second wiring layer is electrically connected to the first wiring layer, and the height difference between the first surface of the second wiring layer and the first surface of the metal pillar is equal to the thickness of the optical chip.

[0012] An electrical chip is electrically connected to the optical chip and the second wiring layer.

[0013] A first bottom filler adhesive is used to fill the bottom of the optical chip;

[0014] A second bottom filler adhesive is used to fill the bottom of the electrical chip;

[0015] The solder ball is electrically connected to the first wiring layer.

[0016] Optionally, the first redistribution layer includes multiple dielectric layers and multiple metal layers; and / or

[0017] The second redistribution layer includes multiple dielectric layers and multiple metal layers.

[0018] Optionally, the thickness of the optical chip is 0.01um-50um.

[0019] A second aspect of the present invention provides a method for manufacturing a first type of optoelectronic encapsulation structure, the method comprising the following steps:

[0020] Bonding adhesive is formed on the first surface of the carrier plate;

[0021] A first redistribution layer and a metal pillar are formed on the first surface of the bonding adhesive;

[0022] A second overlay layer is formed on the first surface of the first overlay layer, such that the height difference between the first surface of the second overlay layer and the first surface of the metal pillar is equal to the thickness of the optical chip.

[0023] The optical chip is arranged on the first surface of the metal pillar, and the bottom of the optical chip is filled with a first bottom filler adhesive;

[0024] An electrical chip is arranged on the first surface of the optical chip and the second redistribution layer, and a second underfill adhesive is filled at the bottom of the electrical chip.

[0025] Remove the carrier board, arrange solder balls on the second surface of the first redistribution layer, and cut it into an optoelectronic encapsulation structure.

[0026] A third aspect of the present invention provides a second optoelectronic sealing structure, the structure comprising:

[0027] First wiring layer;

[0028] A first metal pillar is disposed on the first surface of the first redistribution layer;

[0029] An optical chip is disposed on the first surface of the first metal pillar;

[0030] The second metal pillar is disposed on the first surface of the first redistribution layer. The second metal pillar is electrically connected to the first redistribution layer, and the height difference between the first surface of the second metal pillar and the first surface of the first metal pillar is equal to the thickness of the optical chip.

[0031] A molding layer is used to mold and encapsulate the second metal column;

[0032] An electrical chip is electrically connected to the optical chip and the second metal pillar;

[0033] A first bottom filler adhesive is used to fill the bottom of the optical chip;

[0034] A second bottom filler is applied to the bottom of the electrical chip.

[0035] The solder ball is electrically connected to the first wiring layer.

[0036] Optionally, the first redistribution layer includes multiple dielectric layers and multiple metal layers.

[0037] Optionally, the thickness of the optical chip is 50um-300um.

[0038] Optionally, the height of the first metal column is 3µm-20µm; and / or

[0039] The height of the second metal column is 50um-400um.

[0040] A fourth aspect of the present invention provides a method for manufacturing a second optoelectronic encapsulation structure, the method comprising the following steps:

[0041] Bonding adhesive is formed on the first surface of the carrier plate;

[0042] A first redistribution layer, a first metal pillar, and a second metal pillar are formed on the first surface of the bonding adhesive;

[0043] The second metal column is encapsulated and covered to form an encapsulation layer;

[0044] Thin the molding layer to expose the first surface of the second metal pillar, such that the height difference between the first surface of the second metal pillar and the first surface of the first metal pillar is equal to the thickness of the optical chip;

[0045] The optical chip is arranged on the first surface of the first metal pillar, and the bottom of the optical chip is filled with a first bottom filler adhesive;

[0046] An electrical chip is arranged on the first surface of the optical chip and the second metal pillar, and a second bottom filler is filled at the bottom of the electrical chip;

[0047] Remove the carrier board, arrange solder balls on the second surface of the first redistribution layer, and cut it into an optoelectronic encapsulation structure.

[0048] Optionally, the encapsulation is injection molded; and / or

[0049] The material of the encapsulation layer is epoxy resin.

[0050] Compared with the prior art, the present invention has the following advantages:

[0051] 1. The optoelectronic encapsulation structure provided by the present invention achieves high-speed interconnection between the two by F2F (face to face, which means the functional surfaces of the two chips are interconnected "face to face") welding between the active surfaces of the optical chip and the electrical chip.

[0052] 2. The optoelectronic encapsulation structure provided by the present invention can precisely control the vertical position of the optical chip after DA (Die Attach) by fabricating metal pillars on the first wiring layer, overcoming the vertical position deviation of the optical chip caused by uneven DA glue amount / machine performance limitations / chip tilt / DA glue curing shrinkage in the traditional DA process.

[0053] 3. The optoelectronic encapsulation structure provided by this invention allows for vertical interconnection between the electronic chip and the first wiring layer, depending on the thickness of the optical chip, by using a second wiring layer or a second metal pillar below the electronic chip. Both the second wiring layer and the second metal pillar allow for precise control of their vertical height, ensuring that their top pads are on the same horizontal plane as the pads on the upper surface of the optical chip, thereby guaranteeing high-quality, high-density soldering between the optical chip and the electronic chip.

[0054] 4. The optoelectronic encapsulation structure provided by this invention ensures that the photosensitive area of ​​the optical chip is not contaminated, and the photosensitive area faces upward, which facilitates the subsequent coupling of the optical chip and the optical fiber. It is suitable for various optical coupling forms such as vertical coupling and end-face coupling.

[0055] 5. This invention does not use expensive silicon adapters and through-silicon vias, further reducing packaging costs. Attached Figure Description

[0056] To further illustrate the above and other advantages and features of the various embodiments of the present invention, a more specific description of the various embodiments of the present invention will be presented with reference to the accompanying drawings. It is to be understood that these drawings depict only typical embodiments of the invention and are therefore not intended to limit its scope. In the drawings, identical or corresponding parts will be indicated by identical or similar reference numerals for clarity.

[0057] Figure 1 shows a schematic diagram of an embodiment of the first optoelectronic sealing structure of the present invention;

[0058] Figure 2 shows a flowchart of an embodiment of the manufacturing method of the first optoelectronic sealing structure of the present invention;

[0059] Figures 3a-3f show process cross-sectional schematic diagrams of an embodiment of the manufacturing method of the first optoelectronic sealing structure of the present invention;

[0060] Figure 4 shows a schematic diagram of an embodiment of the second photoelectric sealing structure of the present invention;

[0061] Figure 5 shows a flowchart illustrating an embodiment of the manufacturing method for the second optoelectronic encapsulation structure of the present invention; and

[0062] Figures 6a-6g show process cross-sectional schematic diagrams of an embodiment of the manufacturing method of the second optoelectronic sealing structure of the present invention. Detailed Implementation

[0063] In the following description, the invention is described with reference to various embodiments. However, those skilled in the art will recognize that the embodiments may be practiced without one or more specific details or with other alternatives and / or additional methods, materials, or components. In other instances, well-known structures, materials, or operations are not shown or described in detail so as not to obscure the inventive points of the invention. Similarly, for illustrative purposes, specific quantities, materials, and configurations are set forth to provide a comprehensive understanding of embodiments of the invention. However, the invention is not limited to these specific details. Furthermore, it should be understood that the embodiments shown in the drawings are illustrative representations and are not necessarily drawn to scale.

[0064] In this specification, references to "an embodiment" or "this embodiment" mean that a particular feature, structure, or characteristic described in connection with that embodiment is included in at least one embodiment of the invention. The phrase "in one embodiment" appearing throughout this specification does not necessarily refer to the same embodiment in all instances.

[0065] In this specification, unless otherwise specified, "arranged on," "arranged above," and "arranged on top of" do not exclude the possibility of an intermediate element between them. Furthermore, "arranged on or above" merely indicates the relative positional relationship between two components, and in certain cases, such as when the product orientation is reversed, it can also be converted to "arranged below or under," and vice versa.

[0066] In this specification, unless otherwise specified, "first surface" and "second surface" are used only to describe surfaces that distinguish the same component. Furthermore, "first," "second," and "third" are used only for distinguishing descriptions and do not imply differences in size.

[0067] In this specification, unless otherwise specified, the quantifiers “one” and “one” do not exclude scenarios involving multiple elements, and the quantifiers “multiple” and “more” refer to one or more elements.

[0068] It should be noted that the embodiments of the present invention describe the method steps in a specific order; however, this is only for illustrating the specific embodiment and not for limiting the order of the steps. On the contrary, in different embodiments of the present invention, the order of the steps can be adjusted according to actual needs.

[0069] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention.

[0070] This invention provides two optoelectronic encapsulation structures and their manufacturing methods, respectively targeting thin and thick optical chips, ensuring that the first surface of the optical chip is flush with the first surface of the second redistribution layer or the second metal pillar, facilitating the subsequent bonding of electrical chips.

[0071] For situations where the optical chip is relatively thin (the thickness of the optical chip is in the range of 0.01um-50um), the present invention provides a first optoelectronic encapsulation structure.

[0072] Figure 1 shows a schematic diagram of an embodiment of the first optoelectronic encapsulation structure of the present invention. As shown in Figure 1, the first optoelectronic encapsulation structure includes a first redistribution layer 103, a metal pillar 104, a second redistribution layer 105, an optical chip 106, a first bottom filler 107, an electrical chip 108, a second bottom filler 109, and solder balls 110.

[0073] As shown in Figure 1, metal pillars 104 are arranged on the first surface of the first wiring layer 103, and optical chip 106 is arranged on the first surface of metal pillars 104. The first wiring layer 103 is electrically connected to solder balls 110. Electrical chip 108 is electrically connected to the solder pads of optical chip 106 and the second wiring layer 105 through the bottom solder pads. The second wiring layer 105 is arranged on the first surface of the first wiring layer 103, and is electrically connected to the first wiring layer 103. The height difference between the first surface of the second wiring layer 105 and the first surface of the metal pillars 104 is equal to the thickness of optical chip 106, that is, the first surface of the second wiring layer 105 is flush with the first surface of optical chip 106, thereby ensuring high-quality, high-density soldering between the optical chip and the electrical chip. The metal pillars 104 mainly serve to fix the vertical position of optical chip 106 and may not be electrically connected to optical chip 106. The optoelectronic encapsulation structure provided by this invention ensures that the photosensitive area 1061 of the optical chip is not contaminated, and the photosensitive area faces upward, which facilitates the subsequent coupling of the optical chip and the optical fiber. It is suitable for various optical coupling forms such as vertical coupling and end-face coupling.

[0074] As shown in Figure 1, the first bottom filler 107 fills the bottom of the optical chip 106, that is, the area between the optical chip and the first multiple wiring layer; the second bottom filler 109 fills the bottom of the electrical chip 108, that is, the area between the electrical chip and the optical chip, the electrical chip and the second multiple wiring layer, and also the area between the electrical chip and the first multiple wiring layer. The materials of the first bottom filler 107 and the second bottom filler 109 can be selected as needed, and any insulating material is sufficient; no excessive restrictions are imposed here.

[0075] In one embodiment of the present invention, the first redistribution layer 103 may include multiple dielectric layers and multiple metal layers; and / or the second redistribution layer 105 may include multiple dielectric layers and multiple metal layers. In one embodiment of the present invention, the dielectric layer may be an organic material such as polyimide (PI), FR-4, or BT resin, or an inorganic material such as SiOx or SiNx. In one embodiment of the present invention, the metal material of the metal layer is preferably one or a combination of copper, tungsten, aluminum, copper alloy, and titanium.

[0076] In one embodiment of the present invention, the thickness of the optical chip 106 can be in the range of 0.01µm-50µm. In another embodiment, the optical chip 106 can be an active optical device chip or a passive optical device chip. The optical chip 106 can comprise multiple identical chips, multiple chips of the same type, or multiple chips of different types. In another embodiment, the electrical chip 108 can comprise multiple identical chips, multiple chips of the same type, or multiple chips of different types. These chips can be logic chips such as CPUs, DSPs, GPUs, and FPGAs; memory chips such as DRAM, Flash, and HBM; or other types of chips such as SoCs or sensors (such as MEMS sensors).

[0077] In one embodiment of the present invention, the material of the solder ball 110 can be a single-layer metal such as copper, nickel, tin, silver or other metals, or a composite metal.

[0078] Figure 2 shows a flowchart illustrating an embodiment of the manufacturing method of the first optoelectronic encapsulation structure of the present invention. Figures 3a-3f show cross-sectional schematic diagrams illustrating the process of an embodiment of the manufacturing method of the first optoelectronic encapsulation structure of the present invention.

[0079] The manufacturing method of the first photoelectric sealing structure of the present invention will be described below with reference to Figures 2 and 3a-3f.

[0080] First, a bonding adhesive is formed on the first surface of the carrier 101. As shown in FIG. 3a, the bonding adhesive 102 is located on the first surface of the carrier 101. In one embodiment of the present invention, the carrier 101 may be a metal carrier, glass, or a silicon wafer. In one embodiment of the present invention, the bonding adhesive 102 may be a bonding agent from TMAT, BSI, 3M, or DuPont.

[0081] Next, a first redistribution layer 103 and metal pillars 104 are formed on the first surface of the bonding adhesive 102, as shown in FIG3b. In one embodiment of the present invention, the first redistribution layer 103 includes multiple dielectric layers and multiple metal layers. To meet the requirements of high-density I / O interconnects, the first redistribution layer can be fabricated as a line width of 1µm or less. In one embodiment of the present invention, the first redistribution layer further includes an under-bump metallization (UBM) structure on the surface in contact with the bonding adhesive for subsequent electrical connection with solder balls. In one embodiment of the present invention, the material of the metal pillars 104 is preferably one or a combination of copper, tungsten, aluminum, copper alloy, and titanium.

[0082] Next, on the first surface of the first wiring layer 103, a second wiring layer 105 is formed in the region without metal pillars, such that the height difference between the first surface of the second wiring layer 105 and the first surface of the metal pillars 104 is equal to the thickness of the optical chip, as shown in FIG3c. In one embodiment of the present invention, the second wiring layer 105 includes multiple dielectric layers and multiple metal layers. To meet the requirements of high-density I / O interconnection, the second wiring layer can be fabricated as a line width of 1µm or less. In one embodiment of the present invention, the first surface of the second wiring layer also includes some pad structures for subsequent electrical connection with the electronic chip.

[0083] Next, the optical chip 106 is arranged on the first surface of the metal pillar, and a first underfill adhesive 107 is filled at the bottom of the optical chip, as shown in Figure 3d. The photosensitive area 1061 of the optical chip faces upward to facilitate subsequent coupling between the optical chip and the optical fiber.

[0084] Next, the electrical chip 108 is placed on the first surface of the optical chip 106 and the second wiring layer 105, and a second underfill adhesive 109 is filled at the bottom of the electrical chip 108, as shown in FIG3e. The electrical chip 108 is electrically connected to the pads of the optical chip 106 and the second wiring layer 105 through the bottom pads.

[0085] Finally, the carrier board is removed, solder balls 110 are arranged on the second surface of the first redistribution layer 103, and cut into an optoelectronic encapsulation structure, as shown in Figure 3f. In one embodiment of the present invention, the carrier board can be removed by mechanical separation, thermal sliding, or laser separation. In one embodiment of the present invention, the material of the solder balls 110 can be a single-layer metal such as copper, nickel, tin, silver, or other metals, or a composite metal.

[0086] For cases where the optical chip is relatively thick (the thickness of the optical chip is in the range of 50um-300um), the present invention provides a second optoelectronic encapsulation structure.

[0087] Figure 4 shows a schematic diagram of an embodiment of the second optoelectronic encapsulation structure of the present invention. As shown in Figure 4, the second optoelectronic encapsulation structure includes a first redistribution layer 203, a first metal pillar 204, a second metal pillar 205, a molding compound 206, an optical chip 207, a first bottom filler 208, an electrical chip 209, a second bottom filler 210, and solder balls 211.

[0088] As shown in Figure 4, a first metal pillar 204 is disposed on the first surface of the first redistribution layer 203, and an optical chip 207 is disposed on the first surface of the first metal pillar 204. The first redistribution layer 203 is electrically connected to solder balls 211. An electrical chip 209 is electrically connected to the solder pads of the optical chip 207 and the second metal pillar 205 through its bottom solder pads. The second metal pillar 205 is disposed on the first surface of the first redistribution layer 203, and is electrically connected to the first redistribution layer 203. The height difference between the first surface of the second metal pillar 205 and the first surface of the first metal pillar 204 is equal to the thickness of the optical chip 207, that is, the first surface of the second metal pillar 205 is flush with the first surface of the optical chip 207, thereby ensuring high-quality, high-density soldering between the optical chip and the electrical chip. The first metal pillar 204 mainly serves to fix the vertical position of the optical chip 207 and may not be electrically connected to the optical chip 207. The optoelectronic encapsulation structure provided by this invention ensures that the photosensitive area 2071 of the optical chip faces upward, which facilitates the subsequent coupling of the optical chip and the optical fiber. It is suitable for various optical coupling forms such as vertical coupling and end-face coupling.

[0089] As shown in Figure 4, the first bottom filler 208 fills the bottom of the optical chip 207, that is, the area between the optical chip and the first redistribution layer; the second bottom filler 210 fills the bottom of the electrical chip 209, that is, the area between the electrical chip and the optical chip, the electrical chip and the molding compound, and also the area between the electrical chip and the first redistribution layer. The materials of the first bottom filler 208 and the second bottom filler 210 can be selected as needed, as long as they are insulating materials, and no excessive restrictions are imposed here.

[0090] In one embodiment of the present invention, the first redistribution layer 203 may include multiple dielectric layers and multiple metal layers. In one embodiment of the present invention, the dielectric layer may be an organic material such as polyimide (PI), FR-4, or BT resin, or an inorganic material such as SiOx or SiNx. In one embodiment of the present invention, the metal material of the metal layer is preferably one or a combination of copper, tungsten, aluminum, copper alloys, and titanium.

[0091] In one embodiment of the present invention, the thickness of the optical chip 207 can be in the range of 50µm-300µm. In another embodiment, the optical chip 207 can be an active optical device chip or a passive optical device chip. The optical chip 207 can comprise multiple identical chips, multiple chips of the same type, or multiple chips of different types. In another embodiment, the electrical chip 209 can comprise multiple identical chips, multiple chips of the same type, or multiple chips of different types. These chips can be logic chips such as CPUs, DSPs, GPUs, and FPGAs; memory chips such as DRAM, Flash, and HBM; or other types of chips such as SoCs or sensors (such as MEMS sensors).

[0092] In one embodiment of the present invention, the height of the first metal column 204 can be 3µm-20µm; and / or the height of the second metal column 205 can be 50µm-400µm. In one embodiment of the present invention, the materials of the first metal column 204 and the second metal column 205 are preferably one or a combination of copper, tungsten, aluminum, copper alloy, and titanium.

[0093] In one embodiment of the present invention, the material of the solder ball 211 can be a single-layer metal such as copper, nickel, tin, silver or other metals, or a composite metal.

[0094] Figure 5 shows a flowchart illustrating an embodiment of the manufacturing method of the second optoelectronic encapsulation structure of the present invention. Figures 6a-6g show cross-sectional schematic diagrams illustrating the process of an embodiment of the manufacturing method of the second optoelectronic encapsulation structure of the present invention.

[0095] The manufacturing method of the second photoelectric sealing structure of the present invention will be described below with reference to Figures 5 and 6a-6g.

[0096] First, a bonding adhesive is formed on the first surface of the carrier 201. As shown in FIG6a, the bonding adhesive 202 is located on the first surface of the carrier 201. In one embodiment of the present invention, the carrier 201 may be a metal carrier, glass, or a silicon wafer. In one embodiment of the present invention, the bonding adhesive 202 may be a bonding agent from TMAT, BSI, 3M, or DuPont.

[0097] Next, a first redistribution layer 203, a first metal pillar 204, and a second metal pillar 205 are formed on the first surface of the bonding adhesive 202, as shown in FIG6b. In one embodiment of the present invention, the first redistribution layer 203 includes multiple dielectric layers and multiple metal layers. To meet the requirements of high-density I / O interconnection, the first redistribution layer can be fabricated with a linewidth of 1µm or less. In one embodiment of the present invention, the first redistribution layer further includes an under-bump metallization (UBM) structure on the surface in contact with the bonding adhesive for subsequent electrical connection with solder balls. In one embodiment of the present invention, the height of the first metal pillar 204 can be 3µm-20µm; and / or the height of the second metal pillar 205 can be 50µm-400µm. In one embodiment of the present invention, the materials of the first metal pillar 204 and the second metal pillar 205 are preferably one or a combination of copper, tungsten, aluminum, copper alloy, and titanium.

[0098] Next, the second metal pillar 205 is encapsulated and covered to form an encapsulation layer 206, as shown in Figure 6c. In one embodiment of the present invention, the encapsulation can be selectively performed using a mold, i.e., only the area of ​​the second metal pillar 205 is encapsulated; the encapsulation can be injection molded; and / or the material of the encapsulation layer 206 can be epoxy resin.

[0099] Next, the molding layer 206 is thinned to expose the first surface of the second metal pillar 205, such that the height difference between the first surface of the second metal pillar 205 and the first surface of the first metal pillar 204 is equal to the thickness of the optical chip, as shown in Figure 6d.

[0100] Next, the optical chip 207 is placed on the first surface of the first metal pillar 204, and the bottom of the optical chip is filled with a first underfill adhesive 208, as shown in Figure 6e. The photosensitive area 2071 of the optical chip faces upward to facilitate subsequent coupling between the optical chip and the optical fiber.

[0101] Next, the electrical chip 209 is placed on the first surface of the optical chip 207 and the second metal pillar 205, and a second underfill adhesive 210 is filled at the bottom of the electrical chip, as shown in Figure 6f. The electrical chip 209 is electrically connected to the pads of the optical chip 207 and the second metal pillar 205 through the bottom pads.

[0102] Finally, the carrier board is removed, solder balls 211 are arranged on the second surface of the first redistribution layer 203, and cut into an optoelectronic encapsulation structure, as shown in Figure 6g. In one embodiment of the present invention, the carrier board can be removed by mechanical separation, thermal sliding, or laser separation. In one embodiment of the present invention, the material of the solder balls 211 can be a single-layer metal such as copper, nickel, tin, silver, or other metals, or a composite metal.

[0103] The optoelectronic encapsulation structure provided by this invention allows for precise vertical height control of either the second redistribution layer or the second metal pillar, ensuring that the top pads are on the same horizontal plane as the pads on the upper surface of the optical chip. This guarantees high-quality, high-density welding between the optical chip and the electrical chip. The welding between the active surfaces of the optical chip and the electrical chip enables high-speed interconnection of the two via the shortest signal path. With the photosensitive area of ​​the optical chip facing upwards, it facilitates subsequent coupling between the optical chip and the optical fiber, making it suitable for various optical coupling methods such as vertical coupling and end-face coupling.

[0104] Although various embodiments of the present invention have been described above, it should be understood that they are presented by way of example only and not as limitations. It will be apparent to those skilled in the art that various combinations, modifications, and alterations can be made without departing from the spirit and scope of the invention. Therefore, the breadth and scope of the invention disclosed herein should not be limited to the exemplary embodiments disclosed above, but should be defined only according to the technical solutions of the invention and their equivalents.

Claims

1. A photoelectric hermetic structure, characterized by, Comprising: a first redistribution layer; a metal post disposed on a first surface of the first redistribution layer; an optical chip disposed on a first surface of the metal post; a second redistribution layer disposed on a first surface of the first redistribution layer, the second redistribution layer electrically connected with the first redistribution layer, and a height difference between a first surface of the second redistribution layer and the first surface of the metal post is equal to a thickness of the optical chip; an electrical chip electrically connected with the optical chip and the second redistribution layer; a first underfilling glue filling a bottom of the optical chip; a second underfilling glue filling a bottom of the electrical chip; a solder ball electrically connected with the first redistribution layer. 2.The optoelectronic hybrid package structure of claim 1, wherein: the first redistribution layer comprises a plurality of dielectric layers and a plurality of metal layers; and / or the second redistribution layer comprises a plurality of dielectric layers and a plurality of metal layers. 3.The optoelectronic hybrid package structure of claim 1, wherein: the thickness of the optical chip is 0.01um-50um.

4. A method of manufacturing the opto-electric hermetic structure according to any one of claims 1 to 3, characterized in that, Comprising the steps of: forming a bonding glue on a first surface of a carrier board; forming a first redistribution layer and a metal post on a first surface of the bonding glue; forming a second redistribution layer on a first surface of the first redistribution layer, such that a height difference between a first surface of the second redistribution layer and the first surface of the metal post is equal to a thickness of the optical chip; disposing an optical chip on a first surface of the metal post and filling a first underfilling glue at a bottom of the optical chip; disposing an electrical chip on a first surface of the optical chip and the second redistribution layer and filling a second underfilling glue at a bottom of the electrical chip; removing the carrier board, disposing a solder ball on a second surface of the first redistribution layer, and cutting into an optoelectronic hybrid package structure.

5. A photoelectric hermetic structure, characterized by, Comprising: a first redistribution layer; a first metal post disposed on a first surface of the first redistribution layer; an optical chip disposed on a first surface of the first metal post; a second metal post disposed on a first surface of the first redistribution layer, the second metal post electrically connected with the first redistribution layer, and a height difference between a first surface of the second metal post and the first surface of the first metal post is equal to a thickness of the optical chip; a plastic encapsulation layer encapsulating and covering the second metal post; an electrical chip electrically connected with the optical chip and the second metal post; a first underfilling glue filling a bottom of the optical chip; a second underfilling glue filling a bottom of the electrical chip; a solder ball electrically connected with the first redistribution layer. 6.The optoelectronic hybrid package structure of claim 5, wherein: the first redistribution layer comprises a plurality of dielectric layers and a plurality of metal layers. 7.The optoelectronic hybrid package structure of claim 5, wherein: the thickness of the optical chip is 50um-300um. 8.The optoelectronic hybrid package structure of claim 5, wherein: a height of the first metal post is 3um-20um; and / or a height of the second metal post is 50um-400um.

9. A method of manufacturing a photoelectric hermetic structure according to any one of claims 5 to 8, characterized by, Comprising the steps of: forming a bonding glue on a first surface of a carrier board; forming a first redistribution layer, a first metal pillar and a second metal pillar on the first surface of the bonding glue; encapsulating the second metal pillar to form an encapsulation layer; thinning the encapsulation layer to expose a first surface of the second metal pillar, so that a height difference between the first surface of the second metal pillar and the first surface of the first metal pillar is equal to a thickness of an optical chip; arranging the optical chip on the first surface of the first metal pillar and filling a first underfill glue at a bottom of the optical chip; arranging an electrical chip on the optical chip and the first surface of the second metal pillar and filling a second underfill glue at a bottom of the electrical chip; removing the carrier board, arranging solder balls on a second surface of the first redistribution layer, and cutting into an optoelectronic package structure.

10. The method of claim 9, wherein the encapsulation is injection molding; and / or the material of the encapsulation layer is epoxy resin. ​ ​

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