Printed wiring board

Abstract

A printed wiring board 100 comprises a dielectric layer 40 and a conductor pattern 50. The conductor pattern 50 has a first signal pattern 51 and a second signal pattern 52 that form a pair of differential signal lines, and a first land 53 and a second land 54. The first signal pattern 51 and the second signal pattern 52 each extend along a first direction DR1 in a plan view. The first signal pattern 51 and the second signal pattern 52 are arranged at an interval along a second direction DR2 perpendicular to the first direction DR1 in a plan view. The first land 53 and the second land 54 are respectively connected to an end of the first signal pattern 51 in the first direction DR1 and an end of the second signal pattern 52 in the first direction DR1. In the second direction DR2, the distance D2 between a center position of the first land 53 and a center position of the second land 54 is larger than the distance D1 between a center position of the first signal pattern 51 and a center position of the second signal pattern 52.

Description

printed wiring board

[0001] The present disclosure relates to a printed wiring board. This application claims priority to Japanese Patent Application No. 2024-116052, filed on July 19, 2024. The entire contents of the Japanese patent application are incorporated herein by reference.

[0002] Japanese Patent Laid-Open Publication No. 2022-151716 (Patent Document 1) describes a printed wiring board including a first dielectric layer, a first signal line and a second signal line disposed on the first dielectric layer, and a second dielectric layer covering the first signal line and the second signal line.

[0003] Japanese Patent Application Laid-Open No. 2022-151716

[0004] The printed wiring board of the present disclosure includes a dielectric layer and a conductor pattern disposed on the dielectric layer. The conductor pattern includes first and second signal patterns that form a pair of differential signal lines, and first and second lands. Each of the first and second signal patterns extends along a first direction in a plan view. The first and second signal patterns are arranged at intervals along a second direction perpendicular to the first direction in a plan view. The first and second lands are connected to an end of the first signal pattern in the first direction and an end of the second signal pattern in the first direction, respectively. In the second direction, the distance between the center of the first land and the center of the second land is greater than the distance between the center of the first signal pattern and the center of the second signal pattern.

[0005] FIG. 1 is a first plan view of printed wiring board 100. FIG. 2 is a second plan view of printed wiring board 100. FIG. 3 is a cross-sectional view of printed wiring board 100. FIG. 4A is a plan view of modified example 1 of printed wiring board 100. FIG. 4B is a plan view of modified example 2 of printed wiring board 100. FIG. 5 is a plan view of modified example 3 of printed wiring board 100. FIG. 6 is a manufacturing process diagram of printed wiring board 100. FIG. 7 is a cross-sectional view illustrating preparation step S1. FIG. 8 is a cross-sectional view illustrating etching step S2. FIG. 9 is a cross-sectional view illustrating dielectric layer attachment step S3. FIG. 10 is a cross-sectional view illustrating etching step S4. FIG. 11 is a cross-sectional view illustrating hole drilling step S5. FIG. 12 is a plan view of printed wiring board 200. FIG. 13 is a simulation result showing the relationship between the frequency of signals flowing through signal patterns 51 and 52 and the return loss in samples 1 to 3.

[0006] [Problem to be Solved by the Present Disclosure] In the printed wiring board described in Patent Document 1, it is conceivable to arrange the third signal line and the fourth signal line on the second dielectric layer and connect the third signal line and the fourth signal line to the first signal line and the second signal line, respectively. However, in this case, if the pitch between the third signal line and the fourth signal line (between the first signal line and the second signal line) is reduced, there is a risk that the reflection characteristics at the connection portion between the first signal line and the third signal line (the connection portion between the second signal line and the fourth signal line) will deteriorate.

[0007] The present disclosure has been made in consideration of the above-described problems of the conventional art. More specifically, the present disclosure provides a printed wiring board capable of improving the reflection characteristics between signal patterns on different layers.

[0008] [Advantages of the Present Disclosure] According to the printed wiring board of the present disclosure, it is possible to improve the reflection characteristics between signal patterns on different layers.

[0009] [Description of Embodiments of the Present Disclosure] First, embodiments of the present disclosure will be listed and described.

[0010] (1) A printed wiring board according to an embodiment includes a dielectric layer and a conductor pattern disposed on the dielectric layer. The conductor pattern includes a first signal pattern and a second signal pattern that form a pair of differential signal lines, and a first land and a second land. Each of the first signal pattern and the second signal pattern extends along a first direction in a plan view. The first signal pattern and the second signal pattern are arranged at intervals along a second direction perpendicular to the first direction in a plan view. The first land and the second land are connected to an end of the first signal pattern in the first direction and an end of the second signal pattern in the first direction, respectively. In the second direction, the distance between the center of the first land and the center of the second land is greater than the distance between the center of the first signal pattern and the center of the second signal pattern. The printed wiring board according to (1) above can improve the reflection characteristics between signal patterns on different layers.

[0011] (2) In the printed wiring board of (1) above, the width of the first land may be larger than the width of the first signal pattern in the second direction, and the width of the second land may be larger than the width of the second signal pattern.

[0012] (3) In the printed wiring board of (1) or (2) above, the distance between the first land and the second land in the second direction may be 0.5 to 1.5 times the distance between the first signal pattern and the second signal pattern.

[0013] (4) In the printed wiring boards of (1) to (3) above, the conductor pattern may further include a ground pattern. The ground pattern may surround the first signal pattern, the second signal pattern, the first land, and the second land in a planar view. In a planar view, the minimum value of the spacing between the first land and the ground pattern may be 0.5 to 1.5 times the minimum value of the spacing between the first signal pattern and the ground pattern. In a planar view, the minimum value of the spacing between the second land and the ground pattern may be 0.5 to 1.5 times the minimum value of the spacing between the second signal pattern and the ground pattern.

[0014] (5) In the printed wiring boards of (1) to (4) above, the dielectric layer may have a relative dielectric constant of 2.0 or more and a dielectric loss tangent of 0.01 or less.

[0015] (6) In the printed wiring boards of (1) to (5) above, the center position of the first land may be farther from the second signal pattern in the second direction than the center position of the first signal pattern.

[0016] (7) In the printed wiring boards of (1) to (6) above, the center position of the second land may be farther from the first signal pattern in the second direction than the center position of the second signal pattern.

[0017] (8) In the printed wiring boards of (1) to (7) above, the distance between the center of the first land and the center of the second land in the second direction may be 500 μm or less. The spacing between the first land and the second land in the second direction may be 100 μm or more. The thickness of the conductor pattern may be 10 μm or more.

[0018] [Details of the embodiment of the present disclosure] The details of the embodiment of the present disclosure will be described with reference to the drawings. In the following drawings, the same or corresponding parts are designated by the same reference numerals, and redundant description will not be repeated. The printed wiring board according to the embodiment is referred to as a printed wiring board 100.

[0019] FIG. 1 is a first plan view of the printed wiring board 100. FIG. 2 is a second plan view of the printed wiring board 100. In FIG. 2, the dielectric layer 40 and the conductor pattern 50 are omitted. FIG. 3 is a cross-sectional view of the printed wiring board 100. Note that FIG. 3 shows a cross-section of the printed wiring board 100 perpendicular to the second direction DR2. As shown in FIGS. 1 to 3, the printed wiring board 100 has a dielectric layer 10, a conductor pattern 20, a conductor pattern 30, a dielectric layer 40, and a conductor pattern 50.

[0020] Viewing printed wiring board 100 along the normal direction of main surface 40 a is referred to as a planar view. One direction in the planar view is referred to as a first direction DR1, and a direction perpendicular to first direction DR1 in the planar view is referred to as a second direction DR2. A direction perpendicular to first direction DR1 and second direction DR2 is referred to as a third direction DR3.

[0021] The dielectric layer 10 has a principal surface 10a and a principal surface 10b. The principal surface 10b is the surface opposite to the principal surface 10a. The principal surfaces 10a and 10b are end surfaces in the thickness direction (third direction DR3) of the dielectric layer 10. The constituent material of the dielectric layer 10 is, for example, a fluororesin.

[0022] The conductor pattern 20 is disposed on the main surface 10a. The conductor pattern 20 includes signal patterns 21 and 22, lands 23 and 24, and a ground pattern 25. The conductor pattern 20 is made of, for example, copper or a copper alloy.

[0023] The signal patterns 21 and 22 extend along a first direction DR1 in a plan view. The signal patterns 21 and 22 are arranged at intervals along a second direction DR2 in a plan view. The signal patterns 21 and 22 form a pair of differential signal lines.

[0024] The lands 23 and 24 are connected to the ends of the signal pattern 21 in the first direction DR1 and the ends of the signal pattern 22 in the first direction DR1, respectively. The lands 23 and 24 are arranged at intervals along the second direction DR2 in a plan view. The ground pattern 25 surrounds the signal pattern 21, the signal pattern 22, the lands 23, and the lands 24 at intervals in a plan view. A ground potential is applied to the ground pattern 25.

[0025] The conductor pattern 30 is disposed on the main surface 10b. The conductor pattern 30 is made of, for example, copper or a copper alloy. The conductor pattern 30 has a ground pattern 31. A ground potential is applied to the conductor pattern 30 (ground pattern 31).

[0026] The dielectric layer 40 is disposed on the dielectric layer 10 so as to cover the conductor pattern 20. The dielectric layer 40 has a main surface 40a and a main surface 40b. The main surface 40b faces the dielectric layer 10 and is the surface opposite to the main surface 40a. The main surfaces 40a and 40b are end surfaces of the dielectric layer 40 in the thickness direction (third direction DR3). The constituent material of the dielectric layer 40 is, for example, a fluororesin.

[0027] The dielectric constant of the dielectric layer 40 is, for example, 2.0 or more. The dielectric constant of the dielectric layer 40 may be 2.2 or more. The dielectric loss tangent of the dielectric layer 40 is, for example, 0.01 or less. The dielectric loss tangent of the dielectric layer 40 may be 0.003 or less. The dielectric constant of the dielectric layer 40 is measured by a split cylinder method or a phase difference method. The dielectric loss tangent of the dielectric layer 40 is measured by a split cylinder method or a phase difference method.

[0028] The conductor pattern 50 is disposed on the main surface 40a. The conductor pattern 50 includes signal patterns 51 and 52, lands 53 and 54, and a ground pattern 55. The conductor pattern 50 is made of, for example, copper or a copper alloy. The thickness of the conductor pattern 50 is defined as thickness T. The thickness T is, for example, 10 μm or more. The thickness T may be 12 μm or more.

[0029] The signal patterns 51 and 52 extend along a first direction DR1 in a plan view. The signal patterns 51 and 52 are arranged at intervals along a second direction DR2 in a plan view. The signal patterns 51 and 52 form a pair of differential signal lines.

[0030] The land 53 and the land 54 are connected to an end of the signal pattern 51 in the first direction DR1 and an end of the signal pattern 52 in the first direction DR1, respectively. The land 53 and the land 54 are arranged at intervals along the second direction DR2 in a plan view.

[0031] In the second direction DR2, the width of the land 53 is greater than the width of the signal pattern 51. In the second direction DR2, the width of the land 54 is greater than the width of the signal pattern 52. In a plan view, the lands 53 and 54 overlap with the lands 23 and 24, respectively. In a plan view, the land 23 may be located inside the outer periphery of the land 53, and the land 24 may be located inside the outer periphery of the land 54.

[0032] In the second direction DR2, the distance between the center position of the signal pattern 51 and the center position of the signal pattern 52 is defined as distance D1. In the second direction DR2, the distance between the center position of the land 53 and the center position of the land 54 is defined as distance D2. Distance D2 is greater than distance D1. From another perspective, in the second direction DR2, the center position of the land 53 is offset from the center position of the signal pattern 51 so as to be away from the signal pattern 52, and the center position of the land 54 is offset from the center position of the signal pattern 52 so as to be away from the signal pattern 51. Distance D2 is, for example, two times or less of distance D1. Distance D2 is, for example, 500 μm or less. Distance D2 may also be 450 μm or less.

[0033] In the second direction DR2, the distance between the signal patterns 51 and 52 is defined as distance SP1, and the distance between the lands 53 and 54 is defined as distance SP2. The distance SP2 is 0.5 to 1.5 times the distance SP1. The distance SP2 is, for example, 100 μm or more.

[0034] In a plan view, the ground pattern 55 surrounds, at intervals, the signal pattern 51, the signal pattern 52, the land 53, and the land 54. A ground potential is applied to the ground pattern 55.

[0035] A through hole 60 is formed in the land 53 and the dielectric layer 40. The through hole 60 penetrates the land 53 and the dielectric layer 40 along the third direction DR3. The land 23 is exposed from the through hole 60. A through hole 61 is formed in the land 54 and the dielectric layer 40. The through hole 61 penetrates the land 54 and the dielectric layer 40 along the third direction DR3. The land 24 is exposed from the through hole 61.

[0036] A conductor layer 62 is disposed on the lands 23 exposed from the through hole 60, on the inner wall surface of the through hole 60, and on the lands 53 around the through hole 60. A conductor layer 63 is disposed on the lands 24 exposed from the through hole 61, on the inner wall surface of the through hole 61, and on the lands 54 around the through hole 61. The conductor layers 62 and 63 are made of, for example, copper or a copper alloy. The conductor layer 62 electrically connects the signal pattern 51 to the signal pattern 21. The conductor layer 63 electrically connects the signal pattern 52 to the signal pattern 22.

[0037] 4A is a plan view of Modification 1 of printed wiring board 100. As shown in Fig. 4A, in the second direction DR2, the center position of land 53 is offset from the center position of signal pattern 51 so as to be away from signal pattern 52, while the center position of land 54 does not have to be offset from the center position of signal pattern 52 so as to be away from signal pattern 51.

[0038] 4B is a plan view of Modification 2 of the printed wiring board 100. As shown in Fig. 4B , in the second direction DR2, the center position of the land 53 is not offset from the center position of the signal pattern 51 so as to be away from the signal pattern 52, while the center position of the land 54 may be offset from the center position of the signal pattern 52 so as to be away from the signal pattern 51. In other words, in the printed wiring board 100, it is only necessary that the distance D2 is greater than the distance D1, and it is not essential that both the land 53 and the land 54 are offset in the second direction DR2.

[0039] 5 is a plan view of modified example 3 of printed wiring board 100. As shown in Fig. 5, the minimum value of the spacing between signal pattern 51 and ground pattern 55 is set to spacing SP3, and the minimum value of the spacing between signal pattern 52 and ground pattern 55 is set to spacing SP4. Furthermore, the minimum value of the spacing between land 53 and ground pattern 55 is set to spacing SP5, and the minimum value of the spacing between land 54 and ground pattern 55 is set to spacing SP6.

[0040] A notch 55a and a notch 55b may be formed in the ground pattern 25 around the lands 53 and 54. As a result, the interval SP5 may be 0.5 to 1.5 times the interval SP3, and the interval SP6 may be 0.5 to 1.5 times the interval SP4.

[0041] (Method of Manufacturing Printed Wiring Board 100) A method of manufacturing the printed wiring board 100 will be described below.

[0042] 6 is a manufacturing process diagram of the printed wiring board 100. As shown in Fig. 6, the manufacturing method of the printed wiring board 100 includes a preparation step S1, an etching step S2, a dielectric layer attachment step S3, an etching step S4, a hole drilling step S5, and a plating step S6.

[0043] 7 is a cross-sectional view illustrating the preparation step S1. As shown in FIG. 7, in the preparation step S1, a dielectric layer 10 is prepared. In the dielectric layer 10 prepared in the preparation step S1, a conductor layer 26 is disposed on the main surface 10a, and a conductor layer 32 is disposed on the main surface 10b. After the preparation step S1, an etching step S2 is performed.

[0044] FIG. 8 is a cross-sectional view illustrating the etching step S2. As shown in FIG. 8, in the etching step S2, the conductor layer 26 is patterned by etching to form the conductor pattern 20. Note that the conductor layer 32 is not etched and remains as is to form the conductor pattern 30. In the etching step S2, first, a resist pattern is formed on the conductor layer 26. The resist pattern is formed by, for example, applying a dry film resist to the conductor layer 26 and then exposing and developing the applied dry film resist. Second, the conductor layer 26 is etched using the resist pattern as a mask. After the etching step S2, a dielectric layer application step S3 is performed.

[0045] 9 is a cross-sectional view illustrating the dielectric layer attachment step S3. As shown in FIG. 9, in the dielectric layer attachment step S3, a dielectric layer 40 is attached to the main surface 10a so as to cover the conductor pattern 20. In the dielectric layer attachment step S3, first, the dielectric layer 40 is prepared. The prepared dielectric layer 40 has a conductor layer 56 formed on the main surface 40a. Second, with the main surface 40b facing the dielectric layer 10, the dielectric layer 40 is heated and pressed toward the dielectric layer 10. After the dielectric layer attachment step S3, an etching step S4 is performed.

[0046] 10 is a cross-sectional view illustrating the etching step S4. As shown in FIG. 10, in the etching step S4, the conductor layer 56 is patterned by etching to form the conductor pattern 50. In the etching step S4, first, a resist pattern is formed on the conductor layer 56. The resist pattern is formed, for example, by applying a dry film resist to the conductor layer 56 and then exposing and developing the applied dry film resist. Second, the conductor layer 56 is etched using the resist pattern as a mask. After the etching step S4, a hole-making step S5 is performed.

[0047] 11 is a cross-sectional view illustrating the drilling step S5. As shown in Fig. 11, in the drilling step S5, a through hole 60 is formed in the land 53 and the dielectric layer 40, and a through hole 61 is formed in the land 54 and the dielectric layer 40, for example, by laser processing. After the drilling step S5, a plating step S6 is performed.

[0048] In the plating step S6, a conductor layer 62 is formed on the lands 23 exposed from the through holes 60, on the inner wall surfaces of the through holes 60, and on the lands 53 around the through holes 60. In addition, in the plating step S6, a conductor layer 63 is formed on the lands 24 exposed from the through holes 61, and on the inner wall surfaces of the through holes 61 and on the lands 54 around the through holes 61.

[0049] In the plating step S6, first, a resist pattern is formed on the dielectric layer 40 and the conductor pattern 50. The resist pattern has openings at positions overlapping with the through holes 60 and 61 in a plan view. Second, electroless plating is performed using the resist pattern as a mask, thereby forming the conductor layers 62 and 63. In this way, the structure of the printed wiring board 100 shown in FIGS. 1 to 3 is formed.

[0050] (Effects of Printed Wiring Board 100) The effects of the printed wiring board 100 will be described below in comparison with a comparative example.

[0051] The printed wiring board according to the comparative example is referred to as printed wiring board 200. Fig. 12 is a plan view of printed wiring board 200. As shown in Fig. 12, in printed wiring board 200, distance D2 is equal to distance D1 in second direction DR2. Therefore, in printed wiring board 200, when distance D1 is reduced, distance D2 also becomes reduced.

[0052] When the distance D2 is small, the capacitance between the land 53 and the land 54 increases, and the impedance mismatch at the connection between the signal pattern 51 and the signal pattern 21 (between the signal pattern 52 and the signal pattern 22) increases, deteriorating the reflection characteristics at the connection. Furthermore, when the distance D2 is small, it becomes difficult to form the conductor pattern 20 by etching. This becomes more pronounced as the thickness T increases.

[0053] On the other hand, in printed wiring board 100, at least one of land 53 and land 54 is offset along second direction DR2 so that distance D2 is greater than distance D1. Therefore, even if distance D1 is reduced, distance D2 is ensured, and the capacitance between land 53 and land 54 is unlikely to increase, which is unlikely to hinder the formation of conductive pattern 20 by etching.

[0054] By offsetting the positions of the lands 53 and 54, the intervals SP5 and SP6 become smaller, and the capacitance between the ground pattern 55 and the lands 53 and 54 increases. In this case, by forming the notches 55a and 55b and setting the interval SP5 to be 0.5 to 1.5 times the interval SP3 and setting the interval SP6 to be 0.5 to 1.5 times the interval SP4, it is possible to suppress deterioration of the reflection characteristics at the connection between the signal pattern 51 and the signal pattern 21 (between the signal pattern 52 and the signal pattern 22).

[0055] FIG. 13 shows simulation results illustrating the relationship between the frequency of signals flowing through the signal patterns 51 and 52 and the return loss in Samples 1 to 3. The vertical axis of FIG. 13 represents return loss (unit: dB), and the horizontal axis of FIG. 13 represents frequency (unit: GHz). In Sample 1, the distances D1 and D2 were set to 500 μm. In Sample 2, the distances D1 and D2 were set to 350 μm. In Sample 3, the distances D1 and D2 were set to 350 μm and 450 μm, respectively. In Samples 1 to 3, the width of the land 53 in the second direction DR2 and the width of the land 54 in the second direction DR2 were set to 300 μm. Therefore, the spacing SP2 in Sample 1 was 200 μm, the spacing SP2 in Sample 2 was 50 μm, and the spacing SP2 in Sample 3 was 150 μm. Thus, Sample 1 and Sample 2 were printed wiring boards 200, while Sample 3 was printed wiring board 100.

[0056] 13, in sample 1, the return loss was smaller than −20 dB when the frequency of the signals flowing through signal patterns 51 and 52 was within a range of 70 GHz or less. However, when distance D1 was reduced to 350 μm, in sample 2, the return loss exceeded −20 dB when the frequency of the signals flowing through signal patterns 51 and 52 exceeded 40 GHz.

[0057] On the other hand, in sample 3, even when distance D1 was reduced to 350 μm, the return loss was less than −20 dB within the range of 70 GHz or less of the frequency of the signals flowing through signal patterns 51 and 52. This demonstrates that printed wiring board 100 can suppress the deterioration of return loss even when signal patterns 51 and 52 are arranged at a narrower pitch.

[0058] The embodiments disclosed herein are illustrative in all respects and should not be considered limiting. The scope of the present invention is defined by the claims, not by the above-described embodiments, and is intended to include all modifications within the meaning and scope of the claims.

[0059] 10 Dielectric layer, 10a, 10b Main surface, 20 Conductive pattern, 21, 22 Signal pattern, 23, 24 Land, 25 Ground pattern, 26 Conductive layer, 30 Conductive pattern, 31 Ground pattern, 32 Conductive layer, 40 Dielectric layer, 40a, 40b Main surface, 50 Conductive pattern, 51, 52 Signal pattern, 53 Land, 54 Land, 55 Ground pattern, 55a, 55b Notch, 56 Conductive layer, 60 Through hole, 61 Through hole, 62, 63 Conductive layer, 100, 200 Printed wiring board, D1, D2 Distance, DR1 First direction, DR2 Second direction, DR3 Third direction, S1 Preparation step, S2 Etching step, S3 Dielectric layer attachment step, S4 Etching step, S5 Hole drilling step, S6 Plating process, SP1, SP2, SP3, SP4, SP5, SP6 spacing, T thickness.

Claims

1. A printed wiring board comprising: a dielectric layer; and a conductor pattern disposed on the dielectric layer, wherein the conductor pattern has first and second signal patterns that form a pair of differential signal lines, and first and second lands; each of the first and second signal patterns extends along a first direction in a planar view; the first and second signal patterns are arranged at intervals along a second direction perpendicular to the first direction in a planar view; the first and second lands are connected to an end of the first signal pattern in the first direction and an end of the second signal pattern in the first direction, respectively; and the distance between the center position of the first land and the center position of the second land in the second direction is greater than the distance between the center position of the first signal pattern and the center position of the second signal pattern.

2. The printed wiring board according to claim 1, wherein, in the second direction, the width of the first land is greater than the width of the first signal pattern, and the width of the second land is greater than the width of the second signal pattern.

3. A printed wiring board as described in claim 1 or claim 2, wherein the distance between the first land and the second land in the second direction is 0.5 to 1.5 times the distance between the first signal pattern and the second signal pattern.

4. A printed wiring board according to any one of claims 1 to 3, wherein the conductor pattern further has a ground pattern, the ground pattern surrounding the first signal pattern, the second signal pattern, the first land, and the second land in a planar view, the minimum value of the spacing between the first land and the ground pattern being 0.5 to 1.5 times the minimum value of the spacing between the first signal pattern and the ground pattern, and the minimum value of the spacing between the second land and the ground pattern being 0.5 to 1.5 times the minimum value of the spacing between the second signal pattern and the ground pattern in a planar view.

5. A printed wiring board according to any one of claims 1 to 4, wherein the dielectric layer has a relative permittivity of 2.0 or more and a dielectric loss tangent of 0.01 or less.

6. A printed wiring board according to any one of claims 1 to 5, wherein the center position of the first land is farther from the second signal pattern in the second direction than the center position of the first signal pattern.

7. A printed wiring board according to any one of claims 1 to 6, wherein the center position of the second land is farther from the first signal pattern than the center position of the second signal pattern in the second direction.

8. A printed wiring board as described in any one of claims 1 to 7, wherein the distance between the center position of the first land and the center position of the second land in the second direction is 500 μm or less, the spacing between the first land and the second land in the second direction is 100 μm or more, and the thickness of the conductor pattern is 10 μm or more.

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