Layered structure, method for manufacturing same, and semiconductor device

Abstract

This layered structure (100) is configured such that an n-type germanium layer (10) and a metal layer (20) are bonded via a layered compound layer (30), the layered structure (100) having ohmic properties, wherein the layered compound layer (30) is composed of a compound represented by general formula GexBi3−xTe4 (where 0 < x ≤ 1), and the n-type germanium layer (10) and the layered compound layer (30) are bonded via a van der Waals interface.

Description

Stacked structure and manufacturing method thereof, and semiconductor device

[0001] This application claims priority to Japanese Patent Application No. 2024-115146, filed on July 18, 2024, the contents of which are incorporated herein by reference.

[0002] Germanium (Ge) has higher electron and hole mobility than silicon (Si), and research and development into miniaturized transistors that operate at low voltages is underway.

[0003] Conventionally, in a junction between a metal and Ge, Fermi level pinning (FLP) occurs near the valence band edge, so that most junctions between metals and n-type Ge form a high Schottky barrier regardless of the work function of the metal. In recent years, there has been a report that Fermi level pinning is suppressed and the Schottky barrier is reduced by contacting bismuth (Bi), a semimetallic material with a low density of states, with Si and Ge (Non-Patent Document 1).

[0004] T. Nishimura, X. Luo, S. Matsumoto, T. Yajima, and A. Toriumi, AIP Adv. 9, 095013 (2019) “Almost pinning-free bismuth / Ge and / Si interfaces”

[0005] However, the contact resistance at the interface between typical metal electrodes and Ge has hindered device performance improvement. This is thought to be primarily due to the inability to sufficiently eliminate interface states and interfacial conditions between the metal electrode and Ge. While Ge is well known for its superior performance in p-type FETs compared to Si, a major issue with n-type FETs is the FLP phenomenon caused by the interfacial states and interfacial conditions between the metal electrode and Ge, resulting in high contact resistance. FLP creates a large Schottky barrier between the metal electrode and n-type Ge, and there was no established method to completely remove this barrier. Furthermore, because CMOS circuits that make up LSIs are composed of a complementary combination of n-type and p-type FETs, reducing the contact resistance of n-type Ge was necessary.

[0006] The present disclosure has been made in view of the above circumstances, and provides a stacked structure in which the contact resistance is reduced in an n-type Ge contact structure, a manufacturing method thereof, and a semiconductor device.

[0007] To solve the above problems, the present disclosure provides the following means.

[0008] A first aspect of the present disclosure is a layered structure having an ohmic contact between an n-type germanium layer and a metal layer via a layered compound layer, the layered compound layer being represented by the general formula Ge ｘ Bi ３－ｘ Te ４ (where 0<x≦1), and the n-type germanium layer and the layered compound layer are joined via a van der Waals interface, forming a laminated structure.

[0009] Aspect 2 of the present disclosure is a layered structure having ohmic properties in which an n-type germanium layer and a metal layer are joined via a layered compound layer, and the layered compound layer is made of Bi. ２ Te ３ The n-type germanium layer and the layered compound layer are joined via an interface layer containing Ge, Bi, Te, and O, forming a laminated structure.

[0010] Aspect 3 of the present disclosure is the laminated structure of aspect 1, wherein the layered compound layer has a thickness of 1 nm or more and 50 nm or less.

[0011] A fourth aspect of the present disclosure is the laminated structure of the second aspect, wherein the layered compound layer has a thickness of 1 nm or more and 50 nm or less.

[0012] A fifth aspect of the present disclosure is the stacked structure of the second or fourth aspect, wherein the interface layer has a thickness of 1 nm or more and 5 nm or less.

[0013] A sixth aspect of the present disclosure is a semiconductor device including the stacked structure of any one of the first to fifth aspects.

[0014] A seventh aspect of the present disclosure is a semiconductor device including a field effect transistor having the stacked structure of any one of the first to fifth aspects.

[0015] Aspect 8 of the present disclosure is a method for producing the laminate structure of any one of Aspects 1 to 5, comprising a step of crystallizing the layered compound layer by either thermal film formation or heat treatment.

[0016] According to the present invention, it is possible to provide a stacked structure in which the contact resistance is reduced in an n-type Ge contact structure.

[0017] 1 is a cross-sectional schematic diagram of a stacked structure according to a first embodiment; FIG. 2 is a cross-sectional STEM image at 4,000,000 magnification of the vicinity of the interface between an n-type germanium layer and a layered compound layer in the stacked structure according to the first embodiment; FIG. 3 is a cross-sectional STEM image at 20,000,000 magnification of the vicinity of the interface between an n-type germanium layer and a layered compound layer in the stacked structure according to the first embodiment; (a) is an HAADF-STEM image; (b) is an elemental mapping image (EDX image) of Te; (c) is an elemental mapping image (EDX image) of Bi; (d) is a superposition of elemental mapping images (EDX images) of Te and Bi; (e) is an elemental mapping image (EDX image) of Ge; and (f) is an elemental mapping image (EDX image) of O. FIG. 3 is a cross-sectional schematic diagram of a stacked structure according to a second embodiment; FIG. 4 is a cross-sectional STEM image at 20,000,000 magnification of the vicinity of the interface between an n-type germanium layer and a layered compound layer in the stacked structure according to the second embodiment. (a) is an HAADF-STEM image, (b) is an elemental mapping image (EDX image) of Te, (c) is an elemental mapping image (EDX image) of Bi, (d) is a superposition of elemental mapping images (EDX image) of Te and Bi, (e) is an elemental mapping image (EDX image) of Ge, and (f) is an elemental mapping image (EDX image) of O. This figure shows the results of comparing the current-voltage (IV) characteristics of a conventional stacked structure and the stacked structure of the present disclosure. This figure shows the temperature dependence of the current-voltage (IV) characteristics of the stacked structure of the present disclosure. This figure shows the results of X-ray diffraction (XRD) performed on the stacked structure of the present disclosure, as deposited, before annealing, and after deposition, with annealing temperatures of 250°C, 300°C, and 400°C. 1 shows current-voltage (IV) characteristics of the stacked structure of the present disclosure before annealing, at an annealing temperature of 300° C., and at an annealing temperature of 400° C. ２ Te ４11A is a crystalline structure of (database). A simulation was performed based on the crystal structure shown in FIG. 10A, and the results of investigating the composition dependency of the XRD pattern are shown. FIG. 11B is an XRD pattern of a stacked structure produced by annealing after deposition at 400°C. FIG. 11C is a cross-sectional schematic diagram of an example of a stacked structure of the present disclosure. FIG. 11B is a cross-sectional schematic diagram of an example of a stacked structure of the present disclosure shown in FIG. 11A, applied to a top-gate field-effect transistor. FIG. 11C is a cross-sectional schematic diagram of an example of a stacked structure of the present disclosure shown in FIG. 11A, applied to a photo-field-effect transistor.

[0018] The present disclosure will be described in detail below with reference to the drawings as appropriate. The drawings used in the following description may show characteristic portions enlarged for convenience in order to make the features easier to understand, and the dimensional ratios of each component may differ from the actual ones. The dimensions and the like exemplified in the following description are merely examples, and the present disclosure is not limited thereto. Appropriate changes can be made within the scope of the effects of the present disclosure. Unless otherwise specified below, a configuration described in one embodiment may be applied to other embodiments.

[0019] 1 shows a cross-sectional schematic diagram of a stacked structure according to the first embodiment. The stacked structure 100 shown in FIG. 1 is a stacked structure having ohmic properties, in which an n-type germanium layer 10 and a metal layer 20 are joined via a layered compound layer 30. The layered compound layer 30 is a compound represented by the general formula Ge ｘ Bi ３－ｘ Te ４ (where 0<x≦1), and the n-type germanium layer 10 and the layered compound layer 30 are bonded via a van der Waals interface.

[0020] The stacked layer structure according to the first embodiment can be included in various semiconductor devices. Conventionally, the contact resistance at the interface between a general metal electrode and an n-type germanium layer has hindered the improvement of device performance. However, in the stacked layer structure according to the first embodiment, the Schottky barrier and contact resistance in the n-type Ge contact structure are reduced by sandwiching a layered compound layer in the contact portion with the n-type germanium layer.

[0021] There are no particular limitations on the material of the metal layer 20, and examples thereof include tungsten (W), titanium (Ti), nickel (Ni), aluminum (Al), platinum (Pt), gold (Au), titanium nitride (TiN), tantalum nitride (TaN), and alloys or laminated films containing two or more of these.

[0022] The material of the layered compound layer 30 is represented by the general formula Ge ｘ Bi ３－ｘ Te ４ (where 0<x≦1). The thickness of the layered compound layer 30 can be, for example, 1 nm or more. The thickness of the layered compound layer 30 can be 50 nm or less, 30 nm or less, and preferably 20 nm or less.

[0023] 2A and 2B show cross-sectional STEM (scanning transmission electron microscope) images of the vicinity of the interface between the n-type germanium layer and the layered compound layer in the stacked structure according to the first embodiment. Fig. 2A is a cross-sectional STEM image at 4 million magnifications, and Fig. 2B is a cross-sectional STEM image at 20 million magnifications. The cross-sectional STEM images of Fig. 2A and Fig. 2B reveal that a layered contact structure is formed.

[0024] The sample of the stacked structure according to the first embodiment was prepared by depositing a layer material Bi on an n-type germanium substrate (100) at a deposition temperature of 230°C. ２ Te ３ The n-type germanium substrate was prepared by sputtering a 20 nm thick layer (thermal deposition), depositing tungsten (W) to a thickness of 30 nm on the layered material layer, and then annealing at 400°C. The annealing was performed in an Ar atmosphere with a 10 minute heating time. The annealing at 400°C improved the crystallinity of the layered material layer and the interface characteristics between the n-type germanium layer and the layered compound layer. The n-type germanium substrate may have a surface other than the (100) surface, such as the (111) surface.

[0025] 2B , it can be seen that the interface (indicated by the thick arrow in the figure) between the n-type germanium layer 10 and the layered compound layer 30 is an atomically flat (or steep) interface. Furthermore, both the n-type germanium layer 10 and the layered compound layer 30 have no disorder in the atomic arrangement, including at the interface, indicating that the n-type germanium layer 10 and the layered compound layer 30 are bonded by van der Waals forces. In this specification, an interface having no disorder in the atomic arrangement, including at the interface, and having atomically flat (steep) characteristics is referred to as a van der Waals interface.

[0026] 3 shows an HAADF-STEM image and elemental mapping images (EDX images) of each constituent element of the layered compound layer 30. Fig. 3(a) is an HAADF-STEM image, Fig. 3(b) is an elemental mapping image (EDX image) of Te, Fig. 3(c) is an elemental mapping image (EDX image) of Bi, Fig. 3(d) is a superposition of elemental mapping images (EDX images) of Te and Bi, Fig. 3(e) is an elemental mapping image (EDX image) of Ge, and Fig. 3(f) is an elemental mapping image (EDX image) of O.

[0027] Fig. 4 shows a cross-sectional schematic diagram of a laminated structure according to the second embodiment. In the following, the same components as those in the embodiment described with reference to Figs. 1 to 3 are denoted by the same reference numerals, and the description thereof may be omitted.

[0028] The layered structure 200 shown in FIG. 4 is an ohmic layered structure in which an n-type germanium layer 10 and a metal layer 20 are joined via a layered compound layer 30. The layered compound layer 30 is made of Bi. ２ Te ３ and an interface layer 30B containing Ge, Bi, Te and O, and the n-type germanium layer 10 and the layered compound layer 30 are joined via the interface layer 30B.

[0029] The stacked structure according to the second embodiment can be included in various semiconductor devices. Conventionally, the contact resistance at the interface between a general metal electrode and an n-type germanium layer has hindered the improvement of device performance. However, in the stacked structure according to the second embodiment, the Schottky barrier and contact resistance in the n-type Ge contact structure are reduced by sandwiching a layered compound layer in the contact portion with the n-type germanium layer.

[0030] The layered compound layer 30 is made of Bi ２ Te ３ and an interface layer 30B containing Ge, Bi, Te, and O. The thickness of the layered compound layer 30 can be, for example, 1 nm or more. The thickness of the layered compound layer 30 can be, for example, 50 nm or less, 30 nm or less, and preferably 20 nm or less. The thickness of the main layer compound layer 30A can be, for example, 1 nm or more. The thickness of the interface layer 30B can be, for example, 1 nm or more and 5 nm or less.

[0031] 5 shows a cross-sectional STEM (scanning transmission electron microscope) image of the vicinity of the interface between the n-type germanium layer and the layered compound layer in the stacked structure according to the second embodiment. Fig. 5 is a cross-sectional STEM image at 20 million magnifications.

[0032] The sample of the stacked structure according to the second embodiment was prepared by depositing a layer material Bi on an n-type germanium substrate (100) at a deposition temperature of 230°C. ２ Te ３ The layered material layer was deposited to a thickness of 20 nm by sputtering (thermal deposition), and tungsten (W) was deposited to a thickness of 30 nm on the layered material layer, followed by annealing at 300°C. The annealing was performed by heating for 1 minute in an Ar atmosphere and holding for 10 minutes. Annealing at 300°C improved the crystallinity of the layered material layer and the interface characteristics between the n-type germanium layer and the layered compound layer.

[0033] 5, the interface between the n-type germanium layer 10 and the layered compound layer 30 (indicated by the thick arrow in the figure) does not have the same atomic level flatness as the stacked structure according to the first embodiment, but many atomic images are visible, indicating that it has high flatness. The n-type germanium layer 10 and the layered compound layer 30 are bonded via an interface layer 30B. The bonded surface between the n-type germanium layer 10 and the layered compound layer 30 in the stacked structure according to the second embodiment is expected to have a higher peel strength than a van der Waals interface.

[0034] 6 shows an HAADF-STEM image of the layered compound layer 30 and elemental mapping images (EDX images) of each constituent element. Fig. 6(a) is an HAADF-STEM image, Fig. 6(b) is an elemental mapping image (EDX image) of Te, Fig. 6(c) is an elemental mapping image (EDX image) of Bi, Fig. 6(d) is a superposition of elemental mapping images (EDX images) of Te and Bi, Fig. 6(e) is an elemental mapping image (EDX image) of Ge, and Fig. 6(f) is an elemental mapping image (EDX image) of O. The elemental mapping images are different from those of the first embodiment, and the difference is particularly clear in the elemental mapping image of Bi.

[0035] 7 shows the results of comparing the current-voltage (IV) characteristics of a Ge Schottky diode between a conventional stacked structure and the stacked structure of the present disclosure. Specifically, the results are shown for a stacked structure (conventional structure) of an n-type germanium layer (for example, resistivity of 0.1 Ωcm) and a metal (tungsten, for example) layer, and a layered compound (Bi) between these layers. ２ Te ３ 1 shows the results of comparing the current-voltage (IV) characteristics of a laminate structure (present disclosure) having a SiO 2 layer sandwiched therebetween.

[0036] The sample of the layered structure of the present disclosure was fabricated as follows: A layered material Bi was deposited on the (100) surface of an n-type germanium substrate at a deposition temperature of 230°C. ２ Te ３A 20 nm thick layer of tungsten (W) was deposited on the layered material layer by sputtering (thermal deposition). A 30 nm thick layer of tungsten (W) was then deposited on the layered material layer, and the electrode region was defined by lithography. The electrode metal was then formed by dry etching. The sample was then annealed at 300°C to 400°C. The annealing was performed in an Ar atmosphere with a 1 minute temperature increase and a 10 minute hold time.

[0037] As shown in FIG. 7, in the conventional laminated structure (conventional structure) with metal junction (metal contact), the current is small when a reverse voltage is applied and the laminated structure does not have ohmic characteristics. ２ Te ３ In the laminated structure with a Bi layer sandwiched between the two layers, the current increases when a reverse voltage is applied, but there is almost no difference in the current when a forward voltage is applied, and the structure has ohmic characteristics. ２ Te ３ By using the contact, we were able to achieve ohmic contact to n-type Ge, which is direct evidence of a significant reduction in the Schottky barrier.

[0038] Figure 8A shows the temperature dependence of the current-voltage (IV) characteristics of the stacked structure of the present disclosure, and Figure 8B shows an Arrhenius plot as a function of temperature. ２ Te ３ The Schottky barrier between Bi and Ge was found to be less than 0.1 eV. ２ Te ３ This is thought to be due to the low density of states and the formation of van der Waals interfaces.

[0039] 9A shows the results of X-ray diffraction (XRD) performed on the stacked structure of the present disclosure, as deposited (as-deposited) and on stacked structures annealed at temperatures of 250°C, 300°C, and 400°C after deposition. Annealing was performed in an Ar atmosphere with a 1-minute temperature increase and a 10-minute hold time. The Bi of the sample annealed up to 300°C ２ Te ３It can be seen that the peak of the crystalline phase in the XRD pattern is shifted in the sample prepared at an annealing temperature of 400°C.

[0040] 9B shows the current-voltage (IV) characteristics of the stacked structure of the present disclosure when as-deposited, annealed at 300°C, and annealed at 400°C. It can be seen that the Ge Schottky diode fabricated at 400°C has improved ohmic characteristics compared to the Ge Schottky diode fabricated at 300°C. The Ge Schottky diode fabricated at 500°C has slightly worse ohmic characteristics than the Ge Schottky diode fabricated at 400°C.

[0041] Comparing the XRD results, the IV characteristic measurement results, and the cross-sectional STEM images and element mapping images described above, it was found that the stacked structure fabricated by annealing after deposition at 400°C has a stacked structure in which the n-type germanium layer and the layered compound layer are joined at a van der Waals interface, thereby significantly improving the ohmic characteristics. On the other hand, the stacked structure fabricated by annealing after deposition at 300°C does not obtain a van der Waals junction, but it was found that high ohmic characteristics can be obtained by joining via a thin interface layer.

[0042] GeBi having the crystal structure shown in FIG. ２ Te ４ (database), the occupancy rate of Ge sites is calculated as Ge １－ｙ Bi ｙ Simulations were performed assuming a mixture of Ge and Bi by varying y between 0 and 1 in increments of 0.1. The results of investigating the composition dependence of the XRD patterns are shown in Figure 10B. Figure 10C shows the XRD pattern of a stacked structure fabricated by annealing at 400°C after deposition.

[0043] From the simulated XRD pattern shown in Figure 10B, it can be seen that as x increases, the peak near 2θ = 13° becomes smaller and the peak near 2θ = 20° becomes larger. When y = 0.8, the intensity ratio of the peak near 2θ = 13° to the peak near 2θ = 20° in the simulated XRD pattern shown in Figure 10B becomes approximately the same as the intensity ratio of the peak near 2θ = 13° to the peak near 2θ = 20° in the XRD pattern of Figure 10C. Based on this result, it can be seen that the layered compound layer in the stacked structure fabricated by annealing after deposition at 400°C has the general formula Ge ｘ Bi ３－ｘ Te ４ (where 0<x<1)

[0044] (Method for manufacturing laminated structure) The method for manufacturing a laminated structure of the present disclosure is characterized by including a step of crystallizing the layered compound layer in the laminated structure of the present disclosure by either thermal film formation or heat treatment. Here, "thermal film formation" refers to heating an n-type Ge layer or an n-type Ge substrate to form a layered compound layer while crystallizing the layered compound layer, and "heat treatment" refers to heat treatment for crystallizing the layered compound layer after film formation.

[0045] (Application Example 1) Fig. 11A shows an example of a stacked structure of the present disclosure, and Fig. 11B shows an example in which the stacked structure is applied to a top-gate field effect transistor (FET). Figs. 11A and 11B are cross-sectional schematic views. Components having the same reference numerals as those described above have the same functions, and their explanations will be omitted.

[0046] In the example of the stacked structure of the present disclosure shown in FIG. 11A , the elements denoted by the reference numerals 20A and 20B are metal layers spaced apart from each other, and the elements denoted by the reference numerals 30A and 30B are layered compound layers spaced apart from each other and disposed between the n-type germanium layer 10 and the metal layer 20A, and between the n-type germanium layer 10 and the metal layer 20B.

[0047] In the field effect transistor shown in FIG. 11B, metal layers 20A and 20B are source / drain electrodes, reference numeral 40 denotes a gate insulating film, reference numeral 50 denotes a gate electrode, reference numeral 60 denotes an interlayer insulating film, and reference numerals 20AA and 20BB denote plug electrodes connected to the source / drain electrodes 20A and 20B, respectively.

[0048] The material of the gate insulating film 40 is a known gate insulating film material, for example, SiO ２ , Al ２ O ３ , HfO ２ , ZrO ２ , Y ２ O ３ , La ２ O ３ The interlayer insulating film 60 may be made of a known material for an interlayer insulating film, such as SiO ２ For example, an oxide film such as SiN or a nitride film such as SiN can be used.

[0049] The gate electrode layer 50 can be made of known gate electrode layer materials, such as tungsten (W), titanium (Ti), nickel (Ni), aluminum (Al), platinum (Pt), gold (Au), titanium nitride (TiN), tantalum nitride (TaN), or an alloy or laminated film containing two or more of these.

[0050] (Application Example 2) An example in which an example of the stacked structure of the present disclosure shown in Fig. 11A is applied to a photo field effect transistor (FET) shown in Fig. 12 is shown. Fig. 12 is a schematic cross-sectional view. Components denoted by the same reference numerals as those described above have the same functions, and their explanations will be omitted.

[0051] In the photo-FET shown in FIG. 12, reference numeral 70 denotes an insulating film, for example, SiO ２ An oxide film such as silicon dioxide (Si) or a nitride film such as silicon nitride (SiN) can be used. Reference numeral 80 denotes a semiconductor substrate, which may be made of silicon (Si), germanium (Ge), gallium arsenide (GaAs), indium phosphide (InP), sapphire (Al ２ O ３) or a glass substrate can be used.

[0052] 10 n-type germanium layer 20 metal layer 30 layered compound layer 100 stacked structure

Claims

1. An n-type germanium layer and a metal layer are joined via a layered compound layer, and the layered compound layer has an ohmic property. ｘ Bi ３－ｘ Te ４ (where 0<x≦1), and the n-type germanium layer and the layered compound layer are bonded via a van der Waals interface.

2. An n-type germanium layer and a metal layer are joined via a layered compound layer, and the layered compound layer has an ohmic property. ２ Te ３ The n-type germanium layer and the layered compound layer are joined via an interface layer containing Ge, Bi, Te, and O.

3. The laminated structure according to claim 1, wherein the layered compound layer has a thickness of 1 nm or more and 50 nm or less.

4. The laminated structure according to claim 2, wherein the layered compound layer has a thickness of 1 nm or more and 50 nm or less.

5. The laminate structure according to claim 2, wherein the thickness of the interface layer is 1 nm or more and 5 nm or less.

6. A semiconductor device comprising the laminate structure according to any one of claims 1 to 5.

7. A semiconductor device comprising a field effect transistor having the stacked structure according to any one of claims 1 to 5.

8. A method for producing a laminated structure according to any one of claims 1 to 5, comprising the step of crystallizing the layered compound layer by either thermal film formation or heat treatment.

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