Plasma processing apparatus, bias power source, and plasma processing method

Abstract

The plasma processing apparatus in the present disclosure includes a bias power source. The bias power source is electrically coupled to a substrate support in a chamber. The bias power source includes first and second conversion circuits and first and second pulse generation circuits. The first and second conversion circuits respectively generate a first DC voltage and a second DC voltage from an input DC voltage. The first pulse generation circuit generates a first sequence of first voltage pulses from the first DC voltage in a first sub-period within a period. The second pulse generation circuit generates a second sequence of second voltage pulses from the second DC voltage in a second sub-period within the period. The first and second voltage pulses have different potential differences with respect to a reference potential.

Description

Plasma processing apparatus, bias power supply, and plasma processing method

[0001] SUMMARY Exemplary embodiments of the present disclosure relate to a plasma processing apparatus, a bias power supply, and a plasma processing method.

[0002] A plasma processing apparatus is used in plasma processing of a substrate. The plasma processing apparatus includes a chamber, a substrate support, a plasma generation unit, and a bias power supply. The substrate support is disposed in the chamber. The plasma generation unit is configured to generate plasma from a gas in the chamber. The bias power supply is configured to supply a bias signal to the substrate support to attract ions from the plasma to a substrate on the substrate support. Patent Document 1 listed below discloses a plasma processing apparatus configured to supply a voltage pulse as the bias signal from the bias power supply.

[0003] Japanese Patent Application Laid-Open No. 2021-176191

[0004] The present disclosure provides techniques for rapidly and switchably supplying a sequence of voltage pulses having different voltage levels to a substrate support of a plasma processing apparatus.

[0005] In one exemplary embodiment, a plasma processing apparatus is disclosed. The plasma processing apparatus includes a chamber, a substrate support, a plasma generation unit, and a bias power supply. The substrate support is disposed within the chamber. The plasma generation unit is configured to generate a plasma from a gas within the chamber. The bias power supply is electrically coupled to the substrate support and configured to generate a bias signal to attract ions from the plasma to a substrate on the substrate support. The bias power supply includes a first conversion circuit, a second conversion circuit, a first pulse generation circuit, and a second pulse generation circuit. The first conversion circuit is configured to generate a first DC voltage from an input DC voltage. The second conversion circuit is configured to generate a second DC voltage from the input DC voltage. The first pulse generation circuit is configured to periodically pulse the first DC voltage during a first sub-period within a repeating period to generate a first sequence of first voltage pulses as the bias signal. The first voltage pulses have a first potential difference with respect to a reference potential. The second pulse generating circuit is configured to periodically pulse the second DC voltage during a second subperiod within the period to generate a second sequence of second voltage pulses, the second voltage pulses having a second potential difference with respect to a reference potential that is different from the first potential difference.

[0006] According to one exemplary embodiment, a sequence of voltage pulses having different voltage levels can be rapidly switched to provide a substrate support in a plasma processing apparatus.

[0007] 4A and 4B are timing charts showing a first voltage pulse sequence and a second voltage pulse sequence, respectively. FIG. 4A is a diagram for explaining an example of the configuration of a plasma processing system. FIG. 4B is a diagram for explaining an example of the configuration of a capacitively coupled plasma processing apparatus. FIG. 4C is a diagram showing a plasma processing apparatus according to an exemplary embodiment. FIG. 4A is a timing chart showing an example of a plasma processing method according to an exemplary embodiment. FIG. 4B is a partial enlarged cross-sectional view of an exemplary substrate. FIG. 4C is a partial enlarged cross-sectional view of an exemplary substrate. FIG. 4D is a timing chart showing another example of a plasma processing method according to an exemplary embodiment. FIG. 4E is a timing chart showing yet another example of a plasma processing method according to an exemplary embodiment. FIG. 4F is a block diagram of a processing circuit for performing the operations described herein on a computer.

[0008] Various exemplary embodiments will be described in detail below with reference to the drawings, in which the same or equivalent parts are designated by the same reference numerals.

[0009] FIG. 1 is a diagram illustrating an exemplary configuration of a plasma processing system. In one embodiment, the plasma processing system includes a plasma processing apparatus 1 and a control unit 2. The plasma processing system is an example of a substrate processing system, and the plasma processing apparatus 1 is an example of a substrate processing apparatus. The plasma processing apparatus 1 includes a plasma processing chamber 10, a substrate support 11, and a plasma generation unit 12. The plasma processing chamber 10 has a plasma processing space. The plasma processing chamber 10 also has at least one gas supply port for supplying at least one processing gas to the plasma processing space and at least one gas exhaust port for exhausting gas from the plasma processing space. The gas supply port is connected to a gas supply unit 20 (described later), and the gas exhaust port is connected to an exhaust system 40 (described later). The substrate support 11 is disposed in the plasma processing space and has a substrate support surface for supporting a substrate.

[0010] The plasma generating unit 12 is configured to generate plasma from at least one processing gas supplied into the plasma processing space. The plasma formed in the plasma processing space may be capacitively coupled plasma (CCP), inductively coupled plasma (ICP), electron-cyclotron-resonance plasma (ECR plasma), helicon wave plasma (HWP), or surface wave plasma (SWP). Various types of plasma generators may be used, including alternating current (AC) plasma generators and direct current (DC) plasma generators. In one embodiment, the AC signal (AC power) used in the AC plasma generator has a frequency in the range of 100 kHz to 10 GHz. Thus, AC signals include radio frequency (RF) signals and microwave signals. In one embodiment, the RF signal has a frequency in the range of 100 kHz to 150 MHz.

[0011] The control unit 2 processes computer-executable instructions that cause the plasma processing apparatus 1 to perform various processes described in this disclosure. The control unit 2 may be configured to control each element of the plasma processing apparatus 1 to perform various processes described herein. In one embodiment, part or all of the control unit 2 may be included in the plasma processing apparatus 1. The control unit 2 may include a processing unit 2a1, a storage unit 2a2, and a communication interface 2a3. The control unit 2 may be implemented by, for example, a computer 2a. The processing unit 2a1 may be configured to read a program from the storage unit 2a2 and execute the read program to perform various control operations. This program may be stored in the storage unit 2a2 in advance or may be acquired via a medium when needed. The acquired program is stored in the storage unit 2a2 and read from the storage unit 2a2 by the processing unit 2a1 for execution. The medium may be various storage media readable by the computer 2a or a communication line connected to the communication interface 2a3. The processing unit 2a1 may be a CPU (Central Processing Unit). The storage unit 2a2 may include a random access memory (RAM), a read-only memory (ROM), a hard disk drive (HDD), a solid state drive (SSD), or a combination thereof. The communication interface 2a3 may communicate with the plasma processing apparatus 1 via a communication line such as a local area network (LAN).

[0012] The following describes a configuration example of a capacitively coupled plasma processing apparatus as an example of the plasma processing apparatus 1. Fig. 2 is a diagram for explaining a configuration example of a capacitively coupled plasma processing apparatus.

[0013] The capacitively coupled plasma processing apparatus 1 includes a plasma processing chamber 10, a gas supply 20, a power supply 30, and an exhaust system 40. The plasma processing apparatus 1 also includes a substrate support 11 and a gas inlet. The gas inlet is configured to introduce at least one process gas into the plasma processing chamber 10. The gas inlet includes a showerhead 13. The substrate support 11 is disposed within the plasma processing chamber 10. The showerhead 13 is disposed above the substrate support 11. In one embodiment, the showerhead 13 forms at least a portion of the ceiling of the plasma processing chamber 10. The plasma processing chamber 10 has a plasma processing space 10s defined by the showerhead 13, a sidewall 10a of the plasma processing chamber 10, and the substrate support 11. The plasma processing chamber 10 is grounded. The showerhead 13 and the substrate support 11 are electrically insulated from the housing of the plasma processing chamber 10.

[0014] The substrate support 11 includes a main body 111 and a ring assembly 112. The main body 111 has a central region 111a for supporting a substrate W and an annular region 111b for supporting the ring assembly 112. A wafer is an example of a substrate W. The annular region 111b of the main body 111 surrounds the central region 111a of the main body 111 in a plan view. The substrate W is disposed on the central region 111a of the main body 111, and the ring assembly 112 is disposed on the annular region 111b of the main body 111 so as to surround the substrate W on the central region 111a of the main body 111. Therefore, the central region 111a is also called a substrate support surface for supporting the substrate W, and the annular region 111b is also called a ring support surface for supporting the ring assembly 112.

[0015] In one embodiment, the main body 111 includes a base 1110 and an electrostatic chuck 1111. The base 1110 includes a conductive member. The conductive member of the base 1110 can function as a lower electrode. The electrostatic chuck 1111 is disposed on the base 1110. The electrostatic chuck 1111 includes a ceramic member 1111a and an electrostatic electrode 1111b disposed within the ceramic member 1111a. The ceramic member 1111a has a central region 111a. In one embodiment, the ceramic member 1111a also has an annular region 111b. Note that the annular region 111b may also be provided by another member surrounding the electrostatic chuck 1111, such as an annular electrostatic chuck or an annular insulating member. In this case, the ring assembly 112 may be disposed on the annular electrostatic chuck or the annular insulating member, or may be disposed on both the electrostatic chuck 1111 and the annular insulating member. Furthermore, at least one RF / DC electrode coupled to an RF power supply 31 and / or a DC power supply 32, which will be described later, may be disposed within the ceramic member 1111a. In this case, the at least one RF / DC electrode functions as a lower electrode. When a bias RF signal and / or a DC signal, which will be described later, is supplied to the at least one RF / DC electrode, the RF / DC electrode is also called a bias electrode. Note that the conductive member of the base 1110 and the at least one RF / DC electrode may function as multiple lower electrodes. Furthermore, the electrostatic electrode 1111b may function as a lower electrode. Therefore, the substrate support 11 includes at least one lower electrode.

[0016] The ring assembly 112 includes one or more annular members. In one embodiment, the one or more annular members include one or more edge rings and at least one cover ring. The edge rings are formed of a conductive or insulating material, and the cover rings are formed of an insulating material.

[0017] The substrate support 11 may also include a temperature adjustment module configured to adjust at least one of the electrostatic chuck 1111, the ring assembly 112, and the substrate to a target temperature. The temperature adjustment module may include a heater, a heat transfer medium, a flow passage 1110a, or a combination thereof. A heat transfer fluid such as brine or a gas flows through the flow passage 1110a. In one embodiment, the flow passage 1110a is formed in the base 1110, and one or more heaters are disposed in the ceramic member 1111a of the electrostatic chuck 1111. The substrate support 11 may also include a heat transfer gas supply configured to supply a heat transfer gas to a gap between the backside of the substrate W and the central region 111a.

[0018] The showerhead 13 is configured to introduce at least one process gas from the gas supply unit 20 into the plasma processing space 10s. The showerhead 13 has at least one gas supply port 13a, at least one gas diffusion chamber 13b, and multiple gas inlets 13c. The process gas supplied to the gas supply port 13a passes through the gas diffusion chamber 13b and is introduced into the plasma processing space 10s from the multiple gas inlets 13c. The showerhead 13 also includes at least one upper electrode. In addition to the showerhead 13, the gas inlet may also include one or more side gas injectors (SGIs) attached to one or more openings formed in the sidewall 10a.

[0019] The gas supply unit 20 may include at least one gas source 21 and at least one flow controller 22. In one embodiment, the gas supply unit 20 is configured to supply at least one process gas from a corresponding gas source 21 to the showerhead 13 via a corresponding flow controller 22. Each flow controller 22 may include, for example, a mass flow controller or a pressure-controlled flow controller. Additionally, the gas supply unit 20 may include at least one flow modulation device that modulates or pulses the flow rate of the at least one process gas.

[0020] The power supply 30 includes an RF power supply 31 coupled to the plasma processing chamber 10 via at least one impedance matching circuit. The RF power supply 31 is configured to supply at least one RF signal (RF power) to at least one lower electrode and / or at least one upper electrode. This generates a plasma from at least one processing gas supplied to the plasma processing space 10s. Therefore, the RF power supply 31 can function as at least a part of the plasma generation unit 12. Furthermore, by supplying a bias RF signal to the at least one lower electrode, a bias potential is generated on the substrate W, thereby attracting ion components in the formed plasma to the substrate W.

[0021] In one embodiment, the RF power supply 31 includes a first RF generating unit 31a and a second RF generating unit 31b. The first RF generating unit 31a is coupled to at least one lower electrode and / or at least one upper electrode via at least one impedance matching circuit and is configured to generate a source RF signal (source RF power) for plasma generation. In one embodiment, the source RF signal has a frequency in the range of 10 MHz to 150 MHz. In one embodiment, the first RF generating unit 31a may be configured to generate multiple source RF signals having different frequencies. The generated one or more source RF signals are supplied to at least one lower electrode and / or at least one upper electrode.

[0022] The second RF generator 31b is coupled to at least one lower electrode via at least one impedance matching circuit and is configured to generate a bias RF signal (bias RF power). The frequency of the bias RF signal may be the same as or different from the frequency of the source RF signal. In one embodiment, the bias RF signal has a frequency lower than the frequency of the source RF signal. In one embodiment, the bias RF signal has a frequency in the range of 100 kHz to 60 MHz. In one embodiment, the second RF generator 31b may be configured to generate multiple bias RF signals having different frequencies. The generated one or more bias RF signals are supplied to at least one lower electrode. In various embodiments, at least one of the source RF signal and the bias RF signal may be pulsed.

[0023] The power supply 30 may also include a DC power supply 32 coupled to the plasma processing chamber 10. The DC power supply 32 includes a first DC generator 32a and a second DC generator 32b. In one embodiment, the first DC generator 32a is connected to the at least one lower electrode and configured to generate a first DC signal. The generated first DC signal is applied to the at least one lower electrode. In one embodiment, the second DC generator 32b is connected to the at least one upper electrode and configured to generate a second DC signal. The generated second DC signal is applied to the at least one upper electrode.

[0024] In various embodiments, the first and second DC signals may be pulsed. In this case, a sequence of voltage pulses is applied to at least one lower electrode and / or at least one upper electrode. The voltage pulses may have a rectangular, trapezoidal, triangular, or combination thereof pulse waveform. In one embodiment, a waveform generator for generating the sequence of voltage pulses from the DC signal is connected between the first DC generator 32a and at least one lower electrode. Thus, the first DC generator 32a and the waveform generator constitute a voltage pulse generator. When the second DC generator 32b and the waveform generator constitute a voltage pulse generator, the voltage pulse generator is connected to at least one upper electrode. The voltage pulses may have either positive or negative polarity. Furthermore, the sequence of voltage pulses may include one or more positive voltage pulses and one or more negative voltage pulses within one period. The first and second DC generating units 32a and 32b may be provided in addition to the RF power supply 31, or the first DC generating unit 32a may be provided instead of the second RF generating unit 31b.

[0025] The exhaust system 40 may be connected to, for example, a gas exhaust port 10e provided at the bottom of the plasma processing chamber 10. The exhaust system 40 may include a pressure regulating valve and a vacuum pump. The pressure in the plasma processing space 10s is regulated by the pressure regulating valve. The vacuum pump may include a turbomolecular pump, a dry pump, or a combination thereof.

[0026] Reference will now be made to Figure 3, which is a diagram illustrating a plasma processing apparatus according to an exemplary embodiment. Figure 3 illustrates a bias power supply 50 employed in the plasma processing apparatus 1, together with the chamber 10 and the substrate support 11. The bias power supply 50 is electrically coupled to the substrate support 11 and is configured to generate a bias signal for attracting ions from the plasma in the chamber 10 to the substrate W on the substrate support 11. The bias power supply 50 is part of the power supply 30 and includes a voltage pulse generator, i.e., a first DC generator 32a, and a waveform generator.

[0027] 3, the bias power supply 50 includes a DC generating section 52 and a waveform generating section 54. The DC generating section 52 includes a first conversion circuit 521 and a second conversion circuit 522. The first conversion circuit 521 is configured to generate a first DC voltage (DC1) from an input DC voltage, i.e., an input DC voltage (DCi). The second conversion circuit 522 is configured to generate a second DC voltage (DC2) from the input DC voltage. Each of the first conversion circuit 521 and the second conversion circuit 522 may be a DC / DC converter.

[0028] The DC generating unit 52 may further include an input 530, an AC / DC converter 520, a control circuit 523, a first output 531, and a second output 532. The input of the AC / DC converter 520 is electrically connected to the input 530. The AC / DC converter 520 is configured to generate a DC voltage from AC power input to the input 530. The output of the AC / DC converter 520 is connected to the inputs of a first conversion circuit 521 and a second conversion circuit 522. The DC voltage generated by the AC / DC converter 520 is input to the first conversion circuit 521 and the second conversion circuit 522 as an input DC voltage. In response to a command from a higher-level control unit such as the control unit 2, the control circuit 523 sends control signals specifying the voltage level of the first DC voltage and the voltage level of the second DC voltage to the first conversion circuit 521 and the second conversion circuit 522, respectively. The output of the first conversion circuit 521 and the output of the second conversion circuit 522 are electrically connected to a first output 531 and a second output 532, respectively. The first DC voltage is output from the first output 531, and the second DC voltage is output from the second output 532.

[0029] The waveform generating unit 54 includes a first pulse generating circuit 541 and a second pulse generating circuit 542. The waveform generating unit 54 may further include a control circuit 543, a sensor 544, a first input 551, a second input 552, and an output 560. Hereinafter, reference will be made to Figures 4(a) and 4(b) in addition to Figure 3. Figures 4(a) and 4(b) are timing charts showing a sequence of first voltage pulses and a sequence of second voltage pulses, respectively.

[0030] The first input 551 is electrically connected to the first output 531. The first DC voltage output from the first output 531 is input to the first input 551. The first input 551 is connected to an input of a first pulse generating circuit 541. The first DC voltage input to the first input 551 is input to the first pulse generating circuit 541. The first pulse generating circuit 541 periodically pulses the first DC voltage in a first sub-period SP1 within a repeating cycle CY. The first pulse generating circuit 541 may include one or more switching elements for pulsing the first DC voltage. The first pulse generating circuit 541 is configured to pulse the first DC voltage to generate, as a bias signal, a first sequence VS1 of first voltage pulses VP1 having a first potential difference (|Vref-V1|) with respect to a reference potential Vref. The output of the first pulse generating circuit 541 is electrically coupled to the substrate support 11 via output 560, and the first sequence VS1 of first voltage pulses VP1 is supplied to the substrate support 11 via output 560.

[0031] The period CY has a time length that is the reciprocal of the frequency, for example, not less than 10 Hz and not more than 50 kHz. The reference potential Vref is, for example, 0 (V), but may be a different potential. The first voltage pulse VP1 may have any polarity as long as it can attract ions from the plasma to the substrate W. The first voltage pulse VP1 may have negative polarity. The generation period of the first voltage pulse VP1, i.e., the shortest generation time interval of the first voltage pulse VP1, has a time length that is the reciprocal of the bias frequency. The bias frequency is, for example, not less than 100 kHz and not more than 400 kHz.

[0032] The second input 552 is electrically connected to the second output 532. The second DC voltage output from the second output 532 is input to the second input 552. The second input 552 is connected to an input of the second pulse generation circuit 542. The second DC voltage input to the second input 552 is input to the second pulse generation circuit 542. The second pulse generation circuit 542 periodically pulses the second DC voltage in a second sub-period SP2 within the repeating cycle CY. The second pulse generation circuit 542 may include one or more switching elements for pulsing the second DC voltage. The second pulse generation circuit 542 is configured to pulse the second DC voltage to generate a second sequence VS2 of second voltage pulses VP2 having a second potential difference (|Vref-V2|) with respect to a reference potential Vref as a bias signal. The output of the second pulse generating circuit 542 is electrically coupled to the substrate support 11 via output 560, and the second sequence VS2 of second voltage pulses VP2 is supplied to the substrate support 11 via output 560.

[0033] The second potential difference may be larger than the first potential difference, as shown in Figures 4(a) and 4(b). Alternatively, the second potential difference may be smaller than the first potential difference. The second voltage pulse VP2 may have any polarity as long as it can attract ions from the plasma to the substrate W. The second voltage pulse VP2 may have negative polarity. The generation cycle of the second voltage pulse VP2, i.e., the shortest generation time interval between the second voltage pulses VP2, also has a time length that is the reciprocal of the bias frequency. As described above, the bias frequency is, for example, 100 kHz or more and 400 kHz or less.

[0034] As shown in FIG. 4A, the second sequence VS2 may be continuous with the first sequence VS1. That is, the first sub-period SP1 and the second sub-period SP2 may be continuous within the cycle CY. Alternatively, there may be a period having a certain time length between the first sequence VS1 and the second sequence VS2. During this period, the bias signal may be stopped. That is, the first sub-period SP1 and the second sub-period SP2 may be discontinuous within the cycle CY.

[0035] The control circuit 543 outputs a synchronization signal SS1 synchronized with the first sub-period SP1 to the first pulse generation circuit 541. In response to this synchronization signal SS1, the first pulse generation circuit 541 generates a first sequence VS1 in the first sub-period SP1 within the cycle CY. The control circuit 543 also outputs a synchronization signal SS2 synchronized with the second sub-period SP2 to the second pulse generation circuit 542. In response to this synchronization signal SS2, the second pulse generation circuit 542 generates a second sequence VS2 in the second sub-period SP2 within the cycle CY. Note that the control circuit 543 may output a signal informing the first pulse generation circuit 541 of the start timing of the first sub-period SP1 and the duty ratio of the first sub-period SP1, instead of the synchronization signal SS1. In this case as well, the first pulse generating circuit 541 can generate the first sequence VS1 in the first sub-period SP1 within the cycle CY in response to a signal from the control circuit 543. Furthermore, the control circuit 543 may output a signal informing the second pulse generating circuit 542 of the start timing of the second sub-period SP2 and the duty ratio of the second sub-period SP2, instead of the synchronization signal SS2. In this case as well, the second pulse generating circuit 542 can generate the second sequence VS2 in the second sub-period SP2 within the cycle CY in response to the signal from the control circuit 543.

[0036] The sensor 544 is configured to measure the voltage and current of the bias signal. The measured voltage and current levels of the bias signal are fed back to the control circuit 543. The control circuit 543 can control the first pulse generation circuit 541 and the second pulse generation circuit 542 in accordance with the feedback result from the sensor 544. The measured voltage and current levels of the bias signal are also fed back to the control circuit 523 via the control circuit 543. The control circuit 523 controls the first conversion circuit 521 and / or the second conversion circuit 522 in accordance with the feedback result from the sensor 544 to adjust the level of the first DC voltage and / or the level of the second DC voltage.

[0037] As described above, the plasma processing apparatus 1 and the bias power supply 50 pulse the DC voltages having different voltage levels generated by the first conversion circuit 521 and the second conversion circuit 522. Therefore, the plasma processing apparatus 1 and the bias power supply 50 can quickly switch between supplying the first sequence VS1 of the first voltage pulses VP1 and the second sequence VS2 of the second voltage pulses VP2, which have different voltage levels, to the substrate support part 11.

[0038] Hereinafter, a plasma processing method according to an exemplary embodiment using the plasma processing apparatus 1 will be described with reference to Fig. 5, and the operation of each part of the plasma processing apparatus 1 in the plasma processing method will be described. Fig. 5 is a flow chart showing the plasma processing method according to an exemplary embodiment. In the plasma processing method shown in Fig. 5 (hereinafter referred to as "method MT"), each part of the plasma processing apparatus 1 can be controlled by a control unit 2.

[0039] The method MT begins with step STa, in which a substrate W is prepared on a substrate support 11. In the subsequent step STb, a processing gas is supplied from the gas supply unit 20 into the chamber 10. In step STc, the substrate W is etched using plasma generated from the processing gas in the chamber 10.

[0040] During the execution period of the process STc, a cycle CY is repeated. During the process STc, a first sequence VS1 of first voltage pulses VP1 is supplied from the first pulse generation circuit 541 to the substrate support part 11 during a first sub-period SP1 within the cycle CY. Also, during the process STc, a second sequence VS2 of second voltage pulses VP2 is supplied from the second pulse generation circuit 542 to the substrate support part 11 during a second sub-period SP2 within the cycle CY. This allows the energy of ions supplied to the substrate W during the process STc to be quickly switched from the energy of ions supplied to the substrate W during the first sub-period SP1 to the energy of ions supplied to the substrate W during the second sub-period SP2.

[0041] An example of the method MT will be described below with reference to Fig. 6. Fig. 6 is an example timing chart related to a plasma processing method according to one exemplary embodiment. Fig. 6 shows changes over time in the power level of a source RF signal and the level of a bias signal. In the following description, Figs. 7 to 9 will be referenced in addition to Fig. 6. Each of Figs. 7 to 9 is an enlarged partial cross-sectional view of an example substrate.

[0042] In step STa of the method MT, a substrate W shown in FIG. 7 may be prepared. As shown in FIG. 7, the substrate W may include a first region R1 and a second region R2. The first region R1 may have at least one recess R1a. The first region R1 may have a plurality of recesses R1a. Each recess R1a may be a recess for forming a contact hole. The recess R1a may be filled with a second region R2. The second region R2 may be provided so as to cover the first region R1.

[0043] In one embodiment, the first region R1 includes silicon and nitrogen. The first region R1 includes silicon nitride (SiN ｘ The first region R1 may include a silicon nitride (SiN ｘ The first portion may include a first portion including silicon carbide (SiC), and a second portion including silicon carbide (SiC). In this case, the first portion has the recess R1a.

[0044] The aspect ratio of the recess R1a may be, for example, 3 or more, 4 or more, 5 or more, or 10 or more. The aspect ratio of the recess R1a indicates the ratio of the depth of the recess R1a to the maximum width dimension of the recess R1a.

[0045] The second region R2 includes silicon and oxygen. The second region R2 includes silicon oxide (SiO ｘ The second region R2 may be a region formed by, for example, CVD or the like, or may be a region obtained by oxidizing silicon.

[0046] The substrate W may further include a third region R3. The third region R3 is provided on the second region R2. The third region R3 may include a metal, carbon, and nitrogen. The metal of the third region R3 may include tungsten. The third region R3 may have an opening OP3. The width of the opening OP3 may correspond to the width of the recess R1a.

[0047] The substrate W may include an underlying region UR and at least one raised region RA provided on the underlying region UR. The underlying region UR and the at least one raised region RA are covered by a first region R1. The underlying region UR may include silicon. A plurality of raised regions RA are located on the underlying region UR. Recesses R1a of the first region R1 are located between the plurality of raised regions RA. Each raised region RA may form a gate region of a transistor.

[0048] The substrate W may include a mask MK. The mask MK may have an opening OPM. The mask MK is provided on the third region R3. The opening OPM corresponds to the opening OP3 in the third region R3. The mask MK may be made of any material as long as the second region R2 can be selectively etched with respect to the mask MK. The mask MK may include metal or silicon.

[0049] The substrate W prepared in step STa may have the shape shown in FIG. 7 as a result of plasma etching, or may have the shape shown in FIG. 7 from the beginning when it is provided to the plasma processing chamber 10.

[0050] Next, in the method MT, the process STb is performed as described above. In the process STb, the controller 2 controls the gas supply unit 20 to supply a processing gas into the chamber 10.

[0051] The processing gas may include a metal constituting the chemical species from the plasma and an etching component for etching the second region R2. In one example, the processing gas may include a metal-containing gas. The processing gas may include an etching component-containing gas. The processing gas may include a carbon-containing gas. The processing gas may include a hydrogen-containing gas. Also, in one example, the processing gas may include, as a metal-containing gas, at least one selected from the group consisting of a tungsten-containing gas, a molybdenum-containing gas, and a titanium-containing gas immediately before the first region R1 is exposed. In one example, the processing gas includes a halide gas as an etching component. The metal-containing gas may be a metal halide-containing gas. The etching component is a component that etches the second region R2.

[0052] The metal-containing gas may include at least one selected from the group consisting of a tungsten-containing gas, a molybdenum-containing gas, and a titanium-containing gas. The tungsten-containing gas may include a tungsten halide gas. The tungsten halide gas may be tungsten hexafluoride (WF ６ ) gas, tungsten hexabromide (WBr ６ ) gas, tungsten hexachloride (WCl ６ ) Gas and WF ５ The tungsten-containing gas may include at least one of tungsten hexacarbonyl (W(CO) ６ The molybdenum-containing gas may include a molybdenum halide gas. The molybdenum halide gas may include molybdenum hexafluoride (MoF ６ ) gas and molybdenum hexachloride (MoCl ６ The titanium-containing gas may include at least one selected from the group consisting of titanium tetrachloride (TiCl ４ ) may also be included.

[0053] The etching component-containing gas includes a halogenated gas. The halogenated gas may include at least one selected from the group consisting of a fluorine-containing gas, a chlorine-containing gas, and a bromine-containing gas. The fluorine-containing gas may include a fluorocarbon gas.

[0054] The carbon-containing gas is CH ４ Gas, C ２ H ２ Gas, C ２ H ４ Gas, CH ３ F gas, CH ２ F ２ Gas, CHF ３ The gas may include at least one selected from the group consisting of a nitrogen gas and a CO gas.

[0055] The hydrogen-containing gas is H ２ Gas, SiH ４ Gas and NH ３ The gas may include at least one selected from the group consisting of:

[0056] The process gas may further include a noble gas, such as argon gas, helium gas, xenon gas, or neon gas. ２ ) gas.

[0057] In the method MT, a process STc is then performed. In the process STc, the second region R2 is etched using a plasma PL generated from the processing gas in the chamber 10. In the process STc, the second region R2 may be etched so as to expose a shoulder portion SH of the recess R1a of the first region R1. The process STc is performed while the processing gas supplied in the process STb is present in the chamber. The process STc may also be performed during the execution of the process STb.

[0058] 6 , the cycle CY repeated in the process STc includes a first period P1, a second period P2, a third period P3, and a fourth period P4. During the first period P1, the control unit 2 controls the first RF generating unit 31a (i.e., the source high frequency power supply) to supply a source RF signal having a first power level PL1 to generate a plasma PL from the processing gas. During the first period P1, the supply of the bias signal may be stopped. During the first period P1, chemical species from the plasma PL are deposited on the surface of the substrate W to form a deposit DP. In one embodiment, the deposit DP is formed of tungsten, WF ６ The metal inclusions may include the above-mentioned metal inclusions.

[0059] The second period P2 is a period after or following the first period P1. During the second period P2, the controller 2 controls the first RF generator 31a to supply a source RF signal having a second power level PL2 to generate plasma PL from the processing gas. The second power level PL2 may be lower than the first power level PL1. During the second period P2, the supply of the bias signal may be stopped. During the second period P2, as shown in FIG. 8 , deposits DP are further formed on the surface of the substrate W, and the amount of deposits DP on the surface of the substrate W is adjusted.

[0060] The third period P3 is a period following or after the second period P2. During the third period P3, the controller 2 controls the first RF generator 31a to supply a source RF signal having a third power level PL3 to generate plasma PL from the process gas. During the third period P3, the controller 2 may control the first RF generator 31a to intermittently supply the source RF signal, as shown in FIG. 6 . The third power level PL3 may be lower than the first power level PL1. The third power level PL3 may be the same as or different from the second power level PL2. The third power level PL3 may be lower than the second power level PL2.

[0061] During the third period P3, the control unit 2 controls the bias power supply 50 to supply the first sequence VS1 to the substrate support 11. In the example of FIG. 6 , the third period P3 and the first sub-period SP1 are identical to each other. During the third period P3, ions are attracted from the plasma PL to the deposit DP. The first potential difference of the first voltage pulse VP1 in the first sequence VS1 is lower than the second potential difference of the second voltage pulse VP2 in the second sequence VS2. The voltage level of the first voltage pulse VP1 in the first sequence VS1 is set so that the ions attracted from the plasma PL to the deposit DP modify the deposit DP and / or adjust the profile of the deposit DP.

[0062] The fourth period P4 is a period following or following the third period P3. During the fourth period P4, the control unit 2 controls the first RF generating unit 31a to set the power level of the source RF signal to a fourth power level PL4. The fourth power level PL4 may be lower than the first power level PL1. The fourth power level PL4 may be the same as the second power level PL2 and the third power level PL3, or may be different from the second power level PL2 and / or the third power level PL3. The fourth power level PL4 may be lower than the second power level PL2. The fourth power level PL4 may be the same as the third power level PL3.

[0063] Furthermore, during the fourth period P4, the control unit 2 controls the bias power supply 50 to supply the second sequence VS2 to the substrate support 11. In the example of FIG. 6, the fourth period P4 and the second sub-period SP2 are identical to each other. The second potential difference of the second voltage pulse VP2 in the second sequence VS2 is greater than the first potential difference of the first voltage pulse VP1 in the first sequence VS1. The second potential difference of the second voltage pulse VP2 in the second sequence VS2 is set to promote etching of the second region R2. During the fourth period P4, the second sequence VS2 of the second voltage pulse VP2, which monochromatizes the ion energy distribution, is used as the bias signal, so that the second region R2 can be etched to form a recess with high verticality (see FIG. 9 ).

[0064] Reference will now be made to FIG. 10 . FIG. 10 is a timing chart of another example related to a plasma processing method according to an exemplary embodiment. The example of FIG. 10 will be described below in terms of differences from the example of FIG. 6 . As shown in FIG. 10 , in another example of the method MT, the control unit 2 controls the bias power supply 50 and the first RF generation unit 31a to supply a first sequence VS1 of first voltage pulses VP1 alternately with the source RF signal during a third period P3. Note that in the example of FIG. 10 , the third period P3 includes multiple first sub-periods SP1. During the third period P3 of the example of FIG. 10 , the deposit DP is also modified, and the profile of the deposit DP is adjusted.

[0065] Reference is now made to FIG. 11 , which is a timing chart of yet another example related to a plasma processing method according to an exemplary embodiment. The example of FIG. 11 will be described below in terms of differences from the example of FIG. 6 . As shown in FIG. 11 , in yet another example of the method MT, the control unit 2 controls the bias power supply 50 and the first RF generating unit 31a to alternately supply a second sequence VS2 of second voltage pulses VP2 with a source RF signal and a first sequence VS1 of first voltage pulses VP1 during a third period P3. Note that in the example of FIG. 11 , the third period P3 includes another repeated cycle CYA. The cycle CYA includes a first sub-period SP1 and a second sub-period SP2. In the cycle CYA, the first sub-period SP1 and the second sub-period SP2 may be consecutive to each other. During the first sub-period SP1 within the cycle CYA, the deposit DP is modified. In the second sub-period SP2 within the cycle CYA, the profile of the deposit DP is adjusted and the deposit DP at the bottom of the recess in the second region R2 is removed. Note that in the example of Figure 11, the cycle CY does not have to include the second period P2. In this case, the third period P3 follows the first period P1.

[0066] Reference will now be made to FIG. 12 . FIG. 12 is a timing chart of yet another example related to a plasma processing method according to an exemplary embodiment. The example of FIG. 12 will be described below in terms of differences from the example of FIG. 10 . As shown in FIG. 12 , in yet another example of the method MT, the controller 2 may control the second RF generator 31b to supply a bias RF signal to the substrate support 11 during the second period P2. The amount of deposits DP on the surface of the substrate W is also adjusted during the second period P2 in the example of FIG. 12 . Note that the supply of the bias RF signal may be stopped during the first period P1, the third period P3, and the fourth period P4.

[0067] 12, the control unit 2 may control the first RF generation unit 31a to stop supplying the source RF signal during a fourth period P4. During the fourth period P4 in the example shown in Fig. 12, ions from the plasma generated during the third period P3 and remaining in the chamber 10 are attracted to the substrate W, thereby etching the second region R2.

[0068] Examples of processing circuits that can be used as one or more processing circuits in the plasma processing apparatus 1, such as the control unit 2, are described below. FIG. 13 is a block diagram of a processing circuit that performs the operations described herein on a computer. FIG. 13 illustrates a processing circuit 130 that can be used to control a control process on any computer. The descriptions or blocks in the flowcharts represent modules, segments, or portions of code that include one or more executable instructions for implementing specific logical functions or steps of the process. As will be understood by those skilled in the art, other examples having functions that can be performed in a different order than that shown or described, such as substantially concurrently or in reverse order, depending on the functionality involved, are included within the scope of exemplary embodiments of the present disclosure. The various elements, features, and processes described herein may be used independently of each other or combined in various ways. All conceivable combinations and subcombinations are within the scope of the present disclosure.

[0069] In Figure 13, processing circuitry 130 includes a CPU 1200 that performs one or more of the control processes described above and / or below. Process data and instructions may be stored in memory 1202. These process data and instructions may be stored on a storage medium disk 1204, such as a hard disk drive (HDD) or a portable storage medium, or may be stored remotely. Furthermore, the claimed disclosure is not limited by the form of computer-readable medium on which instructions for processes according to the present invention are stored. For example, these instructions may be stored on a CD, DVD, flash memory, RAM, ROM, PROM, EPROM, EEPROM, hard disk, or any other information processing device, such as a server and / or computer, with which processing circuitry 130 communicates.

[0070] Furthermore, the claimed disclosure may be provided as a utility application, a background daemon, a component of an operating system, or a combination thereof, and may execute in conjunction with CPU 1200 and an operating system known to those skilled in the art, such as Microsoft Windows®, UNIX®, Solaris®, LINUX®, Apple MAC-OS, etc.

[0071] The hardware elements making up the processing circuit 130 can be realized by various circuit elements. Furthermore, each function of the above-described embodiments can be implemented by a circuit including one or more processing circuits. As shown in FIG. 13, the processing circuit includes a specifically programmed processing unit, such as a processing unit (CPU) 1200. The processing circuit also includes devices such as application specific integrated circuits (ASICs) or conventional circuit components configured to perform the described functions.

[0072] 13, processing circuitry 130 includes a CPU 1200 that performs the above-described processing. Processing circuitry 130 may be a general-purpose computer or a specialized machine. In one embodiment, processing circuitry 130 functions as a specialized machine when processing device 1200 is programmed to control various components of plasma processing device 1, such as gas supply 20 and power supply 30.

[0073] Alternatively or additionally, CPU 1200 may be implemented on an FPGA, ASIC, PLD, or using discrete logic circuitry, as will be appreciated by those skilled in the art. Furthermore, CPU 1200 may be implemented as multiple processing units cooperating to perform in parallel the instructions of the processes of the present invention described above.

[0074] The processing circuitry 130 of Figure 13 also includes a network controller 1206, such as an Intel Ethernet PRO network interface card from Intel Corporation of America, for interfacing with a network 1228. As can be appreciated, the network 1228 may be a public network such as the Internet, a private network such as a LAN or WAN, or any combination thereof, and may also include sub-networks such as PSTN or ISDN. The network 1228 may also be wired, such as an Ethernet network, or wireless, such as a cellular network including EDGE, 3G, and 4G wireless cellular systems. The wireless network may also be Wi-Fi, Bluetooth, or any other known form of wireless communication.

[0075] The processing circuitry 130 further includes a display device controller 1208, such as a graphics card or graphics adapter, for interfacing with a display device 1210, such as a monitor. A general-purpose I / O interface 1212 interfaces with a keyboard and / or mouse 1214 and a touch panel 1216, which may be integral with or separate from the display device 1210. The general-purpose I / O interface also connects to various peripheral devices 1218, such as printers and scanners.

[0076] The storage controller 1224 is connected to the storage media disk 1204 via a communication bus 1226, such as ISA, EISA, VESA, PCI, etc., and all components of the processing circuit 130 are connected to each other. The display device 1210, keyboard and / or mouse 1214, and the general features and functions of the display device controller 1208, storage controller 1224, network controller 1206, audio controller 1220, and general purpose I / O interface 1212 are not described herein for the sake of brevity, as they are well known.

[0077] The exemplary circuit elements described in this disclosure may be substituted with other elements and may have different structures than the examples described herein. Furthermore, circuits configured to implement the features described herein may be implemented in multiple circuit units (e.g., chips), or these features may be combined into the circuitry of a single chipset.

[0078] The functions and features described herein may also be performed by various distributed components on a system. For example, one or more processing devices may perform the functions of these systems, where the processing devices are distributed across multiple components communicating within a network. Distributed components may include various human interface and communication devices (e.g., display monitors, smartphones, tablets, personal digital assistants (PDAs)), as well as one or more client and server machines that can share processing. The network may be a private network, such as a LAN or WAN, or a public network, such as the Internet. Input to the system may be received directly by a user or remotely in real time or as a batch process. Furthermore, portions of the embodiments may be implemented on modules or hardware other than those described above. Accordingly, other embodiments are within the scope of the claims.

[0079] Although various exemplary embodiments have been described above, the present invention is not limited to the above-described exemplary embodiments, and various additions, omissions, substitutions, and modifications may be made. Furthermore, elements in different embodiments may be combined to form other embodiments.

[0080] Various exemplary embodiments included in the present disclosure are now described in [E1] to [E20] below.

[0081] a first conversion circuit configured to generate a first DC voltage from an input DC voltage; a second conversion circuit configured to generate a second DC voltage from the input DC voltage; a first pulse generation circuit configured to periodically pulse the first DC voltage in a first sub-period within a repeating period to generate a first sequence of first voltage pulses having a first potential difference with respect to a reference potential as the bias signal; and a second pulse generation circuit configured to periodically pulse the second DC voltage in a second sub-period within the period to generate a second sequence of second voltage pulses having a second potential difference with respect to the reference potential as the bias signal, the second potential difference being different from the first potential difference.

[0082] [E2] The plasma processing apparatus according to E1, wherein the bias power supply further includes a control circuit configured to output a synchronization signal synchronized with the first sub-period to the first pulse generating circuit and to output a synchronization signal synchronized with the second sub-period to the second pulse generating circuit.

[0083] [E3] The plasma processing apparatus according to E1 or E2, wherein the first sub-period and the second sub-period are continuous.

[0084] [E4] The plasma generating unit further comprises a controller, wherein the plasma generating unit includes an RF generating unit configured to supply a source RF signal to generate the plasma, and the controller controls the RF generating unit and the bias power supply to: supply the source RF signal having a first power level from the RF generating unit during a first period within the period; supply the source RF signal having a second power level lower than the first power level from the RF generating unit during a second period within the period after the first period; supply the source RF signal having a third power level lower than the first power level from the RF generating unit during a third period within the period after the second period, the third period including the first sub-period; and supply the first sequence of first voltage pulses to the substrate support; the source RF signal having a fourth power level that is lower than the first power level is supplied from the RF generating unit, and the second sequence of the second voltage pulses having the second potential difference that is greater than the first potential difference is supplied to the substrate support unit during a fourth period in the cycle after the third period and including the second sub-period.

[0085] [E5] The plasma processing apparatus according to E4, wherein the control unit is configured to control the RF generation unit to intermittently supply the source RF signal during the third period.

[0086] [E6] The plasma processing apparatus according to E5, wherein the control unit is configured to control the bias power supply to supply the first sequence of the first voltage pulses alternately with the source RF signal during the third time period.

[0087] [E7] The plasma processing apparatus of E5, wherein the control unit is configured to control the bias power supply to supply the second sequence of the second voltage pulses alternately with the source RF signal and the first sequence of the first voltage pulses during the third period.

[0088] [E8] The plasma processing apparatus according to any one of E4 to E7, wherein the second power level is greater than the third power level and the fourth power level.

[0089] [E9] The plasma processing apparatus according to any one of E1 to E8, wherein the period has a time length that is the reciprocal of a frequency of 10 Hz or more and 50 kHz or less.

[0090] [E10] The plasma processing apparatus according to any one of E1 to E9, wherein the first pulse generating circuit and the second pulse generating circuit are configured to generate the first voltage pulse in the first sequence and the second voltage pulse in the second sequence at time intervals having a time length that is the reciprocal of a frequency of 100 kHz or more and 400 kHz or less.

[0091] [E11] A bias power supply comprising: a first conversion circuit configured to generate a first DC voltage from an input DC voltage; a second conversion circuit configured to generate a second DC voltage from the input DC voltage; a first pulse generation circuit electrically coupled to a substrate support in a chamber of a plasma processing apparatus, the first pulse generation circuit configured to periodically pulse the first DC voltage in a first sub-period within a repeating period to generate a first sequence of first voltage pulses having a first potential difference with respect to a reference potential as a bias signal for attracting ions from the plasma to a substrate on the substrate support; and a second pulse generation circuit electrically coupled to the substrate support, the second pulse generation circuit configured to periodically pulse the second DC voltage in a second sub-period within the period to generate a second sequence of second voltage pulses having a second potential difference with respect to the reference potential as the bias signal, the second potential difference being different from the first potential difference.

[0092] [E12] The bias power supply according to E11, further including a control circuit configured to output a synchronization signal synchronized with the first sub-period to the first pulse generating circuit and to output a synchronization signal synchronized with the second sub-period to the second pulse generating circuit.

[0093] [E13] The bias power supply according to E11 or E12, wherein the first sub-period and the second sub-period are continuous.

[0094] [E14] The bias power supply according to any one of E11 to E13, wherein the period has a time length that is the reciprocal of a frequency that is equal to or greater than 10 Hz and equal to or less than 50 kHz.

[0095] [E15] The bias power supply according to any one of E11 to E14, wherein the first pulse generation circuit and the second pulse generation circuit are configured to generate the first voltage pulse in the first sequence and the second voltage pulse in the second sequence at time intervals having a time length that is the reciprocal of a frequency that is equal to or greater than 100 kHz and equal to or less than 400 kHz.

[0096] [E16] A method for etching a substrate on a substrate support in a chamber of a plasma processing apparatus, comprising: (a) providing a substrate on a substrate support in a chamber of the plasma processing apparatus; (b) supplying a process gas into the chamber; and (c) etching the substrate using plasma generated from the process gas in the chamber, the plasma processing apparatus comprising: the chamber; the substrate support; a plasma generation unit configured to generate plasma from a gas in the chamber; and a bias power supply electrically coupled to the substrate support and configured to generate a bias signal for attracting ions from the plasma to a substrate on the substrate support, the bias power supply comprising: a first conversion circuit configured to generate a first DC voltage from an input DC voltage; a second conversion circuit configured to generate a second DC voltage from the input DC voltage; and a first pulse generation circuit configured to periodically pulse the first DC voltage in a first sub-period within a repeating period to generate a first sequence of first voltage pulses having a first potential difference with respect to a reference potential as the bias signal. a second pulse generating circuit configured to periodically pulse the second DC voltage during a second sub-period within the period to generate, as the bias signal, a second sequence of second voltage pulses having a second potential difference with respect to the reference potential, the second potential difference being different from the first potential difference; wherein the first sequence of first voltage pulses is supplied to the substrate support from the first pulse generating circuit during the first sub-period within the period repeated during execution of (c); and the second sequence of second voltage pulses is supplied to the substrate support from the second pulse generating circuit during the second sub-period within the period repeated during execution of (c).

[0097] [E17] The plasma generating unit includes an RF generating unit configured to supply a source RF signal to generate the plasma, and the substrate includes a first region containing silicon and nitrogen and a second region containing silicon and oxygen, and (c) includes: (c1) supplying the source RF signal having a first power level from the RF generating unit during a first period within the cycle to generate the plasma from the processing gas; and (c2) supplying the source RF signal having a second power level lower than the first power level from the RF generating unit during a second period within the cycle after the first period to deposit chemical species from the plasma generated from the processing gas onto the substrate to form a deposit on the substrate. (c3) during a third period in the cycle after the second period and including the first sub-period, supplying the source RF signal having a third power level lower than the first power level and supplying the first sequence of the first voltage pulses to the substrate support, to modify the deposit with chemical species from the plasma generated from the process gas; and (c4) during a fourth period in the cycle after the third period and including the second sub-period, supplying the source RF signal having a fourth power level lower than the first power level and supplying the second sequence of the second voltage pulses to the substrate support, to etch the second region with chemical species from the plasma generated from the process gas.

[0098] [E18] The plasma processing method according to E17, wherein (c3) includes intermittently supplying the source RF signal from the RF generating unit during the third period.

[0099] [E19] The plasma processing method according to E18, wherein (c3) includes supplying a first sequence of the first voltage pulses from the bias power supply alternating with the source RF signal during the third time period.

[0100] [E20] The plasma processing method of E19, wherein (c3) includes supplying the second sequence of the second voltage pulses alternating with the source RF signal and the first sequence of the first voltage pulses during the third time period.

[0101] From the foregoing, it will be understood that various embodiments of the present disclosure have been described herein for purposes of illustration, and that various modifications may be made without departing from the scope and spirit of the present disclosure. Accordingly, the various embodiments disclosed herein are not intended to be limiting, with the true scope and spirit being indicated by the appended claims.

[0102] 1...plasma processing apparatus, 10...chamber, 11...substrate support part, 12...plasma generation part, 50...bias power supply, 521...first conversion circuit, 522...second conversion circuit, 541...first pulse generation circuit, 542...second pulse generation circuit.

Claims

1. A plasma processing apparatus comprising: a chamber; a substrate support within the chamber; a plasma generation unit configured to generate a plasma from a gas within the chamber; and a bias power supply electrically coupled to the substrate support and configured to generate a bias signal to attract ions from the plasma to a substrate on the substrate support, wherein the bias power supply includes: a first conversion circuit configured to generate a first DC voltage from an input DC voltage; a second conversion circuit configured to generate a second DC voltage from the input DC voltage; a first pulse generation circuit configured to periodically pulse the first DC voltage in a first sub-period within a repeating period to generate a first sequence of first voltage pulses having a first potential difference with respect to a reference potential as the bias signal; and a second pulse generation circuit configured to periodically pulse the second DC voltage in a second sub-period within the period to generate a second sequence of second voltage pulses having a second potential difference with respect to the reference potential as the bias signal, the second potential difference being different from the first potential difference.

2. The plasma processing apparatus of claim 1, wherein the bias power supply further includes a control circuit configured to output a synchronization signal synchronized with the first sub-period to the first pulse generating circuit and to output a synchronization signal synchronized with the second sub-period to the second pulse generating circuit.

3. The plasma processing apparatus according to claim 1, wherein the first sub-period and the second sub-period are continuous.

4. A control unit is further provided, wherein the plasma generation unit includes an RF generation unit configured to supply a source RF signal to generate the plasma, and the control unit controls the RF generation unit and the bias power supply to: supply the source RF signal having a first power level from the RF generation unit during a first period within the period; supply the source RF signal having a second power level lower than the first power level from the RF generation unit during a second period within the period after the first period; supply the source RF signal having a third power level lower than the first power level from the RF generation unit during a third period within the period after the second period, the third period including the first sub-period; and supply the first sequence of first voltage pulses to the substrate support; 4. The plasma processing apparatus according to claim 1, wherein, in a fourth period in the cycle after the third period and including the second sub-period, the source RF signal having a fourth power level lower than the first power level is supplied from the RF generating unit, and the second sequence of the second voltage pulses having the second potential difference greater than the first potential difference is supplied to the substrate support.

5. The plasma processing apparatus according to claim 4, wherein the control unit is configured to control the RF generating unit so as to supply the source RF signal intermittently during the third period.

6. The plasma processing apparatus of claim 5, wherein the control unit is configured to control the bias power supply to supply the first sequence of the first voltage pulses alternately with the source RF signal during the third period.

7. The plasma processing apparatus of claim 5, wherein the control unit is configured to control the bias power supply to supply the second sequence of the second voltage pulses alternately with the source RF signal and the first sequence of the first voltage pulses during the third period.

8. The plasma processing apparatus of claim 4, wherein the second power level is greater than the third power level and the fourth power level.

9. The plasma processing apparatus according to any one of claims 1 to 3, wherein the period has a time length that is the reciprocal of a frequency that is 10 Hz or more and 50 kHz or less.

10. A plasma processing apparatus according to any one of claims 1 to 3, wherein the first pulse generating circuit and the second pulse generating circuit are configured to generate the first voltage pulse in the first sequence and the second voltage pulse in the second sequence at time intervals having a time length that is the reciprocal of a frequency of 100 kHz or more and 400 kHz or less.

11. A bias power supply comprising: a first conversion circuit configured to generate a first DC voltage from an input DC voltage; a second conversion circuit configured to generate a second DC voltage from the input DC voltage; a first pulse generation circuit electrically coupled to a substrate support in a chamber of a plasma processing apparatus and configured to periodically pulse the first DC voltage during a first sub-period within a repeating period to generate a first sequence of first voltage pulses having a first potential difference with respect to a reference potential as a bias signal for attracting ions from a plasma to a substrate on the substrate support; and a second pulse generation circuit electrically coupled to the substrate support and configured to periodically pulse the second DC voltage during a second sub-period within the period to generate a second sequence of second voltage pulses having a second potential difference with respect to the reference potential as the bias signal, the second potential difference being different from the first potential difference.

12. The bias power supply of claim 11, further comprising a control circuit configured to output a synchronization signal synchronized with the first sub-period to the first pulse generating circuit and to output a synchronization signal synchronized with the second sub-period to the second pulse generating circuit.

13. The bias power supply of claim 11, wherein the first sub-period and the second sub-period are consecutive.

14. A bias power supply according to any one of claims 11 to 13, wherein the period has a time length that is the reciprocal of a frequency that is equal to or greater than 10 Hz and equal to or less than 50 kHz.

15. A bias power supply as claimed in any one of claims 11 to 13, wherein the first pulse generating circuit and the second pulse generating circuit are configured to generate the first voltage pulse in the first sequence and the second voltage pulse in the second sequence, respectively, at time intervals having a time length that is the reciprocal of a frequency that is equal to or greater than 100 kHz and equal to or less than 400 kHz.

16. A plasma processing apparatus comprising: (a) providing a substrate on a substrate support in a chamber of a plasma processing apparatus; (b) supplying a process gas into the chamber; and (c) etching the substrate using plasma generated from the process gas in the chamber, the plasma processing apparatus comprising: the chamber; the substrate support; a plasma generation unit configured to generate a plasma from a gas in the chamber; and a bias power supply electrically coupled to the substrate support and configured to generate a bias signal for attracting ions from the plasma to a substrate on the substrate support, the bias power supply comprising: a first conversion circuit configured to generate a first DC voltage from an input DC voltage; a second conversion circuit configured to generate a second DC voltage from the input DC voltage; and a first pulse generation circuit configured to periodically pulse the first DC voltage in a first sub-period within a repeating period to generate a first sequence of first voltage pulses having a first potential difference with respect to a reference potential as the bias signal. a second pulse generating circuit configured to periodically pulse the second DC voltage during a second sub-period within the period to generate, as the bias signal, a second sequence of second voltage pulses having a second potential difference with respect to the reference potential, the second potential difference being different from the first potential difference; wherein the first sequence of first voltage pulses is supplied to the substrate support from the first pulse generating circuit during the first sub-period within the period repeated during execution of (c); and the second sequence of second voltage pulses is supplied to the substrate support from the second pulse generating circuit during the second sub-period within the period repeated during execution of (c).

17. The plasma generating unit includes an RF generating unit configured to supply a source RF signal to generate the plasma, and the substrate includes a first region containing silicon and nitrogen and a second region containing silicon and oxygen, and (c) includes: (c1) supplying the source RF signal having a first power level from the RF generating unit during a first period within the cycle to generate the plasma from the processing gas; and (c2) supplying the source RF signal having a second power level lower than the first power level from the RF generating unit during a second period within the cycle after the first period to deposit chemical species from the plasma generated from the processing gas onto the substrate to form a deposit on the substrate.

17. The plasma processing method of claim 16, further comprising: (c3) supplying the source RF signal having a third power level lower than the first power level from the RF generator during a third period in the cycle after the second period and including the first sub-period, and supplying the first sequence of the first voltage pulses to the substrate support, to modify the deposit with chemical species from the plasma generated from the process gas; and (c4) supplying the source RF signal having a fourth power level lower than the first power level from the RF generator during a fourth period in the cycle after the third period and including the second sub-period, and supplying the second sequence of the second voltage pulses to the substrate support, to etch the second region with chemical species from the plasma generated from the process gas.

18. The plasma processing method according to claim 17, wherein (c3) includes intermittently supplying the source RF signal from the RF generating unit during the third period.

19. The plasma processing method of claim 18, wherein (c3) includes supplying a first sequence of the first voltage pulses from the bias power supply alternating with the source RF signal during the third time period.

20. The plasma processing method of claim 19, wherein (c3) includes supplying the second sequence of the second voltage pulses alternating with the source RF signal and the first sequence of the first voltage pulses during the third period.

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