Method for manufacturing power semiconductor device by using two-step thinning process

Abstract

The present invention relates to a method for manufacturing a power semiconductor device by using a two-step thinning process, and to a method for manufacturing a power semiconductor device by using a two-step thinning process in which a support substrate having a high heat dissipation capacity is formed on a sapphire growth substrate thinned in two steps, thereby enabling the performance and reliability of the power semiconductor device to be improved.

Description

Method for manufacturing power semiconductor devices using a two-step thinning process

[0001] The present invention relates to a method for manufacturing a power semiconductor device using a two-step thinning process, and more specifically, to a method for manufacturing a power semiconductor device using a two-step thinning process, which can improve the performance and reliability of a power semiconductor device by forming a support substrate having high heat dissipation capability on a sapphire growth substrate thinned in two steps.

[0002] In the conventional group III nitride (GaN material) power semiconductor HEMT device structure, a GaN buffer layer is typically formed by heavily doping impurities such as iron (Fe) or carbon (C) to have high resistance in order to suppress leakage current under the GaN channel layer.

[0003] However, according to the conventional group III nitride (GaN material) power semiconductor HEMT device structure, there is a problem that the crystal quality of the GaN material is greatly degraded due to excessive doping of impurities such as iron (Fe) or carbon (C), and it promotes an increase in leakage current due to a fatal crystal defect, that is, an increase in dislocation density. In addition, there is a problem that the GaN channel layer and AlGaN barrier layer grown on top of the GaN buffer layer with low crystal quality also have low crystal quality.

[0004] Accordingly, in order to improve the crystal quality, the GaN on Sapphire method, which has the next best crystal quality after the power semiconductor devices manufactured by the GaN on GaN method, is widely used, and the epitaxial film deposition technology for the method has already been developed and matured. However, the only drawback of the GaN on Sapphire method is that the heat dissipation performance of sapphire is poor, which limits its application to high-power products. In other words, the performance and reliability of GaN HEMT devices are sensitive to the heat dissipation performance characteristics of the final support substrate.

[0005] To overcome this, high-output products have been developed using SiC and Si growth substrates with high heat dissipation, but they are inferior to epitaxy grown on sapphire growth substrates in terms of performance, crystal quality, defects, and cost.

[0006] Furthermore, when manufacturing a power semiconductor device by completely separating and removing the growth substrate and directly bonding a high-heat dissipation support substrate such as a polycrystalline diamond thick film to a semiconductor layer (e.g., a GaN HEMT active layer), there is an advantage that the heat dissipation performance of the power semiconductor device can be significantly improved, but there is a problem in terms of device reliability because micro-cracks are created in the semiconductor layer due to the residual stress relief caused by removing the growth substrate.

[0007] The purpose of the present invention is to solve the above-described conventional problems, and to provide a method for manufacturing a power semiconductor device using a two-step thinning process, which can improve the performance and reliability of the power semiconductor device by forming a support substrate having high heat dissipation performance on a two-step thinned sapphire growth substrate.

[0008] The present invention is achieved by a method for manufacturing a power semiconductor device using a two-step thinning process, comprising: a growth step of growing a semiconductor layer on a growth substrate; a fab step of performing a fabrication (FAB) process on the grown semiconductor layer; a first polishing step of polishing the growth substrate to form a first thickness; a chip step of cutting the polished growth substrate into chip units to manufacture chips; an adhesion step of bonding the chip to a temporary substrate so that the semiconductor layer of the manufactured chip faces the temporary substrate; a second polishing step of polishing the growth substrate of the chip to form a second thickness; and a forming step of forming a support substrate on the polished growth substrate.

[0009] Additionally, the first thickness may be less than 100 μm.

[0010] Additionally, the second thickness may be less than 50 μm.

[0011] In addition, after the chip step, a first classification step of measuring and classifying the performance of the chip may be further included, and after the forming step, a second classification step of measuring and classifying the performance of the chip may be further included.

[0012] Additionally, the semiconductor layer may include at least one of a buffer layer, a channel layer, and a barrier layer.

[0013] Additionally, the bonding step can bond the chip to the temporary substrate using a pick and place device.

[0014] According to the present invention, by forming a growth substrate into an ultrathin shape without completely removing the growth substrate, and then forming a support substrate having high heat dissipation capability on the ultrathin-shaped growth substrate, the performance and reliability of a power semiconductor device can be significantly improved, and a cost-effective power semiconductor device can be manufactured.

[0015] In addition, according to the present invention, since the polishing step is performed in two steps, the growth substrate is already cut when cutting the support substrate, so only the support substrate needs to be cut, and thus there is an effect of being able to easily cut (diced) into a single chip without process or quality issues.

[0016] Meanwhile, the effects of the present invention are not limited to the effects mentioned above, and various effects may be included within a range obvious to those skilled in the art from the contents described below.

[0017] FIG. 1 is a flowchart of a method for manufacturing a power semiconductor device using a two-step thinning process according to one embodiment of the present invention.

[0018] FIG. 2 and FIG. 3 illustrate a process of manufacturing a power semiconductor device according to a method for manufacturing a power semiconductor device using a two-step thinning process according to one embodiment of the present invention.

[0019] FIG. 4 illustrates a second polishing step or forming step of a method for manufacturing a power semiconductor device using a two-step thinning process according to one embodiment of the present invention.

[0020] Hereinafter, some embodiments of the present invention will be described in detail with reference to exemplary drawings. When designating components in each drawing, it should be noted that, where possible, identical components are given the same reference numerals, even if they appear in different drawings.

[0021] In addition, when describing an embodiment of the present invention, if a detailed description of a related known configuration or function is judged to hinder understanding of the embodiment of the present invention, the detailed description is omitted.

[0022] Additionally, when describing components of embodiments of the present invention, terms such as first, second, A, B, (a), (b), etc. may be used. These terms are only intended to distinguish the components from other components, and the nature, order, or sequence of the components are not limited by the terms.

[0023]

[0024] From now on, with reference to the attached drawings, a method (S100) for manufacturing a power semiconductor device using a two-step thinning process according to one embodiment of the present invention will be described in detail.

[0025] FIG. 1 is a flowchart of a method for manufacturing a power semiconductor device using a two-step thinning process according to an embodiment of the present invention, FIGS. 2 and 3 illustrate a process for manufacturing a power semiconductor device using a two-step thinning process according to an embodiment of the present invention, and FIG. 4 illustrates a second polishing step or forming step of a method for manufacturing a power semiconductor device using a two-step thinning process according to an embodiment of the present invention.

[0026] As illustrated in FIGS. 1 to 3, a method (S100) for manufacturing a power semiconductor device using a two-step thinning process according to one embodiment of the present invention includes a growth step (S110), a fab step (S120), a first polishing step (S130), a chip step (S140), a first sorting step (S150), a bonding step (S160), a second polishing step (S170), a forming step (S180), and a second sorting step (S190).

[0027] The growth stage (S110) is a stage in which a semiconductor layer (120) is grown on a growth substrate (110).

[0028] Here, the growth substrate (110) is provided as a sapphire substrate so that a high-quality semiconductor layer (120) can be grown. This sapphire substrate is an optically transparent substrate with high-temperature heat resistance, and can be provided as α-phase Al2O3 sapphire (including ScAlMgO4), etc. In addition, it is preferable that the growth substrate (110) have a protrusion shape that is regularly or irregularly patterned in various dimensions (size and shape) in the micro-scale or nano-scale in order to minimize crystal defects such as dislocations within the thin film of the group III nitride semiconductor layer (120) grown on the upper portion.

[0029] More specifically, the semiconductor layer (120) formed of a group III nitride semiconductor includes at least one of a buffer layer (121), a channel layer (122), and a barrier layer (123), and may be a multilayer structure in which the buffer layer (121), the channel layer (122), and the barrier layer (123) are sequentially stacked on a growth substrate (110).

[0030] The group III nitride semiconductor layer (120) may be composed of a single layer or multiple layers of group III nitride semiconductors, and may be composed of AlN, AlGaN, GaN, AlGaN / GaN SLs, AlN / GaN SLs, AlGaN / AlN SLs, InGaN, InAlN, GaN / InAlN, AlScN, GaN / AlScN, etc., which have high temperature (HT) and high resistance (HR) characteristics. In this group III nitride semiconductor layer (120), reducing the density of a fatal crystal defect, i.e., a threading dislocation (existing in a vertical direction with respect to the initial growth substrate (110)) is a critical quality factor (≤ Low 10 8 / ㎠).

[0031] In addition, the topmost layer region of the group III nitride semiconductor layer (120) is a p-type group III semiconductor containing a magnesium (Mg) dopant that injects positive holes, or includes a SiNx protective layer formed inside the MOCVD reactor to suppress surface damage in the subsequent subsequent device manufacturing process.

[0032] In general, in the case of a power semiconductor having a horizontal channel structure such as a HEMT device, the semiconductor layer (120) is composed of a channel layer (122) having a relatively small energy band gap and a barrier layer (123) having a relatively large energy band gap. For example, in the present embodiment, the buffer layer (121) of the group III nitride semiconductor layer (120) may be formed of GaN or AlN, the channel layer (122) may be formed of GaN (3.42 eV), and the barrier layer (123) may be formed of AlGaN (3.45-6.2 eV).

[0033] Meanwhile, in order to achieve high quality and high performance of the channel layer (122) and the barrier layer (123), it is generally desirable to grow a nucleation layer region (not shown) to form a group III nitride semiconductor layer (120) on a sapphire growth substrate (110). The nucleation layer region is composed of aluminum nitride (AlN), aluminum gallium nitride (AlGaN), gallium nitride (GaN), etc. It is important to first grow a high quality, high-resistivity buffer layer (121) on the nucleation region. The high-resistivity buffer layer (121) can be formed of carbon or iron-doped GaN (C-doped GaN or Fe-doped GaN), an AlN thick film, an Al-rich AlGaN thick film, etc., and the channel layer (122) can be formed of GaN, and the barrier layer (123) can be formed of AlGaN, AlScN, InAlN. And in the present invention, a p-type group III semiconductor region (e.g., pGaN, pAlGaN, pInAlN) may be provided on the upper portion depending on the operation mode (Normally-Off or Normally-On) of the gate electrode (G), and in order to improve reliability, a SiNx passivation layer (P) or an AlN or GaN thin film may be formed on the upper portion of the semiconductor layer (120) as a capping layer.

[0034] The Fab stage (S120) is a stage in which the dimensions of the power semiconductor device are designed on the grown semiconductor layer (120) and various processes including electrode formation are performed.

[0035] Specifically, the fab step (S120) is a step of etching the semiconductor layer (120) if necessary depending on the device structure such as a HEMT (High Electron Mobility Transistor), a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), or a JFET (Junction Field Effect Transistor), and then forming a plurality of electrodes electrically connected to the semiconductor layer (120). In the case of a HEMT, a source electrode (S) and a drain electrode (D), which are Ohmic contact electrodes, are formed, and a gate electrode (G), which is a Schottky contact electrode, is formed. Then, the semiconductor device can be manufactured in the form of a single chip or a multi-chip through an isolation process. In addition, when forming the source electrode (S) and the drain electrode (D), which are Ohmic contact electrodes, it is preferable to perform an annealing heat treatment process at least 800°C or higher.

[0036] The first polishing step (S130) is a step following the fab step (S120) in which the growth substrate (110) is primarily polished and formed into the first thickness.

[0037] Unlike conventional vertically structured GaN LED devices, GaN HEMT devices have high-voltage driving conditions in addition to currents of several amperes to tens of amperes. Accordingly, when a power semiconductor device is manufactured by completely separating and removing the growth substrate (110) and then directly bonding a high-heat dissipation support substrate (170), such as a polycrystalline diamond thick film, to a semiconductor layer (120) (e.g., a GaN HEMT active layer), there is an advantage that the heat dissipation performance of the power semiconductor device can be significantly improved. However, there is a problem that the reliability of the device is vulnerable because micro-cracks, etc. are generated in the semiconductor layer (120) due to residual stress relief caused by removing the growth substrate (110).

[0038] That is, the first polishing step (S130) and the second polishing step (S170) of the present invention are intended to solve the above-described problem, and unlike the conventional method, the sapphire growth substrate (110) is not completely removed, and in order to control the low heat dissipation ability of the sapphire growth substrate (110), the sapphire growth substrate (110) is formed into an ultra-thin type, and then a support substrate (170) having high heat dissipation ability is bonded or plated (electroless plating) to the ultra-thinly formed sapphire growth substrate (110), thereby improving the performance and reliability of the power semiconductor device.

[0039] At this time, in the present invention, the polishing step is divided into a first polishing step (S130) and a second polishing step (S170), and it is preferable that the first thickness of the growth substrate (110) be formed to be less than 100㎛ in the first polishing step (S130). This is to enable the sapphire growth substrate (110) to be easily cut into chip units in the chip process described later, and at the same time, to have an appropriate thickness so that it can function as a carrier sapphire substrate when the chips are adhered on a temporary substrate (160) using a pick and place device in the adhesion step (S160) described later.

[0040] The chip step (S140) is a step of manufacturing chips by cutting a thinly polished growth substrate (110) into chip units.

[0041] That is, in the chip stage (S140), the growth substrate (110) that has been polished into a thin shape through mechanical polishing, etc. is cut into isolated chip units. This is because, if the thinned sapphire growth substrate (110) is not cut in advance and a high-heat dissipation support substrate (170) is formed (bonded or plated) on the entire back surface of the sapphire top substrate, considerable difficulties arise in the process of finally cutting it into single chip units, and it becomes difficult to ensure reliability in terms of quality.

[0042] The first classification step (S150) is a step for primarily measuring and classifying the performance of the power semiconductor device chip before bonding the temporary substrate (160). That is, the first classification step (S150) is a step for measuring and classifying the characteristics of the power semiconductor device, i.e., the performance and / or reliability of the power semiconductor device, before bonding the manufactured chip to the temporary substrate (160).

[0043] The bonding step (S160) is a step of bonding the chip to the temporary substrate (160) so that the semiconductor layer (120) of the manufactured chip faces the temporary substrate (160).

[0044] Here, the temporary substrate (160) is preferably formed to have a coefficient of thermal expansion (CTE) that is equal to or similar to that of the growth substrate (110), but the difference in the coefficient of thermal expansion (CTE) with respect to the growth substrate (110) is preferably no more than 2 ppm. The material of the temporary substrate (160) is preferably sapphire with polished surfaces, and may include silicon carbide (SiC) or glass with a coefficient of thermal expansion (CTE) adjusted to have a difference of 2 ppm or less with respect to the growth substrate (110).

[0045] On the temporary substrate (160), a sacrificial layer (150) and an adhesive layer (140) for removing the temporary substrate (160) through a laser lift-off (LLO) method can be sequentially formed, and on the semiconductor layer (120), a separate protective layer (130) and an adhesive layer (140) for protecting the semiconductor layer (120) can be sequentially formed, and chips classified in the first classification step (S150) can be bonded to the temporary substrate (160) through the adhesive layer (140).

[0046] At this time, in the present invention, since a thin sapphire growth substrate (110) remains after the chip step (S140), the chips can be moved using a pick and place device using the sapphire growth substrate (110) as a carrier sapphire, and then the chips can be bonded onto a temporary substrate (160). Accordingly, there is an advantage in that the pick and place device, which is a conventional semiconductor device, can be used as is even though the process has changed.

[0047] The second polishing step (S170) is a step of polishing the chip growth substrate (110) and forming it into a second thickness.

[0048] As shown in FIG. 4, it is preferable that the second thickness of the growth substrate (110) be formed to be less than 50 ㎛. Specifically, in the second polishing step (S170), the growth substrate (110) formed to be less than 100 ㎛ in the first polishing step (S130) is precisely polished again through mechanical polishing, chemical mechanical polishing (CMP), etc., so that it can be formed into an ultra-thin type of less than 50 ㎛.

[0049] The forming step (S180) is a step of bonding a support substrate (170) to a secondarily polished growth substrate (110) or forming a film by plating (electroless plating) the support substrate (170).

[0050] Specifically, in the forming step (S180), a high heat dissipation support substrate (170) may be bonded to the back of an ultra-thin molded growth substrate (110) by a wafer bonding method, or a high heat dissipation support substrate (170) may be formed on the back of an ultra-thin molded growth substrate (110) by a metal (Cu, CuW, MoCu, etc.) plating method.

[0051] Here, the support substrate (170) can be selected from among substrates such as SiC, Si, AlNcera, or Diamond, which are suitable for the purpose of the power semiconductor device to be manufactured. Among these, the AlNcera substrate can be preferentially selected due to its advantages such as increased thickness of the laminated structure, improved composition uniformity, high heat dissipation performance, reduced cost, and IC processability due to its matching coefficient of thermal expansion with the HEMT laminated structure.

[0052] At this time, if a high-heat dissipation support substrate (170) is bonded to the back of an ultra-thinly formed growth substrate (110) by a wafer bonding method, the support substrate (170) can be cut into chip units. Since the growth substrate (110) is already cut into chip units in the chip stage (S140), only the support substrate (170) needs to be cut, so it is possible to easily cut (dicing) into a single chip without process or quality issues.

[0053] The second classification step (S190) is a step for finally measuring and classifying the performance of the chip after bonding the support substrate (170). In other words, the second classification step (S190) is a step for finally measuring and classifying the characteristics of the power semiconductor device, i.e., the performance and / or reliability of the power semiconductor device, before manufacturing the power semiconductor device product.

[0054] After the second classification step (S190), the final substrate is electrically connected to the main body through direct bonding (D / B) and / or wire bonding (W / B), and then the direct bonded or wire bonded chip is sealed with a molding compound material, thereby finally manufacturing a power semiconductor package.

[0055]

[0056] Although all components constituting the embodiments of the present invention have been described as being combined or operating in combination as one, the present invention is not necessarily limited to such embodiments. That is, within the scope of the present invention, all of the components may be selectively combined and operated in one or more combinations.

[0057] Furthermore, terms such as "include," "comprise," or "have" described above, unless specifically stated otherwise, imply that the corresponding component may be present, and therefore should be interpreted to include other components rather than excluding other components. All terms, including technical or scientific terms, have the same meaning as commonly understood by a person of ordinary skill in the art to which the present invention pertains, unless otherwise defined. Commonly used terms, such as terms defined in dictionaries, should be interpreted to be consistent with the contextual meaning of the relevant technology, and shall not be interpreted in an ideal or overly formal sense, unless explicitly defined in the present invention.

[0058] The above description is merely an example of the technical idea of ​​the present invention, and those skilled in the art will appreciate that various modifications and variations can be made without departing from the essential characteristics of the present invention.

[0059] Accordingly, the embodiments disclosed in the present invention are intended to illustrate, rather than limit, the technical concept of the present invention, and the scope of the technical concept of the present invention is not limited by these embodiments. The scope of protection of the present invention should be interpreted by the following claims, and all technical concepts within the scope equivalent thereto should be construed as being included within the scope of the present invention.

Claims

1. Growth stage of growing a semiconductor layer on a growth substrate; A fab step for performing a fabrication (FAB) process on the grown semiconductor layer; A first polishing step of polishing the growth substrate to form it into a first thickness; A chip step of manufacturing chips by cutting the polished growth substrate into chip units; A bonding step of bonding the manufactured chip to a temporary substrate so that the semiconductor layer of the manufactured chip faces the temporary substrate; A second polishing step of polishing the growth substrate of the chip to form it into a second thickness; and A method for manufacturing a power semiconductor device using a two-step thinning process, including a forming step of forming a support substrate on the polished growth substrate.

2. In claim 1, The above first thickness is, A method for manufacturing a power semiconductor device using a two-step thinning process with a thickness of less than 100㎛.

3. In claim 2, The above second thickness is, A method for manufacturing a power semiconductor device using a two-step thinning process having a thickness of less than 50㎛.

4. In claim 1, After the above chip step, Further comprising a first classification step of measuring and classifying the performance of the above chip, After the above formation stage, A method for manufacturing a power semiconductor device using a two-step thinning process, further comprising a second classification step of measuring and classifying the performance of the chip.

5. In claim 1, The above semiconductor layer, A method for manufacturing a power semiconductor device using a two-step thinning process, the method comprising at least one of a buffer layer, a channel layer, and a barrier layer.

6. In claim 1, The above bonding step is, A method for manufacturing a power semiconductor device using a two-step thinning process, wherein the chip is bonded to the temporary substrate using a pick and place device.

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