Component preparation method and system, chip product and device

Abstract

A component preparation method and system, a chip product and a device, relating to the technical field of micro-nano fabrication. The method comprises: providing a substrate having a recess, wherein a protrusion (301) is provided at the bottom of the recess; using a first solution to etch the protrusion, so as to flatten the recess (302); and depositing a conductor film layer on the substrate by evaporation to form a first component (303). In the embodiments of the present application, during a preparation process of the first component, by means of first etching the protrusion at the bottom of the recess and then depositing, on the basis of the recess subjected to flattening processing, the conductor film layer by evaporation, the probability of the conductor film layer breaking due to the protrusion is reduced, thereby effectively improving the preparation stability of the component.

Description

Component fabrication methods, systems, chip products and equipment

[0001] This application claims priority to Chinese Patent Application No. 202410987085.0, filed on July 22, 2024, entitled "Method, System, Chip Product and Equipment for Component Preparation", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of micro-nano fabrication technology, and in particular to a method, system, chip product, and equipment for fabricating components. Background Technology

[0003] Josephson junctions are currently a commonly used qubit structure. Taking superconducting quantum chips as an example, the relevant technology uses carbon tetrafluoride as the etching gas and employs dry etching technology to etch a superconducting thin film on the substrate to form a groove. Then, based on the groove, a superconductor, an insulator, and another superconductor are sequentially constructed to fabricate a Josephson junction.

[0004] However, during the dry etching process, the polymer formed by carbon tetrafluoride makes the bottom of the groove rough (e.g., uneven). Since the scale of the Josephson junction is only 200-300 nanometers, when constructing a superconductor based on the groove, the superconductor is easily broken due to the protrusion at the bottom of the groove, making the prepared Josephson junction prone to open circuits, thus resulting in low stability of the Josephson junction preparation. Summary of the Invention

[0005] This application provides a method, system, chip product, and equipment for fabricating electronic components. The technical solutions provided by this application are as follows:

[0006] According to one aspect of the embodiments of this application, a method for manufacturing electronic components is provided, the method comprising:

[0007] A substrate with a groove is provided, the bottom of which has a protrusion;

[0008] The protrusion is etched with a first solution to flatten the groove;

[0009] A conductor film is deposited on the substrate to form the first component.

[0010] According to one aspect of the embodiments of this application, a component fabrication system is provided, the system comprising: an etching machine and a vapor deposition machine;

[0011] The etching machine is used to etch the protrusions at the bottom of the grooves of a substrate with grooves using a first solution, so as to level the grooves.

[0012] The vapor deposition machine is used to vapor deposit a conductor film layer on the substrate to form a first component.

[0013] According to one aspect of the embodiments of this application, a chip product is provided, the chip product comprising a first component prepared by the method described above.

[0014] According to one aspect of the embodiments of this application, an apparatus is provided, the apparatus including a chip product, the chip product including a first component prepared by the method described above.

[0015] The technical solutions provided in this application embodiment may have the following beneficial effects:

[0016] In the fabrication process of the first component, the protrusions on the bottom of the groove used to fabricate the first component are etched away with the first solution to level the groove before the conductor film is deposited. This reduces the probability of the conductor film breaking due to the protrusions and effectively reduces the impact of the size fluctuations of the protrusions on the fabrication of the component. This helps to improve the fabrication stability of the component and thus improve the success rate of the component fabrication.

[0017] In addition, as the bumps are eliminated, the contact area between the substrate (such as the substrate's substrate) and the air is reduced, which helps to reduce the TLS (Two Level System) loss of the chip product corresponding to the substrate. Attached Figure Description

[0018] Figure 1 is a schematic diagram of a Josephson junction provided in an embodiment of this application;

[0019] Figure 2 is a schematic diagram of the effect of a protrusion on a Josephson junction according to an embodiment of this application;

[0020] Figure 3 is a flowchart of a component fabrication method provided in an embodiment of this application;

[0021] Figure 4 is a schematic diagram of the groove before leveling treatment provided in one embodiment of this application;

[0022] Figure 5 is a schematic diagram of a leveled groove provided in one embodiment of this application;

[0023] Figure 6 is a schematic diagram of the preparation of Josephson junctions based on grooves after leveling according to an embodiment of this application;

[0024] Figure 7 is a flowchart of a Josephson junction preparation method provided in an embodiment of this application;

[0025] Figure 8 is a comparative schematic diagram of the groove before and after leveling treatment provided in an embodiment of this application;

[0026] Figure 9 is a graph showing the relationship between the reflected signal and phase angle data and frequency, respectively, according to an embodiment of this application.

[0027] Figure 10 is a schematic diagram of a component fabrication system provided in an embodiment of this application;

[0028] Figure 11 is a schematic diagram of an application scenario of a solution provided in an embodiment of this application. Detailed Implementation

[0029] Before introducing the technical solutions of this application, some terms involved in this application will be explained. The following related explanations are optional and can be combined with the technical solutions of the embodiments of this application in any way, all of which fall within the protection scope of the embodiments of this application. The embodiments of this application include at least some of the following contents.

[0030] Superconducting quantum chip: refers to a chip used for superconducting quantum computing. Superconducting quantum chips can be fabricated based on superconducting thin films (such as aluminum (Al), niobium (Nb), titanium nitride (TiN), or tantalum) deposited on substrates such as silicon (Si) or sapphire Al2O3 (aluminum oxide). The first film deposited on the substrate is usually called the bottom film of the superconducting quantum chip. If the bottom film is aluminum, the chip can be called an aluminum-based superconducting quantum chip; if the bottom film is tantalum, the chip can be called a tantalum-based superconducting quantum chip, and so on. In the embodiments of this application, the substrate and the bottom film are collectively referred to as the substrate.

[0031] Superconducting quantum chips are composed of components, such as readout lines, resonant cavities, bit capacitors, control lines, air bridges, Josephson junctions, indium pillar solder joints, and deep holes. These components can also be fabricated based on superconducting thin films using processes such as photolithography.

[0032] Superconducting refers to a property of a material that, below a certain temperature, exhibits a sudden change in electrical resistance to zero and complete diamagnetism.

[0033] Airbridge: A component in superconducting quantum chips that has an arch-like structure.

[0034] Josephson junction: A component in superconducting quantum chips, it has a sandwich-like stacked structure of superconductor-insulator-superconductor, also known as a superconducting tunnel junction, where the two superconductors are connected by an insulator. A Josephson junction is generally a structure consisting of two superconductors sandwiched by a very thin barrier layer (thickness ≤ the coherence length of a Cooper pair), such as an S (Superconductor)-I (Semiconductor or Insulator)-S (Superconductor) structure, abbreviated as SIS. In a Josephson junction, superconducting electrons can tunnel from one side through a semiconductor or insulator film to the other side via the tunneling effect.

[0035] TLS (Two Level System) loss refers to the loss of the two-level system in the superconducting quantum chip material. Due to the interaction between the two-level system and the microwaves in the quantum chip, the relaxation time of the qubit is shortened.

[0036] Etching: A microfabrication process that selectively removes material using physical or chemical methods to achieve a designed structural pattern. Etching includes dry etching and wet etching. Dry etching uses plasma to etch away the parts of the material (such as superconducting thin films) to be removed, while wet etching uses an etchant to etch away the parts of the material to be removed.

[0037] In-situ: Multi-step processes are carried out in a single vacuum chamber or multiple interconnected vacuum chambers without being exposed to the atmosphere.

[0038] Photoresist: A gel-like substance that undergoes chemical changes when exposed to ultraviolet light or bombarded by an electron beam (i.e., photolithography). The irradiated or bombarded parts will also have significantly different solubility compared to the unirradiated or unbombarded parts, thus enabling the fabrication of the desired structural patterns.

[0039] Substrate: refers to the substrate on which thin films (such as tantalum films) are deposited, such as silicon (Si) and sapphire substrates mentioned above.

[0040] In some embodiments, superconducting quantum chips fabricated on silicon substrates are gaining increasing attention due to their excellent compatibility with the semiconductor field. Currently, the main processes used for etching superconducting thin films on silicon substrates are wet etching and dry etching. Wet etching, due to its poor etching directionality and large processing errors, cannot be used to process fine structures, and has now been largely replaced by dry etching.

[0041] For superconducting thin films, aluminum films, niobium films, and tantalum films are commonly used. Among them, tantalum films have been widely used in the fabrication of superconducting quantum chips due to their lower TLS losses. In the process of etching tantalum films using dry etching, the etching gas is usually sulfur hexafluoride or carbon tetrafluoride. Because sulfur hexafluoride reacts violently with silicon, it can cause significant over-etching. Therefore, sulfur hexafluoride is not suitable for etching silicon-based thin films, i.e., the substrate formed by a silicon substrate and a superconducting thin film.

[0042] In contrast, carbon tetrafluoride forms a CxFy polymer during etching, which adsorbs onto the silicon substrate, preventing over-etching of the silicon. Therefore, carbon tetrafluoride is more suitable for etching superconducting thin films on silicon substrates. However, it has been found that the presence of the polymer during etching makes the etched silicon substrate very rough, which affects the subsequent fabrication of components involving the silicon substrate, such as Josephson junctions, resonant cavities (a common design in superconducting quantum chips), and any components whose fabrication process involves the etched substrate.

[0043] Taking the Josephson junction as an example, referring to Figure 1, a schematic diagram of a Josephson junction provided in one embodiment of this application is shown. The resonant cavity 100 includes: a connector 101, a readout line 102, a resonant cavity body 103, and a Josephson junction 104. The connector 101 can connect the connector on the chip product to the pins on the sample box via wire bonding. The readout line 102 can be used to couple microwave signals into the qubits. The resonant cavity body 103 in superconducting quantum chips is often a two-dimensional resonant cavity composed of coplanar waveguides. The Josephson junction 104 has the characteristics of nonlinear inductance, which can give the circuit nonlinear energy levels for encoding the qubits. The Josephson junction 104 has a sandwich-stacked layered structure formed by superconductor-insulator-superconductor.

[0044] After etching the trenches for fabricating the Josephson junction 104 using carbon tetrafluoride, with the silicon substrate as the bottom, the polymer formed by the carbon tetrafluoride adsorbs onto the silicon substrate, resulting in uneven etching and protrusions in the silicon. This makes the bottom of the trench very rough (uneven). Since the scale of the Josephson junction (e.g., the thickness of the superconductor) is only 200–300 nanometers, the superconductor is easily affected by these protrusions and may break, making the fabricated Josephson junction prone to open circuits and thus resulting in low fabrication stability. Furthermore, the increased roughness of the trenches also increases the contact area between the silicon substrate and the air, leading to increased TLS losses.

[0045] Referring to Figure 2, a schematic diagram illustrating the effect of a protrusion on a Josephson junction according to an embodiment of this application is shown. The substrate includes a substrate 201 (such as a silicon substrate) and a bottom film 202 (such as a superconducting thin film layer in a superconducting quantum chip). The Josephson junction includes a superconductor 203, an insulator 205, and a superconductor 206, where the superconductor 203 and superconductor 206 are superconducting metal thin films (such as aluminum films). During the etching process of the grooves used to fabricate the Josephson junction on the substrate, the compounds formed by the etching gas adsorb onto the substrate 201, resulting in uneven etching of the substrate 201. For example, the substrate covered by the polymer is not etched, while the substrate not covered by the polymer is etched, thereby causing a protrusion 204 at the bottom of the groove.

[0046] For protrusions 204 with small undulations (i.e., small height), the superconductor 203 / superconductor 206 are less affected during deposition, and a good connection can still be formed without affecting the operation of the Josephson junction. However, for protrusions 204 with large undulations (i.e., large height), the superconductor 203 / superconductor 206 are more affected during deposition, and there is a certain probability of open circuit, which can lead to Josephson junction failure. As shown in region 207, the superconductor 206 is affected by the protrusion 204 corresponding to region 207 and thus open circuit.

[0047] The techniques used to obtain grooves with low surface roughness have the following drawbacks:

[0048] 1. Grooves with smaller roughness can be obtained by optimizing etching parameters, such as controlling parameters like gas flow rate, pressure, and power. However, the improvement effect of this method is limited.

[0049] 2. By applying a bias voltage to the sample (i.e., the substrate mentioned above) during the etching process using carbon tetrafluoride to rapidly remove the polymer, this method significantly increases the over-etching degree of the silicon substrate.

[0050] 3. By adding an endpoint detection function to the equipment, the equipment can detect the spectrum of the silicon substrate after the superconducting thin film has been etched, at which point the etching process stops. This function requires a sufficiently large exposed area on the silicon substrate; this method cannot be used for smaller samples or samples with small patterned areas.

[0051] The technical solution provided in this application does not require optimization of etching parameters, application of bias voltage, or addition of endpoint detection function during the component fabrication process. It can effectively remove the protrusions on the groove simply by using the first solution, thereby stably fabricating the component and improving the success rate of component fabrication.

[0052] The technical solutions provided in this application are applicable to any scenario where a conductive thin film needs to be deposited on an etched substrate, such as the fabrication of Josephson junctions on chip products (such as superconducting quantum chips, quantum chips, etc.) and the fabrication of resonant cavities. This application does not limit these scenarios.

[0053] The technical solutions provided in this application will be described below through method embodiments. For content not described in the embodiments of this application, please refer to the above embodiments, which will not be repeated here.

[0054] Please refer to Figure 3, which shows a flowchart of a component fabrication method provided in one embodiment of this application. The method may include at least one of steps 301 to 303.

[0055] Step 301, providing a base with a groove, the bottom of which has a protrusion.

[0056] In this application, the substrate can refer to a substrate with a bottom layer film deposited on it, such as a silicon substrate with a superconducting thin film deposited on it. The substrate can also refer to the substrate of the chip product to be fabricated. The chip product can be a semi-finished product in the final chip fabrication process, such as a semi-finished product for fabricating a first component, or a finished chip requiring the addition of a first component. This application does not limit the specific application in this regard. Optionally, the chip product can be at least one of the following: a superconducting quantum chip, or a quantum chip.

[0057] The substrate can be at least one of the following: a sapphire substrate or a silicon substrate. The bottom film can be at least one of the following: an aluminum film, a tantalum film, or a niobium film. The bottom film can be used to fabricate a bottom circuit, which can consist of at least one of the following: a coplanar waveguide, a readout line, a resonant cavity, a bit capacitor, a control line, an air bridge, a Josephson junction, an indium pillar solder joint, or a deep via. Optionally, the bottom circuit (such as the various components in the bottom circuit) can be fabricated by photolithography-development-deposition. Alternatively, the bottom circuit (such as the various components in the bottom circuit) can also be fabricated by film deposition-photolithography-etching. Alternatively, the bottom circuit (such as the various components in the bottom circuit) can also be fabricated by nanoimprint lithography; this embodiment of the application does not limit this method.

[0058] A groove can refer to a recessed groove on the substrate surface, and the substrate surface can refer to the surface of the underlying film, such as the surface of a superconducting thin film. In the embodiments of this application, the aforementioned groove can refer to a groove formed by etching away a portion of the substrate, and the surface exposed by the etching forms a new surface of the substrate, such as the etched and exposed substrate surface or the etched and exposed underlying film surface. The aforementioned groove is used to fabricate a first component, that is, the first component can be referred to as a recessed component. The embodiments of this application do not limit the first component, which can be such as a Josephson junction, a resonant cavity, or any component that requires the deposition of a conductive thin film on the etched substrate.

[0059] The depth of the groove can be determined based on the dimensions of the first component. For example, the depth of the groove can be determined based on the thickness of the first component, and the length of the groove can be determined based on the length of the first component. Taking a Josephson junction as an example, the depth of the groove can be determined based on the thickness of the superconductor in the Josephson junction, such as the groove depth being the same as the thickness of the superconductor in the Josephson junction.

[0060] In one example, the aforementioned groove is an inverted trapezoid, meaning the size of the upper opening is larger than the size of the lower opening. The groove can consist of two parts: one part is the unetched bottom film on the substrate, and the other part is the unetched substrate. If we denote the area occupied by the groove on the substrate as the fourth region, then the bottom film within the fourth region of the substrate is completely etched, and a portion of the substrate material within the fourth region is etched, thus forming the groove. The fourth region can be determined based on the groove; if the area of ​​the fourth region is the same as the area of ​​the groove, the position of the fourth region coincides with the position of the groove. The bottom of the groove is the upper surface of the substrate.

[0061] The embodiments of this application do not limit the source of the groove. For example, it can be prepared in real time during the fabrication of the first component, that is, the groove needs to be prepared during the fabrication of the first component to provide a substrate with the groove. Alternatively, it can be prepared before the fabrication of the first component, such as the groove being pre-reserved on the substrate, in which case a substrate with the groove can be directly provided during the fabrication of the first component.

[0062] In one example, a substrate with grooves can be formed by etching the fourth region of the substrate.

[0063] For example, a dry etching process can be used to etch the fourth region of the substrate to form a substrate with grooves.

[0064] For example, photoresist is used to perform homogenization photolithography on the substrate surface for the fourth region to define the scope of the fourth region. Then, carbon tetrafluoride is used as the etching gas to etch the fourth region. After all the bottom film in the fourth region is etched, part of the substrate in the fourth region is also etched, thereby forming a groove.

[0065] In this dry etching process, the etching gas reacts with the substrate material to form a polymer, which is adsorbed onto the exposed surface of the substrate. Areas on the substrate covered by the polymer are not etched, forming protrusions; that is, these protrusions are composed of the substrate material. This embodiment of the application, by employing a dry etching process to prepare grooves, utilizes the polymer formed by the reaction of the etching gas and the substrate to prevent over-etching of the substrate, thereby improving the controllability of groove preparation and ultimately enhancing the accuracy of groove preparation.

[0066] For example, a polymer formed by the reaction of carbon tetrafluoride with a silicon substrate is adsorbed onto a portion of the silicon substrate exposed by etching of the underlying film. No reaction occurs between the polymer and the carbon tetrafluoride, resulting in an un-etched area on the silicon substrate, forming a protrusion made of silicon. This protrusion is higher than the bottom plane of the groove, and the area on the substrate not covered by the polymer is etched by the etching gas to form the bottom plane of the groove, making the protrusion more prominent.

[0067] For example, referring to Figure 4, for a substrate having a substrate 401 and a bottom film 402, a fourth region of the substrate is etched using a dry etching process to form a groove, thereby obtaining a substrate with grooves. The groove may have four sides and a bottom plane (i.e., the bottom). The sides of the groove are jointly formed by the surfaces of the unetched portions of the substrate 401 and the unetched portions of the bottom film 402 within the fourth region. The bottom of the groove is formed by the etched surface of the substrate 401 within the fourth region. The bottom of the groove has a protrusion 403, which is made of the substrate material. It should be noted that, in order to visualize the effect of the protrusion 403 on the conductor film layer, the protrusion 403 has been adaptively enlarged in this embodiment.

[0068] Step 302: The protrusion is etched with a first solution to level the groove.

[0069] The first solution reacts with the substrate material to etch and dissolve the protrusion, thus leveling the groove and forming a leveled groove. Optionally, the criterion for leveling can be that the height of the protrusion is less than a height threshold. That is, the leveled groove can be a groove where the height of the protrusion is less than the height threshold, which can be determined based on the size of the first component to avoid open circuits in the first component due to the protrusion. For example, the surface (especially the bottom) of the leveled groove is approximately flat.

[0070] The first solution is used to level the surface of the groove. Leveling can refer to the process of dissolving the protrusions to make the surface of the groove tend to be flat. This application does not limit the first solution; it can be set and selected according to actual usage requirements. For example, the protrusions can be formed from the substrate material of the base. Any solution that can react with the substrate material, reacts slowly with the oxide layer of the substrate material, and does not damage the underlying film can be used as the first solution.

[0071] For example, when the substrate material is silicon (i.e., the bumps are formed of silicon), the first solution can be a tetramethylammonium hydroxide solution, abbreviated as TMAH solution. TMAH is a white crystalline solid with strong alkalinity, readily soluble in water and organic solvents, thus yielding the first solution. TMAH is stable at temperatures not exceeding its decomposition point and is easily removed without contamination.

[0072] TMAH has strong oxidizing properties. TMAH solution can selectively etch silicon. For example, in anisotropic etching, the etching rate of TMAH solution depends on the atomic density and interface density on the crystal surface. That is, for silicon, the etching rate of TMAH solution is different for different crystal surfaces, which is beneficial to eliminate protrusions composed of silicon and avoid excessive etching of silicon outside the protrusions.

[0073] In one example, the substrate (i.e., the substrate with grooves) can be immersed in a first solution to etch the protrusions, thereby leveling them and forming the leveled grooves. Since the first solution does not corrode the underlying film, immersing the substrate in it will not damage the underlying film (underlying circuitry). Furthermore, because the reaction between the first solution and the oxide layer of the substrate material is slow, controlling the immersion time of the substrate in the first solution within an appropriate range can also prevent damage to the substrate.

[0074] Due to the influence of the crystal plane, the corrosion rate between the first solution and the protrusion is greater than the corrosion rate between the first solution and other parts of the bottom of the groove. This allows the protrusion to be quickly corroded and dissolved, while other parts of the bottom of the groove are corroded more slowly. This reduces the height difference between the protrusion and other parts of the bottom of the groove, making the surface of the groove flatter and smoother, and less likely to cause the conductor film deposited on it to break, thus effectively improving the success rate of component fabrication.

[0075] In one example, since the bumps are formed from the substrate material of the base, and the reaction between the first solution and the oxide layer of the substrate material is slow (e.g., the reaction rate between TMAH and silicon dioxide is one-thousandth that between TMAH and silicon), the etching rate of the bumps can be increased by using a second solution to remove the oxide layer of the substrate before immersing the substrate with the grooves in the first solution.

[0076] The second solution is used to remove the oxide layer on the surface of the groove. For example, the oxide layer at the bottom of the groove is formed by the oxidation of the substrate material. The second solution can be used to clean the groove to remove the oxide layer on the groove surface without removing all the oxide layer on the substrate surface. In a feasible example, the second solution can also be used only to clean the protrusions to remove the oxide layer on their surfaces. After the oxide layer on the protrusions is removed, the first solution can quickly corrode the protrusions, thereby improving the processing efficiency of the groove.

[0077] This application does not limit the second solution, which can be set and selected according to actual usage requirements. For example, when the substrate material is silicon (i.e., the bumps are composed of silicon), the second solution can be hydrofluoric acid. Hydrofluoric acid reacts with the oxide layer (i.e., silicon dioxide) to remove the oxide layer. For example, using a suitable concentration of hydrofluoric acid and cleaning the groove for a suitable time can remove the oxide layer on the bottom surface of the groove, thus forming a groove with the surface oxide layer removed. For instance, cleaning the groove with 2% concentration hydrofluoric acid for 2 minutes can form a groove with the surface oxide layer removed. This application does not limit the concentration of hydrofluoric acid or the cleaning time of the groove.

[0078] Optionally, within a first time period after removing the oxide layer from the bottom surface of the groove, the protrusion is etched with a first solution to level the groove. This prevents the bottom surface of the groove from being oxidized again, thereby affecting the etching rate of the protrusion.

[0079] In one example, the first duration is less than or equal to 2 minutes. For example, after the oxide layer on the bottom surface of the groove is removed, the substrate can be immediately (e.g., within 1 minute) immersed in the first solution.

[0080] In one example, the substrate is immersed in the first solution for between 1 and 3 minutes, which can prevent the substrate in the fourth region from being over-etched and the oxide layer on the substrate surface outside the fourth region from being over-etched while the protrusion is etched away.

[0081] For example, the substrate can be removed after immersing it in the first solution for 2 minutes. Alternatively, the first solution can be placed in a container, such as a glass container, which is not easily corroded by the first solution.

[0082] Optionally, the temperature of the first solution also affects the corrosion efficiency of the protrusions. For example, under the same immersion time, the higher the temperature of the first solution, the faster the corrosion efficiency of the protrusions. By controlling the temperature of the first solution within a suitable range, it is beneficial to improve the removal efficiency of the protrusions.

[0083] For example, the temperature of the first solution is between 60 degrees Celsius and 80 degrees Celsius. Optionally, the temperature of the first solution can be maintained between 60 degrees Celsius and 80 degrees Celsius by a hot plate. The hot plate can be used for heating.

[0084] For example, before soaking the substrate with the first solution, the temperature of the first solution can be adjusted to 80 degrees Celsius using a hot plate. During the soaking process of the substrate with the first solution, the temperature of the first solution can be controlled at around 80 degrees Celsius using a hot plate.

[0085] Optionally, the concentration of the first solution also affects the corrosion efficiency of the protrusion. For example, the corrosion efficiency of the protrusion decreases as the concentration of the first solution increases. By controlling the concentration of the first solution within an appropriate range, it is beneficial to improve the removal efficiency of the protrusion.

[0086] For example, the concentration of the first solution is between 24% and 26%. For instance, a first solution with a concentration of 25% can be prepared using TMAH, that is, the protrusions formed by silicon are etched with a first solution of 25% concentration to smooth out the grooves.

[0087] For example, referring to Figures 4 and 5, when the substrate 401 is made of silicon, a 25% TMAH solution at 80 degrees Celsius can be used to soak the substrate for 1 minute to dissolve the protrusion 403 at the bottom of the groove, thereby forming a groove with an approximately smooth surface, i.e., a groove after leveling treatment.

[0088] Step 303: A conductor film layer is deposited on the substrate to form the first component.

[0089] In this embodiment, the first component is constructed based on a groove, and the fabrication area corresponding to the first component includes the fourth region. If the fabrication area corresponding to the first component is larger than the fourth region, the fabrication area refers to the area occupied by the first component on the substrate.

[0090] Depositing a conductive film layer on a substrate can refer to depositing a conductive film layer on the aforementioned preparation area to form a first component, thereby forming a substrate having the first component. Exemplarily, the first component may be constructed from a conductive film layer, all or part of which is located in a groove. The shape, size, position, etc., of the conductive film layer can be determined according to the parameters of the first component.

[0091] The embodiments of this application do not limit the material of the conductor film. Exemplarily, the conductor film can refer to a metal film, such as an aluminum film or a tantalum film. For example, when the first component is a Josephson junction, the conductor film can be made of aluminum.

[0092] In one example, the first component mentioned above includes a Josephson junction, and the conductor film layer includes a first metal film layer and a second metal film layer. Then, step 303 may also include the following:

[0093] 1. A first metal film layer is deposited on a first region of the substrate by vapor deposition.

[0094] The first region is used to fabricate the superconductor of the Josephson junction, such as the superconductor located at the bottom of the structure corresponding to the Josephson junction. This first metal film layer can form the superconductor of the Josephson junction. The material of the first metal film layer can be aluminum. The length, thickness, etc., of the first metal film layer can be determined based on the dimensions of the Josephson junction.

[0095] The first metal film layer comprises two parts: a first part located within the groove and a second part located outside the groove. The first and second parts are integrally formed to create the first superconductor of the Josephson junction. The first part covers a portion of the bottom of the groove and a first side of the groove, which can refer to any one of the four sides of the groove. The second part covers a portion of the bottom film of the substrate. The first region is identical to the region formed by the first and second parts.

[0096] For example, referring to Figure 6, an aluminum film can be deposited in the first region within the coating chamber using electron beam evaporation to form a first metal film layer 404. Since the protrusion at the bottom of the groove is eliminated, the probability of an open circuit in the first metal film layer 404 is low, which helps improve the success rate of Josephson junction fabrication. A first portion of the first metal film layer 404 is located within the groove, covering a portion of the bottom of the groove and the first side of the groove. A second portion of the first metal film layer 404 is located outside the groove, such as on the underlying film 402.

[0097] 2. An insulator is prepared in the second region of the first metal film layer, and the insulator is located in the groove.

[0098] The second region is used to prepare the insulator for the Josephson junction. The second region includes one end of the first metal film layer located in the groove. For example, the second region can be a portion of the first part of the first metal film layer near the second side of the groove. The second side is another side of the groove's four sides located in a target direction and different from the first side (i.e., the side of the groove opposite to the first side). The target direction is used to indicate the direction from the second part of the first metal film layer to the first part of the first metal film layer. The area of ​​the second region is smaller than the area occupied by the first part. Optionally, insulating material can be directly deposited in the second region to form an insulator. Alternatively, the first metal film layer in the second region can be directly oxidized to form an oxide layer, which is the insulator. The embodiments of this application do not limit the method of preparing the insulator.

[0099] For example, referring to Figure 6, the substrate can be transferred to the oxidation chamber, and oxygen can be introduced to oxidize the first metal film layer in the second region to obtain insulator 405 (such as aluminum oxide). The areas outside the second region can be shielded by photoresist to prevent oxidation. Alternatively, an angled deposition process can be used to deposit a film in the second region to form insulator 405.

[0100] 3. On the third region of the substrate, a second metal film layer is deposited by vapor deposition to form a Josephson junction.

[0101] The Josephson junction consists of a first metal film layer, an insulator, and a second metal film layer, which are connected by the insulator. The second metal film layer is made of the same material as the first metal film layer.

[0102] The third region is used to fabricate another superconductor for the Josephson junction, such as the superconductor located on top of the corresponding structure of the Josephson junction. This second metal film layer can form another superconductor for the Josephson junction. The length, thickness, etc., of the second metal film layer can be determined based on the dimensions of the Josephson junction.

[0103] The second metal film layer also comprises two parts: a first part located within the groove and a second part located outside the groove. The first and second parts form a single unit, together forming the second superconductor of the Josephson junction. The first part covers the insulator, a portion of the bottom of the groove, and the second side of the groove. The second part covers a portion of the bottom film of the substrate. The third region is identical to the region formed by the first and second parts of the second metal film layer.

[0104] Optionally, the overlapping area between the third region and the first region is the second region, that is, the first part of the second metal film layer covers the insulator, and the second part of the second metal film layer covers part of the bottom film of the substrate.

[0105] Referring to Figure 6, an aluminum film can be deposited in the third region within the coating chamber using electron beam evaporation to form the second metal film layer 406. Since the protrusion at the bottom of the groove is eliminated, the probability of an open circuit in the second metal film layer 406 is low, which is beneficial for improving the success rate of Josephson junction fabrication. The first portion of the second metal film layer 406 is located within the groove, and the second portion is located outside the groove, such as on the underlying film 402, thereby forming a superconductor-insulator-superconductor structure, forming a Josephson junction, and subsequently forming a substrate with a Josephson junction.

[0106] In summary, the technical solution provided in this application reduces the probability of the conductor film breaking due to the protrusion during the fabrication of the first component. This effectively reduces the impact of the size fluctuation of the protrusion on the fabrication of the component, thereby improving the fabrication stability of the component and ultimately increasing the success rate of the component fabrication.

[0107] In addition, as the bumps are eliminated, the contact area between the substrate (such as the substrate's substrate) and the air is reduced, which helps to reduce the TLS (Two Level System) loss of the chip product corresponding to the substrate.

[0108] In some embodiments, taking the fabrication of a Josephson junction on a superconducting quantum chip as an example, the technical solution provided by the embodiments of this application is described. Referring to FIG7, the embodiments of this application may also include the following:

[0109] 1. Clean the oxide layer on the substrate using hydrofluoric acid.

[0110] The aforementioned substrate can refer to a silicon substrate (such as high-resistivity silicon) used to fabricate superconducting quantum chips. The substrate can be cleaned with 2% hydrofluoric acid for 2 minutes to remove oxide layers, such as those formed from silicon dioxide.

[0111] Alternatively, methods such as ion milling can be used to remove the oxide layer on the substrate.

[0112] 2. A superconducting thin film (i.e., the aforementioned bottom film) is formed on the substrate.

[0113] Optionally, a superconducting tantalum film can be grown on the substrate using magnetron sputtering. For example, a pure α-phase tantalum film can be generated on the substrate using magnetron sputtering equipment, which refers to equipment prepared using magnetron sputtering technology.

[0114] 3. Etch the underlying structure, which includes the grooves used to fabricate the Josephson junction.

[0115] Optionally, a pattern for fabricating the underlying circuit is first photolithographically patterned on the superconducting thin film, and then the tantalum film in the exposed area is etched away using carbon tetrafluoride. After removing the photoresist on the substrate, the underlying structure of the superconducting quantum chip can be obtained. This underlying structure may include transmission lines, resonant cavities, capacitors, etc. on the superconducting quantum chip, as well as grooves for fabricating Josephson junctions.

[0116] Due to the influence of compounds formed by carbon tetrafluoride, there are protrusions at the bottom of the grooves, such as those formed by silicon that is shielded by the compounds and not etched.

[0117] 4. Remove the oxide layer from the bottom surface of the groove.

[0118] Since the reaction rate between TMAH and silicon dioxide is only one-thousandth that between TMAH and silicon, it is necessary to remove the oxide layer on the bottom surface of the groove first to improve the removal efficiency of the protrusion.

[0119] Alternatively, continue cleaning the groove with 2% hydrofluoric acid for 2 minutes to remove the oxide layer on the bottom surface of the groove.

[0120] Alternatively, methods such as ion milling can be used to remove the oxide layer on the bottom surface of the groove.

[0121] 5. Immerse the substrate in TMAH solution.

[0122] Optionally, after the oxide layer on the bottom surface of the groove is removed, the substrate is quickly (e.g., within 1 minute) immersed in a TMAH solution to prevent the bottom surface of the groove from being oxidized again, thus affecting the removal efficiency of the protrusions. For example, the protrusions on the bottom of the groove can be eliminated by immersing the substrate in a 25% TMAH solution at 80 degrees Celsius for 1 minute, resulting in a groove with an approximately flat surface (i.e., the groove after the above-mentioned leveling treatment).

[0123] For example, referring to Figure 8, the bottom surface of groove 801 before leveling has a rough, ravine-like morphology, i.e., it has protrusions. Compared to groove 801 before leveling, the bottom surface of groove 802 after leveling changes from a relatively rough ravine-like morphology to an approximately flat and smooth plain morphology. This effectively reduces the probability of possible open circuits in the Josephson junction, thereby improving the success rate of Josephson junction fabrication. Furthermore, Figure 8 shows that the TMAH solution has no effect on the tantalum film.

[0124] For example, referring to Figure 9, to verify the reduction in TLS loss after the groove is smoothed, the quality factor (Q value) of a single photon in a two-dimensional resonant cavity at low temperature was measured in this embodiment of the application. Curve 901 is the relationship between the frequency of the groove before the leveling treatment and the reflected signal, curve 902 is the relationship between the frequency of the groove before the leveling treatment and the phase angle, curve 903 is the relationship between the frequency of the groove after the leveling treatment and the reflected signal, and curve 904 is the relationship between the frequency of the groove after the leveling treatment and the phase angle.

[0125] The Q-values ​​of the resonant cavity obtained by fitting curves 901 and 902 are approximately 2.3*106, and the Q-values ​​of the resonant cavity obtained by fitting curves 903 and 904 are approximately 2.1*107. It can be clearly seen that, compared with the groove before the leveling treatment, the Q-value of the resonant cavity corresponding to the groove after the leveling treatment is increased by more than 9 times.

[0126] Therefore, the leveled grooves can effectively improve the fabrication success rate of Josephson junctions and reduce the contact area between the substrate and air, thereby reducing the TLS loss of the superconducting quantum chip. The leveled grooves can also improve the quality factor of the resonant cavity, enabling the single-photon Q-value to reach over 20 million, thus effectively improving the performance of the superconducting quantum chip.

[0127] 6. Prepare Josephson knots on the leveled grooves.

[0128] Alternatively, a Josephson junction can be fabricated on the leveled groove using electron beam evaporation and tilting deposition processes to complete the fabrication of a superconducting quantum chip.

[0129] For example, in the process of fabricating a Josephson junction, firstly, an electron beam evaporation process is used to deposit an aluminum film on a leveled groove to form a first superconductor. The first superconductor covers part of the bottom of the groove, the first side of the groove, and part of the bottom film. Then, an insulator is fabricated on the first superconductor using an angled deposition process. Finally, an aluminum film is deposited again on the leveled groove in the deposition chamber to fabricate a second superconductor. The second superconductor covers part of the bottom of the groove, the second side of the groove, and part of the bottom film, thereby forming a superconductor-insulator-superconductor structure to obtain a Josephson junction.

[0130] In summary, the technical solution provided in this application, in the process of preparing the Josephson junction, after removing the protrusions on the bottom of the groove used to prepare the Josephson junction using TMAH solution, and then performing the evaporation of the metal film layer, can reduce the probability of the metal film layer breaking due to the protrusions, effectively reduce the impact of the size fluctuation of the protrusions on the preparation of the Josephson junction, thereby improving the preparation stability of the Josephson junction and thus improving the preparation success rate of the Josephson junction.

[0131] In addition, as the bumps are eliminated, the contact area between the substrate (such as the substrate material) and the air is reduced, which helps to reduce the TLS (Two Level System) loss of the chip product corresponding to the substrate.

[0132] Figure 10 shows a schematic diagram of a component fabrication system provided in one embodiment of this application. This component fabrication system can be implemented as production line equipment. As shown in Figure 10, the component fabrication system includes an etching machine 1001 and a vapor deposition machine 1002.

[0133] Etching machine 1001 is used to etch the protrusions at the bottom of a groove with a first solution to level the groove on a substrate having a groove.

[0134] Evaporation machine 1002 is used to vapor deposit a conductor film layer on the substrate to form a first component.

[0135] In some embodiments, the etching machine 1001 is further configured to immerse the substrate in the first solution to etch the protrusion.

[0136] In some embodiments, the substrate is immersed in the first solution for a duration between 1 minute and 3 minutes.

[0137] In some embodiments, the temperature of the first solution is between 60 degrees Celsius and 80 degrees Celsius.

[0138] In some embodiments, the concentration of the first solution is between 24% and 26%.

[0139] In some embodiments, the first solution is a tetramethylammonium hydroxide solution.

[0140] In some embodiments, the etching machine 1001 is further configured to remove the oxide layer of the substrate using a second solution.

[0141] In some embodiments, the etching machine 1001 is further configured to etch the protrusion with the first solution within a first time period after the oxide layer is removed, the first time period being less than or equal to 2 minutes.

[0142] In some embodiments, the first component includes a Josephson junction, and the conductor film includes a first metal film and a second metal film; the evaporation machine 1002 is further used for:

[0143] The first metal film layer is deposited on the first region of the substrate by vapor deposition;

[0144] An insulator is prepared in a second region of the first metal film layer, the insulator being located within the groove;

[0145] The second metal film layer is deposited on the third region of the substrate to form the Josephson junction, wherein the overlapping region between the third region and the first region is the second region.

[0146] In some embodiments, the above-described component fabrication system further includes an etching machine 1003. The etching machine 1003 is used to fabricate a substrate with grooves.

[0147] For example, the etching machine 1003 is further configured to etch a fourth region of the substrate using a dry etching process to form a substrate having the groove; wherein, the polymer formed by the reaction of the etching gas used in the dry etching process with the substrate material of the substrate is adsorbed on the substrate exposed on the surface of the substrate, and the area on the substrate covered by the polymer is not etched to form the protrusion.

[0148] Optionally, the above-mentioned production line equipment also includes a processor, which can be electrically connected to the etching machine 1001, the vapor deposition machine 1002 and the etching machine 1003 respectively, to control the etching machine 1001, the vapor deposition machine 1002 and the etching machine 1003, etc.

[0149] Optionally, the production line equipment also includes a power supply to provide power to electrical equipment such as the processor, etching machine 1001, vapor deposition machine 1002, and etching machine 1003.

[0150] Alternatively, the machines can be spatially connected by conveyor belts, or the movement of the prepared material between the machines can be accomplished using robotic arms.

[0151] Optionally, the production line equipment also includes a memory that can be used to store at least one computer instruction, which the processor executes to cause the production line equipment to perform the above-described component fabrication method.

[0152] In some embodiments, a computer-readable storage medium is also provided, which stores at least one computer instruction that is executed by a processor in a production line device to cause the production line device to perform the above-described component fabrication method.

[0153] In some embodiments, a computer program product is also provided, comprising computer instructions stored in a computer-readable storage medium. A processor of the production line equipment reads the computer instructions from the computer-readable storage medium and executes the computer instructions, causing the production line equipment to perform the aforementioned component fabrication method.

[0154] In some embodiments, a chip product is also provided, which includes a first component prepared by the method described above.

[0155] Optionally, the chip product is used to fabricate a superconducting quantum chip, or the chip product is a superconducting quantum chip.

[0156] In some embodiments, an apparatus is also provided, the apparatus including a chip product, the chip product including a first component prepared by the method described above.

[0157] In summary, the technical solution provided in this application reduces the probability of the conductor film breaking due to the protrusion during the fabrication of the first component. This effectively reduces the impact of the size fluctuation of the protrusion on the fabrication of the component, thereby improving the fabrication stability of the component and ultimately increasing the success rate of the component fabrication.

[0158] In addition, as the bumps are eliminated, the contact area between the substrate (such as the substrate's substrate) and the air is reduced, which helps to reduce the TLS (Two Level System) loss of the chip product corresponding to the substrate.

[0159] Please refer to Figure 11, which shows a schematic diagram of an application scenario of the solution provided in one embodiment of this application. As shown in Figure 11, the application scenario can be a superconducting quantum computing platform, which includes: a quantum computing device 1101, a dilution refrigerator 1102, a control device 1103, and a computer 1104.

[0160] The quantum computing device 1101 is a circuit operating on physical qubits. The quantum computing device 1101 can be implemented as a quantum chip, such as a superconducting quantum chip located near absolute zero. This quantum chip can be prepared using the component fabrication method shown in the above embodiments of this application. The dilution refrigerator 1102 is used to provide an absolute zero environment for the superconducting quantum chip.

[0161] Control device 1103 controls quantum computing device 1101, and computer 1104 controls control device 1103. For example, a pre-written quantum program is compiled into instructions by software in computer 1104 and sent to control device 1103 (such as an electronic / microwave control system). Control device 1103 converts these instructions into electronic / microwave control signals, which are then input to dilution refrigerator 1102 to control the superconducting qubits at a temperature below 10 mK. The reading process is the reverse; the read waveform is transmitted to quantum computing device 1101.

[0162] It should be understood that "multiple" as used herein refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. Furthermore, the step numbers described herein are merely illustrative of one possible execution order. In some other embodiments, the steps may not be executed in numerical order, such as two steps with different numbers being executed simultaneously, or two steps with different numbers being executed in the reverse order of the illustration. This application does not limit this.

[0163] The above description is merely an exemplary embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A method for manufacturing a component, the method comprising: providing a substrate having a recess, the recess having a protrusion at the bottom of the recess; etching the protrusion with a first solution to flatten the recess; evaporating a conductor film layer on the substrate to form a first component. The etching the protrusion with a first solution to flatten the recess comprises: immersing the substrate in the first solution to etch the protrusion. The immersion of the substrate in the first solution lasts between 1 minute and 3 minutes. The first solution has a temperature between 60 degrees Celsius and 80 degrees Celsius.

2. The method of claim 1, wherein, The first solution has a concentration between 24% and 26%. The first solution is a tetramethylammonium hydroxide solution.

3. The method of claim 2, wherein, The etching the protrusion with a first solution to flatten the recess further comprises: removing an oxide layer of the substrate with a second solution before the etching the protrusion with a first solution to flatten the recess.

4. The method according to any one of claims 1 to 3, wherein, The etching the protrusion with a first solution to flatten the recess comprises: etching the protrusion with the first solution within a first time period after the removal of the oxide layer, the first time period being less than or equal to 2 minutes.

5. The method according to any one of claims 1 to 4, wherein, The first component comprises a Josephson junction, and the conductor film layer comprises a first metal film layer and a second metal film layer.

6. The method according to any one of claims 1 to 5, wherein, The evaporating a conductor film layer on the substrate to form a first component comprises: evaporating the first metal film layer on a first region of the substrate; preparing an insulator within a second region of the first metal film layer, the insulator being located within the recess; and evaporating the second metal film layer on a third region of the substrate to form the Josephson junction, wherein an overlapping region between the third region and the first region is the second region.

7. The method according to any one of claims 1 to 6, wherein, The providing a substrate having a recess comprises: etching a fourth region of the substrate with a dry etching process to form the substrate having the recess; wherein an etching gas used in the dry etching process reacts with a substrate material of the substrate to form a polymer that is adsorbed on an exposed substrate of the substrate, and a region of the exposed substrate covered by the polymer is not etched to form the protrusion. An etching machine and an evaporating machine.

8. The method of claim 7, wherein, The etching machine is configured to etch a protrusion at the bottom of a recess of a substrate with a first solution to flatten the recess. The evaporating machine is configured to evaporate a conductor film layer on the substrate to form a first component.

9. The method according to any one of claims 1 to 8, wherein, 12.A chip product comprising a first component manufactured by the method of any one of claims 1 to 10. The chip product is used to manufacture a superconducting quantum chip, or the chip product is the superconducting quantum chip. 14.An apparatus comprising a chip product, the chip product comprising a first component manufactured by the method of any one of claims 1 to 10. ​ ​ 10. The method according to any one of claims 1 to 9, wherein, ​ ​ ​ 11. A component preparation system, the system comprising: ​ ​ ​ ​ 13. The chip product according to claim 12, wherein, ​ ​

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