Embedded-component substrate, power supply apparatus, and electronic device

Abstract

An embedded-component substrate, a power supply apparatus, and an electronic device. The embedded-component substrate comprises a core substrate, build-up layers, and chips embedded in the core substrate, wherein the front side of each chip comprises an outer protective layer located on the outer side of pads of the chip, and the outer protective layer is provided with windows corresponding to the pads. The build-up layers comprise a front build-up layer covering the core substrate, and a circuit layer of the front build-up layer is electrically connected to each pad of the chip by means of a first conduction structure; circuit layers in the build-up layers are electrically connected by means of second conduction structures; and at least one of the first conduction structure and the second conduction structure is a strip extending within a substrate surface of the embedded-component substrate. By means of the configuration, the proportion of the current-carrying cross-section of the conduction structure can be effectively increased, and on the basis of improving the vertical current-carrying capacity of the chip, parasitic resistance can be rationally controlled, and the planar current-carrying capability between layers can be enhanced. In addition, on the basis of the configuration of the strip-shaped conduction structure, the heat dissipation capability can be improved at the same time, thereby achieving good reliability.

Description

Embedded substrate, power supply and electronic equipment

[0001] This application claims priority to Chinese Patent Application No. 202410995965.2, filed on July 23, 2024, entitled "Embedded Substrate, Power Supply Device and Electronic Equipment", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of electronic component packaging technology, and in particular to an embedded substrate, a power supply device, and an electronic device. Background Technology

[0003] Embedded substrate technology embeds electronic components, such as but not limited to chips, resistors, capacitors, and inductors, within a substrate, interconnecting them through external circuitry to form highly integrated, high-density functional modules. Embedded substrate technology can be used in various application scenarios. As product functionality continues to evolve, achieving high current, high heat dissipation, and high reliability has become a core requirement for embedded substrates.

[0004] A typical power chip packaging module embeds components such as chips within a core board structure. Add-on layers are stacked on the core board surface to achieve highly integrated circuitry for interconnection. Typically, the pads on the front side of the chip are exposed through windows in the polyimide (PI) layer. Blind vias are formed in the add-on layer adjacent to the chip using laser technology to establish electrical connections between the chip side and the add-on layer side. Furthermore, the circuitry layers within the embedded add-on layer are interconnected through these blind vias. However, the limitations of the blind via's current-carrying cross-sectional area prevent the fulfillment of performance requirements such as high current, high heat dissipation, low parasitics, and high reliability. Summary of the Invention

[0005] The application provides an embedded substrate, a power supply device, and electronic equipment. Through the optimization of the embedded substrate structure, high current, high heat dissipation, low parasitics, and high reliability are achieved.

[0006] A first aspect of this application provides an embedded substrate, comprising a core retainer, an add-in layer, and a chip embedded in the core retainer. The core retainer includes a first surface and a second surface. The front surface of the chip faces the first surface of the core retainer. The front surface of the chip includes an outer protective layer located outside its pads, and the outer protective layer has openings corresponding to the pads. The add-in layer includes a front-side add-in layer covering the first surface of the core retainer. The circuit layers of the front-side add-in layer and the pads of the chip are electrically connected via a first conductive structure. The circuit layers in the add-in layer are electrically connected via a second conductive structure. At least one of the first and second conductive structures is a strip extending within the surface of the embedded substrate. The strip-shaped conductive structure has a strip-shaped current-passing cross-section, where "current-passing cross-section" refers to the cross-section of the corresponding conductive structure that intersects the embedded substrate vertically.

[0007] This configuration, for the first conductive structure used for electrical connections to chip pads, effectively increases the current-carrying cross-sectional area ratio by using a strip-shaped first conductive structure. This significantly increases the current-carrying area output from the chip side, improving the chip's current-carrying capacity while allowing for reasonable control of the resistance value of the current-carrying path, effectively reducing parasitics. For the second conductive structure used for electrical connections between add-on circuit layers, the strip-shaped second conductive structure also increases the current-carrying cross-sectional area ratio in the local vertical current-carrying region, improving the vertical current-carrying capacity. Simultaneously, the strip-shaped second conductive structure extending along the surface of the embedded substrate further enhances the current-carrying effect, strengthening the planar current-carrying capacity between layers. Furthermore, the strip-shaped conductive structure also improves the heat dissipation capacity of the embedded substrate, providing a good technical guarantee for ensuring the stable operation of embedded components such as chips. Overall, it exhibits good reliability.

[0008] For example, the core retainer may be a core board, or the core retainer may be a filler layer made of filler material.

[0009] Other examples include the extension direction of the strip-shaped conductive structure within the surface of the embedded substrate, which can be transverse, longitudinal, or oblique at an angle to both the transverse and longitudinal directions.

[0010] In practical applications, any combination of the above-mentioned extension directions can be used for the strip-shaped second conductive structure.

[0011] Based on the first aspect, this application also provides a first implementation of the first aspect: the added layer further includes a back-side added layer covering the second side of the core retainer. This allows for flexible arrangement of the paths for current flow and heat conduction between the embedded substrate and the outside, and provides technical advantages such as high current flow, low parasitics, high heat dissipation, and high reliability on both sides of the embedded substrate based on the strip-shaped second conductive structure.

[0012] Based on the first aspect, or the first embodiment of the first aspect, this application also provides a second embodiment of the first aspect: the first conductive structure is a strip extending within the surface of the embedded substrate, with windows on the outer protective layer on the chip side corresponding to multiple co-network pads of the chip, and the strip-shaped first conductive structure is electrically connected to the multiple co-network pads. Compared to the traditional structure where each pin pad is interconnected using blind vias with circular current-carrying cross-sections, the strip-shaped first conductive structure electrically connected to multiple co-network pads can effectively increase the proportion of the current-carrying cross-section and increase the current-carrying area output from the chip side. Simultaneously, based on the strip-shaped first conductive structure connected to multiple co-network pads, the thermal resistance of the chip's heat dissipation path can be further reduced, improving heat dissipation capacity.

[0013] For example, the adapted strip-shaped first conductive structure and window can be configured to correspond to two pads of the same network of the chip, or to correspond to a plurality of other pads of the same network.

[0014] Based on the first implementation of the first aspect, this application also provides a third implementation of the first aspect: the window on the outer protective layer on the chip side is a strip-shaped window adapted to the first conductive structure, and there is a gap between the strip-shaped window and the first conductive structure. This improves the reliability of the connection structure.

[0015] For example, for a chip, multiple strip-shaped openings can be set for the pads of different networks, and electrical connections can be achieved through corresponding strip-shaped first conductive structures. In practical applications, the multiple openings can be arranged regularly in an array, or they can be arranged irregularly to correspond to the specific settings of the pads of multiple different network pins on the chip side.

[0016] Based on the first aspect, or the first implementation of the first aspect, or the second implementation of the first aspect, or the third implementation of the first aspect, this application also provides a fourth implementation of the first aspect: multiple chips are configured, and the pads of at least one chip are electrically connected to the front-side overlay circuit layer via a strip-shaped first conductive structure. This provides good adaptability.

[0017] In practical applications, each chip embedded in the embedded substrate can be electrically connected to the circuit layer on the front-side augmentation layer using a strip-shaped first conductive structure. In other practical applications, some chips embedded in the embedded substrate can also be electrically connected to the circuit layer on the front-side augmentation layer using a strip-shaped first conductive structure.

[0018] Based on the first aspect, or the first implementation of the first aspect, or the second implementation of the first aspect, or the third implementation of the first aspect, or the fourth implementation of the first aspect, this application also provides a fifth implementation of the first aspect: the chip includes multiple pads, and at least some of the pads of the chip are electrically connected to the front-side overlay circuit layer through a strip-shaped first conductive structure. In practical applications, other pads of the chip can be electrically connected to the circuit layer using conductive blind vias, which can further improve adaptability.

[0019] Based on the first aspect, or the first implementation of the first aspect, or the second implementation of the first aspect, or the third implementation of the first aspect, or the fourth implementation of the first aspect, or the fifth implementation of the first aspect, this application also provides a sixth implementation of the first aspect: the second conductive structure is a strip extending within the surface of the embedded substrate, the added layer includes multiple circuit layers, and adjacent circuit layers are electrically connected through the strip-shaped second conductive structure.

[0020] For example, the local vertical current-carrying region between two circuit layers is electrically connected by multiple strip-shaped second conductive structures. In this way, the technical advantages of large current carrying capacity, low parasitics, high heat dissipation, and high reliability can be specifically obtained based on the strip-shaped second conductive structures.

[0021] In practical applications, for the corresponding multiple strip-shaped second conductive structures in the local vertical flow area, they can be extended in the same direction within the surface of the embedded substrate, or they can be extended in different directions.

[0022] Based on the sixth implementation of the first aspect, this application also provides a seventh implementation of the first aspect: multiple local vertical current-carrying regions are included between the two line layers, and at least some of the local vertical current-carrying regions are electrically connected through a strip-shaped second conductive structure. This further improves adaptability.

[0023] Based on the sixth or seventh implementation of the first aspect, this application also provides an eighth implementation of the first aspect: each second conductive structure located between two circuit layers extends in the same direction within the surface of the embedded substrate, or extends in different directions.

[0024] Based on the sixth, seventh, or eighth implementation of the first aspect, this application also provides a ninth implementation of the first aspect: a strip-shaped second conductive structure located in two vertically adjacent and overlapping local vertical flow regions, extending in the same direction within the surface of the embedded substrate, or extending in different directions.

[0025] In practical applications, strip-shaped second conductive structures located in two vertically adjacent and overlapping local vertical current-carrying regions extend in different directions within the surface of the embedded substrate. In other words, for layer add-ins with multiple circuit layers, the strip-shaped second conductive structures in the two vertically overlapping local vertical current-carrying regions between adjacent layers extend in different directions, which can improve the uniformity of interlayer microstructure stress and enhance the overall reliability of the embedded substrate.

[0026] Based on the first aspect, or the first embodiment of the first aspect, or the second embodiment of the first aspect, or the third embodiment of the first aspect, or the fourth embodiment of the first aspect, or the fifth embodiment of the first aspect, or the sixth embodiment of the first aspect, or the seventh embodiment of the first aspect, or the eighth embodiment of the first aspect, or the ninth embodiment of the first aspect, this application also provides a tenth embodiment of the first aspect: the embedded substrate further includes a plurality of electronic components embedded in the core retainer, at least one of the plurality of electronic components being a capacitor or a resistor. This configuration allows for flexible configuration according to product functional requirements.

[0027] A second aspect of this application provides a power supply device including a chip and an inductor. The chip is embedded in a package using an embedded substrate as described above, and the inductor is surface-mounted on the embedded substrate. The embedded substrate structure forms vertical and intra-board fast transmission channels, reducing the overall resistance between the power chip, system board, and processor chip, as well as between the power chip and the inductor, thereby improving current carrying capacity. Simultaneously, it allows for reasonable control of link parasitics, achieving both good thermal conductivity and reliability.

[0028] For example, the inductor can be surface-mounted on the front side of the embedded substrate, which can shorten the link length between the power chip and the inductor and reduce parasitic resistance. Alternatively, the inductor can also be surface-mounted on the back side of the embedded substrate.

[0029] Based on the second aspect, this application also provides a first implementation of the second aspect: the power supply device further includes multiple electronic components, a portion of which, along with a chip, forms an embedded package using an embedded substrate, while another portion of which, along with an inductor, is surface-mounted on the embedded substrate. In practical applications, it can be flexibly configured according to product functional requirements, exhibiting good designability.

[0030] A third aspect of this application provides an electronic device, which includes a system board and a power supply device, wherein the power supply device is disposed on the system board and is the power supply device as described above.

[0031] In practical applications, this electronic device can be a server, computer, or high-performance computing cluster, such as a high-power, highly integrated, and ultra-large-scale data center server; in addition, this electronic device can also be a switch, router, or edge device, etc. Attached Figure Description

[0032] Figure 1 is a cross-sectional view of an embedded substrate provided in an embodiment of this application;

[0033] Figure 2 is a cross-sectional view of CC in Figure 1;

[0034] Figure 3 is a cross-sectional view of DD in Figure 1;

[0035] Figure 4 is a cross-sectional view of another embedded substrate structure provided in an embodiment of this application;

[0036] Figure 5 is a cross-sectional view of EE in Figure 4;

[0037] Figure 6 is a schematic diagram of yet another second conductive structure provided in an embodiment of this application;

[0038] Figure 7 is a cross-sectional view of another embedded substrate structure provided in an embodiment of this application;

[0039] Figure 8 is a schematic diagram of the process of the embedded substrate shown in Figure 7;

[0040] Figure 9 is a schematic diagram of an application scenario of a power supply device provided in an embodiment of this application;

[0041] Figure 10 is a schematic diagram of an application scenario of a power supply device provided in an embodiment of this application;

[0042] Figure 11 is a schematic diagram of an electronic device provided in an embodiment of this application. Detailed Implementation

[0043] This application provides an embedded substrate implementation scheme that can achieve high current, high heat dissipation, low parasitics and high reliability, so as to be applied to different high integration and high density application scenarios.

[0044] Embedded substrate technology is used to embed electronic components inside a substrate, which can shorten the connection path between components, reduce transmission loss, improve product integration, and reduce module size. Take an embedded substrate used in power chip packaging modules as an example. In a typical embedded substrate architecture, components such as chips, capacitors, and / or resistors can be embedded in a core board. Add-on layers are stacked on the surface of the core board to achieve interconnection between components and connection to external circuits. Typically, the pads on the front side of the chip are exposed through circular or elliptical openings in the PI layer (outer protective layer). Correspondingly, laser-drilled vias are used in the add-on layer to form blind vias corresponding to the pads, establishing electrical connections between the chip side and the add-on layer side. Simultaneously, the circuit layers within the embedded add-on layer are also connected through blind vias. On the one hand, a ring width needs to be reserved between the blind via and the window in the PI layer. However, the window size of the chip material is fixed, resulting in a blind via diameter smaller than the window size of the chip's PI layer. This limits the improvement of the blind via's current carrying capacity and heat conduction. On the other hand, the blind vias connecting the buried add-on circuit layers are limited by conventional via forming processes, resulting in limitations on the via diameter and spacing. The copper content of the blind via cross-section in the local vertical current carrying area is low, even below 13%, limiting the vertical current carrying capacity. Furthermore, the blind vias between circuit layers have no current carrying effect in the horizontal direction (i.e., the X and Y directions within the substrate extension plane). Here, the X and Y directions refer to two different directions within the substrate extension plane.

[0045] Based on this, this application provides an embedded substrate, which includes a core retainer, an add-in layer, and a chip embedded in the core retainer. The add-in layer covers the surface of the core retainer. The front side of the chip includes an outer protective layer located outside its pads. This outer protective layer has windows corresponding to the pads on the chip. The circuit layers in the add-in layer bonded to the front side of the chip are electrically connected to the chip pads via a first conductive structure, and the circuit layers in the add-in layer are electrically connected to each other via a second conductive structure. At least one of the first and second conductive structures is a strip extending within the surface of the embedded substrate. This strip-shaped conductive structure (the first and second conductive structures) has a strip-shaped current-passing cross-section. Here, "current-passing cross-section" refers to the cross-section of the corresponding conductive structure that intersects the embedded substrate vertically, for example, but not limited to, a cross-section of the corresponding conductive structure perpendicular to the vertical direction, i.e., a cross-section parallel to the surface of the embedded substrate.

[0046] With this configuration, for the first conductive structure used for electrical connections between chip pads, the strip-shaped first conductive structure can effectively increase the proportion of the current-carrying cross-section, significantly increase the current-carrying area output from the chip side, improve the chip's current-carrying capacity, and at the same time, reasonably control the resistance value of the current-carrying path, effectively reducing parasitics. For the second conductive structure used for electrical connections between add-on circuit layers, the strip-shaped second conductive structure can also increase the proportion of the current-carrying cross-section in the local vertical current-carrying region, improving the vertical current-carrying capacity; at the same time, the strip-shaped second conductive structure extending along the inner surface of the embedded substrate can further achieve the current-carrying effect, enhancing the planar current-carrying capacity between layers.

[0047] Furthermore, the strip-shaped conductive structure enhances the heat dissipation capacity of the embedded substrate, providing a strong technical guarantee for the stable operation of embedded components such as chips. Overall, it exhibits good reliability.

[0048] To better understand the technical solutions and effects of this application, without loss of generality, specific embodiments will be described in detail below with reference to the accompanying drawings. Please refer to Figure 1, which is a cross-sectional view of an embedded substrate architecture provided in an embodiment of this application.

[0049] As shown in Figure 1, the core retainer 1 of the embedded substrate 10 can be made of a core board, such as, but not limited to, a core board made of organic material or glass material. Chips 2 and electronic components 3 are embedded in the core retainer 1. For clarity of the basic architectural relationship of the embedded substrate, two chips 2 and two electronic components 3 are illustrated in the figure, by way of example.

[0050] In specific implementations, the number of chips 2 and electronic components 3 can be determined according to the overall product design requirements. For example, but not limited to, electronic components 3 can be capacitors and / or resistors to construct corresponding functional circuits. The electronic components 3 in the core holder 1 are optional components; that is, only chip 2 can be embedded in the embedded substrate 10. This application does not limit the specific implementation.

[0051] In other specific implementations, the substrate of the core holder 1 can be made of organic materials, such as, but not limited to, FR4, BT, or BT-like materials. The chip 2 and electronic components 3 embedded in the grooves on the core holder 1 can be assembled and fixed by filling with ABF (Ajinomoto Build-up Film).

[0052] In this embodiment, the front side of chip 2 faces the first surface 1A of the core holder 1, and correspondingly, the back side of chip 2 faces the first surface 1B of the core holder 1. The outer protective layer on the front side of chip 2 can be a PI layer 21. In other possible implementations, this outer protective layer can also be made of other organic materials, as long as it can provide physical isolation to prevent oxidation of the chip substrate and meet the functional requirements of the chip's external electrical performance. Further details are omitted in the embodiments of this application.

[0053] As shown in Figure 1, the PI layer 21 of chip 2 can be aligned with the first surface 1A of the core holder 1. "Aligned" here includes the case where the first surface 1A of the core holder 1 is completely flush with the surface of the PI layer 21, and also includes the case where the first surface 1A of the core holder 1 and the surface of the PI layer 21 are close to being flush, within a tolerance range. The PI layer 21 has openings 211, which correspond to pads 22 located on the inner layer. The pads 22 are exposed through the corresponding openings 211 to achieve electrical connection with external circuitry.

[0054] In this embodiment, both sides of the core retainer 1 of the embedded substrate 10 are covered with augmentation layers. The circuit layers of the augmentation layers are connected to the devices embedded in the core retainer 1 to achieve more complex circuit connections and functions. Specifically, the first side 1A of the core retainer 1 is covered with a front augmentation layer T, and the second side 1B of the core retainer 1 is covered with a back augmentation layer B, which enables double-sided interconnection and heat dissipation.

[0055] For example, both the front-side add-on layer T and the back-side add-on layer B include three circuit layers 4, which are sequentially stacked from both sides of the core retainer 1 by dielectric layers and circuit layers 4. In other possible implementations, the number of circuit layers 4 on the front-side add-on layer T and the back-side add-on layer B is not limited to the three layers shown in the figure, and can be determined according to the product function. In one scenario, the front-side add-on layer T (not shown in the figure) may only be covered on the first surface 1A of the core retainer 1. This application does not limit the scope of the implementation.

[0056] Among them, the pads 22 of chip 2 can be electrically connected to the circuit layer 4 of the front-side addition layer T through the first conductive structure 5, and the circuit layers 4 of the two-side addition layers can be electrically connected through the second conductive structure 6.

[0057] Please also refer to Figure 2, which is a cross-sectional view of Figure 1 (CC section). To clearly show the vertical connection relationship between the first conductive structure 5 and the chip 2, the chip 2 in Figure 1 is illustrated with a matching set of first conductive structures 5 and windows 211; at the same time, to clearly show the arrangement of the first conductive structures 5 on the front side of the chip 2, the front side of the chip 2 in Figure 2 is illustrated with four sets of first conductive structures 5 and windows 211 arranged in an array.

[0058] The first conductive structure 5 is a strip extending within the surface of the embedded substrate and has a strip-shaped flow passage cross section, as shown in Figure 2. There is a spacing E between the first conductive structure 5 and the opening 211 of the PI layer 21 to improve the reliability of the connection structure.

[0059] The first conductive structure 5 can be a copper strip (bur) in the shape of an inverted trapezoid shown in Figure 1. In a specific implementation, the strip-shaped first conductive structure 5 can be formed by laser grooving followed by electroplating. It should be understood that Figure 2 shows the strip-shaped current-passing cross-section at a cut position of each first conductive structure 5. For the inverted trapezoidal copper strip, its current-passing cross-section is strip-shaped, and the area of ​​each strip-shaped current-passing cross-section decreases from the outside to the inside. The directional terms "outer" and "inner" here are defined based on the embedded substrate, with the side closer to the core retainer 1 in the vertical direction being the inner side, and the other side away from the core retainer 1 being the outer side. It should be understood that the use of the above directional terms is only for clearly describing the specific structure and does not constitute a substantial limitation on the scheme of this application.

[0060] For the window 211 of the chip-side PI layer 21, it can be opened corresponding to multiple same-network pads 22 of the chip 2 to form a strip-shaped window 211 adapted to the strip-shaped first conductive structure 5. Here, "same-network" refers to pin pads that are electrically equivalent, and the pin pads of the same network have the same potential or voltage. For example, but not limited to, they are used for current distribution or signal transmission.

[0061] In contrast to the traditional structure that uses blind vias with circular current-carrying cross-sections for interconnection of each pin pad, this solution, based on the strip-shaped first conductive structure 5, effectively increases the proportion of the current-carrying cross-section and enlarges the current-carrying area exiting the chip side. Simultaneously, the strip-shaped first conductive structure 5 further reduces the thermal resistance of the chip's heat dissipation path, improving heat dissipation capacity. In a typical design, for the same chip pad arrangement area, the current-carrying cross-section of the first conductive structure 5 can be increased by more than two times. Therefore, while improving the chip's current-carrying capacity, the resistance value of this current-carrying path can be reasonably controlled, effectively reducing parasitics.

[0062] In a specific implementation, windows 211 can be opened corresponding to two pads 22 of the same network as chip 2, or windows 211 can be opened corresponding to a plurality of other pads 22 of the same network. In other possible implementations, multiple windows 211 can be opened corresponding to multiple different networks, such as, but not limited to, the four windows 211 shown in Figure 3. The multiple windows 211 can be arranged in a regular array as shown in Figure 3, or multiple windows can be opened irregularly according to the specific settings of the pin pads of multiple different networks on the chip 2 side (not shown in the figure). The embodiments of this application are not limited.

[0063] In a specific implementation, each chip 2 embedded in the embedded substrate 10 can adopt a strip-shaped first conductive structure 5 and be electrically connected to the circuit layer 4 on the front-side addition layer T.

[0064] In other specific implementations, the chips 2 embedded in the embedded substrate 10 may, depending on the actual function of each chip, adopt a strip-shaped first conduction structure 5 (not shown in the figure).

[0065] In other possible implementations, for a chip 2, all pads can be configured with a strip-shaped first conductive structure 5, as shown in Figure 2, and electrically connected to the circuit layer 4 on the front-side augmentation layer T; alternatively, some pads can be configured with a strip-shaped first conductive structure 5, while other pads can be configured with a first conductive structure having a circular current-carrying cross-section (not shown in the figure), and electrically connected to the circuit layer 4 on the front-side augmentation layer T respectively. This application does not limit the scope of the embodiments.

[0066] Please also refer to Figure 3, which is a cross-sectional view of DD in Figure 1. To clearly illustrate the layout of each second conduction structure 6 in the local vertical flow region, the number of second conduction structures 6 shown in Figure 3 is greater than the number of second conduction structures 6 in the corresponding region in Figure 1.

[0067] The second conductive structure 6 is a strip extending within the surface of the embedded substrate and has a strip-shaped flow passage cross-section. As shown in Figure 3, each second conductive structure 6 extends longitudinally (in the direction indicated by arrow X) within the surface of the embedded substrate. In other specific implementations, each second conductive structure 6 may also extend laterally (in the direction indicated by arrow Y) within the surface of the embedded substrate (not shown in the figure), or it may extend obliquely within the surface of the embedded substrate (not shown in the figure), that is, the strip-shaped second conductive structure 6 extends in directions that form angles with respect to the lateral and longitudinal directions, respectively.

[0068] Of course, for each local vertical current-carrying area S between the two line layers 4, the second conductive structure 6 can be set in the same direction. In other words, the strip-shaped second conductive structure 6 located in the same layer can be set in the same direction.

[0069] The second conductive structure 6 can be a copper strip (bur) in the shape of an inverted trapezoid, as shown in Figure 1. In a specific implementation, this strip-shaped second conductive structure 6 can be formed by laser grooving followed by electroplating. It should be understood that Figure 3 shows the strip-shaped flow-through cross-section at a cut position of each second conductive structure 6. For the inverted trapezoidal copper strip, its flow-through cross-section is strip-shaped, and the area of ​​each strip-shaped flow-through cross-section decreases from the outside to the inside.

[0070] Compared to blind via structures with circular flow passage cross-sections, this solution, based on the strip-shaped second conductive structure 6, can increase the proportion of the flow passage cross-section in the local vertical flow passage region S between layers. Under a typical design, for the same local vertical flow passage region, the proportion of the flow passage cross-section can be increased by more than 30%, effectively improving the vertical flow passage capacity. In addition, based on the strip-shaped second conductive structure 6, the thermal resistance of the interlayer heat dissipation path can be further reduced, improving heat dissipation capacity. At the same time, the strip-shaped second conductive structure 6 extending along the inner surface of the embedded substrate 10 achieves a flow passage effect, which can enhance the flow passage capacity in the interlayer plane (in the direction indicated by arrow X).

[0071] In specific implementations, for the interconnections between the inner circuit layers 4, strip-shaped second conductive structures 6 can be used for all interconnections, or, depending on product functional requirements, strip-shaped second conductive structures 6 can be used in some inter-layer interconnections. For two circuit layers 4 interconnected using strip-shaped second conductive structures 6, some interconnections can use strip-shaped second conductive structures 6, while other interconnections can use a first conductive structure with a circular current-carrying cross-section (not shown in the figure). This application does not limit the scope of the embodiments.

[0072] The aforementioned implementation uses a core board as the core retainer 1. In other specific implementations, a filler material can also be used to form the core retainer. That is, a core-free frame structure, which is simple in process and can reasonably control manufacturing costs.

[0073] In the foregoing embodiments, the strip-shaped second conductive structures 6 located on the same layer extend in the same direction. In other specific implementations, the second conductive structures 6 between the two circuit layers may also extend in different directions. Please refer to Figures 4 and 5, where Figure 4 is a cross-sectional view of another embedded substrate architecture provided in this application embodiment, and Figure 5 is an EE cross-sectional view in Figure 4. To clearly illustrate the differences and connections between this embodiment and the embedded substrate described in Figure 1, the same functional configurations and structures are indicated by the same reference numerals in the figures.

[0074] As shown in Figure 4, the main structure of the embedded substrate 10 is the same as that of the embedded substrate described in Figure 1, except that the strip-shaped second conductive structure 6 located in the same layer extends in different directions.

[0075] For example, the figure illustrates two local vertical flow regions located on the same layer, each representing a second conductive structure 6 extending in a different direction. In local vertical flow region S1, each second conductive structure 6 extends longitudinally within the surface of the embedded substrate, as shown in Figure 3. In local vertical flow region S2, each second conductive structure 6a extends laterally (in the direction indicated by arrow Y) within the surface of the embedded substrate.

[0076] In this way, the strip-shaped second conductive structure 6 located in the same layer extends in different directions, and the interlayer plane flow can be realized by the second conductive structure 6 in different extension directions (indicated by arrows X and Y) to further optimize the enhanced flow capacity obtained in the interlayer plane.

[0077] Of course, the strip-shaped second conductive structures 6 located on the same layer can also be configured to extend obliquely within the surface of the embedded substrate, and the specific arrangement can be determined according to the actual needs of the link. Please refer to Figure 6, which is a schematic diagram of another strip-shaped second conductive structure provided in an embodiment of this application. As shown in Figure 6, each strip-shaped second conductive structure 6d extends obliquely, and the strip-shaped second conductive structure 6c extends in directions that form angles with respect to the transverse and longitudinal directions, respectively.

[0078] In other possible implementations, the strip-shaped second conductive structures located on the same layer extend in different directions, including but not limited to at least two of the following: longitudinal extension, lateral extension, or oblique extension within the surface of the embedded substrate. Preferably, different extension directions of the strip-shaped second conductive structures can be selected and configured using local vertical flow areas as configuration units to improve manufacturability. The specific configuration can be determined based on the overall product design, and this application does not limit the specific implementation.

[0079] Furthermore, for an add-on layer with multiple circuit layers 4, the extension directions of the strip-shaped second conductive structures in two vertically overlapping local vertical current-passing regions between adjacent layers can be the same or different. In other words, the strip-shaped second conductive structures in two vertically adjacent and overlapping local vertical current-passing regions can extend in the same direction or in different directions.

[0080] As shown in Figure 4, the front-side layer T includes three circuit layers 4. The first local vertical current-passing region S1 and the third local vertical current-passing region S3 between two adjacent layers on the right side of the front-side layer T overlap vertically, and the strip-shaped second conductive structures 6 within them extend in the same direction, as shown in Figure 3, exhibiting a longitudinal extension. The second local vertical current-passing region S2 and the fourth local vertical current-passing region S4 between two adjacent layers on the left side of the front-side layer T overlap vertically, and the strip-shaped second conductive structures within them extend in different directions. The strip-shaped second conductive structure 6a of the second local vertical current-passing region S2 located between the outer layers extends laterally as shown in Figure 5; the strip-shaped second conductive structure 6a of the fourth local vertical current-passing region S4 located between the inner layers extends longitudinally as shown in Figure 3.

[0081] In this way, by arranging two local vertical flow regions that overlap vertically between adjacent layers into second conductive structures with different extension directions, the uniformity of stress in the interlayer microstructure can be improved, thereby enhancing the overall reliability of the embedded substrate 10.

[0082] It should be noted that the two locally overlapping vertical flow regions between adjacent layers mentioned above include the case of relative vertical overlap as shown in the figure, as well as the case of partial vertical overlap. The specific arrangement can be determined according to the overall product design requirements. As long as the adjacent layers are arranged with second conductive structures extending in different directions, the stress uniformity of the interlayer microstructure can be improved. This application does not impose any limitations on the embodiments.

[0083] Please refer to Figure 7, which is a cross-sectional view of another embedded substrate architecture provided in an embodiment of this application. To clearly illustrate the differences and connections between this embodiment and the embedded substrates described in Figures 1 and 4, the same functional components and structures are indicated by the same reference numerals in the figure.

[0084] As shown in Figure 7, the main structure of the embedded substrate 10 is the same as that described in Figures 1 and 4, except that the extension directions of the strip-shaped second conductive structures in the two vertically overlapping local current-passing regions between adjacent layers are different. In this embodiment, both the front layer T and the back layer B of the embedded substrate 10 include multiple circuit layers 4, and the second conductive structures in the two vertically overlapping local current-passing regions between adjacent layers are set with different extension directions.

[0085] Taking the front-side addition layer T as an example, the fifth local vertical flow region S5 and the sixth local vertical flow region S6 between two adjacent layers on the right side of the front-side addition layer T overlap vertically. The strip-shaped second conductive structure 6a of the fifth local vertical flow region S5 located between the outer layers is arranged laterally as shown in Figure 5; the strip-shaped second conductive structure 6 of the sixth local vertical flow region S6 located between the inner layers is arranged longitudinally as shown in Figure 3. Among them, the seventh local vertical flow region S7 and the eighth local vertical flow region S8 between two adjacent layers on the left side of the front layer T overlap vertically, and the extension directions of the strip-shaped second conductive structures in the two are different; the strip-shaped second conductive structure 6a of the seventh local vertical flow region S7 located between the outer layers is arranged laterally as shown in Figure 5; the strip-shaped second conductive structure 6a of the eighth local vertical flow region S8 located between the inner layers is arranged longitudinally as shown in Figure 3.

[0086] In this implementation scheme, the extension directions of the second conductive structures are also arranged differently between the various circuit layers on the B side of the back-side addition. This will not be elaborated further here.

[0087] In other possible implementations, the extension direction of the strip-shaped second conduction structure between the corresponding layers can be configured according to the link requirements, which can meet the product function requirements of different application scenarios and has good adaptability.

[0088] Furthermore, in the embedded substrates described in the foregoing embodiments, both the first and second conductive structures employ strip-shaped conductive structures. In other possible implementations, either the first or second conductive structure may be a strip-shaped conductive structure, achieving corresponding technical advantages. For example, the first conductive structure electrically connecting the chip pads and the add-on circuit layer employs a strip-shaped conductive structure; the second conductive structure electrically connecting the add-on circuit layers employs a conventional conductive blind via structure. As another example, the first conductive structure electrically connecting the chip pads and the add-on circuit layer employs a conventional conductive blind via structure; the second conductive structure electrically connecting the add-on circuit layers employs a strip-shaped conductive structure.

[0089] Furthermore, the embedded substrates described in the foregoing embodiments all include a front-side uplift layer T and a back-side uplift layer B. In other possible implementations, the back-side uplift layer B may be selectively provided, and this application does not limit this.

[0090] The following is a brief explanation of the manufacturing process of the embedded substrate 10 described in Figure 7, with reference to Figure 8.

[0091] Step S801: Prepare the core retainer 1. In a specific implementation, based on the core board material, through holes 11 and interface pads 111 that form the core retainer 1 can be prepared.

[0092] Step S802: Grooving the core holder 1. An embedded groove 1-1 is formed on the core holder 1. In specific implementations, a UV laser, a CO2 laser, or other machining processes can be used to create the groove.

[0093] Step S803, apply adhesive film. Apply adhesive film 1-2 to the first surface 1A of the core retainer 1.

[0094] Step S804: Mounting the chip and electronic component. Specifically, chip 2 and electronic component 3 are embedded in the embedding groove and mounted face up on adhesive film 1-2; here, electronic component 3 can be a capacitor, resistor or inductor.

[0095] Step S805, back fill lamination. The embedded filler material 1-3 can be ABF, or selected according to actual process conditions. Here, while laminating and filling the gaps between the devices and between the devices and the embedded groove, the embedded filler material 1-3 also forms a dielectric layer that bonds to the second surface 1B side of the core holder 1. At the same time, the surface copper of the circuit layer 4 of the first back-side enhancement layer can also be formed.

[0096] The first back layer here is the back layer structure that is joined to the second surface of the core retainer 1.

[0097] Step S806: Remove the adhesive film and perform front-side filling and lamination. While the embedded filler materials 1-3 are laminating and filling the gaps between the components and between the components and the embedded grooves, a dielectric layer is also formed that bonds to the first side of the core retainer 1. Simultaneously, the surface copper of the first front-side added circuit layer 4 can also be formed.

[0098] The first front layer here is the layer structure in which the front layer is joined to the first surface of the core retainer 1.

[0099] Step S807: Open hole 2-1 on the front side and remove adhesive. This opening 2-1 corresponds to the pin pads of chip 2 and electronic component 3 respectively. In specific implementations, a UV laser, CO2 laser, or other machining processes can be used to open the hole.

[0100] Step S808 involves copper plating and electroplating to form a strip-shaped first conductive structure 5 and other conductive structures, as well as a circuit layer 4.

[0101] Step S809: Lamination to form an intermediate add-on layer. In a specific implementation, based on the front first add-on layer and the back first add-on layer, the front intermediate add-on layer and the back intermediate add-on layer copper layer are laminated to form respectively.

[0102] Step S810: Open hole 2-2 on the front side and remove adhesive. This opening 2-2 corresponds to the interconnection relationship between the two circuit layers 4 in the add-on layer. In specific implementation, the opening can be made using a UV laser, CO2 laser, or other machining processes.

[0103] Step S811 involves copper plating and electroplating to form interlayer strip-shaped second conductive structures and circuit layer 4. The strip-shaped second conductive structure 6 on the front-side layer addition is shown in Figure 3, and the strip-shaped second conductive structure 6a on the back-side layer addition is shown in Figure 5.

[0104] Step S812, surface patterning. In specific implementation, different process routes can be used, such as, but not limited to, processes such as lamination, exposure, development, patterned via-filling electroplating, stripping and flash etching, or processes such as full-board via-filling electroplating, lamination, exposure, development, etching and stripping.

[0105] Step S813 involves laminating to form an outer layer, creating interlayer strip-shaped second conductive structures and circuit layer 4, while simultaneously forming an outer solder mask layer and processing the surface of the outer metal layer. The strip-shaped second conductive structure 6a on the front layer side is shown in Figure 5, and the strip-shaped second conductive structure 6 on the back layer side is shown in Figure 3.

[0106] In specific implementations, surface metal treatments include, but are not limited to, ENEPIG (Electroless Nickel Electroless Palladium Immersion Gold), ENIG (Electroless Nickel / Immersion Gold), OSP (Organic Solderability Preservative), or SOP processes.

[0107] In other possible implementation schemes, the number of layers for each outer layer can be determined according to the overall product design requirements, and corresponding manufacturing processes can be established. This application does not limit the specific implementation.

[0108] The embedded substrate architecture schemes described in the foregoing embodiments can be widely applied to the packaging structures of different functional modules. In practical applications, the above-mentioned technical advantages are particularly significant in power module architecture scenarios. Please refer to Figure 9, which is a schematic diagram of an application scenario of a power supply device provided by an embodiment of this application.

[0109] As shown in Figure 9, the power supply device 100 includes a chip 2, an inductor 20, and multiple electronic components. The electronic components 3 can be capacitors and / or resistors to form corresponding functional circuits. The chip 2 is embedded in a package using the embedded substrate 10 architecture described in Figure 1 or Figure 4; the inductor 20 can be surface-mounted on the back side of the embedded substrate 10, that is, the surface of the second side of the embedded substrate 10 near the core retainer 1. The front side of the embedded substrate 10 is mounted on one side of the system board 200, and the processor 300 is mounted on the other side of the system board 200. For example, but not limited to, the processor can be an XPU.

[0110] In a specific implementation, some of the multiple electronic components can be embedded together with the chip 2 in the embedded substrate 10, while other electronic components can be surface-mounted together with the inductor 20 on the back side of the embedded substrate 10. This application does not limit the scope of the embodiments.

[0111] In use, the high-speed transmission channels formed vertically and within the board surface based on the internal structure of the embedded substrate can reduce the resistance of the entire link between the power chip 2, system board 200 and processor 300 chip, as well as between the power chip 2 and inductor 20, thereby improving the current carrying capacity. At the same time, it can reasonably control link parasitics and take into account good thermal conductivity and reliability.

[0112] In other implementations, the inductor 20 can be surface-mounted on the front side of the embedded substrate 10. Please refer to Figure 10, which is a schematic diagram of another application scenario of the power supply device provided in this embodiment. In order to clearly show the differences and connections between this embodiment and the power supply device described in Figure 9, the same functional configurations or structures are indicated by the same reference numerals in the figure.

[0113] As shown in Figure 10, the power supply device 100 includes a chip 2, an inductor 20, and multiple electronic components. The chip 2 is embedded in a package using the embedded substrate 10 architecture described in Figure 1 or Figure 4. The inductor 20 can be surface-mounted on the front side of the embedded substrate 10, that is, the surface of the first side of the embedded substrate 10 near the core holder 1. The back side of the embedded substrate 10 is mounted on one side of the system board 200, and the processor 300 is mounted on the other side of the system board 200.

[0114] Compared to the power supply device described in Figure 9, this embodiment can shorten the link length between the power chip 2 and the inductor 20, and reduce parasitic resistance. Similarly, in a specific implementation, some of the multiple electronic components can be embedded in the embedded substrate 10 together with the chip 2, while other electronic components can be surface-mounted on the back side of the embedded substrate 10 together with the inductor 20. This application does not limit the scope of the embodiments.

[0115] It should be understood that the other functions of the power supply device are not the core inventive points of this application, and can be implemented by those skilled in the art based on existing technology, so they will not be described in detail here.

[0116] In addition to the aforementioned embedded substrate, this embodiment also provides an electronic device. Please refer to Figure 11, which is a schematic diagram of the structure of an electronic device provided in an embodiment of this application.

[0117] As shown in Figure 11, the electronic device 1000 includes a housing 400 and a system board 200 disposed within the housing 400. The system board 200 is equipped with a power supply device 100 as described in the foregoing embodiments. A processor (not shown in the figure) may be disposed on the system board 200. Based on the power supply device 100's excellent high current carrying capacity, low parasitics, high thermal conductivity, and high reliability, it can be widely used in various high-density application scenarios.

[0118] In specific implementations, the electronic device can be a server, a computer, or a high-performance computing cluster, such as a high-power, highly integrated, and ultra-large-scale data center server; in addition, the electronic device can also be a switch, a router, or an edge device, etc., which are not limited in the embodiments of this application.

[0119] It should be understood that other functions of the electronic device are not the core inventive points of this application, and can be implemented by those skilled in the art based on existing technology, so they will not be described in detail here.

[0120] The above are merely preferred embodiments of the present invention. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. An embedded substrate, characterized by, The inner-embedded substrate comprises a core holding body, a build-up layer and a chip embedded in the core holding body, the core holding body comprises a first surface and a second surface, a front surface of the chip is arranged towards the first surface of the core holding body, the front surface of the chip comprises an outer protective layer outside the pads thereof, the outer protective layer has windows corresponding to the pads; The build-up layer comprises a front build-up layer covering the first surface of the core holding body, the circuit layer of the front build-up layer and the pads of the chip are electrically connected through a first conductive structure; the circuit layers in the build-up layer are electrically connected through a second conductive structure; At least one of the first conductive structure and the second conductive structure is a strip extending in the surface of the inner-embedded substrate.

2. The embedded substrate of claim 1, wherein, The build-up layer further comprises a back build-up layer covering the second surface of the core holding body.

3. The embedded substrate according to claim 1 or 2, wherein The first conductive structure is a strip extending in the surface of the inner-embedded substrate, the windows on the outer protective layer correspond to a plurality of network pads of the chip, and the strip-shaped first conductive structure is electrically connected with the plurality of network pads.

4. The embedded substrate of claim 3, wherein, The windows are strip-shaped windows matched with the first conductive structure, and the strip-shaped windows and the first conductive structure have a spacing therebetween.

5. The embedded substrate according to any one of claims 1 to 4, wherein, The chip is arranged in a plurality of forms, and at least one pad of the chip is electrically connected with the circuit layer of the front build-up layer through the strip-shaped first conductive structure.

6. The embedded substrate according to any one of claims 1 to 5, wherein, The chip comprises a plurality of pads, and at least part of the pads of the chip are electrically connected with the circuit layer of the front build-up layer through the strip-shaped first conductive structure.

7. The embedded substrate according to any one of claims 1 to 6, wherein, The second conductive structure is a strip extending in the surface of the inner-embedded substrate, the build-up layer comprises a plurality of circuit layers, and the strip-shaped second conductive structure is arranged between the adjacent circuit layers.

8. The embedded substrate of claim 7, wherein, The local vertical flow-through areas between two circuit layers are electrically connected through a plurality of strip-shaped second conductive structures.

9. The embedded substrate of claim 8, wherein, The local vertical flow-through areas between two circuit layers comprise a plurality of local vertical flow-through areas, and at least part of the local vertical flow-through areas are electrically connected through the strip-shaped second conductive structure.

10. The embedded substrate according to any one of claims 7 to 9, wherein, Each of the second conductive structures between two circuit layers is arranged in the same direction or in different directions in the surface of the inner-embedded substrate.

11. The embedded substrate according to any one of claims 7 to 10, wherein, The strip-shaped second conductive structures between two vertically adjacent and overlapping local vertical flow-through areas are arranged in the same direction or in different directions in the surface of the inner-embedded substrate.

12. The embedded substrate according to any one of claims 8 to 11, wherein, The plurality of strip-shaped second conductive structures corresponding to the local vertical flow-through areas are arranged in the same direction or in different directions in the surface of the inner-embedded substrate.

13. The embedded substrate according to any one of claims 7 to 12, wherein, The extension direction of the strip-shaped second conductive structure in the surface of the inner-embedded substrate comprises at least one of a horizontal direction, a vertical direction and an oblique direction with respect to the horizontal direction and the vertical direction.

14. The embedded substrate of any one of claims 1 to 13, wherein, The inner-embedded substrate further comprises a plurality of electronic elements embedded in the core holding body, and at least one of the plurality of electronic elements is a capacitor or a resistor.

15. The embedded substrate according to any one of claims 1 to 14, wherein, The core holding body is a core plate or a filling medium layer filled with a filling medium material.

16. A power supply device characterized by comprising: The power supply device comprises a chip and an inductive element, the chip is embedded in the embedded substrate, and the inductive element is attached to the embedded substrate.

17. The power supply device of claim 16, wherein The inductive element is attached to the front surface or the back surface of the embedded substrate.

18. The power supply device of claim 17, wherein The power supply device further comprises a plurality of electronic elements, a part of the plurality of electronic elements is embedded in the embedded substrate, and another part of the plurality of electronic elements is attached to the embedded substrate.

19. An electronic device, comprising: The power supply device comprises a system board and a power supply device, the power supply device is arranged on the system board, and the power supply device is the power supply device according to any one of claims 16 to 18.

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