Display panel and display apparatus

Abstract

The present disclosure relates to the technical field of display, and provides a display panel and a display apparatus. The display panel comprises: a driving substrate, the driving substrate comprising a plurality of thin film transistors; a plurality of light-emitting devices, located on one side of the driving substrate, each light-emitting device comprising a first electrode, a light-emitting functional layer, and a second electrode which are sequentially arranged in the thickness direction of the driving substrate; and lead structures, located on one side of the driving substrate and insulated from the thin film transistors. The first electrodes are electrically connected to the lead structures and the thin film transistors, separately.

Description

Display panel and display device

[0001] The present disclosure claims priority to the Chinese patent application No. 202411024756.X, filed on July 26, 2024, and entitled "Display panel and display device", the entire content of which is incorporated herein by reference. TECHNICAL FIELD

[0002] The present disclosure relates to the technical field of display, and in particular, to a display panel and a display device. BACKGROUND

[0003] OLED (Organic Light Emitting Diode) display panels have the advantages of self-emission, wide viewing angle, wide color gamut, high contrast, thinness, etc., and are widely used in various display products. However, the current display panel is prone to dark spot defects.

[0004] SUMMARY

[0005] Based on the content of the background art, the present disclosure provides a display panel and a display device.

[0006] In a first aspect, the present disclosure provides a display panel, comprising:

[0007] a driving substrate comprising a plurality of thin film transistors;

[0008] a plurality of light emitting devices located on one side of the driving substrate, the light emitting devices comprising a first electrode, a light emitting functional layer and a second electrode arranged in the thickness direction of the driving substrate; and

[0009] a lead structure located on one side of the driving substrate and insulated from the thin film transistors;

[0010] wherein the first electrode is electrically connected to the lead structure and the thin film transistors, respectively.

[0011] Exemplarily, the lead structure comprises a first metal line and a second metal line.

[0012] wherein the first metal line is electrically connected to the first electrode through the second metal line.

[0013] Exemplarily, the first metal line and the second metal line are located in different film layers, respectively.

[0014] wherein the second metal line is overlapped with the first metal line through a via hole formed in a film layer located between the second metal line and the first metal line.

[0015] Exemplarily, the thin film transistor comprises a source electrode and a drain electrode arranged in the same layer.

[0016] The first metal line is arranged in the same layer as the source electrode and the drain electrode.

[0017] Exemplarily, the first metal line is connected with a plurality of the second metal lines.

[0018] Different second metal lines are connected with the first electrodes in different light emitting devices.

[0019] Exemplarily, the display panel further comprises a data line connected with the thin film transistor, and the extension direction of the first metal line is the same as the extension direction of the data line.

[0020] The first metal line and the data line are spaced apart in the planar direction or the thickness direction of the driving substrate.

[0021] Exemplarily, the first metal line and the data line are spaced apart in the planar direction of the driving substrate, and the orthographic projection of the data line on the driving substrate is located between the orthographic projection of the first metal line on the driving substrate and the orthographic projection of the first electrode on the driving substrate.

[0022] The second metal line is not in the same layer as the data line.

[0023] Exemplarily, the second metal line comprises at least one fuse area, and / or the melting point of the second metal line is lower than the melting point of the first metal line.

[0024] When current flows through the lead structure, the metal line in the fuse area breaks before the metal line in the non-fuse area; the non-fuse area is an area of the second metal line other than the fuse area.

[0025] Exemplarily, the melting point of the second metal line is lower than the melting point of the first metal line; and the material of the second metal line comprises lead-antimony alloy or aluminum-antimony alloy.

[0026] Exemplarily, the second metal line comprises at least one fuse area.

[0027] The line width of the fuse area is smaller than the line width of the non-fuse area, and / or the thickness of the fuse area is smaller than the thickness of the non-fuse area.

[0028] Exemplarily, the orthographic projection of at least one of the fuse areas on the driving substrate does not overlap with the orthographic projection of the first electrode on the driving substrate.

[0029] Exemplarily, the first electrode comprises a plurality of metal electrode layers arranged in sequence in a thickness direction of the driving substrate.

[0030] The lead structure is in direct contact with at least one of the metal electrode layers.

[0031] Exemplarily, the driving substrate comprises:

[0032] A light-blocking metal layer, a projection of the light-blocking metal layer on the driving substrate covers a projection of the first electrode on the driving substrate.

[0033] A buffer layer located on a side of the light-blocking metal layer close to the light-emitting device; and

[0034] A driving circuit layer located on a side of the buffer layer close to the light-emitting device, and a plurality of the thin film transistors are located on the driving circuit layer.

[0035] The thin film transistors are electrically connected to the first electrode through the light-blocking metal layer.

[0036] Exemplarily, the light-blocking metal layer comprises a first region, a second region, and a third region located between the first region and the second region.

[0037] The projection of the first region on the driving substrate covers the projection of the first electrode on the driving substrate, and the projection of the second region on the driving substrate does not overlap the projection of the first electrode on the driving substrate.

[0038] The projection of the lead structure on the driving substrate does not overlap the projection of the third region and / or the second region on the driving substrate.

[0039] Exemplarily, the display panel comprises a light-emitting region and a light-transmitting region, the light-emitting device is located in the light-emitting region, and the display panel further comprises:

[0040] A planar layer located on a side of the first electrode close to the driving substrate, a projection of the planar layer on the driving substrate covers the projection of the first electrode on the driving substrate, and partially overlaps the light-transmitting region.

[0041] The lead structure is in direct contact with an edge of the planar layer and then in direct contact with the first electrode.

[0042] Exemplarily, the display panel comprises a light-emitting region and a light-transmitting region, the light-emitting device is located in the light-emitting region, and the display panel further comprises:

[0043] An auxiliary electrode structure located on a side of the driving substrate close to the light-emitting device.

[0044] The light-emitting functional layer and the second electrode are disconnected at the auxiliary electrode structure, the auxiliary electrode structure is electrically connected between the second electrode, and the lead structure is insulated.

[0045] Exemplarily, the auxiliary electrode structure includes a plurality of auxiliary electrode layers arranged in the thickness direction of the driving substrate in sequence.

[0046] At least one of the auxiliary electrode layers is arranged in the same layer as the lead structure.

[0047] In a second aspect, the present disclosure provides a display device including the display panel of any one of the example embodiments of the first aspect.

[0048] The display panel provided by the present disclosure includes a driving substrate including a plurality of thin film transistors, a plurality of light-emitting devices located on one side of the driving substrate, the light-emitting device including a first electrode, a light-emitting functional layer and a second electrode arranged in the thickness direction of the driving substrate in sequence, and a lead structure located on one side of the driving substrate and insulated between the thin film transistors; wherein the first electrode is electrically connected with the lead structure and the thin film transistor, and the lead structure and the thin film transistor are located in different circuits. Since the lead structure and the thin film transistor are insulated and located in different circuits, the lead structure can bypass the thin film transistor to independently introduce a current different from the thin film transistor, such as a current higher than the thin film transistor, to the first electrode, thereby providing a large current to the first electrode through the lead structure. Under the action of the large current, the lump-shaped conductive material in the light-emitting functional layer that causes the short circuit between the first electrode and the second electrode can be passivated into an insulating material, thereby solving the problem of display panel dark spot defects caused by the short circuit between the first electrode and the second electrode.

[0049] The above description is only a summary of the technical solutions of the present disclosure. In order to more clearly understand the technical means of the present disclosure, the following specific embodiments of the present disclosure can be implemented according to the content of the description, and in order to make the above and other purposes, features and advantages of the present disclosure more obvious and easy to understand, the following specific embodiments of the present disclosure are described.

[0050] Brief Description of Drawings

[0051] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or the related art, the following will briefly introduce the drawings needed to be used in the embodiments or related art descriptions. Obviously, the drawings in the following description are some embodiments of the present disclosure, and those skilled in the art can also obtain other drawings according to these drawings without creating any creative labor. It should be noted that the proportions in the drawings are only for illustration and do not represent the actual proportions.

[0052] FIG. 1 shows an electron microscope image caused by growth of a cathode along a clump foreign matter in the related art;

[0053] FIG. 2 shows a cross-sectional structure schematic diagram of a display panel in an embodiment of the present disclosure;

[0054] FIGS. 3 and 4 respectively show two connection schematic diagrams of a light emitting device and a lead structure;

[0055] FIG. 5 shows a planar layout schematic diagram of a display panel when a pixel driving circuit is a 3T1C driving circuit in an embodiment of the present disclosure;

[0056] FIG. 6 shows a circuit schematic diagram between a first electrode and a pixel driving circuit and a lead structure in an embodiment of the present disclosure;

[0057] FIGS. 7-9 respectively show cross-sectional structure schematic diagrams of three other display panels in embodiments of the present disclosure;

[0058] FIGS. 10-11 respectively show top planar schematic diagrams of two other display panels in embodiments of the present disclosure;

[0059] FIG. 12 shows a connection structure schematic diagram between a lead structure and a first electrode in an embodiment of the present disclosure;

[0060] FIGS. 13-15 respectively show cross-sectional structure schematic diagrams of three other display panels in embodiments of the present disclosure;

[0061] FIGS. 16-18 respectively show top planar structure schematic diagrams of a display panel in a process of forming an exemplary display panel in embodiments of the present disclosure.

[0062] 10, driving substrate; 20, light emitting device; 31, planarization layer; 32, passivation layer; 40, lead structure; 50, auxiliary structure; 60, pixel definition layer; 11, substrate; 12, buffer layer; 13, interlayer dielectric layer; 14, light shielding metal layer; 15, thin film transistor; 151, source region; 152, source electrode; 153, gate layer; 154, gate insulating layer; 155, channel region; 156, drain region; 157, drain electrode; 158, extension; 131, third via hole; 132, fourth via hole; 16, gate metal layer; 17, insulating layer; 181, first power line; 182, data line; 183, sensing line; G1, first gate line; G2, second gate line; T1, first thin film transistor; T2, second thin film transistor; T3, third thin film transistor; 21, first electrode; 22, second electrode; 23, light emitting functional layer; 211, fourth metal electrode layer; 212, third metal electrode layer; 213, second metal electrode layer; 214, first metal electrode layer; 311, first via hole; 321, second via hole; 41, first metal line; 42, second metal line; 422, non-fusible region; 421, fusible region; 51, first auxiliary electrode layer; 52, second auxiliary electrode layer; 53, third auxiliary electrode layer; 54, fourth auxiliary electrode layer; 55, fifth auxiliary electrode layer; 56, sixth auxiliary electrode layer.

[0063] DETAILED DESCRIPTION

[0064] In order to make the objects, technical solutions, and advantages of the embodiments of the present disclosure clearer, the technical solutions in the embodiments of the present disclosure will be described clearly and completely below with reference to the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are some but not all of the embodiments of the present disclosure. Based on the embodiments in the present disclosure, all other embodiments obtained by a person of ordinary skill in the art without creative work fall within the protection scope of the present disclosure.

[0065] In the present specification, "parallel" refers to a state in which the angle formed by two straight lines is -10° or more and 10° or less, and thus also includes a state in which the angle is -5° or more and 5° or less. In addition, "perpendicular" refers to a state in which the angle formed by two straight lines is 80° or more and 100° or less, and thus also includes a state in which the angle is 85° or more and 95° or less.

[0066] In the present specification, a polygon is not strictly a triangle, a parallelogram, a trapezoid, a pentagon, or a hexagon, and the like, and can be an approximate polygon, and can include some small deformation due to a tolerance.

[0067] In the OLED display panel, the organic light-emitting layer (light-emitting functional layer 23) EL will generate some conductive foreign matter in the film forming process. Since the cathode is mostly formed by magnetron sputtering process, the diffusion performance is relatively strong, so the cathode will grow along the conductive foreign matter to cause short circuit between the anode below, thereby causing dark point defects. Referring to FIG. 1, an electron microscope image caused by the growth of the cathode along the conductive foreign matter is shown.

[0068] In the related art, the dark point defects can be effectively solved by passivating the conductive foreign matter by applying a large current to the anode. However, since the anode is connected to the thin film transistor 15, the current intensity between the anode and the cathode is limited due to the current limiting effect of the thin film transistor 15 itself, so the above-mentioned dark point defects cannot be completely eliminated.

[0069] Referring to FIGS. 2-4, FIG. 2 shows a cross-sectional structure schematic diagram of a display panel in an embodiment of the present disclosure, FIGS. 3 and 4 respectively show two connection schematic diagrams of a light-emitting device 20 and a lead structure 40. As shown in FIGS. 2-4, the display panel in the embodiment can include:

[0070] A driving substrate 10, the driving substrate 10 includes a plurality of thin film transistors 15;

[0071] A plurality of light-emitting devices 20 located on one side of the driving substrate 10, the light-emitting device 20 includes a first electrode 21, a light-emitting functional layer 23 and a second electrode 22 arranged in the thickness direction of the driving substrate 10; and

[0072] A lead structure 40 located on one side of the driving substrate 10 and insulated between the thin film transistor 15;

[0073] Among them, the first electrode 21 is electrically connected with the lead structure 40 and the thin film transistor 15 respectively.

[0074] In the embodiment, the display panel can include a sub-pixel region and a non-sub-pixel region, wherein the non-sub-pixel region is a region in the display panel other than the sub-pixel region. It should be noted that the sub-pixel region and the non-sub-pixel region are divided on the plane where the display surface of the display panel is located. Specifically, the sub-pixel region and the non-sub-pixel region can be located in the display area of the display panel.

[0075] In an example, the display panel can be a transparent display panel, and the driving substrate 10 can be a transparent driving substrate 10. The sub-pixel region can be referred to as a light-emitting region, and the non-sub-pixel region can be referred to as a light-transmitting region.

[0076] In this embodiment, the plurality of thin film transistors TFT on the driving substrate 10 can constitute a pixel driving circuit for the plurality of light emitting devices 20, and the plurality of pixel driving circuits respectively provide driving voltages for the plurality of light emitting devices 20. The pixel driving circuit of the light emitting device 20 can be a 3T1C driving circuit, a 5T1C driving circuit, or a 7T1C circuit. Referring to FIG. 5, a schematic diagram of a planar layout of a display panel is shown when the pixel driving circuit is a 3T1C driving circuit. As an example, when the pixel driving circuit is a 3T1C driving circuit, the pixel driving circuit of each light emitting device 20 can include a first thin film transistor T1, a second thin film transistor T2, and a third thin film transistor T3. The driving substrate 10 is provided with a data line 182, a sensing line 183, a first power supply line 181, and a plurality of gate lines. The data line 182 is connected to the source region of the first thin film transistor, the sensing line 183 is connected to the source region of the second thin film transistor, the first power supply line 181 is connected to the source region of the third thin film transistor, the drain region of the first thin film transistor is connected to the gate of the third thin film transistor, and the drain of the second thin film transistor is connected to the drain of the third thin film transistor and the drain of the first thin film transistor. The driving substrate 10 further includes a plurality of gate lines, such as a first gate line G1 and a second gate line G2. The first gate line G1 is connected to the gate of the first thin film transistor and is connected to the gate of the first thin film transistor of the next light emitting device 20 through a wire, and the second gate line G2 is connected to the gate of the second thin film transistor. The driving principle of the 3T1C can refer to related technologies, which will not be described in detail here.

[0077] In an example, the thin film transistor 15 can be a top-gate structure or a bottom-gate structure. As shown in FIG. 2, the thin film transistor 15 is a top-gate structure. The driving substrate 10 can include a substrate 11, an active layer on one side of the substrate 11, a gate insulating layer 154 on the side of the active layer away from the substrate 11, a gate layer 153 on the side of the gate insulating layer 154 away from the substrate 11, an interlayer dielectric layer 13 on the side of the gate layer 153 away from the substrate 11, a source electrode 152 and a drain electrode 157 on the side of the interlayer dielectric layer 13 away from the substrate 11. Specifically, the active layer can include a channel region 155 corresponding to the gate layer 153, a source region 151 overlapped with the source electrode 152, and a drain region 156 overlapped with the drain electrode 157. The source region 151 and the drain region 156 are formed after the active layer is conductorized. The gate insulating layer 154, the source electrode 152, the drain electrode 157, the gate layer 153, and the active layer constitute a TFT. As shown in FIG. 2, the drain electrode 157 can be electrically connected to the first electrode 21 in the light emitting device 20.

[0078] In the embodiment, as shown in FIG. 2, the driving substrate 10 further includes a pixel definition layer 60 on one side of the driving substrate 10, the pixel definition layer 60 includes a plurality of openings, the openings are used to define light emitting areas, and the light emitting device 20 can be located in the openings. Specifically, the first electrode 21 in the light emitting device 20 can be located in the openings, the light emitting functional layer 23 can be located in the openings, or the light emitting functional layer 23 can cover the driving substrate 10 entirely; and the second electrode 22 can cover the driving substrate 10 entirely.

[0079] The first electrode 21 can be an anode, and the second electrode 22 can be a cathode, or the first electrode 21 can be a cathode, and the second electrode 22 can be an anode. In the embodiment, the first electrode 21 is taken as an anode, and the second electrode 22 is taken as a cathode as an example for description. Specifically, the first electrode can be formed by ITO (indium tin oxide), and the second electrode can be formed by IZO (indium tin oxide). The first electrode 21 can be close to the driving substrate 10, the light emitting functional layer 23 can be located on the side of the first electrode 21 away from the driving substrate 10, and the second electrode 22 can be located on the side of the light emitting functional layer 23 away from the driving substrate 10.

[0080] The lead structure 40 can be located on the same side of the driving substrate 10 as the light emitting device 20, the lead structure 40 is insulated from the thin film transistor 15, and further, the lead structure 40 and the thin film transistor 15 can be located in different circuits. For example, the thin film transistor 15 is located in a pixel driving circuit, and the lead structure 40 is not located in the pixel driving circuit. The insulation between the lead structure 40 and the thin film transistor 15 can mean that the lead structure 40 and the thin film transistor 15 are not in communication, and the circuit in which the lead structure 40 is located and the circuit in which the thin film transistor 15 is located are not in communication with each other, and there is no current flow between the two circuits. In this way, the lead structure 40 and the thin film transistor 15 can be connected to different sources of the display panel, which means ports for outputting current to the light emitting device 20. For example, the lead structure 40 and the thin film transistor 15 can be connected to different pins of a display driving chip of the display panel, so that the lead structure 40 and the thin film transistor 15 can supply power to the first electrode 21 independently of each other.

[0081] In an example, a plurality of light emitting devices 20 can be connected to a plurality of lead structures 40, and the plurality of lead structures 40 are insulated from each other. For example, as shown in FIG. 3, the first electrodes 21 of different light emitting devices 20 can be connected to different lead structures 40. In this way, the lead structures 40 connected to the plurality of light emitting devices 20 can be independent of each other, so that each light emitting device 20 can be introduced into current by the lead structure 40 independently of other light emitting devices 20, thereby passivating the conductive foreign matter in the light emitting device 20 that appears dark spots in a targeted manner.

[0082] In yet another example, a plurality of light emitting devices 20 can share one lead structure 40, as shown in FIG. 4, the first electrodes 21 of the plurality of light emitting devices 20 in one column can be connected to the same lead structure 40, thus, the first electrodes 21 in the same column can be connected in parallel to the same lead structure 40. In this way, one lead structure 40 can introduce current to a plurality of light emitting devices 20 at the same time, so as to passivate the conductive foreign matter in the form of clusters existing in the plurality of regions.

[0083] In some examples, as shown in FIG. 2, the lead structure 40 can be in the same layer as the first electrode 21 in the light emitting device 20, specifically, the lead structure 40 can be formed after the formation of the first electrode 21 in the layer where the first electrode 21 is located, thus, the lead structure 40 can be formed by one process, for example, by one patterning process. In yet other examples, please refer to the display panel shown in FIG. 8 below, part of the structure in the lead structure 40 can be in the same layer as the light emitting device 20, and the rest of the structure can be in different layers from the light emitting device 20, thus, the lead structure 40 can be formed after multiple processes.

[0084] In this embodiment, the lead structure 40 is formed of a metal material, specifically, in the case where the display panel is a transparent display panel, the lead structure 40 can be formed of a transparent metal material, in practice, the metal material can be different from the material of the first electrode 21.

[0085] In this embodiment, as shown in FIG. 6, a circuit schematic diagram between the first electrode 21 and the pixel driving circuit and the lead structure 40 is shown, as shown in FIG. 6, the current on the data line 182 flows into the first thin film transistor T1, the first gate line G1 turns on the first thin film transistor, so that the current on the data line serves as the gate driving voltage of the third thin film transistor, the first power line inputs the voltage Vdd to the third thin film transistor, which can turn on the third thin film transistor, then, the second gate line can turn on the second thin film transistor, the capacitor structure arranged between the first thin film transistor and the second thin film transistor can serve as a storage capacitor, so that the three thin film transistors are all turned on, so that the current input on the data line is given to the anode of the light emitting device 20, so as to drive the light emitting device to emit light. It should be noted that VSS in FIG. 6 is provided by the second power line, which provides a low voltage, such as a negative voltage. As can be seen from FIG. 6, the lead structure 40 can bypass the pixel driving circuit and introduce a large current to the anode alone, so that the large current directly acts on the anode. In this way, the input end of the anode of the light emitting device 20 is connected in parallel to the pixel driving circuit and the lead structure 40.

[0086] The display panel provided by the embodiment is insulated from the thin film transistor 15 and in different circuits, so that the lead structure 40 and the thin film transistor 15 can independently supply power to the first electrode 21 in the light emitting device 20. The pixel driving circuit in which the thin film transistor 15 is located can provide a driving voltage to the light emitting device 20 to make the light emitting device 20 emit light; the lead structure 40 can input a large current to the first electrode 21 in the light emitting device 20 to make the lump-shaped conductive material in the light emitting functional layer 23 be passivated into insulating material, which causes the short circuit between the first electrode 21 and the second electrode 22. Thus, the introduced lead structure 40 can solve the problem of dark spot defect of the display panel caused by the short circuit between the first electrode 21 and the second electrode 22, bypass the power supply of the thin film transistor 15, so as to be free from the influence of the current limiting of the thin film transistor 15, and can completely eliminate the problem of dark spot of the display panel caused by the existence of the lump-shaped conductive material.

[0087] The display panel includes a light emitting area and a light transmitting area, and the light transmitting area can refer to an area other than the light emitting area. In practice, the light emitting device 20 is located in the light emitting area, and the lead structure 40 can be located in the light transmitting area, so that the lead structure 40 does not occupy or occupies less space of the light emitting area, and does not affect the light emitting efficiency.

[0088] In the embodiment, as shown in FIG. 2, the display panel can further include a pixel defining layer 60, and the pixel defining layer 60 can include a plurality of openings. The openings can define the light emitting area, and the light emitting device 20 can be located in the openings. In one example, the orthographic projection of the lead structure 40 on the driving substrate 10 can be covered by the orthographic projection of the pixel defining layer 60 on the driving substrate 10. In another example, the orthographic projection of the lead structure 40 on the driving substrate 10 can overlap with the orthographic projection of the pixel defining layer 60 on the driving substrate 10, and does not overlap with the orthographic projection of the openings on the driving substrate 10.

[0089] In some embodiments, as shown in FIG. 2, the driving substrate 10 and the light emitting device 20 can include a passivation layer 32 and a planarization layer 31. The passivation layer 32 can cover the driving substrate 10 entirely, and the planarization layer 31 can also cover the driving substrate 10 entirely. Alternatively, the orthographic projection of the planarization layer 31 on the driving substrate 10 can cover the orthographic projection of the first electrode 21 on the driving substrate 10. Thus, for a transparent display panel, the planarization layer 31 can reduce the occupation of the non-light emitting area (light transmitting area), thereby improving the light transmitting property of the display panel. Correspondingly, the light emitting device 20 can be located on the side of the planarization layer 31 away from the driving substrate 10.

[0090] In some embodiments, the lead structure 40 can include a metal line connected with the source end, and a metal line connected with the first electrode 21. For example, the lead structure 40 includes a first metal line 41 and a second metal line 42, the first metal line 41 is electrically connected with the first electrode 21 through the second metal line 42.

[0091] In some embodiments, the lead structure 40 can include a metal line connected with the source end, and a metal line connected with the first electrode 21. For example, the lead structure 40 includes a first metal line 41 and a second metal line 42, the first metal line 41 is electrically connected with the first electrode 21 through the second metal line 42.

[0092] In some embodiments, the lead structure 40 can include a metal line connected with the source end, and a metal line connected with the first electrode 21. For example, the lead structure 40 includes a first metal line 41 and a second metal line 42, the first metal line 41 is electrically connected with the first electrode 21 through the second metal line 42.

[0093] Here, it should be noted that the same layer setting can be understood as that the first metal line 41 and the second metal line 42 of the lead structure 40 are formed by one process, or are formed by two processes, but no other process exists between the two processes. For example, when the lead structure 40 is formed on the side of the passivation layer 32 and the planarization layer 31 away from the driving substrate 10, it can be deposited by one process on the side of the passivation layer 32 and the planarization layer 31 away from the driving substrate 10. Although there is a step between the planarization layer 31 and the passivation layer 32, the metal material can climb up the edge of the planarization layer 31 and thereby be overlapped with the first electrode 21, so that the first metal line 41 and the second metal line 42 are formed in one deposition process.

[0094] Correspondingly, in the case of the same layer setting of the first metal line 41 and the second metal line 42, the lead structure 40 as a whole can also be set in the same layer with the first electrode 21. For example, as shown in FIG. 7, the lead structure 40 and the first electrode 21 are both located on the side of the planarization layer 31 away from the driving substrate 10; or, the lead structure 40 and the first electrode 21 can also be set in different layers.

[0095] In the embodiment, the first metal line 41 and the second metal line 42 are arranged in the same layer, and the whole of the lead structure 40 can be arranged in a different layer from the thin film transistor 15. The two can be insulated by a film layer between the light emitting device 20 and the driving substrate 10, such as a passivation layer 32 and a planarization layer 31.

[0096] In another example, the first metal line 41 and the second metal line 42 can be arranged in different layers. Referring to FIG. 8, a cross-sectional structure diagram of another display panel is shown. As shown in FIG. 8, the first metal line 41 and the second metal line 42 are arranged in different film layers, respectively. The second metal line 42 is connected to the first metal line 41 through a via hole formed in a film layer between the second metal line 42 and the first metal line 41.

[0097] In the example, the driving substrate 10 and the light emitting device 20 include a passivation layer 32 and a planarization layer 31. The passivation layer 32 can cover the driving substrate 10 entirely, and the planarization layer 31 can also cover the driving substrate 10 entirely. Alternatively, the orthographic projection of the planarization layer 31 on the driving substrate 10 can cover the orthographic projection of the first electrode 21 on the driving substrate 10 and only partially overlap with the non-light emitting area (light transmission area). As shown in FIG. 8, the first metal line 41 can be located on the side of the passivation layer 32 away from the driving substrate 10, the planarization layer 31 entirely covers the driving substrate 10 and is located on the side of the first metal line 41 away from the driving substrate 10, the second metal line 42 is located on the side of the planarization layer 31 away from the driving substrate 10 and directly contacts the first electrode 21. Correspondingly, a first via hole 311 is formed in the planarization layer 31, and the second metal line 42 is connected to the first metal line 41 through the first via hole 311.

[0098] Of course, in another example, the first metal line 41 and the second metal line 42 are arranged in different layers. In this case, the first metal line 41 can be arranged in the same layer as the source electrode and the drain electrode of the thin film transistor 15, so that the first metal line 41 and the source electrode and the drain electrode are formed in the same manufacturing process, thereby simplifying the process flow and improving manufacturing efficiency.

[0099] Correspondingly, referring to FIG. 9, a cross-sectional structure diagram of another display panel is shown. As shown in FIG. 9, the thin film transistor 15 includes a source electrode 152 and a drain electrode 157 arranged in the same layer. The first metal line 41 is arranged in the same layer as the source electrode 152 and the drain electrode 157.

[0100] As shown in FIG. 9, the driving substrate 10 and the light emitting device 20 include a passivation layer 32 and a planarization layer 31, wherein the passivation layer 32 can cover the driving substrate 10 entirely, and the planarization layer 31 can also cover the driving substrate 10 entirely; or the orthographic projection of the planarization layer 31 on the driving substrate 10 can cover the orthographic projection of the first electrode 21 on the driving substrate 10 and partially overlap with the light-transmitting region. The first metal line 41 can be located on the side of the driving substrate 10 close to the passivation layer 32, for example, the first metal line 41 is formed on the driving substrate 10 in the same process as the source electrode and the drain electrode. Specifically, the passivation layer 32 is located on the side of the first metal line 41 away from the driving substrate 10, and the second metal line 42 is located on the side of the passivation layer 32 away from the driving substrate 10 and directly contacts the first electrode 21. Correspondingly, a second via hole 321 is formed on the passivation layer 32, and the second metal line 42 contacts the first metal line 41 through the second via hole 321.

[0101] As shown in FIG. 9, the first electrode 21 can be connected to the drain electrode 157 through a via hole formed on the planarization layer 31 and the passivation layer 32, and the second metal line 42 is connected to the first metal line 41 through the second via hole 321 formed on the passivation layer 32.

[0102] It should be noted that, in the case where the first metal line 41 is arranged in the same layer as the source electrode and the drain electrode, the orthographic projection of the first metal line 41 on the driving substrate 10 does not overlap with the orthographic projection of the source electrode 152 on the driving substrate 10, and does not overlap with the orthographic projection of the drain electrode 157 on the driving substrate 10.

[0103] In combination with the above embodiments, the first electrodes 21 of the plurality of light emitting devices 20 can share one lead structure 40, and in the case where the lead structure 40 includes the first metal line 41 and the second metal line 42, one first metal line 41 can be connected to the plurality of first electrodes 21 in parallel through a plurality of second metal lines 42. Specifically, please refer to FIG. 10, which shows a top view of a display panel in another embodiment. As shown in FIG. 10, one first metal line 41 can be connected to a plurality of second metal lines 42; wherein different second metal lines 42 are connected to the first electrodes 21 in different light emitting devices 20.

[0104] In this embodiment, the plurality of light emitting devices 20 can be arranged in an array on the driving substrate 10, for example, can be arranged in multiple rows and multiple columns, wherein the first metal line 41 can extend along the row direction or extend along the column direction, in the case of extending along the row direction, the first electrode 21 in a row of light emitting devices 20 can be electrically connected by a plurality of second metal lines 42. For example, the first metal line 41 in FIG. 10 can extend along the row direction, a plurality of second metal lines 42 are connected on the first metal line 41, each second metal line 42 connects the first electrode 21 of a light emitting device 20, and the second metal line 42 can extend along the column direction, thereby making the first electrodes 21 of the light emitting devices 20 in the same row share one lead structure 40.

[0105] Correspondingly, in a specific example of this embodiment, the first metal line 41 extends along the row direction, and can be the same as the extension direction of the gate line on the driving substrate 10, thereby the first metal line 41 can have a spacing with the gate line, for example, the first metal line 41 and the gate line can be in the same layer, and the first metal line 41 and the gate line have a spacing between the orthographic projections on the driving substrate 10. For another example, the first metal line 41 and the gate line can be in different layers, and the film layer between the first metal line 41 and the gate line includes an insulating film layer, thereby making the first metal line 41 and the gate line have a spacing to avoid short circuit.

[0106] In the case that the first metal line 41 and the gate line are in different layers, the first metal line 41 can be arranged in different layers with the data line on the driving substrate 10, wherein the data line can be used to input a data voltage for the pixel driving circuit.

[0107] In another example of this embodiment, the first metal line 41 can extend along the column direction, and the first metal line 41 can be the same as the extension direction of the data line on the driving substrate 10, so that the lead structure 40 can be electrically connected with the first electrodes 21 of a plurality of light emitting devices 20 located in the same column. Specifically, the display panel can further include a data line connected with the thin film transistor 15, and the extension direction of the first metal line 41 is the same as the extension direction of the data line; wherein the first metal line 41 and the data line have a spacing in the planar direction or the thickness direction of the driving substrate 10.

[0108] In the embodiment, the first metal line 41 extends along the column direction, which can be the same as the extending direction of the data line on the driving substrate 10. Thus, the first metal line 41 can have a spacing with the data line. For example, referring to FIG. 4, the first metal line 41 and the data line can be in the same layer, and the first metal line 41 and the data line have a spacing between their orthographic projections on the driving substrate 10, so that the first metal line 41 and the data line have a spacing in the planar direction of the driving substrate 10. For another example, the first metal line 41 and the data line can be in different layers, and the film layer between the first metal line 41 and the data line includes an insulating film layer, so that the first metal line 41 and the gate line have a spacing in the thickness direction of the driving substrate 10 to avoid short circuit.

[0109] In the case that the first metal line 41 and the data line are in different layers, the first metal line 41 can be arranged in different layers from the gate line on the driving substrate 10. Specifically, the gate line can be used to input a gate driving voltage to the thin film transistor 15 to turn on or turn off the thin film transistor 15, so as to turn off or turn on the pixel driving circuit.

[0110] It should be noted that in FIG. 4 and FIG. 10, the row direction can be the X direction in the figure, and the column direction can be the Y direction in the figure.

[0111] In the case that the first metal line 41 and the data line extend in the same direction, the first metal line 41 can be located on the outer side of the data line relative to the first electrode 21, so that the data line is arranged close to the thin film transistor 15 to reduce the wiring distance of the data line to the thin film transistor 15, while increasing the spacing between the lead structure 40 and the thin film transistor 15 to maintain sufficient insulation performance between the lead structure 40 and the thin film transistor 15.

[0112] Referring to FIG. 11, a top plan view of a display panel is shown. As shown in FIG. 11, the first metal line 41 and the data line have a spacing in the planar direction of the driving substrate 10, and the orthographic projection of the data line on the driving substrate 10 is located between the orthographic projection of the first metal line 41 on the driving substrate 10 and the orthographic projection of the first electrode 21 on the driving substrate 10; wherein the second metal line 42 and the data line are in different layers.

[0113] As shown in FIG. 11, the first metal line 41 is located on the side of the data line away from the first electrode 21, specifically, in the case where the pixel driving circuit is a 3T1C driving circuit, the first metal line 41 is located on the side of the sensing line away from the first electrode 21, and is also located on the side of the data line away from the first electrode 21. In this way, the connection distance between the data line and the thin film transistor 15 is close, thereby shortening the wiring distance between the data line and the thin film transistor 15. Wherein, FIG. 11 shows a planar layout diagram when the pixel driving circuit is 3T1C, and it can be seen from FIG. 11 that the first metal line 41 can be located on the side of the first data line away from the first electrode 21. For example, the orthographic projection of the first data line and the second data line in the data line on the driving substrate 10 is located between the orthographic projection of the first metal line 41 on the driving substrate 10 and the orthographic projection of the first electrode 21 on the driving substrate 10.

[0114] In the embodiment, since the first metal line 41 needs to be connected to the first electrode 21 through the second metal line 42, the extension direction of the second metal line 42 can intersect with the extension direction of the data line, for example, the orthographic projection of the second metal line 42 on the driving substrate 10 intersects with the orthographic projection of the data line on the driving substrate 10, and in order to avoid short circuit between the second metal line 42 and the data line, the second metal line 42 can be different from the data line in layer, for example, the second metal line 42 can be different from the first data line and the second data line in layer.

[0115] In the embodiment, the first metal line 41 and the data line can be arranged in the same layer, for example, the first metal line 41 and the first data line are in the same layer, or the first metal line 41 and the second data line are in the same layer, or the first metal line 41, the first data line and the second data line are in the same layer.

[0116] Of course, in another example, in order to solve the problem of small wiring space and easy short circuit caused by the data line and the first metal line 41 in the same layer, the first metal line 41 and the data line can also be different in layer, for example, the first metal line 41 and the first data line are different in layer, or the first metal line 41 and the second data line are different in layer, or the first metal line 41, the first data line and the second data line are different in layer.

[0117] Wherein, in some other embodiments, when the first metal line 41 and the data line are different in layer and have the same extension direction as the data line, the orthographic projection of the first metal line 41 on the driving substrate 10 can also overlap with the orthographic projection of the data line on the driving substrate 10.

[0118] In combination with the above-described embodiments, the first electrodes 21 of the plurality of light emitting devices 20 can share one lead structure 40, and when sharing one lead structure 40, the plurality of light emitting devices 20 sharing one lead structure 40 are connected in series with each other, which is conducive to rapid detection of dark spots of the display panel. For example, only a voltage needs to be applied to the pixel driving circuit of one row of light emitting devices, so that one row of light emitting devices emits light, and because the anode is electrically connected to the lead structure, the voltage can also be applied to the lead structure. Since one column of light emitting devices shares one lead structure, the anodes of the light emitting devices in the column are driven by the voltage, so that the entire display panel is lit up. Thus, the location of the dark spot can be detected, which is conducive to detection of the location and number of dark spots, and in actual manufacturing process, quality feedback can be provided for the process.

[0119] Of course, under such a connection structure, in one driving cycle of display driving, light emitting devices that should not emit light also emit light. Specifically, under line-by-line scanning driving, the lead structure 40 is connected to the same column of light emitting devices 20, and when one light emitting device 20 is driven to emit light, the first electrode 21 of the light emitting device 20 has a driving current, which is conducted to the first electrodes 21 of other light emitting devices 20 through the lead structure 40, so that the other light emitting devices 20 that should not emit light are driven to emit light, which may cause inaccurate display of the display panel. For example, as shown in FIG. 4, under line-by-line scanning driving, the lead structure 40 is connected to one column of light emitting devices 20, and the light emitting device 20R and the light emitting device 20W share one lead structure 40. In one driving cycle, when the light emitting device 20R is driven to emit light, the first electrode 21 of the light emitting device 20R is connected to the first electrode 21 of the light emitting device 20W through the second metal line 42 and the first metal line 41, so that the light emitting device 20W is driven to emit light, which should not emit light in the driving cycle.

[0120] Of course, if the lead structure 40 is connected to one row of light emitting devices 20 and under line-by-line scanning driving, although the same row of light emitting devices 20 should emit light in the cycle, the lead structure 40 can also affect the driving voltage of the light emitting devices 20 in the row, which may affect the display accuracy of the display picture. For example, the driving voltage of the first electrode 21 of one light emitting device 20 can be affected by the driving voltage of the first electrode 21 of another light emitting device 20.

[0121] Thus, in the case that the first electrodes 21 of the plurality of light emitting devices 20 share one lead structure 40, the lead structure 40 can be provided with a fuse structure, so that the lead structure 40 is automatically fused after being powered for a certain length of time, thereby cutting off the circuit with the first electrodes 21, so that after the elimination of the lumped conductive objects in the light emitting functional layer 23, the lead structure 40 can be disconnected from each first electrode 21, so that in subsequent driving display, the driving light emitting of the light emitting device 20 will not be affected by the lead structure 40.

[0122] Specifically, taking the example that the lead structure 40 includes the first metal wire 41 and the second metal wire 42, how to set the fuse structure of the lead structure 40 is described. The fuse structure can be provided on the first metal wire 41 or on the second metal wire 42. In order to ensure that the plurality of light emitting devices 20 do not affect each other in driving display, the fuse structure can be provided on the second metal wire 42, so that the first electrode 21 of each light emitting device 20 can be disconnected from the first metal wire 41 through the fuse structure.

[0123] Therefore, in specific implementation, the fuse structure on the second metal wire 42 can include at least one fuse area 421, and / or the melting point of the second metal wire 42 is lower than that of the first metal wire 41. Specifically, for the fuse area 421, when current flows through the lead structure 40, the metal wire in the fuse area 421 breaks before the metal wire in the non-fuse area 422. The non-fuse area 422 is the area of the second metal wire 42 other than the fuse area 421.

[0124] In the present example, the second metal wire 42 can include one or more fuse areas 421; or, the melting point of the second metal wire 42 is lower than that of the first metal wire 41, so that the second metal wire 42 is fused before the first metal wire 41 when current flows through the lead structure 40. Alternatively, the melting point of the second metal wire 42 is lower than that of the first metal wire 41, and the second metal wire 42 can include at least one fuse area 421, so that the second metal wire 42 can be fused in the fuse area 421 and the non-fuse area 422 in sequence, thereby ensuring that the connection between the second metal wire 42 and the first metal wire 41 is disconnected, i.e., ensuring that the first electrode 21 is disconnected from the first metal wire 41.

[0125] In the present example, the melting point of the second metal wire 42 in the fuse area 421 can be lower than that in the non-fuse area 422. In this case, the metal material of the fuse area 421 can be slightly different from that of the non-fuse area 422, so that the fuse area 421 is fused before the non-fuse area 422. It should be noted that the fuse area 421 is fused before the non-fuse area 422, which does not mean that the non-fuse area 422 will not be fused. In fact, in some cases, the non-fuse area 422 can also be fused.

[0126] In one example of this embodiment, the melting point of the second metal wire 42 can be lower than the melting point of the first metal wire 41, and the material of the second metal wire 42 can include a lead-antimony alloy or an aluminum-antimony alloy, such as a lead-antimony alloy material or an aluminum-antimony alloy material, and the melting point of the material of the first metal wire 41 can be higher than the melting point of the material of the second metal wire 42, such as the first metal wire 41 can be made of silver, copper or the like to ensure connection with the plurality of second metal wires 42.

[0127] In another example of this embodiment, the second metal wire 42 can include at least one fusing area 421, and the metal wire at the fusing area 421 can be weaker than the metal wire at the non-fusing area 422 since the fusing area 421 can fuse before the non-fusing area 422. For example, in this example, the line width of the fusing area 421 is smaller than the line width of the non-fusing area 422, and / or the thickness of the fusing area 421 is smaller than the thickness of the non-fusing area 422.

[0128] Specifically, referring to FIG. 12, a schematic diagram of the connection structure between the lead structure 40 and the first electrode 21 is shown. As shown in FIG. 12, the second metal wire 42 can include a plurality of fusing areas 421, and the plurality of fusing areas 421 are arranged at intervals. The line width of the fusing area 421 can be smaller than the line width of the non-fusing area 422, and the line width can be the size of the fusing area 421 in the direction perpendicular to the extension direction of the second metal wire 42, such as the x direction in FIG. 12, which can be the connection direction between the first metal wire 41 and the first electrode 21. Alternatively, the thickness of the fusing area 421 can be smaller than the thickness of the non-fusing area 422, and the thickness can be the size of the metal wire of the fusing area 421 in the thickness direction of the driving substrate 10. Alternatively, the line width of the fusing area 421 can be smaller than the line width of the non-fusing area 422 and the thickness of the fusing area 421 can be smaller than the thickness of the non-fusing area 422. With the above arrangement, the metal wire of the fusing area 421 can be weaker and thus more likely to be fused when a large current is introduced through the lead structure 40.

[0129] In this embodiment, as shown in FIG. 12, the orthographic projection of the fusing area 421 on the driving substrate 10 can be a rectangle, and the orthographic projection of the non-fusing area 422 on the driving substrate 10 can also be a rectangle, but in some other examples, the orthographic projection of the fusing area 421 on the driving substrate 10 can be a rectangle, and the orthographic projection of the non-fusing area 422 on the driving substrate 10 can include a circle, an ellipse or an irregular shape, which will not be described here.

[0130] In some examples, in order to ensure the disconnection between the first electrode 21 and the first metal line 41, the fuse area 421 can be provided in multiple or one, in the case of one, the fuse area 421 can be provided close to the first metal line 41, for example, the orthographic projection of the fuse area 421 on the driving substrate 10 can not overlap with the orthographic projection of the first electrode 21 on the driving substrate 10, that is, the fuse area 421 is provided away from the first electrode 21, thereby ensuring that when it is fused, it cuts off the connection between the first electrode 21 and the first metal line 41. In the case of multiple fuse areas 421, at least one of the multiple fuse areas 421 is provided away from the first electrode 21, specifically, at least one of the orthographic projections of the multiple fuse areas 421 on the driving substrate 10 does not overlap with the orthographic projection of the first electrode 21 on the driving substrate 10. For example, the multiple fuse areas 421 can all be provided away from the first electrode 21, for example, as shown in FIG. 12, three fuse areas 421 are all provided away from the first electrode 21; or the multiple fuse areas 421 include fuse areas 421 that overlap with the first electrode 21 and fuse areas 421 that do not overlap with the first electrode 21.

[0131] In combination with the above-described embodiments, the driving substrate 10 includes a data line, the first metal line 41 has the same extension direction as the data line, and the orthographic projection of the second metal line 42 on the driving substrate 10 intersects the orthographic projection of the data line on the driving substrate 10, where the intersection can mean that the orthographic projections of the second metal line 42 and the data line are orthogonal, and in one example, the fuse area 421 on the second metal line 42 can be located at the intersection. For example, there can be an orthographic projection of the fuse area 421 on the driving substrate 10, which is located at the intersection of the orthographic projection of the second metal line 42 on the driving substrate 10 and the orthographic projection of the data line on the driving substrate 10, so that after the fuse area 421 is fused, the second metal line 42 can be prevented from forming a capacitor structure between the intersection and the data line.

[0132] In some embodiments, the first electrode 21 can be a single metal layer, or the first electrode 21 can be stacked by multiple metal electrodes, so that the first electrode 21 can include multiple metal electrode layers arranged in the thickness direction of the driving substrate 10; and the lead structure 40 can be in direct contact with at least one metal electrode layer.

[0133] Please continue to refer to FIG. 2, the first electrode 21 can include a plurality of stacked metal electrode layers, such as a first metal electrode layer 214, a second metal electrode layer 213, a third metal electrode layer 212, and a fourth metal electrode layer 211, wherein the orthographic projection of the first metal electrode layer on the driving substrate 10 can cover the orthographic projections of the second metal electrode layer, the third metal electrode layer, and the fourth metal electrode layer on the driving substrate 10, and the orthographic projections of the second metal electrode layer, the third metal electrode layer, and the fourth metal electrode layer on the driving substrate 10 can coincide.

[0134] In some examples, the lead structure 40 can be in direct contact with the first metal electrode layer, such as the second metal wire 42 can be overlapped on the side of the first metal electrode layer away from the driving substrate 10. Alternatively, in other examples, the lead structure 40 can also be in direct contact with the first metal electrode layer and the second metal electrode layer respectively, referring to FIG. 13, another cross-sectional structure diagram of the display panel is shown, as shown in FIG. 13, the lead structure 402 can also be in direct contact with the first metal electrode layer and the second metal electrode layer respectively; or in yet other examples, the lead structure 40 can be in direct contact with the first metal electrode layer, the second metal electrode layer, and the third metal electrode layer to ensure good contact.

[0135] In combination with the above examples, in the case that the second metal wire 42 includes a fuse area 421, at least one fuse area 421 can be included, and the orthographic projection of the fuse area 421 on the driving substrate 10 does not overlap the orthographic projections of the plurality of metal electrode layers on the driving substrate 10, so that the fuse area 421 can be arranged away from the plurality of metal electrode layers, thereby ensuring the disconnection between the first electrode 21 and the first metal wire 41.

[0136] In some embodiments, the display panel includes a light-emitting area and a light-transmitting area, and the light-emitting device 20 is located in the light-emitting area, such as in the opening of the pixel definition layer 60, wherein the display panel can further include:

[0137] The flat layer 31 is located on the side of the first electrode 21 close to the driving substrate 10, and the orthographic projection of the flat layer 31 on the driving substrate 10 covers the orthographic projection of the first electrode 21 on the substrate 11 and partially overlaps the light-transmitting area.

[0138] In combination with the above examples, in the case that the second metal wire 42 includes a fuse area 421, at least one fuse area 421 can be included, and the orthographic projection of the fuse area 421 on the driving substrate 10 does not overlap the orthographic projections of the plurality of metal electrode layers on the driving substrate 10, so that the fuse area 421 can be arranged away from the plurality of metal electrode layers, thereby ensuring the disconnection between the first electrode 21 and the first metal wire 41.

[0139] Please refer to FIG. 2, the light emitting device 20 is located on the side of the planar layer 31 away from the driving substrate 10, specifically, the first electrode 21 is made on the side of the planar layer 31 away from the driving substrate 10, and the planar layer 31 has a step with the driving substrate 10, for example, the driving substrate 10 and the planar layer 31 are provided with the passivation layer 32, and the planar layer 31 has a step with the passivation layer 32. Wherein, when forming the lead structure 40, the metal material of the lead structure 40 can be made to contact the first electrode 21 after climbing on the edge of the planar layer 31, that is, the lead structure 40 can be directly in contact with the edge of the planar layer 31 and directly in contact with the first electrode 21.

[0140] Wherein, in order to enhance the climbing ability of the lead structure 40 at the edge of the planar layer 31, the planar area of the lead structure 40 in the edge area can be increased, for example, the line width of the lead structure 40 in the edge area can be increased. Exemplarily, in the case that the lead structure 40 includes the first metal line 41 and the second metal line 42, the line width of the second metal line 42 can be appropriately increased to avoid the second metal line 42 from being broken at the edge of the planar layer 31.

[0141] Further, in the case that the second metal line 42 of the lead structure 40 includes the fuse area 421, the fuse area 421 can be avoided to be arranged at the edge of the planar layer 31, that is, the orthographic projection of the fuse area 421 on the driving substrate 10 can not overlap with the orthographic projection of the edge of the planar layer 31 on the driving substrate 10, thereby not only ensuring that the second metal line 42 will not be broken at the edge of the planar layer 31 to maintain the electrical contact between the second metal line 42 and the first electrode 21, but also enabling the second metal line 42 to be broken by the fuse area 421 to disconnect the first electrode 21 and the first metal line 41 after the lump-shaped conductive material in the light emitting functional layer 23 is passivated.

[0142] In some embodiments, based on the substrate 11 process of the display panel, the display panel can include the light shielding metal layer 14, and the orthographic projection of the light shielding metal layer 14 on the driving substrate 10 can cover the orthographic projection of the first electrode 21 on the driving substrate 10. In this embodiment, the first electrode 21 can be connected with the thin film transistor 15 through the light shielding metal layer 14. Specifically, please continue to refer to FIG. 2, the driving substrate 10 can include:

[0143] the light shielding metal layer 14, and the orthographic projection of the light shielding metal layer 14 on the driving substrate 10 covers the orthographic projection of the first electrode 21 on the driving substrate 10;

[0144] the buffer layer 12, located on the side of the light shielding metal layer 14 close to the light emitting device 20; and,

[0145] A driving circuit layer is located on the side of the buffer layer 12 close to the light emitting device 20, and a plurality of thin film transistors 15 are located on the driving circuit layer; wherein the thin film transistor 15 is electrically connected with the first electrode 21 through the light shielding metal layer 14.

[0146] In combination with the above embodiments, the thin film transistor 15 can include an active layer, a gate insulating layer 154, a gate layer 153, and a source electrode 152 and a drain electrode 157, and the driving circuit layer can include the following structure:

[0147] The active layer is located on the side of the buffer layer 12 away from the light shielding metal layer 14;

[0148] The gate insulating layer 154 is located on the side of the active layer away from the buffer layer 12;

[0149] The gate layer 153 is located on the side of the gate insulating layer 154 away from the buffer layer 12;

[0150] The interlayer dielectric layer 13 is located on the side of the gate layer 153 away from the buffer layer 12;

[0151] The drain electrode 157 and the source electrode 152 are located on the side of the interlayer dielectric layer 13 away from the buffer layer 12.

[0152] The buffer layer 12 can be formed of inorganic material, the passivation layer 32 can be formed of inorganic material, the interlayer dielectric layer 13 can be formed of organic material or inorganic material, or formed of a laminated structure of organic material and inorganic material.

[0153] As shown in FIG. 2, the pixel driving circuit is a 3T1C driving circuit, and the light shielding metal layer 14 can be used to form a capacitor structure. Specifically, an insulating layer is formed on the side of the buffer layer 12 away from the substrate 11, and a gate metal layer 16 is formed on the side of the insulating layer away from the substrate 11, wherein the gate metal layer 16 can be disposed in the same layer as the gate layer 153, and both can be formed of the same material. A capacitor is formed between the gate metal layer 16 and the extension 158 of the drain electrode 157, and a capacitor is also formed between the gate metal layer 16 and the light shielding metal layer 14. Specifically, the capacitor can be the capacitor Cst in the circuit structure shown in FIG. 6.

[0154] The third via hole 131 corresponding to the source electrode 152 and the fourth via hole 132 corresponding to the drain electrode 157 can be formed on the interlayer dielectric layer. The source electrode 152 can directly contact the source region 151 on the active layer through the third via hole 131, and the drain electrode 157 can directly contact the drain region 156 on the active layer through the fourth via hole 132.

[0155] The fifth via hole can be formed on the interlayer dielectric layer 13, and the sixth via hole can be formed on the buffer layer 12. The drain electrode 157 includes an extension 158, which can pass through the fifth via hole and the sixth via hole in sequence and be connected to the light-shielding metal layer 14. The first electrode 21 can be directly in contact with the extension 158, so as to realize electrical connection with the drain electrode 157. Specifically, in order to avoid over-etching of the fifth via hole to the active layer, in practice, the fifth via hole can include two sub-via holes, which can avoid the active layer opening.

[0156] In some embodiments, as shown in FIG. 2, a passivation layer 32 and a planarization layer 31 are further arranged between the driving substrate 10 and the light-emitting device 20. The passivation layer 32 can cover the driving substrate 10 entirely. The planarization layer 31 can cover the orthographic projection of the first electrode 21 on the driving substrate 10 without overlapping with the light-transmitting region. Correspondingly, via holes can be formed in the planarization layer 31 and the passivation layer 32. The first electrode 21 can be in direct contact with the extension 158 of the drain electrode 157 through the via holes formed in the planarization layer 31 and the passivation layer 32.

[0157] In a further example of this embodiment, please continue to refer to FIG. 5, the light-shielding metal layer 14 can include a first region, a second region, and a third region between the first region and the second region. The orthographic projection of the first region on the driving substrate 10 covers the orthographic projection of the first electrode 21 on the driving substrate 10. The orthographic projection of the second region on the driving substrate 10 does not overlap with the orthographic projection of the first electrode 21 on the driving substrate 10. The orthographic projection of the lead structure 40 on the driving substrate 10 does not overlap with the orthographic projection of the third region and / or the second region on the driving substrate 10.

[0158] In this embodiment, the light-shielding metal layer 14 can include a first region and a second region. The first region can be used for shielding the thin film transistor 15. The second region can be located in the light-transmitting region. The second region can be connected to the third region. The third region can be connected to the first region.

[0159] The extension 158 of the drain electrode 157 of the thin film transistor 15 can be connected to the second region.

[0160] The orthographic projection of the light-shielding metal layer 14 on the driving substrate 10 covers the orthographic projection of one light-emitting device 20 on the driving substrate 10. The orthographic projections of the light-shielding metal layers 14 corresponding to different light-emitting devices 20 on the driving substrate 10 do not overlap with each other, so as to avoid the problem of connecting the light-shielding metal layers 14 corresponding to adjacent two light-emitting devices 20 in series. The third region, the first region, and the second region can be formed by a patterning process.

[0161] In the embodiment, the orthographic projection of the lead structure 40 on the driving substrate 10 can not overlap with the orthographic projection of the third area on the driving substrate 10, or can not overlap with the orthographic projection of the second area on the driving substrate 10, or can not overlap with the orthographic projection of both the third area and the second area on the driving substrate 10.

[0162] In combination with the above-mentioned embodiments, each light emitting device 20 can correspond to an independent lead structure 40, and in this case, the orthographic projection of the lead structure 40 on the driving substrate 10 can not overlap with the orthographic projection of both the second area and the third area on the driving substrate 10. In the case where the lead structure 40 includes the first metal line 41 and the second metal line 42, the second metal line 42 in the lead structure 40 can not overlap with the third area, and the first metal line 41 can overlap with the third area but not overlap with the second area. For details, please refer to FIG. 11.

[0163] In an example of the embodiment, the first metal line 41 of the lead structure 40 can be connected to the first electrodes 21 of the plurality of light emitting devices 20 through the plurality of second metal lines 42, and in this example, the first metal line 41 can extend along the row direction, and the plurality of metal lines can extend along the column direction and be connected to the first electrodes 21 of the plurality of light emitting devices 20 in the same row. For example, please refer to FIG. 10. In this case, the orthographic projection of the first metal line 41 and the second metal line 42 on the driving substrate 10 can not overlap with the orthographic projection of both the second area and the third area on the driving substrate 10.

[0164] In combination with FIG. 11, in the case where one first metal line 41 is connected to the first electrodes 21 of the plurality of light emitting devices 20 in the same column through the plurality of second metal lines 42, the extension direction of the first metal line 41 is the column direction, and the extension direction of the second metal line 42 is the row direction. In this case, the second metal line 42 in the lead structure 40 can not overlap with the orthographic projection of the third area on the driving substrate 10, the first metal line 41 can overlap with the orthographic projection of the third area on the driving substrate 10, and the first metal line 41 can not overlap with the orthographic projection of the second area on the driving substrate 10.

[0165] In some embodiments, because the second electrode 22 (cathode) is thinner, its resistance is higher and its voltage drop is greater, resulting in a larger current difference between the sub-pixels in the central and edge regions of the display panel. In practice, an auxiliary electrode structure can be provided for the second electrode 22. Referring to Figures 14 and 15, two cross-sectional structural diagrams of the display panel are shown. As shown in Figures 14 and 15, the display panel includes a light-emitting area and a light-transmitting area. The light-emitting device 20 is located in the light-emitting area, and an auxiliary structure 50 is also included in the light-transmitting area. The auxiliary structure 50 can be located on one side of the driving substrate 10, such as on the same side as the light-emitting device 20. In this case, the second electrode 22 and the light-emitting functional layer 23 are both disconnected at the location of the auxiliary structure 50, and the second electrode 22 is in direct contact with the auxiliary structure 50 to achieve electrical connection between the second electrode 22 and the auxiliary structure 50.

[0166] Specifically, the auxiliary structure 50 may include multiple metal layers sequentially disposed in the thickness direction of the driving substrate 10. The cross-sectional structure of the multiple metal layers in the thickness direction of the driving substrate 10 may be an "I" shape, and there is a significant step difference between the auxiliary structure 50 and the driving substrate 10, causing the light-emitting functional layer 23 and the second electrode 22 to undergo a ramp break at the auxiliary structure 50, thereby isolating the second electrode 22 and the light-emitting functional layer 23 at the auxiliary structure 50. Furthermore, the light-emitting functional layer 23 and the second electrode 22 are sequentially stacked on the side of the auxiliary structure 50 facing away from the driving substrate 10. The light-emitting functional layer 23 and the second electrode 22 stacked on the side of the auxiliary structure 50 can be considered as process residues. In practice, after the light-emitting functional layer 23 and the second electrode 22 are formed, the light-emitting functional layer 23 and the second electrode 22 on the side of the auxiliary structure 50 may be removed, or they may not be removed.

[0167] As shown in Figure 14, the auxiliary structure 50 can be located in the light-transmitting area. Furthermore, the auxiliary structure 50 is insulated from the lead structure 40. Specifically, the orthographic projection of the auxiliary structure 50 on the driving substrate 10 does not overlap with the orthographic projection of the lead structure 40 on the driving substrate 10, and the auxiliary structure 50 is insulated from the pixel driving circuit; for example, they do not overlap. In practice, one auxiliary structure 50 can be connected simultaneously to the second electrode 22 of a row of light-emitting devices 20, or one auxiliary structure 50 can be connected to the second electrode 22 of a single light-emitting device 20. Thus, the second electrodes 22 of multiple light-emitting devices 20 can be connected to multiple auxiliary structures 50 respectively.

[0168] In this embodiment, since the auxiliary structure 50 is electrically connected to the second electrode 22, the resistance of the second electrode 22 can be reduced, the voltage drop can be reduced, the current difference between the sub-pixels in the center and edge areas of the display panel can be reduced, and the uniformity of the display brightness of the display panel can be improved.

[0169] In a further example of this embodiment, the auxiliary electrode structure includes a plurality of auxiliary electrode layers arranged in sequence in the thickness direction of the driving substrate 10; wherein at least one of the auxiliary electrode layers is arranged in the same layer as the lead structure 40.

[0170] In this embodiment, the auxiliary structure 50 can include a plurality of auxiliary electrode layers arranged in sequence in the thickness direction of the driving substrate 10, as shown in FIG. 14, including six auxiliary electrode layers, such as a first auxiliary electrode layer 51, a second auxiliary electrode layer 52, a third auxiliary electrode layer 53, a fourth auxiliary electrode layer 54, a fifth auxiliary electrode layer 55, and a sixth auxiliary electrode layer 56, wherein the first auxiliary electrode layer can be arranged in the same layer as the drain electrode 157 of the pixel driving circuit, the outer contour of the fourth auxiliary electrode layer and the fifth auxiliary electrode layer in the orthographic projection on the driving substrate 10 is within the outer contour of the third auxiliary electrode layer in the orthographic projection on the driving substrate 10, and within the outer contour of the sixth auxiliary electrode layer in the orthographic projection on the driving substrate 10. Wherein the second auxiliary electrode layer is formed in a via hole opened in the passivation layer 32, which is not labeled in FIG. 14.

[0171] In this embodiment, the lead structure 40 can be arranged in the same layer as at least one of the auxiliary electrode layers, for example, the lead structure 40 can include a portion arranged in the same layer as the first auxiliary electrode layer closest to the driving substrate 10, and a portion arranged in the same layer as the auxiliary electrode layer between the first auxiliary electrode layer and the fourth auxiliary electrode layer. For example, as shown in FIG. 15, the lead structure 40 includes a first metal line 41 and a second metal line 42, wherein the first metal line 41 and the second metal line 42 are arranged in different layers, the first metal line 41 can be arranged in the same layer as the first auxiliary electrode layer, and the second metal line 42 can be arranged in the same layer as the second auxiliary electrode layer; in this way, the first metal line 41 can be formed in the same process as the first auxiliary electrode layer, and the second metal line 42 can be formed in the same process as the second auxiliary electrode layer. For another example, as shown in FIG. 14, the lead structure 40 includes a first metal line 41 and a second metal line 42, wherein the first metal line 41 and the second metal line 42 are arranged in the same layer, and the lead structure 40 can be arranged in the same layer as the second auxiliary electrode layer; in this way, the second metal line 42 can be formed in the same process as the second auxiliary electrode layer.

[0172] It should be noted that when the second metal line 42 is made of a metal material with a lower melting point, the second metal line 42 and the second auxiliary electrode layer can be formed in different processes, such as first forming the second auxiliary electrode layer, and then forming the second metal line 42, in this case, the second metal line 42 and the second auxiliary electrode layer can be located on the side of the passivation layer 32 away from the driving substrate 10.

[0173] In this embodiment, the first auxiliary electrode layer in the auxiliary structure 50 can be arranged in the same layer as the source electrode 152 and the drain electrode 157 of the thin film transistor 15. As shown in FIG. 14, the first metal line 41, the first auxiliary electrode layer, the source electrode 152, and the drain electrode 157 can be arranged in the same layer. Thus, the first metal line 41, the first auxiliary electrode layer, the source electrode 152, and the drain electrode 157 can be formed at one time in the same process, thereby simplifying the manufacturing process.

[0174] Next, an example of a display panel of the present disclosure is described as an example.

[0175] Referring to FIGS. 15 and 11, the display panel in this example is a transparent display panel, which includes a light-emitting region and a light-transmitting region, where the light-transmitting region is a region other than the light-emitting region. The structure of the display panel mainly includes:

[0176] The driving substrate 10 includes a plurality of thin film transistors 15, which form a plurality of pixel driving circuits. The pixel driving circuit is a 3T1C driving circuit, and the plurality of pixel driving circuits provide driving voltages for the plurality of light-emitting devices 20 to drive the light-emitting devices 20 to emit light.

[0177] The plurality of light-emitting devices 20 are located on one side of the driving substrate 10. The light-emitting device 20 includes a first electrode 21, a light-emitting functional layer 23, and a second electrode 22 arranged in the thickness direction of the driving substrate 10.

[0178] The lead structure 40 is located on one side of the driving substrate 10 and is insulated from the thin film transistor 15. The lead structure 40 and the thin film transistor 15 are located in different circuits, respectively. Specifically, the lead structure 40 and the pixel driving circuit are not electrically connected and are insulated from each other. The first electrode 21 is electrically connected to the lead structure 40 and the drain electrode 157 of the thin film transistor 15, respectively.

[0179] The auxiliary structure 50 is located in the light-transmitting region and includes a plurality of auxiliary electrode layers stacked in the thickness direction of the driving substrate 10. The auxiliary structure 50 mainly includes a first auxiliary electrode layer to a sixth auxiliary electrode layer.

[0180] The auxiliary structure 50 is electrically connected to the second electrode 22, and the light-emitting functional layer 23 is disconnected at the auxiliary structure 50.

[0181] The auxiliary structure 50 is insulated from the pixel driving circuit and the lead structure 40.

[0182] The driving substrate 10 mainly includes the following structures:

[0183] The substrate 11, the light shielding metal layer 14 located on one side of the substrate 11, the buffer layer 12 located on one side of the light shielding metal layer 14, the active layer located on one side of the buffer layer 12, the gate insulating layer 154 located on one side of the active layer away from the substrate 11, the gate layer 153 located on one side of the gate insulating layer 154 away from the substrate 11, and the interlayer dielectric layer 13 located on one side of the gate layer 153 away from the substrate 11, the source electrode 152 and the drain electrode 157 located on one side of the interlayer dielectric layer 13 away from the substrate 11. Specifically, the active layer can include a channel region 155 corresponding to the gate layer 153, a source region 151 overlapped with the source electrode 152, and a drain region 156 overlapped with the drain electrode 157, and the source region 151 and the drain region 156 are formed after the active layer is conductorized. Among them, the gate insulating layer 154, the source electrode 152, the drain electrode 157, the gate layer 153 and the active layer constitute a TFT, and the drain electrode 157 is electrically connected with the first electrode 21 in the light emitting device 20 through the light shielding metal layer 14.

[0184] Among them, the driving substrate 10 and the light emitting device 20 are further sequentially provided with:

[0185] The passivation layer 32 covers the driving substrate 10 in the whole plane;

[0186] The planarization layer 31 only covers the first electrode 21.

[0187] Among them, the lead structure 40 includes a first metal line 41 and a plurality of second metal lines 42, the first metal line 41 extends along the column direction, and the second metal line 42 extends along the row direction, and the plurality of second metal lines 42 are respectively connected with the first electrodes 21 of a plurality of light emitting devices 20 in the same column, so that the light emitting devices 20 in the same column share the same lead structure 40. Specifically, the first metal line 41 is provided in the same layer as the source electrode 152, the drain electrode 157 and the first auxiliary electrode layer of the auxiliary structure 50, the second metal line 42 is located on one side of the passivation layer 32 away from the driving substrate 10, and the second metal line 42 is in direct contact with the first metal electrode layer of the first electrode 21 after being in direct contact with the edge of the planarization layer 31. Among them, the orthographic projection of the first metal electrode layer on the driving substrate 10 and the orthographic projection of the pixel definition layer 60 on the driving substrate 10 have an overlap, the orthographic projection of the first metal electrode layer on the driving substrate 10 covers the orthographic projection of other metal electrode layers in the first electrode 21 on the driving substrate 10, and the orthographic projection of the other metal electrode layers on the driving substrate 10 and the orthographic projection of the pixel definition layer 60 on the driving substrate 10 have no overlap.

[0188] Among them, the second metal line 42 adopts a low-melting-point metal material, such as aluminum-antimony alloy.

[0189] The plurality of first metal lines 41 can be connected to one pin of a driving chip of the display panel, and a large current can be input to the plurality of first metal lines 41 through the driving chip, so that the conductive foreign matter in the form of a cluster in the light-emitting functional layer 23 is passivated into an insulating substance, thereby avoiding the short circuit between the first electrode 21 and the second electrode 22. After a period of time, for example, 10 seconds, the second metal line 42 is fused, thereby disconnecting the plurality of light-emitting devices 20 from the first metal line 41. In this way, the subsequent driving display is not affected, that is, the display panel can be normally driven and displayed.

[0190] In some embodiments, the process of forming the display panel of the above example can be as follows:

[0191] S1: sequentially form a light-shielding metal layer, a buffer layer, an active layer, a gate insulating layer, a gate, and a gate lead on a substrate by patterning, and the formed structure can refer to FIG. 16, which shows a planar layout schematic diagram formed by step S1;

[0192] S2: deposit an interlayer dielectric layer and form a via in the interlayer dielectric layer and the buffer layer by patterning, then deposit and pattern a source electrode, a drain electrode, and a first metal line, and the formed structure can refer to FIG. 17, which shows a planar layout schematic diagram formed by step S2;

[0193] S3: deposit a passivation layer and a planarization layer on the driving substrate formed by step S2, then form a via in the passivation layer and the planarization layer by patterning, and then pattern an anode layer (first electrode), and the formed structure can refer to FIG. 18, which shows a planar layout schematic diagram formed by step S3;

[0194] S4: use an alloy with a low current melting point, such as a lead-antimony alloy, an aluminum-antimony alloy, etc., to pattern and effectively connect the first metal line and the anode. Specifically, refer to the planar layout schematic diagram shown in FIG. 11;

[0195] S5: evaporate a light-emitting functional layer and deposit a second electrode, etc. At this time, due to the presence of a conductive foreign matter in the form of a cluster as shown in FIG. 1, some pixels are short-circuited between the cathode and the anode, causing dark spot defects. Then, a large enough current is introduced to the first metal line that does not pass through the TFT. At this time, the large current will burn the conductive foreign matter in the form of a cluster into a passivated non-conductive substance, thereby cutting off the path between the cathode and the anode (the first electrode and the second electrode), avoiding the generation of dark spot defects. Moreover, due to the large current, the second metal line will also be burned out after a period of time, thereby cutting off the series connection between each first electrode and the first metal line, preventing the short circuit of each light-emitting device connected by the same first metal line.

[0196] The display panel of the embodiment introduces a separate lead structure, so that the TFT current limiting effect is eliminated when eliminating the dark spots. In this way, no matter where the conductive mass is generated, it can pass through the lead structure by inputting a large current, and no longer be limited by the current size of the thin film transistor, thereby passivating the conductive mass in the display panel, and greatly improving the improvement level of dark spot defects.

[0197] The circuit schematic diagram after introducing the large current lead is shown in FIG. 6, and it can be clearly seen that the large current directly acts on the anode.

[0198] Based on the same inventive concept, the display device provided by the embodiment of the disclosure can include the display panel described above, and the display device can be configured with a driving chip and a processor connected with the driving chip, wherein the lead structure in the display panel can be connected with a pin of the driving chip.

[0199] In some examples, the display panel can be a transparent display panel, and the display device can be a transparent display device.

[0200] Each of the embodiments in the specification is described in a progressive manner, and each embodiment focuses on the difference from other embodiments. The same or similar parts between the embodiments can be referred to each other.

[0201] Finally, it should be noted that in this document, relationship terms such as first and second are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply that there is any such actual relationship or order between the entities or operations. Moreover, the terms "include", "contain" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, product or equipment including a series of elements not only includes those elements, but also includes other elements not explicitly listed or inherent to such process, method, product or equipment. Without more limitations, the element defined by the statement "including a" does not exclude the presence of another identical element in the process, method, product or equipment including the element.

[0202] The above describes in detail the display panel and the display device provided by the disclosure. The principles and implementation modes of the disclosure are described by applying specific examples. The above description of the embodiments is only used to help understand the method and core idea of the disclosure; at the same time, for those skilled in the art, according to the idea of the disclosure, the specific implementation mode and application range will be changed; in view of the above, the content of the specification should not be understood as a limitation of the disclosure.

[0203] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This disclosure is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the following claims.

[0204] It should be understood that this disclosure is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this disclosure is limited only by the appended claims.

[0205] The terms "an embodiment," "embodiment," or "one or more embodiments" as used herein mean that a particular feature, structure, or characteristic described in connection with an embodiment is included in at least one embodiment of this disclosure. Furthermore, please note that the examples of the phrase "in one embodiment" do not necessarily all refer to the same embodiment.

[0206] Numerous specific details are set forth in the specification provided herein. However, it will be understood that embodiments of this disclosure may be practiced without these specific details. In some instances, well-known methods, structures, and techniques have not been shown in detail so as not to obscure the understanding of this specification.

[0207] In the claims, any reference signs placed between parentheses should not be construed as limiting the claims. The word "comprising" does not exclude the presence of elements or steps not listed in the claims. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. This disclosure can be implemented by means of hardware comprising a plurality of different elements and by means of a suitably programmed computer. In a unit claim enumerating a plurality of means, several of these means may be embodied by the same item of hardware. The use of the words first, second, and third, etc., does not indicate any order. These words may be interpreted as names.

[0208] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this disclosure, and are not intended to limit them. Although this disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this disclosure.

Claims

1. A display panel, wherein, The display panel comprises: a driving substrate comprising a plurality of thin film transistors; a plurality of light emitting devices located on one side of the driving substrate, the light emitting device comprising a first electrode, a light emitting functional layer and a second electrode arranged in sequence in the thickness direction of the driving substrate; and a lead structure located on one side of the driving substrate and insulated from the thin film transistors; wherein the first electrode is electrically connected to the lead structure and the thin film transistor respectively.

2. The display panel of claim 1, wherein, The lead structure comprises a first metal line and a second metal line; wherein the first metal line is electrically connected to the first electrode through the second metal line.

3. The display panel of claim 2, wherein, The first metal line and the second metal line are located in different film layers respectively; wherein the second metal line is overlapped with the first metal line through a via hole formed in the film layer between the second metal line and the first metal line.

4. The display panel of claim 2, wherein, The thin film transistor comprises a source electrode and a drain electrode arranged in the same layer; wherein the first metal line is arranged in the same layer as the source electrode and the drain electrode.

5. The display panel of claim 2, wherein, The first metal line is connected to a plurality of second metal lines; wherein different second metal lines are connected to the first electrode in different light emitting devices.

6. The display panel of claim 2, wherein, The display panel further comprises a data line connected to the thin film transistor, and the extension direction of the first metal line is the same as the extension direction of the data line; wherein the first metal line and the data line have a spacing in the planar direction and / or the thickness direction of the driving substrate.

7. The display panel of claim 6, wherein, The first metal line and the data line have a spacing in the planar direction of the driving substrate, and the orthographic projection of the data line on the driving substrate is located between the orthographic projection of the first metal line on the driving substrate and the orthographic projection of the first electrode on the driving substrate; wherein the second metal line is different from the data line in layer.

8. The display panel of claim 2, wherein, The second metal line comprises at least one fuse zone, and / or the melting point of the second metal line is lower than the melting point of the first metal line; wherein when current flows through the lead structure, the metal line in the fuse zone breaks before the metal line in the non-fuse zone, and the non-fuse zone is the area of the second metal line other than the fuse zone.

9. The display panel of claim 8, wherein, The melting point of the second metal line is lower than the melting point of the first metal line; and the material of the second metal line comprises lead-antimony alloy or aluminum-antimony alloy.

10. The display panel of claim 8, wherein, The second metal line comprises at least one fuse zone; wherein the line width of the fuse zone is smaller than the line width of the non-fuse zone, and / or the thickness of the fuse zone is smaller than the thickness of the non-fuse zone.

11. The display panel of claim 8, wherein, The orthographic projection of at least one fuse zone on the driving substrate does not overlap with the orthographic projection of the first electrode on the driving substrate.

12. The display panel of any of claims 1-11, wherein, The first electrode comprises a plurality of metal electrode layers arranged in sequence in the thickness direction of the driving substrate; wherein the lead structure is in direct contact with at least one metal electrode layer.

13. The display panel of any of claims 1-11, wherein, The driving substrate comprises: a light shielding metal layer, the orthographic projection of the light shielding metal layer on the driving substrate covers the orthographic projection of the first electrode on the driving substrate; a buffer layer located on the side of the light shielding metal layer close to the light emitting device; and A driving circuit layer is located on the side of the buffer layer close to the light emitting device, and a plurality of thin film transistors are located on the driving circuit layer. The thin film transistor is electrically connected to the first electrode through the light shielding metal layer.

14. The display panel of claim 13, wherein, The light shielding metal layer includes a first region, a second region, and a third region between the first region and the second region. The first region covers the first electrode on the driving substrate, and the second region does not overlap the first electrode on the driving substrate. The third region and / or the second region do not overlap the lead structure on the driving substrate.

15. The display panel of claim 1, wherein, The display panel includes a light emitting region and a light transmitting region, and the light emitting device is located in the light emitting region. A planar layer is located on the side of the first electrode close to the driving substrate, and the planar layer covers the first electrode on the driving substrate and partially overlaps the light transmitting region. The lead structure directly contacts the edge of the planar layer and directly contacts the first electrode.

16. The display panel according to any one of claims 1-11 or any one of claims 14-15, wherein, The display panel includes a light emitting region and a light transmitting region, and the light emitting device is located in the light emitting region. An auxiliary electrode structure is located on the side of the driving substrate close to the light emitting device. The light emitting functional layer and the second electrode are disconnected at the auxiliary electrode structure, and the auxiliary electrode structure is electrically connected to the second electrode and is insulated from the lead structure.

17. The display panel of claim 16, wherein, The auxiliary electrode structure includes a plurality of auxiliary electrode layers arranged in the thickness direction of the driving substrate. At least one auxiliary electrode layer is arranged in the same layer as the lead structure.

18. A display device, wherein, The display device includes any one of the display panels of claims 1-17.

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