Display panel and display apparatus

Abstract

The present disclosure belongs to the technical field of display. Provided are a display panel and a display apparatus. The display panel includes a sub-pixel region, a non-sub-pixel region, and a drive substrate, which comprises a pixel drive circuit. One side of the drive substrate further includes a light-emitting device located in the sub-pixel region and including a first electrode, a light-emitting layer, and a second electrode which are sequentially arranged in the direction of the thickness of the drive substrate; a first connection portion located in the non-sub-pixel region and connected to the pixel drive circuit; and a second connection portion electrically connected to both the first connection portion and the first electrode, wherein the second connection portion comprises one first connection line and / or a plurality of second connection lines connected in parallel, and the maximum line width of the first connection line is greater than the maximum line width of a second connection line.

Description

Display panel and display device

[0001] The present disclosure claims priority to the Chinese patent application No. 202411010256.0, filed on July 25, 2024, and entitled "Display panel and display device", the entire content of which is incorporated herein by reference. TECHNICAL FIELD

[0002] The present disclosure relates to the technical field of display, and in particular, to a display panel and a display device. BACKGROUND

[0003] OLED (Organic Light Emitting Diode) display panels have the advantages of self-emission, wide viewing angle, wide color gamut, high contrast, thinness, etc., and are widely used in various display products. However, the current display panel is prone to display defects such as dark spots and thin dark spots.

[0004] SUMMARY

[0005] Based on the background technology, the present disclosure provides a display panel and a display device.

[0006] In a first aspect, the present disclosure provides a display panel, comprising a sub-pixel region and a non-sub-pixel region, and

[0007] A driving substrate comprising a pixel driving circuit, and further comprising:

[0008] A light emitting device located in the sub-pixel region, comprising a first electrode, a light emitting layer and a second electrode arranged in the thickness direction of the driving substrate in sequence;

[0009] A first connecting portion located in the non-sub-pixel region and overlapping with the pixel driving circuit;

[0010] A second connecting portion electrically connected with the first connecting portion and the first electrode, respectively;

[0011] The second connecting portion comprises a first connecting line and / or a plurality of parallel second connecting lines, and the maximum line width of the first connecting line is greater than the maximum line width of the second connecting line.

[0012] Exemplarily, the size of the orthographic projection of the second connecting portion on the driving substrate in a target direction is greater than or equal to 1 / 5 of the size of the orthographic projection of the first electrode on the driving substrate in the target direction;

[0013] The target direction is orthogonal to the connecting direction of the first connecting portion and the first electrode.

[0014] Exemplarily, the second connecting part comprises one first connecting line, and a ratio of a maximum line width of the first connecting line to a size of the first electrode in the line width direction is 0.2-1.

[0015] Exemplarily, a step difference exists between the first connecting part and the first electrode, and the second connecting part comprises the first connecting line or the second connecting lines at least in a region where the step difference exists.

[0016] Exemplarily, the display panel further comprises:

[0017] a planar layer located on a side of the driving substrate close to the light emitting device; a normal projection of the planar layer on the driving substrate covers a normal projection of the first electrode on the driving substrate and does not overlap with a normal projection of the first connecting part on the driving substrate, so that the step difference exists between the first electrode and the first connecting part;

[0018] wherein a normal projection of the first connecting line or the second connecting lines on the driving substrate overlaps with a normal projection of the planar layer on the driving substrate.

[0019] Exemplarily, the second connecting part comprises one first connecting line and a plurality of second connecting lines.

[0020] wherein the plurality of second connecting lines are connected with the first connecting line and the first electrode respectively; or the first connecting line is connected with the plurality of second connecting lines and the first electrode respectively.

[0021] Exemplarily, the second connecting part comprises a plurality of second connecting lines, the second connecting lines comprise first sub connecting lines and second sub connecting lines connected in sequence, the second sub connecting lines are located in the region where the step difference exists, and a line width of the second sub connecting lines is greater than a line width of the first sub connecting lines.

[0022] Exemplarily, the second connecting part comprises one first connecting line, the first connecting line comprises third sub connecting lines connected with the first connecting part and fourth sub connecting lines connected between the third sub connecting lines and the first electrode.

[0023] wherein the fourth sub connecting lines are located in the region where the step difference exists, and a line width of the fourth sub connecting lines is greater than a line width of the third sub connecting lines.

[0024] Exemplarily, a ratio of the line width of the fourth sub connecting lines to the size of the first electrode in the line width direction is 0.8-1.

[0025] Exemplarily, the sub-pixel region comprises a plurality of light-emitting regions, and the plurality of light-emitting regions respectively correspond to the plurality of light-emitting devices.

[0026] The first electrodes of different light-emitting devices in the same sub-pixel region are connected to the same first connecting part through different second connecting parts.

[0027] Exemplarily, the display panel further comprises:

[0028] A planar layer is located on the side of the driving substrate close to the light-emitting device and comprises a plurality of spaced-apart planar regions.

[0029] The orthogonal projection of each planar region on the driving substrate covers the orthogonal projection of the first electrodes in the two adjacent sub-pixel regions on the driving substrate and does not overlap with the orthogonal projection of the first connecting part on the driving substrate.

[0030] Exemplarily, the first electrode comprises a plurality of metal electrode layers arranged in sequence along the thickness direction of the driving substrate.

[0031] The second connecting part overlaps with at least one of the plurality of metal electrode layers.

[0032] Exemplarily, the display panel further comprises:

[0033] A passivation layer is laminated between the driving substrate and the light-emitting device, and the orthogonal projection of the passivation layer on the driving substrate covers the sub-pixel region and the non-sub-pixel region.

[0034] The first connecting part overlaps with the pixel driving circuit through the first via hole in the passivation layer.

[0035] Exemplarily, the display panel further comprises:

[0036] A buffer layer is located on the side of the driving substrate away from the light-emitting device.

[0037] A conductive light-shielding layer is located on the side of the buffer layer away from the light-emitting device, and the orthogonal projection of the conductive light-shielding layer on the driving substrate covers the orthogonal projection of the first electrode on the driving substrate and overlaps with the orthogonal projection of the first connecting part on the driving substrate.

[0038] A third connecting part is arranged on the side of the driving substrate close to the light-emitting device.

[0039] The second via hole is further formed in the buffer layer, the conductive light-shielding layer is electrically connected between the pixel driving circuit and the third connecting part through the second via hole, and the first connecting part is connected with the third connecting part through the first via hole.

[0040] Exemplarily, a shape of a projection of the first via hole on the driving substrate is different from a shape of a projection of the second via hole on the driving substrate.

[0041] Exemplarily, the conductive light-shielding layer comprises a first area and a second area, a projection of the first area on the driving substrate covers the first electrode, and a projection of the second area on the driving substrate overlaps with the non-sub-pixel area.

[0042] The conductive light-shielding layer further comprises a third area between the first area and the second area, and a projection of the third area on the driving substrate does not overlap with a projection of the second connecting part on the driving substrate.

[0043] In a second aspect, the present disclosure provides a display device comprising the display panel of any one of the first aspect.

[0044] The display panel provided by the present disclosure comprises a sub-pixel area, a non-sub-pixel area, and a driving substrate. The driving substrate comprises a pixel driving circuit. The driving substrate further comprises, on one side thereof, a light-emitting device located in the sub-pixel area, the light-emitting device comprising a first electrode, a light-emitting layer, and a second electrode arranged in sequence in a thickness direction of the driving substrate; a first connecting part located in the non-sub-pixel area and connected with the pixel driving circuit; and a second connecting part electrically connected with the first connecting part and the first electrode. The second connecting part comprises a first connecting line or a plurality of parallel second connecting lines. Each second connecting line is connected with the first connecting part and the second connecting part. The maximum line width of the first connecting line is greater than the maximum line width of the second connecting line. The first electrode of the light-emitting device is connected with the pixel driving circuit through the first connecting part and the second connecting part, thereby realizing the driving of the light-emitting device by the pixel driving circuit. Since the second connecting part comprises a first connecting line or a plurality of parallel second connecting lines, and the line width of the first connecting line is greater than the line width of the second connecting line, a larger electrical contact area is formed between the first electrode and the first connecting part. On the one hand, the probability of disconnection of the second connecting part is reduced. On the other hand, when one of the second connecting lines in the second connecting part is disconnected, the other second connecting lines can still maintain the connection of the path. Thus, the disconnection of the circuit connection between the first connecting part and the first electrode is avoided, thereby avoiding the occurrence of dark spots and thin dark spot defects.

[0045] The above description is only a summary of the technical solutions of the present disclosure. In order to enable one skilled in the art to better understand the technical means of the present disclosure, the following will be implemented according to the content of the description, and in order to enable the above and other purposes, characteristics and advantages of the present disclosure to be more obvious and easy to understand, the specific embodiments of the present disclosure will be described below.

[0046] Brief Description of Drawings

[0047] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or the related art, the drawings needed to be used in the embodiments or related art description will be briefly introduced as follows. Obviously, the drawings in the following description are some embodiments of the present disclosure, and those skilled in the art can also obtain other drawings according to these drawings without creative labor. It should be noted that the proportions in the drawings are only for illustration and do not represent the actual proportions.

[0048] FIG. 1 shows a cross-sectional structure schematic diagram of a display panel in an embodiment of the present disclosure;

[0049] FIG. 2 and FIG. 3 respectively show two top view schematic diagrams of the display panel shown in FIG. 1;

[0050] FIG. 4-FIG. 6 respectively show top view schematic diagrams of three display panels in embodiments of the present disclosure;

[0051] FIG. 7-FIG. 9 respectively show top view schematic diagrams of three sub-pixel regions in embodiments of the present disclosure;

[0052] FIG. 10 shows a top view schematic diagram of another display panel in an embodiment of the present disclosure;

[0053] FIG. 11 shows a cross-sectional structure schematic diagram of the B-B' section of the display panel of FIG. 10;

[0054] FIG. 12 shows a cross-sectional structure schematic diagram of a second via;

[0055] FIG. 13 shows a top view schematic diagram of another display panel in the present embodiment;

[0056] FIG. 14 shows an enlarged schematic diagram of the rectangular region AA in FIG. 13;

[0057] FIG. 15 and FIG. 16 respectively show cross-sectional structure schematic diagrams of two other display panels in the present embodiment;

[0058] FIG. 17 shows a top view schematic diagram of a display panel in Example 2.

[0059] Reference signs: 1a, sub-pixel region; 1b, non-sub-pixel region; 11, substrate; 12, buffer layer; 13, interlayer dielectric layer; 14, passivation layer; 15, planarization layer; 20, driving substrate; 21, source region; 22, source electrode; 23, gate layer; 24, gate insulating layer; 25, channel region; 26, drain region; 27, drain electrode; 28, third connection part; 30, light emitting device; 31, first electrode; 32, second electrode; 33, light emitting layer; 314, first electrode layer; 313, second electrode layer; 312, third electrode layer; 311, fourth electrode layer; 41, first connection part; 42, second connection part; 421, first connection line; 422, second connection line; 50, conductive light shielding layer; 60, pixel defining layer; 70, auxiliary structure; 71, first metal layer; 72, second metal layer; 73, third metal layer; 74, fourth metal layer; 75, fifth metal layer; 76, sixth metal layer; 51, first region; 52, second region; 53, third region; 131, first sub-via; 132, second sub-via; 141, first via; 143, second conductive metal; 422a, first sub-connection line; 422b, second sub-connection line; 421a, third sub-connection line; 421b, fourth sub-connection line.

[0060] DETAILED DESCRIPTION

[0061] In order to make the objects, technical solutions, and advantages of the embodiments of the present disclosure clearer, the technical solutions in the embodiments of the present disclosure will be described clearly and completely below with reference to the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are some but not all of the embodiments of the present disclosure. Based on the embodiments in the present disclosure, all other embodiments obtained by a person of ordinary skill in the art without creative work fall within the protection scope of the present disclosure.

[0062] In the present specification, "parallel" refers to a state in which the angle formed by two straight lines is -10° or more and 10° or less, and thus also includes a state in which the angle is -5° or more and 5° or less. In addition, "perpendicular" refers to a state in which the angle formed by two straight lines is 80° or more and 100° or less, and thus also includes a state in which the angle is 85° or more and 95° or less.

[0063] In the present specification, a polygon is not strictly a triangle, a parallelogram, a trapezoid, a pentagon, or a hexagon, and the like, and can be an approximate polygon, and can include some small deformation due to a tolerance.

[0064] In the related art, in an OLED display panel, especially a transparent OLED display panel, the display panel is prone to display panel dark spots, thin dark spots and other defects. The main reason is that the display panel includes a sub-pixel area and a non-sub-pixel area, and the anode of the light emitting device located in the sub-pixel area has a step difference with the film layer in the non-sub-pixel area. During the process of connecting the pixel driving circuit with the anode, the metal film layer is prone to breakage due to the existence of the step difference, thereby causing the circuit connection between the anode and the pixel driving circuit to be disconnected, which in turn leads to poor contact between the anode and the pixel driving circuit, so that the pixel cannot be lit, and thus dark spots or thin dark spots appear.

[0065] Therefore, the display panel provided in the embodiments of the present disclosure can be used to avoid the problem of dark spot defects caused by the fact that the pixel driving circuit cannot drive the light emitting device.

[0066] Referring to FIGS. 1-3, FIG. 1 shows a schematic diagram of a cross-sectional structure of a display panel, and FIGS. 2 and 3 respectively show two schematic diagrams of a top plane of the display panel shown in FIG. 1. As shown in FIGS. 1-3, the display panel in the embodiments mainly includes a sub-pixel area 1a and a non-sub-pixel area 1b, and

[0067] The driving substrate 20 includes a pixel driving circuit, and further includes, on one side of the driving substrate 20:

[0068] The light emitting device 30 is located in the sub-pixel area 1a and includes a first electrode 31, a light emitting layer 33 and a second electrode 32 arranged in the thickness direction of the driving substrate 20 in sequence.

[0069] The first connecting part 41 is located in the non-sub-pixel area 1b and is overlapped with the pixel driving circuit.

[0070] The second connecting part 42 is electrically connected with the first connecting part 41 and the first electrode 31 respectively.

[0071] The second connecting part 42 includes a first connecting line 421 and / or a plurality of parallel second connecting lines 422, and the maximum line width of the first connecting line 421 is greater than the maximum line width of the second connecting line 422.

[0072] In the embodiments, the display panel can include a sub-pixel area 1a and a non-sub-pixel area 1b. It should be noted that the sub-pixel area and the non-sub-pixel area are a division of the plane on which the display panel is displayed. Specifically, the sub-pixel area and the non-sub-pixel area can be located in the display area of the display panel.

[0073] In an example, the display panel can be a transparent display panel, the driving substrate 20 can be a transparent driving substrate 20, the sub-pixel region can be referred to as a light-emitting region, and the non-sub-pixel region can be referred to as a light-transmitting region.

[0074] In the embodiment, the driving substrate 20 can include a pixel driving circuit, which provides a driving voltage for the light-emitting device 30 on the display panel. The pixel driving circuit can include a plurality of pixel driving circuits, each of which provides a driving voltage for a plurality of light-emitting devices 30. The pixel circuit can be a 3T1C driving circuit or a 7T1C driving circuit. The pixel driving circuit can include a conductive portion at the output end of the pixel driving circuit. Generally, the first electrode 31 in the light-emitting device 30 can be connected to the conductive portion of the pixel driving circuit.

[0075] In an example, as shown in FIG. 1, the pixel driving circuit on the driving substrate 20 can include a thin film transistor TFT. The driving substrate 20 can include a substrate 11, an active layer on one side of the substrate 11, a gate insulating layer 24 on the side of the active layer away from the substrate, a gate layer 23 on the side of the gate insulating layer 24 away from the substrate, and an interlayer dielectric layer 13 on the side of the gate layer 23 away from the substrate 11, a source electrode 22 and a drain electrode 27 on the side of the interlayer dielectric layer 13 away from the substrate 11. Specifically, the active layer can include a channel region 25 corresponding to the gate layer 23, a source region 21 overlapped with the source electrode 22, and a drain region 26 overlapped with the drain electrode 27. The source region 21 and the drain region 26 are formed after the active layer is conductive. The gate insulating layer 24, the source electrode 22, the drain electrode 27, the gate layer 23, and the active layer form a TFT. As shown in FIG. 1, the conductive portion can be the drain electrode 27. The drain electrode 27 is electrically connected to the first electrode 31 in the light-emitting device 30.

[0076] The light-emitting device 30 can be located in the sub-pixel region. The light-emitting device 30 can include a first electrode 31, a light-emitting layer 33, and a second electrode 32. The first electrode 31 is located close to the driving substrate 20. The light-emitting layer 33 is located on the side of the first electrode 31 away from the driving substrate 20. The second electrode 32 is located on the side of the light-emitting layer 33 away from the driving substrate 20. The first electrode 31 can be a cathode, and the second electrode 32 can be an anode. Alternatively, the first electrode 31 can be an anode, and the second electrode 32 can be a cathode.

[0077] In an example, the second electrode 32 can cover the driving substrate 20 entirely, and the light-emitting layer 33 can also cover the driving substrate 20 entirely. That is, the second electrode 32 covers the sub-pixel region and the non-sub-pixel region, and the light-emitting layer 33 covers the sub-pixel region and the non-sub-pixel region. The orthographic projection of the first electrode 31 on the driving substrate 20 can be covered by the sub-pixel region.

[0078] In the embodiment, the first electrode 31 can be electrically connected with the conductive part of the pixel driving circuit through the first connecting part 41 and the second connecting part 42. Specifically, as shown in FIG. 1, the first connecting part 41 can be located in the non-sub-pixel area, and the first connecting part 41 can be overlapped with the conductive part of the pixel driving circuit to realize electrical connection; one end of the second connecting part 42 is connected with the first connecting part 41, and the other end is electrically connected with the first electrode 31. It should be noted that the electrical connection referred to in the embodiment refers to that two metal elements are in direct contact; for example, the first electrode 31 and the second connecting part 42 are in direct contact, and the first connecting part 41 and the second connecting part 42 are in direct contact.

[0079] In the embodiment, the second connecting part 42 can include a first connecting line 421 and / or a plurality of parallel second connecting lines 422. Specifically, as shown in FIG. 2, the second connecting part 42 can include a first connecting line 421, or as shown in FIG. 3, the second connecting part 42 can include a plurality of parallel second connecting lines 422, or in some examples, the second connecting part 42 can include a first connecting line 421 and a plurality of parallel second connecting lines 422. The parallel refers to that the plurality of second connecting lines 422 form a plurality of independent current paths between the first electrode 31 and the first connecting part 41.

[0080] In the case of including the first connecting line 421 and the plurality of parallel second connecting lines 422, one end of the plurality of second connecting lines 422 is connected with the first connecting line 421 at the same time. In this way, the second connecting part 42 can include a plurality of second connecting lines 422 which are parallel to each other at one end of the first connecting line 421, and the other end of the plurality of second connecting lines 422 can be connected with the first electrode 31 or the first connecting part 41. Details can be referred to the description of subsequent embodiments.

[0081] In the embodiment, the second connecting part 42 can include a first connecting line 421 and / or a plurality of parallel second connecting lines 422. Specifically, as shown in FIG. 2, the second connecting part 42 can include a first connecting line 421, or as shown in FIG. 3, the second connecting part 42 can include a plurality of parallel second connecting lines 422, or in some examples, the second connecting part 42 can include a first connecting line 421 and a plurality of parallel second connecting lines 422. The parallel refers to that the plurality of second connecting lines 422 form a plurality of independent current paths between the first electrode 31 and the first connecting part 41.

[0082] In practice, the second connecting part 42 connected with each of the plurality of light emitting devices 30 can include one first connecting line 421, as shown in FIG. 2, and the second connecting part 42 connected with each of the plurality of light emitting devices 30 includes one first connecting line 421. Alternatively, the second connecting part 42 connected with each of the plurality of light emitting devices 30 can include a plurality of second connecting lines 422, as shown in FIG. 3, and the second connecting part 42 connected with each of the plurality of light emitting devices 30 includes a plurality of second connecting lines 422. Alternatively, the second connecting part 42 connected with part of the plurality of light emitting devices 30 can include one second connecting line 422, and the second connecting part 42 connected with the other part of the plurality of light emitting devices 30 can include a plurality of second connecting lines 422.

[0083] Exemplarily, referring to FIG. 4, a top view of another display panel is shown. As shown in FIG. 4, the display panel includes a display area, and the second connecting part 42 connected with the plurality of light emitting devices 30 in the middle region of the display area can include one first connecting line 421, and the second connecting part 42 connected with the plurality of light emitting devices 30 in the edge region of the display area can include a plurality of second connecting lines 422. In this way, the grid formed by the metal lines of the light emitting devices 30 in the middle region of the display area can be as few as possible, so that when the display panel is a transparent display panel, the diffraction effect caused by the grid formed between the metal lines can be avoided, and the clear observation of the background object can be ensured.

[0084] In the above embodiment, the maximum line width of the first connecting line 421 can be greater than the maximum line width of the second connecting line 422, that is, for two light emitting devices 30, one of which is connected with the second connecting part 42 including one first connecting line 421, and the other of which is connected with the second connecting part 42 including a plurality of second connecting lines 422, the maximum line width of the first connecting line 421 is greater than the maximum line width of the second connecting line 422. For example, referring to FIG. 4, the maximum line width of the first connecting line 421 included in the second connecting part 42 connected with the light emitting device 30 in the middle region is greater than the maximum line width of the second connecting line 422 included in the second connecting part 42 connected with the light emitting device 30 in the edge region. For another example, referring to FIG. 2 and FIG. 3, the maximum line width of the first connecting line 421 included in the second connecting part 42 connected with the light emitting device 30 in FIG. 2 is greater than the maximum line width of the second connecting line 422 included in the second connecting part 42 connected with the light emitting device 30 in FIG. 3.

[0085] That is, the first connecting part 41 and the first electrode 31 can be connected by a widened first connecting line 421 or by multiple second connecting lines 422. When connected by the widened first connecting line 421, the contact area between the first electrode 31 and the first connecting part 41 can be increased, so that the first connecting line 421 is less likely to be broken by climbing, and the occurrence of disconnection can be avoided, thereby reducing the probability of occurrence of dark spots. When connected by multiple second connecting lines 422, even if one second connecting line 422 is broken, the electrical connection between the first electrode 31 and the first connecting part 41 can be maintained by other second connecting lines 422 that are not broken, thereby reducing the probability of occurrence of dark spots.

[0086] In this embodiment, the line width can refer to the size of the connecting line (the first connecting line 421 and the second connecting line 422) in the target direction, which is the direction orthogonal to the connection direction between the first connecting part 41 and the first electrode 31. As shown in FIGS. 2 and 3, the target direction is the Y direction in the figure; accordingly, the maximum line width can refer to the maximum size of the connecting line in the target direction, such as the size of the region with the widest line width in the target direction.

[0087] The first electrode 31 and the second electrode 32 can both be transparent electrodes, which can be made of metal or metal oxide, for example, can be formed of indium tin oxide. The first connecting part 41 and the second connecting part 42 can be made of transparent metal or transparent metal oxide, and the thickness of the first electrode 31 can be greater than the thickness of the second electrode 32.

[0088] The display panel of this embodiment can connect the first connecting part 41 and the first electrode 31 by a first connecting line 421 or multiple parallel second connecting lines 422, and the line width of the first connecting line 421 is greater than the line width of the second connecting line 422, so that the first electrode 31 and the first connecting part 41 have a larger electrical contact area. In the case of connection by the first connecting line 421, the probability of disconnection of the second connecting part 42 can be reduced; in the case of connection by multiple second connecting lines 422, when one of the second connecting lines 422 in the second connecting part 42 is disconnected, the other second connecting lines 422 can still maintain the connection of the path. Thus, the disconnection of the electrical connection between the first connecting part 41 and the first electrode 31 can be avoided, thereby avoiding the occurrence of dark spots and thin dark spot defects.

[0089] In some embodiments, no matter whether the second connection part 42 includes a plurality of second connection lines 422 or only includes a first connection line 421, a size occupied by a normal projection of the second connection part 42 on the driving substrate 20 in the target direction is greater than or equal to 1 / 5 of a size of the first electrode 31 in the target direction.

[0090] In the embodiment, when the second connection part 42 includes the first connection line 421, a size occupied by a normal projection of the first connection line 421 on the driving substrate 20 in the target direction can be greater than or equal to 1 / 5 of a size of the first electrode 31 in the target direction. When the second connection part 42 includes the plurality of second connection lines 422, a sum of sizes occupied by normal projections of the plurality of second connection lines 422 on the driving substrate 20 in the target direction can be greater than or equal to 1 / 5 of a size of the first electrode 31 in the target direction.

[0091] The size occupied by the normal projection of the connection line on the driving substrate 20 in the target direction can be understood as a line width of the connection line. In this way, the line width of the second connection part 42 can be 1 / 5 or more of a size of the first electrode 31 in the line width direction, such as the Y direction in FIGS. 2 and 3. Accordingly, the sum of the sizes occupied by the normal projections of the plurality of second connection lines 422 on the driving substrate 20 in the target direction can be a sum of line widths of the plurality of second connection lines 422. Specifically, the line width of the second connection part 42 can be 1 / 5, 1 / 3, 2 / 5, 1 / 2, 3 / 5, 4 / 5, or 0.9 of the size of the first electrode 31 in the line width direction.

[0092] In the embodiment, the second connection part 42 is made to have a wider width as much as possible, so that the contact area between the second connection part 42 and the first electrode 31 is large enough, thereby reducing the risk of disconnection between the first connection part 41 and the first electrode 31, no matter whether the second connection part 42 includes the plurality of second connection lines 422 or only includes the first connection line 421.

[0093] In yet some embodiments, the second connection part 42 can include the first connection line 421, and a ratio of a maximum line width of the first connection line 421 to a size of the first electrode 31 in the line width direction is 0.2-1. The size of the first electrode 31 in the line width direction can be a size of the first electrode 31 in the target direction.

[0094] Please refer to FIG. 2, the second connecting part 42 includes a first connecting line 421, the maximum line width of the first connecting line 421 can account for 0.2, 0.4, 0.5, 0.6, 0.7, 0.8, 0.9 or 1 of the size of the first electrode 31 in the target direction. In the case of 1, the first connecting line 421 can be as wide as the first electrode 31, so as to avoid the risk of breakage.

[0095] In some embodiments, as shown in FIG. 1, the light emitting device 30 can be integrally raised on the driving substrate 20, so that there is a step difference between the first electrode 31 and the first connecting part 41. The main reason for the existence of the step difference can be that the side of the driving substrate 20 close to the light emitting device 30 includes an insulating film layer, and the insulating film layer can be located only in the sub-pixel area but not in the non-sub-pixel area. The insulating film layer can be an inorganic material film layer, an organic material film layer, or a film layer in which inorganic materials and organic materials are superimposed on each other.

[0096] Due to the existence of the step difference, it is easier to cause the second connecting part 42 between the first electrode 31 and the first connecting part 41 to break. In this embodiment, the second connecting part 42 includes at least the first connecting line 421 or the plurality of second connecting lines 422 in the area where the step difference exists.

[0097] In this way, when forming the second connecting part 42, the area where the step difference exists reduces the risk of breakage by the widened first connecting line 421, or ensures the electrical connection performance by forming the plurality of second connecting lines 422.

[0098] In further examples of this embodiment, the step difference can be formed due to the planar layer 15. For example, the display panel can further include a planar layer 15, wherein the planar layer 15 can be located in the sub-pixel area. In this way, when the display panel is a transparent display panel, it can enhance the light transmission performance of the non-sub-pixel area and can raise the light emitting device 30.

[0099] Please continue to refer to FIG. 1, FIG. 5 and FIG. 6, FIG. 5 and FIG. 6 respectively show another two top view schematic diagrams of the display panel shown in FIG. 1. As shown in FIG. 1 and FIG. 5, the planar layer 15 is located on the side of the driving substrate 20 close to the light emitting device 30; the orthographic projection of the planar layer 15 on the driving substrate 20 covers the orthographic projection of the first electrode 31 on the driving substrate 20, and does not overlap with the orthographic projection of the first connecting part 41 on the driving substrate 20.

[0100] Among them, the orthographic projection of the second connecting part 42 on the driving substrate 20 overlaps with the edge of the planar layer 15, and the second connecting part 42 includes at least a first connecting line 421 or a plurality of second connecting lines 422 in the overlapping area where the overlap exists.

[0101] As shown in FIG. 1, the orthogonal projection of the planar layer 15 on the driving substrate 20 covers the orthogonal projection of the first electrode 31 on the driving substrate 20 and does not overlap the orthogonal projection of the first connecting part 41 on the driving substrate 20. In practice, the planar layer 15 can be located in the sub-pixel region and does not overlap the non-sub-pixel region. As shown in FIG. 5, the second connecting part 42 needs to connect the first electrode 31 and the first connecting part 41, so the orthogonal projection of the second connecting part 42 on the driving substrate 20 can overlap the first electrode 31, the first connecting part 41 and the planar layer 15.

[0102] The overlapping region at least includes the region where the second connecting part 42 overlaps the edge of the planar layer 15. For the convenience of patterning and manufacturing, the overlapping region can include the region where the second connecting part 42 overlaps the edge of the planar layer 15 and the region where the second connecting part 42 overlaps the first electrode 31, that is, the overlapping region overlaps the planar layer 15 and the first electrode 31. The outer contour of the orthogonal projection of the overlapping region on the driving substrate 20 can be located outside the edge of the orthogonal projection of the planar layer 15 on the driving substrate 20.

[0103] The second connecting part 42 at least includes the first connecting line 421 or a plurality of second connecting lines 422 in the overlapping region. Specifically, in the overlapping region, there is either one first connecting line 421 or a plurality of second connecting lines 422. The region of the second connecting part 42 other than the overlapping region can include one connecting line or a plurality of connecting lines. Specifically, in the case where the overlapping region also includes one first connecting line 421, if the region other than the overlapping region includes one connecting line, the second connecting part 42 can be considered as a whole to include one first connecting line 421, as shown in FIG. 2 and FIG. 5, the line width of the first connecting line 421 in the overlapping region can be greater than 1 / 5 of the size of the first electrode 31 in the line width direction, or the line width of the whole first connecting line 421 is greater than 1 / 5 of the size of the first electrode 31 in the line width direction.

[0104] Specifically, the overlapping region can include a plurality of second connecting lines 422, and if the region other than the overlapping region includes one connecting line, as shown in FIG. 6, the second connecting part 42 can be considered as a whole to include one first connecting line 421 and a plurality of second connecting lines 422 connected in parallel with the first connecting line 421. The first connecting line 421 is connected with the first connecting part 41 and the plurality of second connecting lines 422, and the plurality of second connecting lines 422 can be connected with the first electrode 31, so that the orthogonal projection of the second connecting part 42 on the driving substrate 20 can have a comb shape.

[0105] By adopting the technical solution of the embodiment, on one hand, the climbing ability of the second connecting portion 42 at the flat layer 15 can be enhanced, and in the case of including the first connecting line 421, the climbing ability is enhanced, so that the second connecting portion 42 is not prone to be broken at the flat layer 15. On the other hand, the electrical connection with the first electrode 31 can also be ensured by the plurality of second connecting lines 422, and if one of the second connecting lines 422 is broken, the electrical connection can be ensured by the other second connecting lines 422, thereby reducing the risk of disconnection between the second connecting portion 42 and the first electrode 31.

[0106] According to the above embodiment, the second connecting portion 42 can include one first connecting line 421 and a plurality of second connecting lines 422, and in some embodiments, the plurality of second connecting lines 422 can be connected with the first connecting line 421 and the first electrode 31 respectively. As shown in FIG. 6, one end of the first connecting line 421 is in direct contact with the first connecting portion 41, and the other end is in contact with one end of the plurality of second connecting lines 422 at the same time, and the other end of the plurality of second connecting lines 422 is in direct contact with the first electrode 31 at the same time.

[0107] In the case where the display panel includes the flat layer 15, and the flat layer 15 is located in the sub-pixel region and does not overlap with the non-sub-pixel region, the plurality of second connecting lines 422 can be located in the overlapping region of the second connecting portion 42 and the flat layer 15, that is, the orthographic projection of each second connecting line 422 on the driving substrate 20 overlaps with the orthographic projection of the flat layer 15 on the driving substrate 20.

[0108] By adopting the structure of the second connecting portion 42, since the second connecting portion 42 includes the plurality of second connecting lines 422 connected with the first electrode 31, and the second connecting lines 422 are located in the overlapping region, when one of the second connecting lines 422 is broken due to climbing, the connection between the first connecting portion 41 and the first electrode 31 can still be ensured by the other second connecting lines 422, thereby avoiding the occurrence of dark spots.

[0109] According to the above embodiment, in the case where the second connecting portion 42 includes the first connecting line 421 and the plurality of second connecting lines 422, the first connecting line 421 can be connected with the first electrode 31, and specifically, one end of the plurality of second connecting lines 422 is in direct contact with the first connecting portion 41 at the same time, the other end of the plurality of second connecting lines 422 is connected with one end of the first connecting line 421 at the same time, and the other end of the first connecting line 421 is connected with the first electrode 31.

[0110] Referring to FIG. 7, a top view of a sub-pixel in this case is shown. As shown in FIG. 7, in the case where the display panel includes a planar layer 15, and the planar layer 15 is located in the sub-pixel region and does not overlap the non-sub-pixel region, the first connecting line 421 can be located in an overlapping region where the second connecting portion 42 overlaps the planar layer 15, one end of the first connecting line 421 is connected to the first connecting portion 41 through a plurality of parallel second connecting lines 422, the other end is connected to the first electrode 31, and the orthogonal projection of the first connecting line 421 on the driving substrate 20 overlaps the orthogonal projection of the planar layer 15 on the driving substrate 20.

[0111] With this structure of the second connecting portion 42, since the second connecting portion 42 includes the first connecting line 421 connected to the first electrode 31, and the line width of the first connecting line 421 is large, the breakage of the second connecting portion 42 at the climbing slope can be avoided, and the occurrence of dark spots can be avoided.

[0112] In some embodiments, in the case where the second connecting portion 42 includes one first connecting line 421, the line width of the first connecting line 421 can be non-uniform, and the position of the maximum line width of the first connecting line 421 can be located at the step. For example, still referring to FIG. 5, the second connecting portion 42 includes one first connecting line 421, the first connecting line 421 includes a third sub-connecting line 421a connected to the first connecting portion 41, and a fourth sub-connecting line 421b connected between the third sub-connecting line 421a and the first electrode 31; wherein the fourth sub-connecting line 421b is located in the region where the step is located, and the line width of the fourth sub-connecting line 421b is greater than the line width of the third sub-connecting line 421a.

[0113] In this embodiment, one end of the fourth sub-connecting line 421b is connected to the third sub-connecting line 421a, the other end is connected to the first electrode 31, the other end of the third sub-connecting line 421a is connected to the first connecting portion 41, and the line width of the third sub-connecting line 421a is less than the line width of the fourth sub-connecting line 421b, so that the line width of the first connecting line 421 can gradually increase in the connection direction from the first connecting portion 41 to the first electrode 31.

[0114] The line width of the third sub-connecting line 421a can be uniform or non-uniform, and in the case of non-uniform, the orthogonal projection of the second connecting portion 42 on the driving substrate 20 can be in the shape of a trapezoid, etc. Specifically, the fourth sub-connecting line 421b is located in the region where the step is located, for example, the orthogonal projection of the fourth sub-connecting line 421b on the driving substrate 20 can overlap the orthogonal projection of the planar layer 15 on the driving substrate 20, so that the second connecting portion 42 is widened in the region where the step is located, and the risk of breakage at the climbing slope is reduced.

[0115] In a further example of this embodiment, since the line width of the third sub-connection line 421a included in the second connection portion 42 is smaller in the area outside the area where the step is located, the line width of the fourth sub-connection line 421b can be set to be larger, for example, the ratio of the line width of the fourth sub-connection line 421b to the size of the first electrode 31 in the line width direction is 0.8-1. It can be 0.8, 0.85, 0.9, 0.95 or 1. When this example is adopted, in the case where the display panel is a transparent display panel, on the one hand, the area of the second connection portion 42 in the light transmission area can be reduced, and the light transmittance can be improved, and on the other hand, the climbing ability of the second connection portion 42 in the area where the step is located can be ensured, and the occurrence of disconnection can be avoided.

[0116] In some embodiments, in the case where the second connection portion 42 includes a plurality of second connection lines 422, the line width of each second connection line 422 can also be non-uniform, and the larger line width is located in the area where the step is located. Specifically, please refer to FIG. 8, which shows a top view schematic diagram of another sub-pixel. As shown in FIG. 8, the second connection portion 42 includes a plurality of second connection lines 422, and the second connection line 422 includes a first sub-connection line 422a and a second sub-connection line 422b connected in sequence.

[0117] Among them, the second sub-connection line 422b is located in the area where the step is located, and the line width of the second sub-connection line 422b is larger than that of the first sub-connection line 422a.

[0118] In this embodiment, the second connection portion 42 includes a plurality of second connection lines 422, each second connection line 422 includes a first sub-connection line 422a with a smaller line width and a second sub-connection line 422b with a larger line width, so that the line width of each second connection line 422 is non-uniform, and the area with a larger line width is located in the area where the step is located.

[0119] Of course, in some examples, part of the second connection line 422 can include the first sub-connection line 422a and the second sub-connection line 422b, so that the line width of part of the second connection line 422 is non-uniform, and the line width of the remaining part of the second connection line 422 is uniform. For this, please refer to FIG. 9, which shows a top view schematic diagram of another sub-pixel. Different from the sub-pixel shown in FIG. 8, the second connection portion 42 includes a plurality of second connection lines 422, part of the second connection line 422 is non-uniform in line width, and the larger line width is located in the area where the step is located, for example, the line width of the second connection line 422 in the middle is non-uniform; the line width of the remaining part of the second connection line 422 is uniform, for example, the line width of the second connection line 422 located on both sides of the second connection portion 42 is uniform.

[0120] The structure of the second connecting portion 42 in this embodiment enables multiple connecting lines to simultaneously connect between the first connecting portion 41 and the first electrode 31, and the connecting area of the region where the step is located is relatively wide, thereby further reducing the probability of occurrence of dark spots.

[0121] In some embodiments, the sub-pixel region can be divided into multiple light emitting regions, and each light emitting region can be configured with a light emitting device 30. The first electrodes 31 of the multiple light emitting devices 30 in the same sub-pixel region can be connected to the same connecting portion, and the light emitting devices 30 located in different light emitting regions are connected to different second connecting portions 42.

[0122] Please refer to FIG. 10 and FIG. 11, FIG. 10 shows a top view schematic diagram of another display panel, and FIG. 11 shows a cross-sectional structure schematic diagram of the B-B' section of the display panel of FIG. 10. As shown in FIG. 10, each sub-pixel region can be divided into two, three or four light emitting regions, for example, the sub-pixel region in FIG. 10 is divided into two light emitting regions, and the two light emitting regions have a spacing therebetween, which can be referred to as a non-light emitting region. In practice, in the case of a transparent display panel, the spacing between the light emitting regions can be set as a light transmission region.

[0123] In this embodiment, the same sub-pixel region can include the same number of light emitting devices 30 as the number of light emitting regions, wherein the first electrodes 31 of the light emitting devices 30 located in different light emitting regions in the same sub-pixel region have no overlap in orthographic projection on the driving substrate 20. In this case, in one example, the second electrodes 32 of the light emitting devices 30 located in different light emitting regions in the same sub-pixel region can be connected to each other, and the light emitting layers 33 of the light emitting devices 30 located in different light emitting regions in the same sub-pixel region can be connected to each other. Alternatively, in another example, the second electrodes 32 of the light emitting devices 30 located in different light emitting regions in the same sub-pixel region can be connected to each other, and the light emitting layers 33 of the light emitting devices 30 located in different light emitting regions in the same sub-pixel region can have no overlap, that is, the light emitting layers 33 in different light emitting regions can be independent of each other.

[0124] As shown in FIG. 10 and FIG. 11, the first electrodes 31 of the multiple light emitting devices 30 in the same sub-pixel region can be connected to the same first connecting portion 41 through the respective corresponding second connecting portions 42. For example, as shown in FIG. 10, the sub-pixel region is divided into two light emitting regions, and the first electrodes 31 of the light emitting devices 30 in the two light emitting regions have no overlap, such as including a light emitting device R1 and a light emitting device R2. The light emitting device R1 is connected to the first connecting portion 41 through three second connecting lines 422, and the light emitting device R2 is also connected to the first connecting portion 41 through three second connecting lines 422.

[0125] In the display panel of the embodiment, in the case where one sub-pixel region is divided into a plurality of light-emitting regions, the plurality of light-emitting regions can be connected to the same first connecting part 41 through the respective second connecting parts 42. In this way, in the case where the second connecting part 42 of one light-emitting region is broken, normal light emission can still be performed through another light-emitting region. In the case where the second connecting part 42 of one light-emitting region is broken, the current on the first connecting part 41 is not shunted, thereby improving the light-emitting brightness of the light-emitting region performing normal light emission, and the brightness loss can be reduced compared to the case where the plurality of light-emitting regions perform normal light emission. Thus, the probability of the occurrence of dark spots or thin dark spots in the sub-pixel is further reduced.

[0126] In a further example of the embodiment, in the case where the sub-pixel region includes a plurality of light-emitting regions, the structure of the second connecting part 42 corresponding to each light-emitting region can be the same, for example, each including a plurality of second connecting lines 422 or each including a first connecting line 421. It should be noted that, in the case where each includes a first connecting line 421, to avoid contact between the second connecting parts 42 of different light-emitting regions, there is no overlap between the second connecting parts 42 corresponding to different light-emitting regions, for example, the line width of the first connecting line 421 can be smaller than the size of the first electrode 31 in the line width direction (i.e., the target direction), so that there is no overlap between the second connecting parts 42 of adjacent two light-emitting regions.

[0127] Alternatively, the structures of the second connecting parts 42 corresponding to the plurality of light-emitting regions can not be completely the same, for example, the second connecting part of one light-emitting region includes a plurality of second connecting lines 422, and the second connecting part 42 of another light-emitting region includes a first connecting line 421. In this way, the same sub-pixel region can be supplied with power by the second connecting parts 42 of two different structures. Thus, one sub-pixel region can avoid breakage by the widened first connecting line 421, and the power supply of the first electrode 31 can be ensured by the plurality of second connecting lines 422.

[0128] In a further example of the embodiment, as shown in FIG. 11, a pixel defining layer 60 can be arranged on one side of the driving substrate 20. The pixel defining layer 60 includes a plurality of openings, wherein the plurality of openings are used to define the light-emitting regions in each sub-pixel region. Specifically, in one example, the openings in the same sub-pixel region have a first distance, and the openings for adjacent two sub-pixel regions have a second distance. The second distance can be greater than the first distance. As shown in FIG. 10, the spacing between the plurality of light-emitting regions in the same sub-pixel region can be smaller than the spacing between the light-emitting regions in different sub-pixel regions and adjacent to each other.

[0129] In a further example of the embodiment, the first electrode 31 and the first connecting part 41 have a step. The main reason for the existence of the step can be that the sub-pixel region includes the planar layer 15, and the non-sub-pixel region does not include the planar layer 15.

[0130] In one example, the planar layer 15 can cover a plurality of light emitting regions of one sub-pixel region, so that each sub-pixel region can correspond to one independent planar layer 15.

[0131] In another example, the planar layer 15 can cover two adjacent sub-pixel regions, so that the two adjacent sub-pixel regions can correspond to one independent planar layer 15. Specifically, please continue to refer to FIG. 10, the display panel further includes: a planar layer 15 located on the side of the driving substrate 20 close to the light emitting device 30, including a plurality of spaced planar regions; wherein the orthographic projection of each planar region on the driving substrate 20 covers the orthographic projection of the first electrode 31 in the two adjacent sub-pixel regions on the driving substrate 20, and does not overlap with the orthographic projection of the first connecting part 41 on the driving substrate 20.

[0132] In this embodiment, the planar layer 15 can include a plurality of planar regions, each planar region can cover two adjacent sub-pixel regions, and in the case that each sub-pixel region includes a plurality of light emitting regions, each planar region can cover a plurality of light emitting regions contained in the two adjacent sub-pixel regions. Wherein, as described in the above embodiment, there is no overlap between the planar region and the first connecting part 41, so that there is a step between the first connecting part 41 and the first electrode 31.

[0133] Wherein, the plurality of sub-pixel regions can be arranged in rows and columns, then the planar region can cover two adjacent sub-pixel regions in the row direction, or can cover two adjacent sub-pixel regions in the column direction (not shown in the figure). As shown in FIG. 10, in the case that one planar region covers two adjacent sub-pixel regions, the first connecting part 41 and the second connecting part 42 corresponding to the two sub-pixel regions respectively can be symmetrically distributed, thereby facilitating the wiring of the light emitting device 30.

[0134] Since one planar region can cover two adjacent sub-pixel regions, the patterning process of the planar layer 15 can be simplified.

[0135] In some embodiments, the connection structure between the first connecting part 41 and the pixel driving circuit is exemplarily described. Specifically, please refer to FIG. 1, the display panel can further include a passivation layer 14, which can be laminated between the driving substrate 20 and the light emitting device 30, the orthographic projection of the passivation layer 14 on the driving substrate 20 covers the light emitting region and the non-light emitting region;

[0136] Wherein, the passivation layer 1414 is provided with a first via hole 141, and the first connecting part 41 is connected with the pixel driving circuit through the first via hole 141.

[0137] In the embodiment, the passivation layer 14 can be located between the planarization layer 15 and the driving substrate 20, the first via hole 141 can be a circular via hole or an elliptical via hole, the first conductive metal is in the first via hole 141, the first connecting part 41 directly contacts the first conductive metal, the first connecting part 41 and the first conductive metal can be the same material, the first conductive metal directly contacts the conductive part of the pixel driving circuit, such as the drain electrode 27, so as to realize the electrical connection between the first connecting part 41 and the pixel driving circuit.

[0138] In some other embodiments, when the display panel is a transparent display panel, the pixel driving circuit can be generally formed in the sub-pixel area, so as to reduce the area occupied by the pixel driving circuit in the light transmission area, and the first connecting part 41 is located in the non-sub-pixel area (light transmission area), so that the connection distance between the first connecting part 41 and the pixel driving circuit located in the sub-pixel area is long. In this case, a plurality of via holes can be formed, and the plurality of via holes can be arranged in different film layers, so as to connect the first connecting part 41 and the pixel driving circuit.

[0139] Please continue to refer to FIG. 1, the display panel further comprises:

[0140] The buffer layer 12 is located on the side of the driving substrate 20 away from the light emitting device 30;

[0141] The conductive light shielding layer 50 is located on the side of the buffer layer 12 away from the light emitting device 30, the orthographic projection of the conductive light shielding layer 50 on the driving substrate 20 covers the orthographic projection of the first electrode 31 on the driving substrate 20, and overlaps with the orthographic projection of the first connecting part 41 on the driving substrate 20;

[0142] The third connecting part 28 is arranged on the side of the driving substrate 20 close to the light emitting device 30;

[0143] The second via hole is further formed in the buffer layer 12, the pixel driving circuit and the third connecting part 28 are electrically connected through the conductive light shielding layer 50 in the second via hole, and the first connecting part 41 is connected with the third connecting part 28 through the first via hole 141.

[0144] In the embodiment, the buffer layer 12 can play a role of blocking water vapor and impurity ions in the driving substrate 20 (especially organic material), and play a role of adding hydrogen ions for the subsequent active layer. The material of the buffer layer 12 is an insulating material, which can insulate and separate the conductive light shielding layer 50 and the active layer; the buffer layer 12 can include silicon nitride, silicon oxide or silicon oxynitride. In some embodiments, the buffer layer 12 can be omitted according to the type or process condition of the driving substrate 20.

[0145] In the embodiment, the passivation layer 14 is formed between the driving substrate 20 and the light emitting device 30, and the driving substrate 20 can include the substrate 11, the conductive light shielding layer 50 located on one side of the substrate 11, the buffer layer 12 located on one side of the conductive light shielding layer 50, the active layer located on one side of the buffer layer 12 away from the substrate 11, the gate insulating layer 24 located on one side of the active layer away from the substrate, the gate layer 23 located on one side of the gate insulating layer 24 away from the substrate, and the interlayer dielectric layer 13 located on one side of the gate layer 23 away from the substrate 11, the source electrode 22 and the drain electrode 27 located on one side of the interlayer dielectric layer 13 away from the substrate 11. Correspondingly, the second via hole can be formed in the interlayer dielectric layer 13 and the buffer layer 12, that is, the second via hole can pass through the interlayer dielectric layer 13 and the buffer layer 12.

[0146] The first via hole 141 passes through the passivation layer 14, and the second via hole passes through the interlayer dielectric layer 13 and the buffer layer 12, and the second conductive metal 143 can be formed in the second via hole, and the second conductive metal 143 is in direct contact with the conductive light shielding layer 50. In the embodiment, the drain electrode 27 of the pixel driving circuit is in direct contact with the second conductive metal 143, and the driving substrate 20 has a third connecting portion 28 in direct contact with the second conductive metal 143, so that the conductive area of the drain electrode 27 is extended through the conductive metal in the second via hole. The first connecting portion 41 can be connected with the third connecting portion 28 through the first via hole 141, so as to realize the connection between the first connecting portion 41 and the pixel driving circuit. As shown in FIG. 1, the drain electrode 27 is in direct contact with the second conductive metal 143, the second conductive metal 143 is in direct contact with the conductive light shielding layer 50, the third connecting portion 28 is in direct contact with the conductive light shielding layer 50, the third connecting portion 28 is in direct contact with the first conductive metal in the first via hole 141, and the first conductive metal is also in direct contact with the first connecting portion 41, so as to realize the electrical connection between the first connecting portion 41 and the pixel driving circuit.

[0147] The conductive metal in the second via hole can be the same metal material as the drain electrode 27.

[0148] The orthographic projection of the third connecting portion 28 on the substrate 11 can cover the orthographic projection of the first connecting portion 41 on the substrate 11, or the orthographic projection of the third connecting portion 28 on the substrate 11 can be covered by the orthographic projection of the first connecting portion 41 on the substrate 11.

[0149] The second via hole can include a plurality of sub-via holes, for example, a first sub-via hole 131 located in the interlayer dielectric layer 13 and a second sub-via hole 132 located in the buffer layer 12. The first sub-via hole 131 and the second sub-via hole 132 have overlapping projections on the substrate 11. In order to prevent the second via hole from being etched to the active layer, the second via hole can avoid the active layer opening. Referring to FIG. 12, a cross-sectional structure of the second via hole is shown. As shown in FIG. 12, the distance from the bottom of the first sub-via hole 131 to the substrate 11 can be greater than the distance from the active layer close to the light emitting device 30 to the substrate 11. The second sub-via hole 132 can be away from the active layer opening. Thus, the first sub-via hole 131 and the second sub-via hole 132 can bypass the active layer opening.

[0150] As shown in FIG. 13, the conductive light shielding layer 50 can cover the light emitting device 30 and the first connection part 41. Specifically, the shape of the projection of the conductive light shielding layer 50 on the substrate 11 can be similar to the pattern formed between the first connection part 41, the light emitting device 30, and the second connection part 42.

[0151] In this embodiment, the conductive light shielding layer 50 can include a first area 51 and a second area 52. The first area 51 can be used to shield the thin film transistor, and the second area 52 can be located in a non-sub-pixel area. The second area 52 can be connected to the first area 51 or not. FIG. 12 shows the case where the first area 51 and the second area 52 are connected.

[0152] The projection of the conductive light shielding layer 50 on the substrate 11 covers the projection of a sub-pixel area on the substrate 11, and there is no overlap between the projections of the conductive light shielding layers 50 corresponding to different sub-pixel areas on the substrate 11, so as to avoid the connection between the conductive light shielding layers 50 of adjacent two sub-pixel areas and the problem of series connection of multiple sub-pixel areas. Specifically, in the case where a sub-pixel area includes a plurality of light emitting areas, and each light emitting area includes a light emitting device 30, the conductive light shielding layer 50 can cover multiple light emitting areas at the same time.

[0153] In combination with the above-described embodiments, the display panel further includes a planar layer 15. The planar layer 15 includes a plurality of planar areas. The projection of a planar area on the substrate 11 can cover the projections of adjacent two sub-pixel areas on the substrate 11. The projection of the conductive light shielding layer 50 on the substrate 11 can further overlap the projection of the planar layer 15 on the substrate 11.

[0154] In the embodiment, the first via hole 141 and the second via hole can have different shapes. For example, referring to FIG. 14, an enlarged schematic view of the rectangular region AA in FIG. 13 is shown. As shown in FIG. 14, the shapes of the normal projections of the first via hole 141 and the second via hole on the driving substrate 20 can be different. For example, the shape of the normal projection of the first via hole 141 on the driving substrate 20 can be an ellipse, and the shape of the normal projection of the second via hole on the driving substrate 20 can be a circle. In the case where the shape of the normal projection of the first via hole 141 on the driving substrate 20 is an ellipse, the current flowing from the second via hole to the area of the first via hole 141 can be enhanced, thereby improving the driving performance of the light emitting device 30.

[0155] In some embodiments, the normal projections of the first via hole 141 and the second via hole on the driving substrate 20 can have no overlap or can have overlap. As shown in FIG. 1, the case where the normal projections of the first via hole 141 and the second via hole on the driving substrate 20 have no overlap is shown.

[0156] In some examples, the normal projection of the second via hole on the driving substrate 20 can have overlap with the normal projection of the second connecting portion 42 on the driving substrate 20, and the normal projection of the first via hole 141 on the driving substrate 20 can have no overlap with the normal projection of the second connecting portion 42 on the driving substrate 20. Alternatively, in some cases, the normal projection of the first via hole 141 on the driving substrate 20 can also have overlap with the normal projection of the second connecting portion 42 on the driving substrate 20. Alternatively, the normal projection of the second via hole on the driving substrate 20 can have no overlap with the normal projection of the second connecting portion 42 on the driving substrate 20.

[0157] In some examples, as described above, the conductive light shielding layer 50 can include a first region 51 and a second region 52. The normal projection of the first region 51 on the driving substrate 20 covers the first electrode 31, and the normal projection of the second region 52 on the driving substrate 20 overlaps with the non-sub-pixel region. Accordingly, the conductive light shielding layer 50 further includes a third region 53 between the first region 51 and the second region 52. The normal projection of the third region 53 on the driving substrate 20 has no overlap with the normal projection of the second connecting portion 42 on the driving substrate 20.

[0158] In the embodiment, as shown in FIG. 13, the normal projection of the first region 51 on the driving substrate 20 covers the normal projection of the first electrode 31 on the driving substrate 20 and is covered by the normal projection of the planar layer 15 on the driving substrate 20. The normal projection of the second region 52 on the driving substrate 20 can cover the normal projection of the first connecting portion 41 on the driving substrate 20. The area of the second region 52 away from the driving substrate 20 is smaller than the area of the first region 51 away from the driving substrate 20, thereby reducing the area occupation of the light transmission region and enhancing the light transmission rate of the display panel.

[0159] As shown in FIG. 13, the first area 51 and the second area 52 can be connected through a third area 53, and the third area 53, the first area 51 and the second area 52 can be formed through a patterning process. Specifically, the third area 53 has no overlap with the orthographic projection of the second connection portion 42 on the driving substrate 20, so that the coupling capacitance between the third area 53 and the second connection portion 42 can be avoided.

[0160] In the embodiment, when the second connection portion 42 includes one first connection line 421, the line width of the first connection line 421 is smaller than the size of the first electrode 31 in the line width direction; when the second connection portion 42 includes a plurality of second connection lines 422, the second connection lines 422 have no overlap with the third area 53.

[0161] In some embodiments, the first electrode 31 can be formed by stacking a plurality of metal electrode layers to improve the electrical conductivity of the first electrode 31. Specifically, the first electrode 31 can include a plurality of metal electrode layers arranged in sequence along the thickness direction of the driving substrate 20; and the second connection portion 42 can be overlapped with at least one of the plurality of metal electrode layers.

[0162] In the embodiment, the first electrode 31 can include two or more metal electrode layers, and the orthographic projection of the metal electrode layer closest to the side of the driving substrate 20 can cover the orthographic projections of the other metal electrode layers on the driving substrate 20, and the orthographic projections of the other metal electrode layers on the driving substrate 20 can substantially coincide.

[0163] For example, as shown in FIG. 1, the first electrode 31 can include a first electrode layer 314, a second electrode layer 313, a third electrode layer 312 and a fourth electrode layer 311, the orthographic projection of the first electrode layer 314 on the driving substrate 20 can cover the orthographic projections of the second electrode layer 313, the third electrode layer 312 and the fourth electrode layer 311 on the driving substrate 20, and the orthographic projections of the second electrode layer 313, the third electrode layer 312 and the fourth electrode layer 311 on the driving substrate 20 can coincide.

[0164] Specifically, the second connection portion 42 can be directly in contact with the first electrode layer 314, and the second connection portion 42 can be overlapped on the side of the first electrode layer 314 away from the driving substrate 20. Alternatively, in some other examples, the second connection portion 42 can be directly in contact with the first electrode layer 314 and the second electrode layer 313 respectively, as shown in FIG. 15, which shows another cross-sectional structure diagram of the display panel. As shown in FIG. 15, the second connection portion 42 can be directly in contact with the first electrode layer 314 and the second electrode layer 313 respectively; or in some other examples, the second connection portion 42 can be directly in contact with the first electrode layer 314, the second electrode layer 313 and the third electrode layer 312.

[0165] Specifically, in the case that the second connecting portion 42 includes one first connecting line 421, it means that the first connecting portion 41 and the first electrode 31 are connected through a widened metal line, and since the line width of the first connecting line 421 is wider, the climbing ability of the first connecting line 421 is enhanced, so the first connecting line 421 can be in direct contact with the first electrode layer 314 and the second electrode layer 313 respectively, or in direct contact with the first electrode layer 314, the second electrode layer 313 and the third electrode layer.

[0166] In the case that the second connecting portion 42 includes a plurality of second connecting lines 422, it means that the first connecting portion 41 and the first electrode 31 are connected through a plurality of metal lines, and compared with the first connecting line 421, the climbing ability of the second connecting line 422 is weaker, so the second connecting line 422 can be in direct contact with the first electrode layer 314, or in direct contact with the first electrode layer 314 and the second electrode layer 313.

[0167] In the embodiment, in the case that the second connecting portion 42 is in contact with a plurality of metal electrode layers, since the second connecting portion 42 can be in contact with at least one metal electrode layer, the second connecting portion 42 and the first electrode 31 maintain good contact, thereby reducing the risk of disconnection between the first electrode 31 and the first connecting portion 41.

[0168] In an example of this embodiment, still referring to FIG. 1, the display panel can include a pixel defining layer 60, the pixel defining layer 60 including a plurality of openings, and the light emitting device 30 being located in the openings, wherein in the case that the second connecting portion 42 is in direct contact with only the first electrode layer 314, the orthographic projection of the second connecting portion 42 on the driving substrate 20 can be covered by the orthographic projection of the pixel defining layer 60 on the driving substrate 20, thereby the second connecting portion 42 can be protected by the pixel defining layer 60.

[0169] In the case that the first connecting portion 41 is in direct contact with the first electrode layer 314 and the second electrode layer 313, the orthographic projection of the first connecting portion 41 on the driving substrate 20 can also be covered by the orthographic projection of the pixel defining layer 60 on the driving substrate 20, thereby realizing the insulation between the first connecting portion 41 and the second electrode 32, and avoiding the short circuit between the second electrode 32 and the first connecting portion 41.

[0170] Of course, in the case that the second connecting portion 42 is in direct contact with a plurality of metal electrode layers, the partial outer contour of the orthographic projection of the second connecting portion 42 on the substrate 11 can coincide with the partial outer contour of the orthographic projection of the pixel defining layer 60 on the driving substrate 20, as shown in FIG. 15.

[0171] In some other embodiments, because the second electrode 32 is thinner, its resistance is larger and its voltage drop is larger, resulting in a larger difference in current between the sub-pixels in the central and edge regions of the display panel. In practice, an auxiliary electrode structure can be provided for the second electrode 32. Referring to FIG16, a cross-sectional structural schematic diagram of another display panel is shown. As shown in FIG16, the display panel also includes an auxiliary structure 70, wherein the second electrode 32 and the light-emitting layer 33 are both disconnected at the position of the auxiliary structure 70, and the second electrode 32 is in direct contact with the auxiliary structure 70 to realize the electrical connection between the second electrode 32 and the auxiliary structure 70.

[0172] Specifically, the auxiliary structure 70 may include a plurality of metal layers sequentially disposed in the thickness direction of the driving substrate 20. The cross-sectional structure of the plurality of metal layers in the thickness direction of the driving substrate 20 may be an "I" shape, and there is a high step difference between the auxiliary structure 70 and the driving substrate 20, causing the light-emitting layer 33 and the second electrode 32 to break at the auxiliary structure 70, thereby isolating the second electrode 32 and the light-emitting layer 33 at the auxiliary structure 70. Thus, the light-emitting layer 33 and the second electrode 32 are also sequentially stacked on the side of the auxiliary structure 70 facing away from the driving substrate 20.

[0173] As shown in Figure 16, for example, the auxiliary structure 70 may include a first metal layer 71, a second metal layer 72, a third metal layer 73, a fourth metal layer 74, a fifth metal layer 75, and a sixth metal layer 76 sequentially disposed in the thickness direction of the driving substrate 20. The first metal layer is disposed on the same layer as the drain electrode 27 of the pixel driving circuit. The outer contours of the orthographic projections of the fourth and fifth metal layers onto the driving substrate 20 are located within the outer contours of the orthographic projections of the third metal layer onto the driving substrate 20, and also within the outer contours of the orthographic projections of the sixth metal layer onto the driving substrate 20. The second metal layer is formed within a third via formed in the passivation layer 14; the third via is not shown in Figure 16.

[0174] In this embodiment, the auxiliary structure 70 can be located in a non-sub-pixel area. Furthermore, there is no overlap between the auxiliary structure 70 and the first connection portion 41, nor between the auxiliary structure 70 and the pixel driving circuit. In practice, one auxiliary structure 70 can be simultaneously connected to the second electrode 32 of a row of light-emitting devices 30, or one auxiliary structure 70 can be connected to the second electrode 32 of a single light-emitting device 30. Thus, the second electrodes 32 of multiple light-emitting devices 30 can be respectively connected to multiple auxiliary structures 70.

[0175] In this embodiment, since the auxiliary structure 70 is electrically connected to the second electrode 32, the resistance of the second electrode 32 is reduced, the voltage drop is reduced, the current difference between the sub-pixels in the center and edge areas of the display panel is reduced, and the uniformity of the display brightness of the display panel is improved.

[0176] In the following, the display panel of the present disclosure is exemplarily described in combination with several specific examples.

[0177] Example 1, please refer to FIG. 16 and FIG. 13, the display panel in the embodiment includes:

[0178] The driving substrate 20 includes a pixel driving circuit, the driving substrate 20 includes a substrate 11, a conductive light shielding layer 50 located on one side of the substrate 11, a buffer layer 12 located on one side of the conductive light shielding layer 50, an active layer located on the side of the buffer layer 12 away from the substrate 11, a gate insulating layer 24 located on the side of the active layer away from the substrate, a gate layer 23 located on the side of the gate insulating layer 24 away from the substrate, and an interlayer dielectric layer 13 located on the side of the gate layer 23 away from the substrate 11, a source electrode 22 and a drain electrode 27 located on the side of the interlayer dielectric layer 13 away from the substrate 11.

[0179] Wherein, the driving substrate 20 further includes a passivation layer 14 on one side, a first via hole 141 is formed on the passivation layer 14, a first sub via hole 131 is formed on the interlayer dielectric layer 13, a second sub via hole 132 is formed on the buffer layer 12, the orthographic projection of the first sub via hole 131 on the substrate 11 covers the orthographic projection of the second sub via hole 132 on the substrate 11, the first sub via hole 131 and the second sub via hole 132 constitute a second via hole, a first conductive metal is formed in the first via hole 141, and a second conductive metal 143 is formed in the second via hole;

[0180] Wherein, the passivation layer 14 further includes a planarization layer 15 on the side away from the driving substrate 20, the planarization layer 15 is located in the sub-pixel area and can not overlap with the non-sub-pixel area;

[0181] The light emitting device 30 is located on the side of the planarization layer 15 away from the driving substrate 20, and the orthographic projection of the light emitting device 30 on the substrate 11 is covered by the planarization layer 15, the light emitting device 30 includes a first electrode 31, a light emitting layer 33 and a second electrode 32 arranged in the thickness direction of the driving substrate 20 in turn;

[0182] The first connecting part 41 is located in the non-sub-pixel area;

[0183] The second connecting part 42 is electrically connected with the first connecting part 41 and the first electrode 31 respectively;

[0184] Wherein, the second connecting part 42 includes a first connecting line 421, the line width of the first connecting line 421 is uniform, and the line width can be greater than 3 / 5 of the size of the first electrode 31 in the line width direction and less than the size of the first electrode 31 in the line width direction.

[0185] The second conductive metal 143 is electrically connected with the conductive light-shielding layer 50, the second conductive metal 143 is connected with the third connecting part 28, the third connecting part 28 is electrically connected with the first conductive metal, the first conductive metal is connected with the first connecting part 41, the first connecting part 41 is connected with the second connecting part 42, the second connecting part 42 is electrically connected with the first electrode 31, and specifically, the first connecting line 421 directly contacts the first electrode layer 314 in the first electrode 31.

[0186] The conductive light-shielding layer 50 includes a first area 51, a second area 52, and a third area 53 connecting the first area 51 and the second area 52, the first area 51 covers a sub-pixel area in the orthographic projection of the substrate 11, and there is no overlap between the first areas 51 corresponding to different sub-pixel areas; the second area 52 covers the first connecting part 41 in the orthographic projection of the substrate 11, and the third area 53 has no overlap with the first connecting line 421 in the orthographic projection of the substrate 11.

[0187] The one sub-pixel area includes two light-emitting areas, the first electrodes 31 in the two light-emitting areas are not overlapped, and are connected to the same first connecting part 41 through the respective first connecting lines 421.

[0188] In addition, the auxiliary structure 70 is located in the non-sub-pixel area, the auxiliary structure 70 includes a first metal layer, a second metal layer, a third metal layer, a fourth metal layer, a fifth metal layer, and a sixth metal layer arranged in the thickness direction of the driving substrate 20 in sequence, the light-emitting layer 33 and the second electrode 32 are disconnected at the auxiliary structure 70, and the second electrode 32 is electrically connected with the auxiliary structure 70 to reduce the resistance of the second electrode 32.

[0189] In example 2, referring to FIGS. 16 and 17, the display panel in the embodiment is different from example 1 in that the second connecting part 42 includes a plurality of second connecting lines 422, and the line widths of the second connecting lines 422 are uniform.

[0190] Based on the same inventive concept, the display device can include the display panel in the above embodiments. The display device can be a transparent display device.

[0191] Each of the embodiments in the specification is described in a progressive manner, and each embodiment focuses on the difference from other embodiments. The same and similar parts of each embodiment can be referred to each other.

[0192] Finally, it should be noted that the terms "first" and "second", and the like, herein do not denote any order, quantity, combination or importance, but are used to identify one element from another, and do not imply referring to a certain number or a certain order. Also, the terms "comprises", "comprising", or any other variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but can include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by an indefinite article "a" or "an" does not exclude the existence of additional identical elements in the process, method, article, or apparatus that includes the element.

[0193] The above describes in detail a display panel and a display device provided by the present disclosure. The principles and implementation manners of the present disclosure are described by using specific examples. The above description of the embodiments is only used to help understand the method of the present disclosure and its core idea. Meanwhile, for those skilled in the art, according to the idea of the present disclosure, the specific implementation manners and application ranges can be changed. In summary, the content of the present description should not be understood as a limitation of the present disclosure.

[0194] Other embodiments of the present disclosure will be apparent to those skilled in the art upon consideration of the specification and practice of the present disclosure disclosed. The present disclosure is intended to cover any variations, uses, or adaptations of the present disclosure following, in general, the principles of the present disclosure and including such departures from the present disclosure that come within known or customary practice within the art to which the present disclosure pertains. The specification and examples are to be considered exemplary only, with the true scope and spirit of the present disclosure being indicated by the following claims.

[0195] It should be understood that the present disclosure is not limited to the precise construction that has been described and shown in the accompanying drawings, and that various modifications and changes can be effected therein by those skilled in the art without departing from the scope of the present disclosure. The scope of the present disclosure is limited only by the claims that follow.

[0196] As used herein, the term "one embodiment", "an embodiment", or "one or more embodiments" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the disclosure. The appearances of the phrase "in one embodiment" in various places in the specification are not necessarily all referring to the same embodiment.

[0197] In the description provided herein, numerous specific details are set forth. However, it is understood that embodiments of the disclosure can be practiced without these specific details. In some instances, well-known methods, structures and techniques have not been described in detail in order not to obscure the understanding of this description.

[0198] In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The word comprising does not exclude the presence of elements or steps other than those listed in a claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. The disclosure can be implemented by means of both hardware and software, and any combination thereof. In a unitary claim, several devices, apparatuses or means can be listed having the same reference numerals and can thus constitute means for performing the same function, even if they are not explicitly mentioned as such. The use of the terms first, second and third, etc. does not imply any ordering, but rather are used for naming purposes only. Features, steps or elements of the various aspects described herein can be combined and / or eliminated to produce suitable combinations and / or subcombinations and the disclosure should be construed to cover any such suitable combinations and / or subcombinations.

[0199] Finally, it should be noted that the above-mentioned embodiments are merely intended for describing and illustrating, not limiting, the technical solutions of the present disclosure; even though the present disclosure has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacements for some technical features therein; and such modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present disclosure.

Claims

1. A display panel, characterized by, The sub-pixel region and the non-sub-pixel region are included, and The driving substrate includes a pixel driving circuit, and further includes The light emitting device is located in the sub-pixel region and includes a first electrode, a light emitting layer and a second electrode arranged in the thickness direction of the driving substrate in sequence; The first connecting part is located in the non-sub-pixel region and is overlapped with the pixel driving circuit; The second connecting part is electrically connected with the first connecting part and the first electrode respectively; The second connecting part includes a first connecting line and / or a plurality of parallel second connecting lines, and the maximum line width of the first connecting line is greater than the maximum line width of the second connecting line.

2. The display panel of claim 1, wherein, The size of the orthographic projection of the second connecting part on the driving substrate in the target direction is greater than or equal to 1 / 5 of the size of the orthographic projection of the first electrode on the driving substrate in the target direction. The target direction is orthogonal to the connection direction of the first connecting part and the first electrode.

3. The display panel of claim 1, wherein, The second connecting part includes a first connecting line, and the ratio of the maximum line width of the first connecting line to the size of the first electrode in the line width direction is 0.2-1.

4. The display panel of claim 1, wherein, There is a step difference between the first connecting part and the first electrode, and the second connecting part includes the first connecting line or a plurality of second connecting lines at least in the region where the step difference is located.

5. The display panel of claim 4, wherein, The display panel further includes The flat layer is located on the side of the driving substrate close to the light emitting device; the orthographic projection of the flat layer on the driving substrate covers the orthographic projection of the first electrode on the driving substrate, and does not overlap with the orthographic projection of the first connecting part on the driving substrate, so that the step difference exists between the first electrode and the first connecting part; The orthographic projection of the first connecting line or the plurality of second connecting lines on the driving substrate overlaps with the orthographic projection of the flat layer on the driving substrate.

6. The display panel of any of claims 1-5, wherein, The second connecting part includes a first connecting line and a plurality of second connecting lines; The plurality of second connecting lines are respectively connected with the first connecting line and the first electrode, or the first connecting line is respectively connected with the plurality of second connecting lines and the first electrode.

7. The display panel of claim 4, wherein, The second connecting part includes a plurality of second connecting lines, and the second connecting line includes a first sub-connecting line and a second sub-connecting line connected in sequence, the second sub-connecting line is located in the region where the step difference is located, and the line width of the second sub-connecting line is greater than the line width of the first sub-connecting line.

8. The display panel of claim 4, wherein, The second connecting part includes a first connecting line, and the first connecting line includes a third sub-connecting line connected with the first connecting part and a fourth sub-connecting line connected between the third sub-connecting line and the first electrode; The fourth sub-connecting line is located in the region where the step difference is located, and the line width of the fourth sub-connecting line is greater than the line width of the third sub-connecting line.

9. The display panel of claim 8, wherein, The ratio of the line width of the fourth sub-connecting line to the size of the first electrode in the line width direction is 0.8-1.

10. The display panel of claim 1, wherein, The sub-pixel region includes a plurality of light emitting regions, and the plurality of light emitting regions correspond to the plurality of light emitting devices respectively. The first electrodes of different light emitting devices in the same sub-pixel region are connected to the same first connecting part through different second connecting parts.

11. The display panel of claim 1, wherein, The display panel further comprises: a planar layer on the side of the driving substrate close to the light emitting device, comprising a plurality of spaced planar regions; wherein the orthographic projection of each planar region on the driving substrate covers the orthographic projection of the first electrodes in the two adjacent sub-pixel regions on the driving substrate, and does not overlap with the orthographic projection of the first connecting part on the driving substrate.

12. The display panel of claim 1, wherein, The first electrode comprises a plurality of metal electrode layers arranged in sequence along the thickness direction of the driving substrate. The second connecting part overlaps with at least one of the plurality of metal electrode layers.

13. The display panel of claim 1, wherein, The display panel further comprises: a passivation layer laminated between the driving substrate and the light emitting device, the orthographic projection of the passivation layer on the driving substrate covering the sub-pixel regions and the non-sub-pixel regions; wherein a first via hole is formed on the passivation layer, and the first connecting part overlaps with the pixel driving circuit through the first via hole.

14. The display panel of claim 13, wherein, The display panel further comprises: a buffer layer on the side of the driving substrate away from the light emitting device; a conductive light shielding layer on the side of the buffer layer away from the light emitting device, the orthographic projection of the conductive light shielding layer on the driving substrate covering the orthographic projection of the first electrode on the driving substrate, and overlapping with the orthographic projection of the first connecting part on the driving substrate; and a third connecting part arranged on the side of the driving substrate close to the light emitting device; wherein a second via hole is further formed on the buffer layer, and the pixel driving circuit and the third connecting part are electrically connected through the conductive light shielding layer in the second via hole, and the first connecting part is connected to the third connecting part through the first via hole.

15. The display panel of claim 13, wherein, The shape of the orthographic projection of the first via hole on the driving substrate is different from the shape of the orthographic projection of the second via hole on the driving substrate.

16. The display panel of claim 13, wherein, The conductive light shielding layer comprises a first region and a second region, the orthographic projection of the first region on the driving substrate covering the first electrode, and the orthographic projection of the second region on the driving substrate overlapping with the non-sub-pixel region; The conductive light shielding layer further comprises a third region between the first region and the second region; wherein the orthographic projection of the third region on the driving substrate does not overlap with the orthographic projection of the second connecting part on the driving substrate.

17. A display device comprising: The display panel comprises any one of claims 1-16.

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