Semiconductor thin film structure

Abstract

This semiconductor thin film structure comprises an Si layer (102) formed on an insulating layer (101), and a semiconductor layer (103). The Si layer (102) is composed of monocrystalline Si, and the planar orientation of the main surface is (110). The semiconductor layer (103) is composed of a group III-V compound semiconductor. The semiconductor layer (103) is grown through crystallization in a direction parallel to the surface of the insulating layer (101) from a side surface (104) of the Si layer (102). The side surface (104) can be a (-111) plane extending in the [1-12] direction of the Si layer (102). The side surface (104) can also be a (1-11) plane extending in the [1-1-2] direction of the Si layer (102).

Description

Semiconductor Thin Film Structure

[0001] The present invention relates to semiconductor thin film structures.

[0002] As a technology to realize miniaturization, low power consumption, and low cost of optical transceivers, attention is being paid to the technology of integrating passive elements such as Si waveguides with active elements such as lasers, photodetectors, and modulators on Si substrates, which can be made large-diameter at low cost. Until now, mature Si microfabrication technology has already realized the technology to monolithically integrate small, low-loss Si optical waveguide elements, photodetectors, modulators, etc. on large-diameter Si substrates.

[0003] Regarding the integration of lasers on Si substrates, it has been difficult to fabricate lasers using indirect transition semiconductors such as Si and Ge, which have been used in conventional silicon platforms, and there has been a problem in that a different material, a direct transition semiconductor such as a III-V compound semiconductor, must be integrated. However, a thin-film structure laser integration has been realized, as shown in Non-Patent Document 1. In this structure, the thickness of the III-V compound semiconductor layer on Si is typically set to 350 nm or less so that it does not exceed the critical thickness. In this case, the effective refractive index of the III-V compound semiconductor layer is roughly matched to the effective refractive index of a 220 nm thick Si waveguide commonly used in the field of silicon photonics, which has the advantage of facilitating optical coupling between the III-V compound semiconductor layer and the Si waveguide.

[0004] The above-mentioned Si waveguide-coupled thin-film laser integration has been realized using so-called heterogeneous integration techniques, such as direct bonding and transfer printing. However, unlike monolithic integration, heterogeneous integration processes such as direct bonding require expensive, small-sized III-V compound semiconductor substrates, which create bottlenecks in material costs and throughput. To resolve these bottlenecks, the realization of monolithic integration of high-performance thin-film semiconductor laser structures, as shown in Non-Patent Document 1, is desired.

[0005] On the other hand, because Si and III-V compound semiconductors have different lattice constants and thermal expansion coefficients, it is generally difficult to monolithically integrate high-quality III-V compound semiconductors on Si. One solution to this problem is to insert a thick buffer layer of several micrometers on Si. However, the presence of this buffer layer has the fatal drawback of making it difficult to optically couple the active layer to the Si optical circuit layer. Therefore, it is necessary to integrate high-quality III-V compound semiconductors on a thin-film buffer or without a buffer. As a solution to this problem, the lateral aspect ratio trapping (ART) growth method on the {111} plane of silicon has recently attracted attention (Non-Patent Document 2).

[0006] This technology forms a hollow structure surrounded by a top selective growth mask, a bottom BOX layer of an SOI (silicon-on-insulator) substrate, and side Si{111} planes. Lateral selective growth of III-V compound semiconductors is then performed starting from the Si{111} planes. Growth starting from the Si{111} planes, which forms a double-step structure, suppresses anti-phase boundaries (APBs). Lateral selective growth in a trench structure with a longer horizontal width (w) than the vertical width (h) of the hollow structure is expected to terminate threading dislocations generated at the Si / III-V compound semiconductor interface onto the top and bottom selective growth masks. This technology enables the integration of III-V compound semiconductor crystals free of APBs and threading dislocations via an ultrathin buffer layer that is essentially bufferless. This may also enable the integration of III-V optical devices fabricated using this structure with Si optical circuit layers.

[0007] Fabrication techniques based on this technology have been used to demonstrate Si waveguide-coupled photodiodes (PDs) (Non-Patent Document 3) and optically injected distributed feedback (DFB) lasers (Non-Patent Document 4). However, current injection lasers have yet to be demonstrated. To achieve this, efforts are needed to improve this technology and further increase the quality and yield of III-V compound semiconductor crystal integration.

[0008] Furthermore, although the background to the above has been explained with application to optical devices in mind, this technology can also be applied to the monolithic integration on Si of electronic devices such as transistors that utilize heterojunctions made of III-V compound semiconductors.

[0009] T. Aihara, T. Hiraki, T. Fujii, K. Takeda, T. Kakitsuka, T. Tsuchizawa, and S. Matsuo, "Membrane III-V / Si DFB Laser Using Uniform Grating and Width-Modulated Si Waveguide," J. Lightwave Technol. 38, 2961-2967 , 2020.Yu Han, Ying Xue, Kei May Lau; Selective lateral epitaxy of dislocation-free InP on silicon-on-insulator. Appl. Phys. Lett. 13 May 2019.P. Wen, P. Tiwari, S. Mauthe, H. Schmid, M. Sousa, M. Scherrer, M. Baumann, B.I. Bitachon, J. Leuthold, B. Gotsmann, K.E. Moselund, “Waveguide coupled III-V photodiodes monolithically integrated on Si,” Nature Communications, 13(1), pp.1-11, 2022.Y. Xue, J. Li, Y. Wang, K. Xu, Z. Xing, K. S. Wong, H. K. Tsang, K. M. Lau, In-Plane 1.5 μm Distributed Feedback Lasers Selectively Grown on (001) SOI. Laser Photonics Rev 2024, 18, 2300549.J. Li et al., "III-V selective regrowth on SOI for telecom lasers in silicon photonics", Journal of Applied Physics, vol. 133, no. 13, 133103, 2023.D. V. Dorp et al., "Epitaxial Defects in Nanoscale InP Fin Structures Revealed by Wet-Chemical Etching", Crystals, vol. 7, no. 4, 98, 2017.

[0010] 15 , the Si layer 302 between the upper selective growth mask 321 and the lower BOX layer 301 of the SOI substrate 311 is side-etched to form a space between the selective growth mask 321 and the BOX layer 301, and the side surface of the Si layer 302 is formed in the space. When a lateral aspect ratio trap is applied to the Si{111} plane in this way, when a substrate is fabricated, as shown in Non-Patent Document 5, the side surface of the Si layer 302 formed by side etching tends to have a "<" shape in a cross section composed of the (111) plane and the (11-1) plane.

[0011] In Si, which is a crystal with a diamond structure, the (111) plane and the (11-1) plane are equivalent planes, and the relationship between these two planes with respect to the [-1-10] direction, which is the side etching direction of the Si layer whose surface is the {111} plane, is symmetrical, resulting in the above-mentioned state. Also, as shown in Non-Patent Document 6, when a III-V group compound semiconductor is grown on the Si {111} plane, the {111}B plane becomes the front facet.

[0012] Considering the two facts mentioned above, the III-V compound semiconductor microcrystals grown from the Si (111) plane and the (11-1) plane have polarities in an antiphase relationship, and nuclei of III-V compound semiconductor microcrystals are formed at different locations on the surface of the Si seed crystal. When these nuclei coalesce, an antiphase boundary (APB) is formed at the interface (FIG. 16). As a result, the crystalline quality of the grown III-V compound semiconductor is significantly degraded, making it very difficult to apply it to devices.

[0013] 17 shows an electron microscope image of the III-V / Si interface of a III-V group compound semiconductor grown using a substrate with a Si surface consisting of (111) and (11-1) planes. The above-mentioned hypothesis that anti-phase InP microcrystals grow from the Si surface consisting of (111) and (11-1) planes and that APB occurs at this interface was actually verified.

[0014] The present invention has been made to solve the above problems, and has as its object to suppress the occurrence of antiphase boundaries at the interface between the Si surface and the III-V group compound semiconductor.

[0015] The semiconductor thin film structure according to the present invention includes a Si layer formed on an insulating layer and made of single-crystal Si with a (110) plane orientation on a main surface, and a semiconductor layer made of a III-V compound semiconductor crystal-grown in a direction parallel to the surface of the insulating layer from either a side surface of the Si layer that is a (-111) plane extending in the [1-1-2] direction or a side surface of the Si layer that is a (1-11) plane extending in the [1-1-2] direction.

[0016] The semiconductor thin film structure according to the present invention includes: a Si layer formed on an insulating layer and made of single-crystal Si with a (111) plane orientation on a main surface; and a semiconductor layer made of a III-V compound semiconductor crystal-grown in a direction parallel to the surface of the insulating layer from any one of a side surface of the Si layer that is a (-111) plane extending in the [0-11] direction, a side surface of the Si layer that is a (1-11) plane extending in the [10-1] direction, and a side surface of the Si layer that is a (11-1) plane extending in the [-110] direction.

[0017] As described above, according to the present invention, a semiconductor layer made of a III-V compound semiconductor is provided, which is crystal-grown from either a side surface of a Si layer having a (110) plane orientation on its main surface, the side surface being a (-111) plane extending in the [1-12] direction, or a side surface of the Si layer being a (1-11) plane extending in the [1-1-2] direction, thereby making it possible to suppress the generation of antiphase boundaries at the interface between the Si surface and the III-V compound semiconductor.

[0018] FIG. 1 is a cross-sectional view (a) and a plan view (b) showing the configuration of a semiconductor thin film structure according to a first embodiment of the present invention. FIG. 2A is a cross-sectional view (a) and a plan view (b) showing the state of a laser in an intermediate process for explaining a manufacturing method of a semiconductor thin film structure according to a first embodiment of the present invention. FIG. 2B is a cross-sectional view (a) and a plan view (b) showing the state of a laser in an intermediate process for explaining a manufacturing method of a semiconductor thin film structure according to a first embodiment of the present invention. FIG. 2C is a cross-sectional view (a) and a plan view (b) showing the state of a laser in an intermediate process for explaining a manufacturing method of a semiconductor thin film structure according to a first embodiment of the present invention. FIG. 2D is a cross-sectional view (a) and a plan view (b) showing the state of a laser in an intermediate process for explaining a manufacturing method of a semiconductor thin film structure according to a first embodiment of the present invention. FIG. 2E is a cross-sectional view (a) and a plan view (b) showing the state of a laser in an intermediate process for explaining a manufacturing method of a semiconductor thin film structure according to a first embodiment of the present invention. FIG. 2F is a cross-sectional view (a) and a plan view (b) showing the state of a laser in an intermediate process for explaining a manufacturing method of a laser using a semiconductor thin film structure according to a first embodiment of the present invention. FIG. 2G is a cross-sectional view (a) and a plan view (b) illustrating a laser in an intermediate process for explaining a method for manufacturing a laser using the semiconductor thin film structure according to the first embodiment of the present invention. FIG. 2H is a cross-sectional view (a) and a plan view (b) illustrating a laser in an intermediate process for explaining a method for manufacturing a laser using the semiconductor thin film structure according to the first embodiment of the present invention. FIG. 2I is a cross-sectional view (a) and a plan view (b) illustrating a laser in an intermediate process for explaining a method for manufacturing a laser using the semiconductor thin film structure according to the first embodiment of the present invention. FIG. 2J is a cross-sectional view (a) and a plan view (b) illustrating a laser in an intermediate process for explaining a method for manufacturing a laser using the semiconductor thin film structure according to the first embodiment of the present invention. FIG. 2K is a cross-sectional view (a) and a plan view (b) illustrating a laser in an intermediate process for explaining a method for manufacturing a laser using the semiconductor thin film structure according to the first embodiment of the present invention. FIG. 2L is a cross-sectional view (a) and a plan view (b) illustrating a laser in an intermediate process for explaining a method for manufacturing a laser using the semiconductor thin film structure according to the first embodiment of the present invention. FIG. 3 is a cross-sectional view showing the configuration of a laser fabricated using the semiconductor thin film structure according to the first embodiment of the present invention.FIG. 4 is a plan view showing the configuration of a laser fabricated using the semiconductor thin film structure according to the first embodiment of the present invention. FIG. 5A is a cross-sectional view (a) and a plan view (b) showing the state of a laser in an intermediate process for explaining a method for manufacturing another laser using the semiconductor thin film structure according to the first embodiment of the present invention. FIG. 5B is a cross-sectional view (a) and a plan view (b) showing the state of a laser in an intermediate process for explaining a method for manufacturing another laser using the semiconductor thin film structure according to the first embodiment of the present invention. FIG. 5C is a cross-sectional view (a) and a plan view (b) showing the state of a laser in an intermediate process for explaining a method for manufacturing another laser using the semiconductor thin film structure according to the first embodiment of the present invention. FIG. 5D is a cross-sectional view (a) and a plan view (b) showing the state of a laser in an intermediate process for explaining a method for manufacturing another laser using the semiconductor thin film structure according to the first embodiment of the present invention. FIG. 6 is a cross-sectional view showing the configuration of another laser fabricated using the semiconductor thin film structure according to the first embodiment of the present invention. FIG. 7 is a plan view showing the configuration of another laser fabricated using the semiconductor thin film structure according to the first embodiment of the present invention. FIG. 8 is a cross-sectional view (a) and a plan view (b) showing the configuration of a semiconductor thin film structure according to a second embodiment of the present invention. FIG. 9A is a cross-sectional view (a) and a plan view (b) showing the state of a laser in an intermediate process for explaining a method for manufacturing a semiconductor thin film structure according to the second embodiment of the present invention. FIG. 9B is a cross-sectional view (a) and a plan view (b) showing the state of a laser in an intermediate process for explaining a method for manufacturing a semiconductor thin film structure according to the second embodiment of the present invention. FIG. 9C is a cross-sectional view (a) and a plan view (b) showing the state of a laser in an intermediate process for explaining a method for manufacturing a semiconductor thin film structure according to the second embodiment of the present invention. FIG. 9D is a cross-sectional view (a) and a plan view (b) showing the state of a laser in an intermediate process for explaining a method for manufacturing a semiconductor thin film structure according to the second embodiment of the present invention. FIG. 9E is a cross-sectional view (a) and a plan view (b) showing the state of a laser in an intermediate process for explaining a method for manufacturing a semiconductor thin film structure according to the second embodiment of the present invention. FIG. 9F is a cross-sectional view (a) and a plan view (b) showing the state of a laser in an intermediate process for explaining a method for manufacturing a laser using the semiconductor thin film structure according to the second embodiment of the present invention.FIG. 9G is a cross-sectional view (a) and a plan view (b) illustrating a laser in an intermediate process for explaining a method for manufacturing a laser using the semiconductor thin film structure according to the second embodiment of the present invention. FIG. 9H is a cross-sectional view (a) and a plan view (b) illustrating a laser in an intermediate process for explaining a method for manufacturing a laser using the semiconductor thin film structure according to the second embodiment of the present invention. FIG. 9I is a cross-sectional view (a) and a plan view (b) illustrating a laser in an intermediate process for explaining a method for manufacturing a laser using the semiconductor thin film structure according to the second embodiment of the present invention. FIG. 9J is a cross-sectional view (a) and a plan view (b) illustrating a laser in an intermediate process for explaining a method for manufacturing a laser using the semiconductor thin film structure according to the second embodiment of the present invention. FIG. 9K is a cross-sectional view (a) and a plan view (b) illustrating a laser in an intermediate process for explaining a method for manufacturing a laser using the semiconductor thin film structure according to the second embodiment of the present invention. FIG. 9L is a cross-sectional view (a) and a plan view (b) illustrating a laser in an intermediate process for explaining a method for manufacturing a laser using the semiconductor thin film structure according to the second embodiment of the present invention. FIG. 10 is a cross-sectional view showing the configuration of a laser fabricated using the semiconductor thin film structure according to the second embodiment of the present invention. FIG. 11 is a plan view showing the configuration of a laser fabricated using the semiconductor thin film structure according to the second embodiment of the present invention. FIG. 12A is a cross-sectional view (a) and a plan view (b) showing the state of a laser in an intermediate process for explaining a method for manufacturing another laser using the semiconductor thin film structure according to the second embodiment of the present invention. FIG. 12B is a cross-sectional view (a) and a plan view (b) showing the state of a laser in an intermediate process for explaining a method for manufacturing another laser using the semiconductor thin film structure according to the second embodiment of the present invention. FIG. 12C is a cross-sectional view (a) and a plan view (b) showing the state of a laser in an intermediate process for explaining a method for manufacturing another laser using the semiconductor thin film structure according to the second embodiment of the present invention. FIG. 12D is a cross-sectional view (a) and a plan view (b) showing the state of a laser in an intermediate process for explaining a method for manufacturing another laser using the semiconductor thin film structure according to the second embodiment of the present invention. FIG. 13 is a cross-sectional view showing the configuration of a laser fabricated using the semiconductor thin film structure according to the second embodiment of the present invention. FIG. 14 is a plan view showing the configuration of a laser fabricated using the semiconductor thin film structure according to the second embodiment of the present invention.Fig. 15 is a cross-sectional view showing a cross section of a conventional semiconductor thin film structure. Fig. 16 is an explanatory diagram illustrating the state in which an antiphase boundary (APB) is formed at the interface between a Si seed crystal and a III-V group compound semiconductor. Fig. 17 is an electron microscope image of the vicinity of the III-V / Si interface of a III-V group compound semiconductor grown using a substrate whose Si surface is composed of the (111) plane and the (11-1) plane.

[0019] A semiconductor thin film structure according to an embodiment of the present invention will be described below.

[0020] First Embodiment First, a semiconductor thin film structure according to a first embodiment of the present invention will be described with reference to Fig. 1. This semiconductor thin film structure includes a Si layer 102 formed on an insulating layer 101, and a semiconductor layer 103.

[0021] The Si layer 102 is made of single-crystal Si, and the plane orientation of the main surface is (110). The semiconductor layer 103 is made of a III-V compound semiconductor. The semiconductor layer 103 undergoes crystal growth from a side surface 104 of the Si layer 102 in a direction parallel to the surface of the insulating layer 101. The side surface 104 may be a single {111} plane extending in the [1-12] direction of the Si layer 102. The side surface 104 may be a single {111} plane extending in the [1-1-2] direction of the Si layer 102.

[0022] For example, by using a well-known SOI substrate, it is possible to form the side surface 104 on the Si layer 102, which is made up only of the (-111) plane of the Si layer 102. Also, by using an SOI substrate, it is possible to form the side surface 104 on the Si layer 102, which is made up only of the (1-11) plane of the Si layer 102.

[0023] Next, a method for manufacturing a semiconductor thin film structure according to the first embodiment and a method for manufacturing a laser using the semiconductor thin film structure will be described with reference to Figures 2A to 2L. In Figures 2A to 2L, (a) shows a cross section taken along line aa' in the plan view shown in (b).

[0024] 2A, an SOI substrate is prepared that includes an insulating layer 101 as a buried insulating layer and an Si layer 102 as a surface Si layer on a base portion 111. Furthermore, the Si layer 102 is formed into a rectangular pattern with its long sides oriented in the [1-12] direction or the [1-1-2] direction in a plan view seen from the normal direction to the surface of the insulating layer 101.

[0025] Next, as shown in FIG. 2B , an upper insulating layer 121 is formed on the Si layer 102 as a selective growth mask. The upper insulating layer 121 is formed to extend laterally along the side surfaces of the insulating layer 101 in a direction parallel to the surface of the insulating layer 101. The upper insulating layer 121 is formed to cover the Si layer 102. Next, as shown in FIG. 2C , an opening 121a is formed in the upper insulating layer 121. The opening 121a is formed so that one long side of the Si layer 102 is exposed and the surface of the insulating layer 101 is exposed. Here, the opening 121a is formed to have a rectangular shape when viewed from the normal direction to the plane of the insulating layer 101. Furthermore, the opening 121a is formed so that the long side of the rectangle is oriented in the [1-12] direction or the [1-1-2] direction. The opening width of the opening 121a in the long side direction can be, for example, approximately the resonator length of the laser to be formed, e.g., 50 μm.

[0026] The Si layer 102 is etched (side-etched) through the opening 121a formed in this manner using an anisotropic Si etchant, thereby forming a space 121b between the insulating layer 101 and the upper insulating layer 121, as shown in FIG. 2D , and a side surface 104 of the Si layer 102 that is a single {111} plane. The angle between the surface of the insulating layer 101, which is parallel to the main surface of the Si layer 102 that has a plane orientation of (110), and the side surface 104 of the Si layer 102 that is the (-111) plane, is perpendicular. Similarly, the angle between the surface of the insulating layer 101 and the side surface 104 of the Si layer 102 that is the (1-11) plane is perpendicular. The depth of the space 121b to the location where the side surface 104 is formed can be, for example, about 10 μm.

[0027] 2E, a semiconductor layer 103 made of a III-V compound semiconductor is grown laterally starting from the side surface 104. The semiconductor layer 103 may be made of, for example, InP.

[0028] The Si layer 102 has a (110) plane orientation on its main surface, and the side surface 104 of the Si layer 102 is composed of a single {111} plane. Therefore, the polarities of the III-V compound semiconductor microcrystal nuclei generated anywhere on the side surface 104 of the Si layer 102 are all in the same phase. As a result, no anti-phase boundary (APB) is generated at the interface of the III-V compound semiconductor microcrystals, and high-quality III-V compound semiconductor can be grown.

[0029] The lower surface of the upper insulating layer 121 on the insulating layer 101 side is parallel to the surface of the insulating layer 101, and a space 121b is formed between them. The semiconductor layer 103 grows in the space 121b thus formed. In this case, the semiconductor layer 103 is formed between the insulating layer 101 and the upper insulating layer 121.

[0030] 2F, an upper opening 121c is formed by opening a portion of upper insulating layer 121 above semiconductor layer 103, thereby exposing the upper surface of semiconductor layer 103. Here, semiconductor layer 103 can be further thinned using a known etching technique or the like in accordance with the desired laser structure.

[0031] Next, as shown in FIG. 2G, a semiconductor layer to be used as an active layer is grown in the direction perpendicular to the substrate (thickness direction) starting from the top surface of the semiconductor layer 103. The active layer can be, for example, an InGaAsP bulk, a multi-quantum well (MQW) made of InGaAsP / InGaAsP, or an MQW made of InGaAs / InP. It is also possible to form a double heterostructure by forming an upper semiconductor layer 106 made of InP, whose energy gap is larger than that of the barrier layer material of the MQW, on the active layer.

[0032] Next, as shown in Fig. 2H, in order to form a buried heterostructure (BH) of the active layer by selective growth, an insulating material layer 107a for forming a hard mask made of an insulating material such as SiO2 is formed, and this layer is patterned by dry etching or the like to form a hard mask 107 as shown in Fig. 2I. The dimensions of the hard mask 107 can be determined taking into consideration the dimensions of the desired laser structure, etc.

[0033] Next, a dry etching process using the hard mask 107 as a mask is performed to form a core-shaped active layer 105a and an upper semiconductor layer 106, as shown in Fig. 2J. Next, buried regrowth is performed on the semiconductor layer 103 on the sides of the active layer 105a, and the active layer 105a is buried with a semiconductor layer 108, as shown in Fig. 2K. For example, the buried growth can be performed using InP.

[0034] Thereafter, for example, by ion implantation and thermal diffusion, an n-type impurity is introduced into the semiconductor layer 108 on one side of the active layer 105a, and a p-type impurity is introduced into the semiconductor layer 108 on the other side of the active layer 105a, thereby forming an n-type layer 108a and a p-type layer 108b as shown in Fig. 2L. Furthermore, a diffraction grating 110 is formed above the active layer 105a, and an insulating layer 112 is formed thereon. After that, an n-electrode 109a and a p-electrode 109b are formed on the n-type layer 108a and the p-type layer 108b via contact layers 108c and 108d, thereby completing the thin-film semiconductor laser shown in Fig. 3A and Fig. 4.

[0035] 3B and 4, an optical waveguide 131 made of a Si core 102a is formed in another region on the insulating layer 101. Here, the extension direction (waveguiding direction) of the active layer 105a of the semiconductor laser formed as described above is formed in the [1-12] or [1-1-2] direction of the Si layer 102 in a plan view, and the crystal orientation is aligned with the Si layer 102. The optical waveguide 131 made of a Si core 102a formed in another region is formed by a butt joint or SiO x Optical coupling can be achieved via an optical waveguide 132 having a core made of silicon dioxide or SiON.

[0036] Although the above description omits the process of removing the portion of the Si layer 102 that is continuous with the side surface 104, it is possible to remove the portion by etching, for example, after growing the semiconductor layer 103 laterally starting from the side surface 104.

[0037] Next, another method for manufacturing a laser using the semiconductor thin film structure according to the first embodiment will be described with reference to Figures 5A to 5D. First, as described with reference to Figures 2A to 2D, space 121b is formed between insulating layer 101 and upper insulating layer 121, and side surface 104, which is the (-111) plane or the (1-11) plane of Si layer 102, is formed at the back of space 121b.

[0038] Next, as shown in FIG. 5A , an n-type layer 103a, an active layer 103b, and a p-type semiconductor layer 103c made of III-V compound semiconductor are grown laterally in sequence starting from the side surface 104. During the growth of the n-type layer 103a and the p-type layer 103c, dopants are added to impart each conductivity type. In this example, a pin junction is formed by adding dopants during the lateral growth of the III-V compound semiconductor starting from the side surface 104.

[0039] Note that, since side surface 104 of Si layer 102, whose main surface has a plane orientation of (110), is composed of a {111} plane, the angle formed by side surface 104 with insulating layer 101 and upper insulating layer 121 is 90°. Accordingly, when n-type semiconductor layer 103a, active layer 103b, p-type layer 103c, etc. are formed by adding dopants during lateral growth, the interface between active layer 103b, which is an i-type region, and p-type semiconductor layer 103c, quantum well layer, etc. also tend to be formed along the {111} plane, and in this case, these interfaces and quantum well layers are also inclined at 90° with respect to the insulating layers above and below.

[0040] 5B, upper insulating layer 121 is partially opened above n-type layer 103 a, active layer 103 b, and p-type layer 103 c to form upper opening 121 c, thereby exposing the top surfaces of n-type layer 103 a, active layer 103 b, and p-type layer 103 c. The dimensions of upper opening 121 c can be determined according to the desired laser structure.

[0041] Next, as shown in Fig. 5C, an upper semiconductor layer 103d, which functions as an upper cladding layer, is formed on the active layer 103b by, for example, regrowth. Next, a diffraction grating 110 is formed on the upper semiconductor layer 103d. The upper semiconductor layer 103d may be made of, for example, InP. Thereafter, as shown in Fig. 5D, an n-electrode 109a and a p-electrode 109b are formed on the n-type layer 103a and the p-type layer 103c, respectively, to produce the thin-film semiconductor laser shown in Figs. 6A and 7.

[0042] To establish ohmic contact with the p-electrode 109b, the p-type layer 103c can be made of, for example, InGaAs or InGaAsP with a high As composition. Note that in this example, the active layer 103b is in contact with the underlying insulating layer 101. Furthermore, an n-electrode 109a and a p-electrode 109b can be formed on the n-type layer 103a and the p-type layer 103c via contact layers for current injection.

[0043] 6(b) and 7, an optical waveguide 131 made of a Si core 102a is formed in another region on the insulating layer 101. Here, the extension direction (waveguiding direction) of the active layer 105a of the semiconductor laser formed as described above is formed in the [1-12] or [1-1-2] direction of the Si layer 102 in a plan view, and the crystal orientation is aligned with the Si layer 102. The optical waveguide 131 made of the Si core 102a formed in another region is formed by a butt joint or SiO x Optical coupling can be achieved via an optical waveguide 132 having a core made of silicon dioxide or SiON.

[0044] Furthermore, a field effect transistor can be manufactured using the semiconductor thin film structure according to the first embodiment by the following method.

[0045] 2A to 2C, an upper insulating layer is formed on the Si layer on the insulating layer, and an opening is formed in the upper insulating layer. The width of the opening in the long side direction may be approximately the same as the dimension in the gate length direction of the transistor to be formed, and may be, for example, 50 μm.

[0046] Next, a space is formed between the insulating layer and the upper insulating layer in the same manner as described with reference to Fig. 2D, and a side surface of the Si layer, which is the {X11} plane, is formed at the back of the space. The depth to the location where the side surface of the space is formed can be, for example, about 10 µm.

[0047] In a manner similar to that described with reference to FIG. 2E, a semiconductor layer made of a III-V compound semiconductor is grown laterally, starting from the side surface of the Si layer, which is the (-111) plane or the (1-11) plane. The semiconductor layer can be, for example, InP. Next, in a manner similar to that described with reference to FIG. 2F, an opening is formed in a portion of the upper insulating layer above the laterally grown semiconductor layer, thereby exposing the upper surface of the semiconductor layer. Here, an opening having an area required for transistor fabrication may be appropriately formed.

[0048] Next, a semiconductor heterojunction structure constituting a heterojunction field-effect transistor is deposited on the semiconductor layer exposed through the opening by a crystal growth method. For example, a 10 nm thick InP buffer layer, a 200 nm thick InAlAs buffer layer, a 15 nm thick InGaAs channel layer, a 10 nm thick InAlAs barrier layer, a 5 nm thick InP recess etching stop layer, a 20 nm thick InAlAs contact layer, and a 20 nm thick InGaAs contact layer are sequentially deposited on the InP semiconductor layer. The barrier layers and contact layers may be doped with Si as appropriate to achieve desired transistor characteristics.

[0049] Next, a gate electrode, a source electrode, and a drain electrode are formed on the heterojunction stacked as described above using known techniques, for example, as described in the references, to obtain a heterojunction field effect transistor. While the heterojunction field effect transistor has been described above as an example, a heterojunction stacked structure, such as a stacked structure constituting a heterojunction bipolar transistor, can also be formed by a crystal growth method. In this case, too, a heterojunction bipolar transistor can be fabricated by forming appropriate electrodes using known techniques.

[0050] Second Embodiment Next, a semiconductor thin film structure according to a second embodiment of the present invention will be described with reference to Fig. 8. This semiconductor thin film structure includes a Si layer 102 formed on an insulating layer 101, and a semiconductor layer 103.

[0051] The Si layer 102 is made of single-crystal Si, and the plane orientation of the main surface is (111). The semiconductor layer 103 is made of a III-V compound semiconductor. The semiconductor layer 103 undergoes crystal growth from a side surface 104a of the Si layer 102 in a direction parallel to the surface of the insulating layer 101. The side surface 104a may be a single {111} plane extending in the [0-11] direction of the Si layer. The side surface 104a may be a single {111} plane extending in the [10-1] direction of the Si layer. The side surface 104a may be a single (11-1) plane extending in the [-110] direction of the Si layer.

[0052] For example, by using a well-known SOI substrate, the side surface 104a can be formed on the Si layer 102.

[0053] Next, a method for manufacturing a semiconductor thin film structure according to the second embodiment and a method for manufacturing a laser using the semiconductor thin film structure will be described with reference to Figures 9A to 9L. In Figures 9A to 9L, (a) shows a cross section taken along line aa' in the plan view shown in (b).

[0054] 9A, an SOI substrate is prepared that includes an insulating layer 101 as a buried insulating layer and an Si layer 102 as a surface Si layer on a base portion 111. Furthermore, the Si layer 102 is formed into a rectangular pattern with its long sides oriented in the [0-11] direction, the [10-1] direction, or the [-110] direction in a plan view seen from the normal direction to the surface of the insulating layer 101.

[0055] Next, as shown in FIG. 9B , an upper insulating layer 121 is formed on the Si layer 102 as a selective growth mask. The upper insulating layer 121 is formed to extend laterally along the side surfaces of the insulating layer 101 in a direction parallel to the surface of the insulating layer 101. The upper insulating layer 121 is formed to cover the Si layer 102. Next, as shown in FIG. 9C , an opening 121a is formed in the upper insulating layer 121. The opening 121a is formed so that one long side of the Si layer 102 is exposed and the surface of the insulating layer 101 is exposed. Here, the opening 121a is formed to have a rectangular shape when viewed from the normal direction to the plane of the insulating layer 101. Furthermore, the opening 121a is formed so that the long side of the rectangle is oriented in the [0-11] direction, the [10-1] direction, or the [−110] direction. The opening width of the opening 121a in the long side direction can be, for example, approximately the resonator length of the laser to be formed, e.g., 50 μm.

[0056] 9D , the Si layer 102 is etched (side-etched) using an anisotropic Si etchant through the opening 121a formed in this manner, thereby forming a space 121b between the insulating layer 101 and the upper insulating layer 121 and forming a side surface 104a of the Si layer 102 that is a single {111} plane. The angle between the surface of the insulating layer 101, which is parallel to the main surface of the Si layer 102 that has a (111) plane orientation, and the side surface 104a is approximately 70°. The depth of the space 121b to the location where the side surface 104a is formed can be, for example, approximately 10 μm.

[0057] 9E, a semiconductor layer 103 made of a III-V compound semiconductor is grown laterally starting from the side surface 104a. The semiconductor layer 103 may be made of, for example, InP.

[0058] The Si layer 102 has a (111) plane orientation on its main surface, and the side surface 104 is composed of a single {111} plane, such as the (-111) plane. Therefore, the polarities of the microcrystalline nuclei of III-V compound semiconductors generated everywhere on the side surface 104a of the Si layer 102 are all in the same phase. As a result, no anti-phase boundary (APB) occurs at the interface of the microcrystalline III-V compound semiconductors, making it possible to grow high-quality III-V compound semiconductors.

[0059] The lower surface of the upper insulating layer 121 on the insulating layer 101 side is parallel to the surface of the insulating layer 101, and a space 121b is formed between them. The semiconductor layer 103 grows in the space 121b thus formed. In this case, the semiconductor layer 103 is formed between the insulating layer 101 and the upper insulating layer 121.

[0060] 9F, an upper opening 121c is formed by opening a portion of upper insulating layer 121 above semiconductor layer 103, thereby exposing the upper surface of semiconductor layer 103. Here, semiconductor layer 103 can be further thinned using a known etching technique or the like in accordance with the desired laser structure.

[0061] Next, as shown in FIG. 9G, a semiconductor layer to be used as an active layer is grown in the direction perpendicular to the substrate (thickness direction) starting from the top surface of the semiconductor layer 103. The active layer can be, for example, an InGaAsP bulk, a multi-quantum well (MQW) made of InGaAsP / InGaAsP, or an MQW made of InGaAs / InP. It is also possible to form a double heterostructure by forming an upper semiconductor layer 106 made of InP, whose energy gap is larger than that of the barrier layer material of the MQW, on the active layer.

[0062] Next, as shown in Fig. 9H, in order to form a buried heterostructure (BH) of the active layer by selective growth, an insulating material layer 107a for forming a hard mask made of an insulating material such as SiO2 is formed, and this layer is patterned by dry etching or the like to form a hard mask 107 as shown in Fig. 9I. The dimensions of the hard mask 107 can be determined taking into consideration the dimensions of the desired laser structure, etc.

[0063] Next, a dry etching process using the hard mask 107 as a mask is performed to form a core-shaped active layer 105a and an upper semiconductor layer 106, as shown in Fig. 9J. Next, buried regrowth is performed on the semiconductor layer 103 on the sides of the active layer 105a, and the active layer 105a is buried with a semiconductor layer 108, as shown in Fig. 9K. For example, the buried growth can be performed using InP.

[0064] Thereafter, for example, by ion implantation and thermal diffusion, an n-type impurity is introduced into the semiconductor layer 108 on one side of the active layer 105a, and a p-type impurity is introduced into the semiconductor layer 108 on the other side of the active layer 105a, thereby forming an n-type layer 108a and a p-type layer 108b as shown in Fig. 9L. Furthermore, a diffraction grating 110 is formed above the active layer 105a, and an insulating layer 112 is formed thereon. After that, an n-electrode 109a and a p-electrode 109b are formed on the n-type layer 108a and the p-type layer 108b via contact layers 108c and 108d, thereby completing the thin-film semiconductor laser shown in Fig. 10(a) and Fig. 11.

[0065] 10(b) and 11, an optical waveguide 131 made of a Si core 102a is formed in another region on the insulating layer 101. Here, the extension direction (waveguiding direction) of the active layer 105a of the semiconductor laser formed as described above is formed in the [0-11] direction, [10-1] direction, or [-110] direction of the Si layer 102 in a plan view, and the crystal orientation is aligned with the Si layer 102. The optical waveguide 131 made of the Si core 102a formed in another region is formed by a butt joint or SiO x Optical coupling can be achieved via an optical waveguide 132 having a core made of silicon dioxide or SiON.

[0066] Although the above description omits the step of removing the portion of the Si layer 102 that is continuous with the side surface 104 a, it is possible to remove the portion by etching, for example, after the semiconductor layer 103 is grown laterally starting from the side surface 104 a.

[0067] Next, another method for manufacturing a laser using the semiconductor thin film structure according to the second embodiment will be described with reference to Figures 12A to 12D. First, as described with reference to Figures 9A to 9D, a space 121b is formed between the insulating layer 101 and the upper insulating layer 121, and a side surface 104a of the Si layer 102, which is the (-111) plane, the (1-11) plane, or the (11-1) plane, is formed at the back of the space 121b.

[0068] Next, as shown in FIG. 12A , an n-type semiconductor layer 103a, an active layer 103b, and a p-type semiconductor layer 103c made of III-V compound semiconductor are grown laterally in sequence, starting from the side surface 104a. During the growth of the p-type layer 103c and the n-type layer 103a, dopants are added to impart their respective conductivity types. In this example, a pin junction is formed by adding dopants during the lateral growth of the III-V compound semiconductor starting from the side surface 104a.

[0069] As described above, since the side surface 104a where the (-111) plane is exposed is inclined at an angle of about 70°, when dopants are added during lateral growth to form the n-type semiconductor layer 103a, the active layer 103b, the p-type layer 103c, and the like, the interface between the active layer 103b, which is an i-type region, and the p-type semiconductor layer 103c, the quantum well layer, and the like also tend to be inclined at an angle of about 70° with respect to the insulating layers above and below.

[0070] 12B, upper insulating layer 121 is partially opened above n-type layer 103 a, active layer 103 b, and p-type layer 103 c to form upper opening 121 c, thereby exposing the top surfaces of n-type layer 103 a, active layer 103 b, and p-type layer 103 c. The dimensions of upper opening 121 c can be determined according to the desired laser structure.

[0071] Next, as shown in Fig. 12C, an upper semiconductor layer 103d, which functions as an upper cladding layer, is formed on the active layer 103b by, for example, regrowth. Next, a diffraction grating 110 is formed on the upper semiconductor layer 103d. The upper semiconductor layer 103d can be made of, for example, InP. Thereafter, as shown in Fig. 12D, an n-electrode 109a and a p-electrode 109b are formed on the n-type layer 103a and the p-type layer 103c, respectively, to produce the thin-film semiconductor laser shown in Figs. 13A and 14.

[0072] To establish ohmic contact with the p-electrode 109b, the p-type layer 103c can be made of, for example, InGaAs or InGaAsP with a high As composition. Note that in this example, the active layer 103b is in contact with the underlying insulating layer 101. Furthermore, an n-electrode 109a and a p-electrode 109b can be formed on the n-type layer 103a and the p-type layer 103c via contact layers for current injection.

[0073] 13(b) and 14, an optical waveguide 131 made of a Si core 102a is formed in another region on the insulating layer 101. Here, the extension direction (waveguiding direction) of the active layer 105a of the semiconductor laser formed as described above is formed in the [0-11] direction, [10-1] direction, or [-110] direction of the Si layer 102 in a plan view, and the crystal orientation is aligned with the Si layer 102. The optical waveguide 131 made of the Si core 102a formed in another region is formed by a butt joint or SiO x Optical coupling can be achieved via an optical waveguide 132 having a core made of silicon dioxide or SiON.

[0074] Furthermore, a field effect transistor can be manufactured using the semiconductor thin film structure according to the second embodiment by the following method.

[0075] 9A to 9C, an upper insulating layer is formed on the Si layer on the insulating layer, and an opening is formed in the upper insulating layer. The width of the opening in the long side direction may be approximately the same as the dimension in the gate length direction of the transistor to be formed, and may be, for example, 50 μm.

[0076] 9D , a space is formed between the insulating layer and the upper insulating layer, and a side surface of the Si layer, which is the {X11} plane, is formed at the back of the space. The depth to the location where the side surface of the space is formed can be, for example, about 10 μm.

[0077] By following the same procedure as described with reference to FIG. 9E, a semiconductor layer made of a III-V compound semiconductor is grown laterally, starting from the side surface of the Si layer, which is the (-111) plane or the (1-11) plane. The semiconductor layer can be, for example, InP. Next, by following the same procedure as described with reference to FIG. 9F, an opening is formed in a portion of the upper insulating layer above the laterally grown semiconductor layer, thereby exposing the upper surface of the semiconductor layer. Here, it is sufficient to form an opening of an area necessary for transistor fabrication.

[0078] Next, a semiconductor heterojunction structure constituting a heterojunction field-effect transistor is deposited on the semiconductor layer exposed through the opening by a crystal growth method. For example, a 10 nm thick InP buffer layer, a 200 nm thick InAlAs buffer layer, a 15 nm thick InGaAs channel layer, a 10 nm thick InAlAs barrier layer, a 5 nm thick InP recess etching stop layer, a 20 nm thick InAlAs contact layer, and a 20 nm thick InGaAs contact layer are sequentially deposited on the InP semiconductor layer. The barrier layers and contact layers may be doped with Si as appropriate to achieve desired transistor characteristics.

[0079] Next, a gate electrode, a source electrode, and a drain electrode are formed on the heterojunction stacked as described above using known techniques, for example, as described in the references, to obtain a heterojunction field effect transistor. While the heterojunction field effect transistor has been described above as an example, a heterojunction stacked structure, such as a stacked structure constituting a heterojunction bipolar transistor, can also be formed by a crystal growth method. In this case, too, a heterojunction bipolar transistor can be fabricated by forming appropriate electrodes using known techniques.

[0080] As described above, the present invention provides a semiconductor layer made of a III-V compound semiconductor crystal-grown from either a side surface of a Si layer having a (110) plane orientation on its main surface, the side surface being a (-111) plane extending in the [1-12] direction, or the side surface being a (1-11) plane extending in the [1-1-2] direction. The present invention also provides a semiconductor layer made of a III-V compound semiconductor crystal-grown from a Si seed crystal surface having a (110) plane orientation on its main surface, the side surface extending in the [1-12] direction being a (-111) plane, and the side surface extending in the [1-1-2] direction being a (1-11) plane. As a result, the present invention provides a semiconductor layer made of a III-V compound semiconductor crystal-grown from a Si seed crystal surface having a (110) plane orientation on its main surface, the side surface extending in the [1-12] direction being a (-111) plane, and the side surface extending in the [1-1-2] direction being a (1-11) plane. As a result, the present invention makes it possible to suppress the generation of antiphase boundaries at the interface between the Si surface and the III-V compound semiconductor.

[0081] It should be noted that the present invention is not limited to the embodiments described above, and it is clear that many modifications and combinations can be made by a person having ordinary knowledge in the art within the technical concept of the present invention.

[0082] [References] T. Enoki et al., "Ultrahigh-Speed ​​Integrated Circuits Using InP-Based HEMTs", Japanese Journal of Applied Physics, vol. 37, no. 3B, pp. 1359-1364, 1998.

[0083] 101...Si layer, 102...Si layer, 103...semiconductor layer, 104...side surface.

Claims

1. A semiconductor thin film structure comprising: a Si layer formed on an insulating layer and made of single-crystal Si with a (110) plane orientation on its main surface; and a semiconductor layer made of a III-V compound semiconductor crystal-grown in a direction parallel to the surface of the insulating layer from either a side surface of the Si layer that is a (-111) plane extending in the [1-1-2] direction or a side surface of the Si layer that is a (1-11) plane extending in the [1-1-2] direction.

2. A semiconductor thin film structure comprising: a Si layer formed on an insulating layer and made of single-crystal Si with a (111) plane orientation on its main surface; and a semiconductor layer made of a III-V compound semiconductor crystal-grown in a direction parallel to the surface of the insulating layer from any one of a side surface of the Si layer that is a (-111) plane extending in the [0-11] direction, a side surface of the Si layer that is a (1-11) plane extending in the [10-1] direction, and a side surface of the Si layer that is a (11-1) plane extending in the [-110] direction.

3. A semiconductor thin film structure according to claim 1 or 2, further comprising an upper insulating layer formed on the Si layer and extending laterally from the side surface in a direction parallel to the surface of the insulating layer, and the semiconductor layer is formed between the insulating layer and the upper insulating layer.

4. A semiconductor thin film structure according to claim 3, wherein the lower surface of said upper insulating layer on said insulating layer side is parallel to the surface of said insulating layer.

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