Semiconductor device

Abstract

The present invention suppresses deterioration of circuit characteristics. A semiconductor device according to an embodiment comprises: a first substrate; a first conductor provided on an upper surface of the first substrate; a first chip provided on an upper surface of the first conductor; a second chip provided on the upper surface of the first conductor and aligned with the first chip in a first direction; a third chip provided on the upper surface of the first conductor, aligned with the first chip and the second chip in the first direction, and located on the opposite side of the first chip with respect to the second chip; a second conductor provided apart from the first conductor on the upper surface of the first substrate and having a first portion located between the first chip and the second chip and a second portion located between the second chip and the third chip; and a third conductor connecting between a source electrode of the first chip and the first portion of the second conductor, between the first portion of the second conductor and a source electrode of the second chip, between the source electrode of the second chip and the second portion of the second conductor, and between the second portion of the second conductor and a source electrode of the third chip.

Description

Semiconductor Devices

[0001] The embodiments relate to a semiconductor device.

[0002] Power modules are known as semiconductor devices that achieve high output. A power module is configured as a single package that integrates multiple chips, each functioning as a power semiconductor. To reduce thermal resistance, the multiple chips integrated in the package are miniaturized and distributed throughout the package.

[0003] Japanese Patent No. 6865838 Japanese Patent No. 7198168 Japanese Patent Application Laid-Open No. 2023-70978

[0004] Suppresses deterioration of circuit characteristics.

[0005] A semiconductor device according to an embodiment includes a first substrate, a first conductor, a first chip, a second chip, a third chip, a second conductor, and a third conductor. The first conductor is provided on an upper surface of the first substrate. The first chip is provided on an upper surface of the first conductor. The second chip is provided on the upper surface of the first conductor and aligned with the first chip in a first direction. The third chip is provided on the upper surface of the first conductor and aligned with the first chip and the second chip in the first direction, and is located on the opposite side of the second chip from the first chip. The second conductor is provided on the upper surface of the first substrate, spaced apart from the first conductor, and has a first portion located between the first chip and the second chip and a second portion located between the second chip and the third chip. The third conductor connects between the source electrode of the first chip and the first portion of the second conductor, between the first portion of the second conductor and the source electrode of the second chip, between the source electrode of the second chip and the second portion of the second conductor, and between the second portion of the second conductor and the source electrode of the third chip.

[0006] 1 is a perspective view showing an external structure of a semiconductor device according to an embodiment; a circuit diagram showing an example of a circuit configuration of a semiconductor device according to an embodiment; a plan view showing an example of a planar layout of a part of the interior of a semiconductor device according to an embodiment; a cross-sectional view taken along line IV-IV in FIG. 3 showing an example of a cross-sectional structure of the interior of a semiconductor device according to an embodiment; a circuit diagram showing an example of an equivalent circuit of a part of the circuit configuration of a semiconductor device according to an embodiment; a plan view showing an example of a planar layout of a part of the interior of a semiconductor device according to a first modified example; a plan view showing an example of a planar layout of a part of the interior of a semiconductor device according to a second modified example; and a plan view showing an example of a planar layout of a part of the interior of a semiconductor device according to a third modified example.

[0007] Hereinafter, embodiments will be described with reference to the drawings. The dimensions and proportions of the drawings are not necessarily the same as those in reality.

[0008] In the following description, components having substantially the same functions and configurations are denoted by the same reference numerals. When elements having similar configurations are to be particularly distinguished from one another, different letters or numbers may be added to the end of the same reference numerals.

[0009] 1. Embodiment A semiconductor device according to an embodiment will be described.

[0010] The semiconductor device according to the embodiment is a power module, and is applied to, for example, a power conversion device for a railway vehicle, or industrial equipment for a renewable energy power generation system.

[0011] First, the external structure of the semiconductor device according to the embodiment will be described.

[0012] 1 is a perspective view showing an example of the external structure of a semiconductor device according to an embodiment. The semiconductor device 1 includes, as its external structure, a base substrate 10, a case 11, and a lid 12. The base substrate 10, the case 11, and the lid 12 form a container for the semiconductor device 1. A circuit configuration (not shown) including semiconductor elements is housed inside the container for the semiconductor device 1.

[0013] The base substrate 10 is a support for the semiconductor device 1. The base substrate 10 has a flat plate shape. The base substrate 10 corresponds to the lower part of the container of the semiconductor device 1. The base substrate 10 has, for example, screw holes at the four corners. The base substrate 10 can be fixed to an external device (not shown) of the semiconductor device 1 via the screw holes. The base substrate 10 includes, for example, copper (Cu) or ceramics.

[0014] A case 11 is provided on the upper surface of the base substrate 10. The case 11 is, for example, an insulating body having a rectangular cylindrical shape. The case 11 corresponds to a side portion of a container for the semiconductor device 1. The case 11 is fixed to the base substrate 10. The case 11 includes, for example, polyphenylene sulfide (PPS).

[0015] A lid 12 is provided on the top surface of the case 11. The lid 12 is an insulating material having a flat plate shape. The lid 12 corresponds to the top of the container of the semiconductor device 1. The lid 12 is fixed to the case 11. The lid 12 includes, for example, PPS.

[0016] By assembling the base substrate 10, case 11, and lid 12 as described above, a space for arranging a circuit configuration is formed inside the container. In the following description, a plane parallel to the contact surface between the base substrate 10 and case 11 is referred to as the XY plane. Within the XY plane, the long side direction and short side direction of the base substrate 10 are referred to as the X direction and the Y direction, respectively. The extension direction of the case 11 relative to the base substrate 10 is referred to as the Z direction or upward direction. The +X direction view, +Y direction view, and −Z direction view correspond to a front view, a side view, and a plan view, respectively.

[0017] The semiconductor device 1 further includes terminals 13 , 14 , 15 , and 16 .

[0018] Terminals 13, 14, 15, and 16 are ends of bus bars (not shown) that electrically connect between external devices and the internal circuit configuration of the semiconductor device 1. In the example of Fig. 1, one terminal 13, one terminal 14, two terminals 15, and seven terminals 16 are shown. Note that the number of each of the terminals 13, 14, 15, and 16 is not limited to the example of Fig. 1 and can be designed to be any number.

[0019] The terminal 13 is an input terminal and has a P (positive) polarity. The terminal 13 is disposed on one of two opposing short sides of the semiconductor device 1.

[0020] The terminal 14 is an input terminal and has a negative (N) polarity. The terminal 14 is arranged on one of two opposing short sides of the semiconductor device 1 so as to be aligned with the terminal 14 in the Y direction.

[0021] The terminal 15 is an output terminal, also called an AC (Alternating Current) terminal, and is disposed on the other of the two opposing short sides of the semiconductor device 1.

[0022] The terminals 16 are control terminals and monitor terminals. The control terminals are, for example, terminals for controlling whether or not a semiconductor element included in the circuit configuration of the semiconductor device 1 is driven. The monitor terminals are, for example, terminals for monitoring the electrical characteristics or temperature characteristics of the circuit configuration of the semiconductor device 1. The terminals 16 are arranged on two opposing long sides of the semiconductor device 1, respectively.

[0023] Next, the circuit configuration of the semiconductor device according to the embodiment will be described.

[0024] 2 is a circuit diagram showing an example of a circuit configuration of a semiconductor device according to an embodiment. In the example of FIG. 2, a semiconductor device 1 includes transistors Tup and Tlow as electrical elements included in the internal circuit configuration.

[0025] The transistors Tup and Tlow are, for example, field-effect transistors (MOSFETs: Metal-Oxide-Silicon Field-Effect Transistors) using silicon carbide (SiC). The transistors Tup and Tlow are n-type transistors. The transistors Tup and Tlow are connected in series.

[0026] Specifically, the transistor Tup has a drain terminal connected to the node P, a source terminal connected to the node AC, and a gate terminal connected to the node G1. The transistor Tlow has a drain terminal connected to the node AC, a source terminal connected to the node N, and a gate terminal connected to the node G2. The second terminal of the transistor Tup and the drain terminal of the transistor Tlow are commonly connected to the nodes AC and S1. The source terminal of the transistor Tlow and the node N are commonly connected to the node S2.

[0027] Nodes P, N, and AC correspond to terminals 13, 14, and 15, respectively. Nodes G1 and G2 correspond to two different control terminals of terminal 16. Nodes S1 and S2 correspond to two different monitor terminals of terminal 16, respectively.

[0028] With the above-described configuration, the semiconductor elements inside the semiconductor device 1 can be controlled by a voltage supplied from outside the semiconductor device 1 .

[0029] The circuit configuration of the semiconductor device 1 is not limited to the example shown in Fig. 2. For example, the transistors Tup and Tlow may be IGBTs (Insulated-Gate Bipolar Transistors). Although the example shown in Fig. 2 shows one transistor each, in reality, each of the transistors Tup and Tlow is composed of multiple transistors connected in parallel.

[0030] Next, the internal structure of the semiconductor device according to the embodiment will be described.

[0031] Fig. 3 is a plan view showing an example of a planar layout of a portion of the interior of a semiconductor device according to an embodiment. Case 11 and lid 12 are omitted from Fig. 3. Fig. 3 also shows a planar layout of a structure corresponding to the portion from node AC to node N (i.e., the low side) of the structure corresponding to the circuit configuration shown in Fig. 2. Although omitted from Fig. 3, the planar layout of the structure corresponding to the portion from node P to node AC (i.e., the high side) may have a planar layout equivalent to that of the structure corresponding to the low side.

[0032] The internal structure of the semiconductor device 1, both on the high side and the low side, is provided on the same base substrate 10. Specifically, the semiconductor device 1 includes a semiconductor element 30, an insulating substrate 40, and conductors 51, 52, 53, 54, 61, 62, 63, and 64 as the internal structure of the low side.

[0033] The insulating substrate 40 is an insulating substrate that supports the circuit configuration of the semiconductor device 1. The insulating substrate 40 is provided above the base substrate 10. The insulating substrate 40 includes, for example, a resin. A ceramic substrate such as silicon nitride (SiN), aluminum nitride, or alumina may also be used as the insulating substrate 40. The example of FIG. 3 shows a case where one insulating substrate 40 is provided so as to cover the entire upper surface of the base substrate 10.

[0034] Conductors 51, 52, 53, and 54 are provided at intervals on the upper surface of the insulating substrate 40. The conductors 51, 52, 53, and 54 are conductive wiring patterns.

[0035] In a region not shown, the conductor 51 is electrically connected to the terminal 13 that functions as a node P. In addition, the conductor 51 and the conductor 52 form a high-side planar layout in a region not shown.

[0036] The conductor 52 is electrically connected to the terminal 15, which functions as a node AC, in a region not shown. A first comb-shaped portion is provided on the conductor 52. The first comb-shaped portion includes a plurality of finger portions (three in FIG. 3 ) that are spaced apart from each other in the Y direction and each extend in the X direction.

[0037] The conductor 53 is electrically connected to the terminal 14, which functions as a node N, in a region not shown. A second comb-shaped portion is provided on the conductor 53. The second comb-shaped portion includes a plurality of finger portions (three in FIG. 3 ) that are spaced apart from each other in the Y direction and each extend in the X direction. The plurality of finger portions of the second comb-shaped portion and the plurality of finger portions of the first comb-shaped portion are arranged to interdigitate with each other.

[0038] The conductor 54 is disposed on the periphery of the insulating substrate 40 relative to the conductors 51 , 52 , and 53 .

[0039] A plurality of semiconductor elements 30 are provided on the upper surface of the plurality of finger portions of the first comb-shaped portion of the conductor 52. Each of the plurality of semiconductor elements 30 is a semiconductor chip that functions as a transistor Tlow. A drain electrode is provided on the lower surface of each of the plurality of semiconductor elements 30 and is electrically connected to the conductor 52. A gate electrode and a source electrode are provided on the upper surface of each of the plurality of semiconductor elements 30. The example of FIG. 3 shows a case where twelve semiconductor elements 30 are provided, four on each finger portion of the first comb-shaped portion of the conductor 52. As a result, the twelve semiconductor elements 30 are dispersed and arranged in a matrix of three rows and four columns on the upper surface of the conductor 52 in a plan view.

[0040] Hereinafter, of the twelve semiconductor elements 30, the four semiconductor elements 30 arranged in the first finger portion from the top of the first comb-shaped portion will also be referred to as semiconductor elements 30(1,1), 30(1,2), 30(1,3), and 30(1,4) in order from the left side of the page. The four semiconductor elements 30 arranged in the second finger portion from the top of the first comb-shaped portion will also be referred to as semiconductor elements 30(2,1), 30(2,2), 30(2,3), and 30(2,4) in order from the left side of the page. The four semiconductor elements 30 arranged in the third finger portion from the top of the first comb-shaped portion will also be referred to as semiconductor elements 30(3,1), 30(3,2), 30(3,3), and 30(3,4) in order from the left side of the page.

[0041] The conductor 61 includes a plurality of bonding wires (28 in FIG. 3 ). The conductor 61 extends in the Y direction and electrically connects the source electrodes of each of the plurality of semiconductor elements 30 to the conductor 53. In the example of FIG. 3 , four conductors 61 connect, in this order, the source electrode of the semiconductor element 30 (1, 1), the first finger portion of the second comb-shaped portion from the top of the page, the source electrode of the semiconductor element 30 (2, 1), the second finger portion of the second comb-shaped portion from the top of the page, the source electrode of the semiconductor element 30 (3, 1), and the third finger portion of the second comb-shaped portion from the top of the page. The other four conductors 61 connect, in this order, the source electrode of the semiconductor element 30(1,2), the first finger portion from the top of the paper of the second comb-shaped portion, the source electrode of the semiconductor element 30(2,2), the second finger portion from the top of the paper of the second comb-shaped portion, the source electrode of the semiconductor element 30(3,2), and the third finger portion from the top of the paper of the second comb-shaped portion. The other four conductors 61 connect, in this order, the source electrode of the semiconductor element 30(1,3), the first finger portion from the top of the paper of the second comb-shaped portion, the source electrode of the semiconductor element 30(2,3), the second finger portion from the top of the paper of the second comb-shaped portion, the source electrode of the semiconductor element 30(3,3), and the third finger portion from the top of the paper of the second comb-shaped portion. The other four conductors 61 connect, in this order, the source electrode of the semiconductor element 30(1,4), the first finger portion from the top of the paper of the second comb-shaped portion, the source electrode of the semiconductor element 30(2,4), the second finger portion from the top of the paper of the second comb-shaped portion, the source electrode of the semiconductor element 30(3,4), and the third finger portion from the top of the paper of the second comb-shaped portion. In addition, the other 12 conductors 61 connect, in this order, the first finger portion from the top of the paper of the second comb-shaped portion, the second finger portion from the top of the paper of the second comb-shaped portion, and the third finger portion from the top of the paper of the second comb-shaped portion.

[0042] The conductor 62 includes multiple bonding wires (four in FIG. 3 ). The conductor 62 extends in the Y direction and electrically connects the gate electrodes of the multiple semiconductor elements 30 to the conductor 54. In the example of FIG. 3 , one conductor 62 connects the gate electrode of the semiconductor element 30(1,1), the gate electrode of the semiconductor element 30(2,1), the gate electrode of the semiconductor element 30(3,1), and the conductor 54, in this order. Another conductor 62 connects the gate electrode of the semiconductor element 30(1,2), the gate electrode of the semiconductor element 30(2,2), the gate electrode of the semiconductor element 30(3,2), and the conductor 54, in this order. Another conductor 62 connects the gate electrode of the semiconductor element 30(1,3), the gate electrode of the semiconductor element 30(2,3), the gate electrode of the semiconductor element 30(3,3), and the conductor 54, in this order. Another conductor 62 connects the gate electrode of the semiconductor element 30(1,4), the gate electrode of the semiconductor element 30(2,4), the gate electrode of the semiconductor element 30(3,4), and the conductor 54 in this order.

[0043] The conductor 63 includes a bonding wire and electrically connects the conductor 54 to the terminal 16 that functions as the node G2.

[0044] The conductor 64 includes a bonding wire and electrically connects the conductor 53 to the terminal 16 that functions as the node S2.

[0045] 4 is a cross-sectional view illustrating an example of the internal cross-sectional structure of the semiconductor device according to the embodiment, taken along line IV-IV in FIG. 4. As shown in FIG. 4, the semiconductor device 1 includes conductive layers 41, 42, and 43.

[0046] A conductor layer 41 is provided on the lower surface of the insulating substrate 40. The conductor layer 41 is, for example, a wiring pattern that functions as a lower electrode. A conductor layer 42 is provided between the lower surface of the conductor layer 41 and the upper surface of the base substrate 10. The conductor layer 42 is made of, for example, solder. The conductor layer 42 fixes the conductor layer 41 to the base substrate 10.

[0047] Furthermore, a conductor layer 43 is provided between the upper surface of the conductor 52 and the lower surface of the semiconductor element 30. The conductor layer 43 is made of, for example, solder. Note that, instead of solder, a sintered material that is difficult to melt (for example, at least one material selected from copper, silver, lead, tin-copper compounds, tin-silver compounds, and tin-nickel compounds) may be used. The conductor layer 43 fixes the semiconductor element 30 to the conductor 52.

[0048] With the above-described configuration, the semiconductor element 30 is fixed to the base substrate 10 via the insulating substrate 40. Here, the conductor 52, the insulating substrate 40, the conductor layers 41 and 42, and the base substrate 10 also function as a heat dissipation path for heat generated in the semiconductor element 30.

[0049] From the viewpoint of reducing thermal resistance, it is preferable that the heat dissipation paths of adjacent semiconductor elements 30 do not overlap at least up to the insulating substrate 40, which has a relatively low thermal conductivity. The spreading angle of the heat dissipation path from the lower surface of the semiconductor element 30 toward the upper surface of the base substrate 10 is θ, and the distance between the upper surface of the insulating substrate 40 and the lower surface of the semiconductor element 30 is t. １ , where d is the distance between adjacent semiconductor elements 30, the condition for the heat dissipation paths of adjacent semiconductor elements 30 not to overlap is d>2t １ × tan θ.

[0050] Here, the spread angle θ of the heat dissipation path depends on the materials of the insulating substrate 40, the conductive layers 41 and 42, and the conductive material 52 provided between the semiconductor element 30 and the base substrate 10. However, if θ=45 degrees, the above condition is satisfied: d>2t １ It can be considered as follows.

[0051] In order to further enhance the heat dissipation effect, it is preferable that the heat dissipation paths of adjacent semiconductor elements 30 do not overlap until they reach the base substrate 10. The distance between the upper surface of the base substrate 10 and the lower surface of the semiconductor element 30 is defined as t ２ Then, the condition for preventing the heat dissipation paths of adjacent semiconductor elements 30 from overlapping is d>2t1×tanθ (=2t ２ )

[0052] 4, the connection relationship between the conductor 51 and the semiconductor element 20 is the same as the connection relationship between the conductor 52 and the semiconductor element 30. Therefore, from the viewpoint of reducing thermal resistance, it is preferable that the above-mentioned condition regarding the distance between adjacent semiconductor elements 30 is also satisfied for the semiconductor element 20.

[0053] According to the embodiment, it is possible to suppress the deterioration of the circuit characteristics of the semiconductor device 1 .

[0054] Conductors 52 and 53 are provided on the upper surface of insulating substrate 40, spaced apart from each other. Semiconductor elements 30(1,1), 30(2,1), and 30(3,1) are provided on the upper surface of conductor 52, arranged in this order in the Y direction. Conductor 53 has a second comb-shaped portion. Of the multiple finger portions that make up the second comb-shaped portion, the first finger portion from the top of the paper is located between semiconductor elements 30(1,1) and 30(2,1). The second finger portion from the top of the paper is located between semiconductor elements 30(2,1) and 30(3,1). The conductor 61 connects the source electrode of the semiconductor element 30(1,1) to the first finger portion of the second comb-shaped portion, the first finger portion of the second comb-shaped portion to the source electrode of the semiconductor element 30(2,1), the source electrode of the semiconductor element 30(2,1) to the second finger portion of the second comb-shaped portion, and the second finger portion of the second comb-shaped portion to the source electrode of the semiconductor element 30(3,1). This allows the source electrodes of the parallel-connected semiconductor elements 30(1,1), 30(2,1), and 30(3,1) to be connected over a relatively short distance by the conductor 63. This shortens the source loop between adjacent semiconductor elements 30, thereby reducing source inductance. This suppresses oscillation during switching of the semiconductor device 1.

[0055] Additionally, when a plurality of semiconductor elements 20 are connected in parallel to form a transistor Tup, or when a plurality of semiconductor elements 30 are connected in parallel to form a transistor Tlow, part of the circuit shown in FIG. 2 can be reduced to a Colpitts oscillator circuit by modifying the equivalent circuit if certain conditions are met.

[0056] 6 is a circuit diagram showing an example of an equivalent circuit of a part of the circuit configuration of the semiconductor device according to the embodiment. Fig. 6 shows an equivalent circuit of the peripheral part of the transistor Tup or Tlow. As shown in Fig. 6, the equivalent circuit is composed of a transistor TR, capacitors Cds, Cgd, and Cgs, and inductors Ld, Lg, and Ls.

[0057] The transistor TR has a first end connected to the node D, a second end connected to the node S, and a control end connected to the node G.

[0058] Capacitor Cds has a first end connected to node D and a second end connected to node S.

[0059] Capacitor Cgd has a first end connected to node D and a second end connected to node G.

[0060] Capacitor Cgs has a first end connected to node G and a second end connected to node S.

[0061] The inductor Ld has a first end connected to the node D and a second end connected to the node M.

[0062] The inductor Lg has a first end connected to the node M and a second end connected to the node G. The inductor Lg corresponds to half of the inductance between the gates of each of the plurality of semiconductor elements 30 or half of the inductance between the gates of each of the plurality of semiconductor elements 20.

[0063] The inductor Ls has a first end connected to the node M and a second end connected to the node S. The inductor Ls corresponds to half of the inductance between the sources of the plurality of semiconductor elements 30 or half of the inductance between the sources of the plurality of semiconductor elements 20.

[0064] In an equivalent circuit having the above configuration, if the inductance of inductor Lg is small and the inductance of inductor Ls is large, current does not easily flow through inductor Ls and current easily flows through inductor Lg. In such a case, the equivalent circuit satisfies the conditions for a Colpitts oscillator circuit, and therefore oscillation is likely to occur during switching.

[0065] On the other hand, if the inductance of inductor Lg is large and the inductance of inductor Ls is small, current flows less easily through inductor Lg and more easily through inductor Ls. In such a case, the equivalent circuit does not satisfy the conditions for a Colpitts oscillator, and oscillation is less likely to occur during switching. Thus, to make oscillation less likely in semiconductor device 1, it is preferable to increase the inductance of inductor Lg and decrease the inductance of inductor Ls.

[0066] According to the embodiment, between adjacent semiconductor elements 30, the semiconductor elements 30 arranged in different rows but in the same column (e.g., semiconductor elements 30(1,1) and 30(2,1)) have their source electrodes connected over a relatively short distance by the conductor 61. Furthermore, between adjacent semiconductor elements 30 arranged in the same row but in different columns (e.g., semiconductor elements 30(1,1) and 30(1,2)), their source electrodes are connected over a relatively short distance by the conductor 61 and the first finger portion of the second comb-shaped portion of the conductor 53. This makes it possible to shorten the source loop between adjacent semiconductor elements 30, thereby suppressing oscillation.

[0067] Furthermore, between adjacent semiconductor elements 30, semiconductor elements 30 arranged in the same row but in different columns (for example, semiconductor elements 30(1,1) and 30(1,2)) have their gate electrodes connected over a relatively long distance by conductors 62 and 54. This allows the gate loop between adjacent semiconductor elements 30 to be longer, thereby suppressing oscillation.

[0068] Similarly, by making the high side configuration equivalent to that of the low side, the source loop between adjacent semiconductor elements 20 can be shortened while the gate loop between adjacent semiconductor elements 20 can be lengthened, thereby suppressing oscillation.

[0069] 2. First Modification Various modifications can be applied to the above-described embodiment.

[0070] The first modification differs from the embodiment in that the parallel-connected semiconductor elements are arranged in a staggered pattern. The following mainly describes the configuration that differs from the embodiment. The description of the configuration that is the same as the embodiment will be omitted as appropriate.

[0071] 6 is a plan view showing an example of a planar layout inside a semiconductor device according to a first modification, which corresponds to FIG.

[0072] As shown in FIG. 6 , the semiconductor device 1 includes conductors 52A and 53A instead of the conductors 52 and 53. The multiple finger portions of the first comb-shaped portion of the conductor 52A and the multiple finger portions of the second comb-shaped portion of the conductor 53A do not have to be linear. Accordingly, the multiple semiconductor elements 30 may be arranged in a staggered pattern rather than a matrix. In the example of FIG. 6 , the semiconductor elements 30(1,1), 30(2,1), and 30(3,1) are aligned in the Y direction. Meanwhile, the semiconductor elements 30(1,1), 30(1,2), 30(1,3), and 30(1,4) are aligned in the X direction but are also offset in the Y direction.

[0073] Even with the above configuration, as in the embodiment, oscillation during switching can be suppressed by connecting each finger portion of the conductor 53A to the source electrodes of the semiconductor elements 30 arranged in the Y direction by the conductor 61.

[0074] Furthermore, by arranging the plurality of semiconductor elements 30 in a staggered pattern, the distance between adjacent semiconductor elements 30 can be increased compared to when the semiconductor elements 30 are arranged in a matrix, thereby improving the heat dissipation characteristics of the semiconductor device 1.

[0075] 3. Second Modification The second modification differs from the first modification in that the two directions in which the parallel-connected semiconductor elements are arranged are not orthogonal to each other. The following mainly describes the configuration that differs from the first modification. Descriptions of the configuration that is equivalent to the first modification will be omitted as appropriate.

[0076] 7 is a plan view showing an example of a planar layout of the inside of a semiconductor device according to the second modification, which corresponds to FIG. 6 in the first modification.

[0077] As shown in FIG. 7 , the semiconductor device 1 includes conductors 52B and 53B instead of the conductors 52A and 53A. The multiple finger portions of the first comb-shaped portion of the conductor 52B and the multiple finger portions of the second comb-shaped portion of the conductor 53A do not need to extend in the X direction. Accordingly, the multiple semiconductor elements 30 may be arranged in a staggered pattern rather than a matrix. In the example of FIG. 7 , the semiconductor elements 30(1,1), 30(2,1), and 30(3,1) are aligned in the Y direction. Meanwhile, the semiconductor elements 30(1,1), 30(1,2), 30(1,3), and 30(1,4) are aligned in the P direction, which intersects with both the X direction and the Y direction in the XY plane.

[0078] Even with the above configuration, as in the embodiment, oscillation during switching can be suppressed by connecting each finger portion of the conductor 53B to the source electrodes of the semiconductor elements 30 arranged in the Y direction by the conductor 61.

[0079] Furthermore, by arranging the plurality of semiconductor elements 30 in a staggered pattern, the distance between adjacent semiconductor elements 30 can be increased compared to when the semiconductor elements 30 are arranged in a matrix, thereby improving the heat dissipation characteristics of the semiconductor device 1.

[0080] 4. Third Modification The third modification differs from the embodiment in that the conductor connecting the source electrodes of the semiconductor elements is not a bonding wire. The following mainly describes the configuration that differs from the embodiment. The description of the configuration that is equivalent to the embodiment will be omitted as appropriate.

[0081] 8 is a plan view showing an example of a planar layout inside a semiconductor device according to a third modification, which corresponds to FIG.

[0082] As shown in FIG. 8 , the semiconductor device 1 includes a conductor 61C instead of the conductor 61. The conductor 61C includes multiple (four in FIG. 8 ) bonding ribbons or connectors. The conductor 61C extends in the Y direction and electrically connects the source electrodes of each of the multiple semiconductor elements 30 to the conductor 53. In the example of FIG. 8 , one conductor 61C connects, in this order, the source electrode of the semiconductor element 30(1,1), the first finger portion of the second comb-shaped portion from the top of the page, the source electrode of the semiconductor element 30(2,1), the second finger portion of the second comb-shaped portion from the top of the page, the source electrode of the semiconductor element 30(3,1), and the third finger portion of the second comb-shaped portion from the top of the page. Another conductor 61C connects, in this order, the source electrode of the semiconductor element 30(1,2), the first finger portion of the second comb-shaped portion from the top of the paper, the source electrode of the semiconductor element 30(2,2), the second finger portion of the second comb-shaped portion from the top of the paper, the source electrode of the semiconductor element 30(3,2), and the third finger portion of the second comb-shaped portion from the top of the paper. Another conductor 61C connects, in this order, the source electrode of the semiconductor element 30(1,3), the first finger portion of the second comb-shaped portion from the top of the paper, the source electrode of the semiconductor element 30(2,3), the second finger portion of the second comb-shaped portion from the top of the paper, the source electrode of the semiconductor element 30(3,3), and the third finger portion of the second comb-shaped portion from the top of the paper. Another conductor 61C connects, in this order, the source electrode of semiconductor element 30 (1, 4), the first finger portion of the second comb-shaped portion from the top of the paper, the source electrode of semiconductor element 30 (2, 4), the second finger portion of the second comb-shaped portion from the top of the paper, the source electrode of semiconductor element 30 (3, 4), and the third finger portion of the second comb-shaped portion from the top of the paper.

[0083] Even with the above configuration, as in the embodiment, oscillation during switching can be suppressed by connecting each finger portion of the conductor 53 to the source electrodes of the semiconductor elements 30 arranged in the Y direction by the conductor 61C.

[0084] Furthermore, when using a bonding ribbon or connector, the wiring width can be made longer than when using a bonding wire, which allows the inductance of the inductor Ls to be made smaller, thereby further suppressing oscillation during switching.

[0085] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the inventions and their equivalents as defined in the claims.

[0086] DESCRIPTION OF SYMBOLS 1...Semiconductor device 10...Base substrate 11...Case 12...Lid 13, 14, 15, 16...Terminals 20, 30...Semiconductor element 40...Insulating substrate 41, 42, 43...Conductor layers 51, 52, 52A, 52B, 53, 53A, 53B, 54, 61, 61C, 62, 63, 64...Conductors Tup, Tlow, TR...Transistors Cds, Cgd, Cgs...Capacitors Ld, Lg, Ls...Inductors

Claims

a first conductor provided on a top surface of the first substrate; a first chip provided on the top surface of the first conductor; a second chip provided on the top surface of the first conductor and aligned with the first chip in a first direction; a third chip provided on the top surface of the first conductor and aligned with the first and second chips in the first direction and located on the opposite side of the second chip from the first chip; a second conductor provided on the top surface of the first substrate and spaced apart from the first conductor, having a first portion located between the first chip and the second chip and a second portion located between the second chip and the third chip; and a third conductor connecting between a source electrode of the first chip and the first portion of the second conductor, between the first portion of the second conductor and the source electrode of the second chip, between the source electrode of the second chip and the second portion of the second conductor, and between the second portion of the second conductor and the source electrode of the third chip.

2. The semiconductor device according to claim 1, further comprising: a fourth chip provided on the upper surface of the first conductor and aligned with the first chip in a second direction intersecting the first direction; a fifth chip provided on the upper surface of the first conductor and aligned with the second chip in the second direction; a sixth chip provided on the upper surface of the first conductor and aligned with the third chip in the second direction; and a fourth conductor connecting between the source electrode of the fourth chip and the first portion of the second conductor, between the first portion of the second conductor and the source electrode of the fifth chip, between the source electrode of the fifth chip and the second portion of the second conductor, and between the second portion of the second conductor and the source electrode of the sixth chip.

3. The semiconductor device according to claim 1, further comprising a fifth conductor connecting between the gate electrode of said first chip and the gate electrode of said second chip, and between the gate electrode of said second chip and the gate electrode of said third chip.

4. The semiconductor device according to claim 1, wherein the first conductor and the second conductor are wiring patterns, and the third conductor is a bonding wire, a bonding ribbon, or a connector.

5. The semiconductor device according to claim 2, wherein the distance between said first chip and said fourth chip is more than twice the distance between the upper surface of said first substrate and the lower surface of said first chip.

6. The semiconductor device according to claim 2, further comprising a second substrate provided below said first substrate, said first substrate being an insulating substrate, and said second substrate being a base substrate.

7. The semiconductor device according to claim 6, wherein the distance between said first chip and said fourth chip is longer than twice the distance between the upper surface of said second substrate and the lower surface of said first chip.

8. The semiconductor device according to claim 2, wherein the first chip, the second chip, the third chip, the fourth chip, the fifth chip, and the sixth chip are arranged in a matrix.

9. The semiconductor device according to claim 2, wherein the first chip, the second chip, the third chip, the fourth chip, the fifth chip, and the sixth chip are arranged in a staggered pattern.

10. The semiconductor device according to claim 1, wherein each of the first chip, the second chip, and the third chip functions as a first transistor having a drain electrode on its lower surface and a gate electrode and a source electrode on its upper surface, and is connected in parallel between the first conductor and the second conductor.

11. The semiconductor device according to claim 10, further comprising: a sixth conductor provided on the upper surface of the first substrate at a distance from the first conductor and the second conductor; a second transistor provided on the upper surface of the sixth conductor; and a seventh conductor connecting the source electrode of the second transistor and the first conductor.

12. The semiconductor device according to claim 11, wherein the second transistor has a drain electrode on a lower surface thereof, and a gate electrode and a source electrode on an upper surface thereof.

13. The semiconductor device according to claim 12, further comprising: a first terminal connected to an end of the first conductor; a second terminal connected to an end of the second conductor; and a third terminal connected to an end of the sixth conductor.

14. The semiconductor device according to claim 13, wherein the semiconductor device is a power module.

15. The semiconductor device of claim 2, wherein the second conductor further has a third portion extending in the second direction and located on the opposite side of the third chip from the second portion, the first conductor has a fourth portion, a fifth portion, and a sixth portion each extending in the second direction, the first chip and the fourth chip are provided on an upper surface of the fourth portion, the second chip and the fifth chip are provided on an upper surface of the fifth portion, and the third chip and the sixth chip are provided on an upper surface of the sixth portion.

16. The semiconductor device according to claim 15, wherein the fourth portion, the first portion, the fifth portion, the second portion, the sixth portion, and the third portion are arranged in this order in the first direction.

17. The semiconductor device according to claim 16, wherein the first portion, the second portion, and the third portion are comb-shaped portions of the second conductor, and the fourth portion, the fifth portion, and the sixth portion are comb-shaped portions of the first conductor.

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