Light detection device and electronic apparatus

Abstract

[Problem] To provide a light detection device that can be reduced in size. [Solution] A light detection device according to an embodiment of the present disclosure comprises a first substrate, at least one second substrate laminated on the lower side of the first substrate, and a third substrate laminated on the lower side of the second substrate. The first substrate has a first circuit arrangement region in which a photoelectric conversion circuit for photoelectrically converting incident light is arranged, an opening region provided outside the first circuit arrangement region, and an electrode pad exposed from the opening region. The second substrate has a second circuit arrangement region facing the first circuit arrangement region, and a connection region provided outside the second circuit arrangement region and facing the electrode pad. The third substrate has a third circuit arrangement region facing the second circuit arrangement region, and a fourth circuit arrangement region provided outside the third circuit arrangement region and facing the electrode pad across the connection region.

Description

Photodetector and electronic equipment

[0001] The present disclosure relates to photodetection devices and electronic equipment.

[0002] In recent years, stacked solid-state imaging devices have become widespread as an example of photodetector devices, in which a pixel substrate on which pixels are formed is stacked with a control substrate on which control circuits for controlling the pixels and processing pixel signals are formed. In stacked solid-state imaging devices, opening regions that expose electrode pads are formed on the pixel substrate. The electrode pads are wire-bonded through the opening regions. To avoid damage during wire bonding, circuits on the control substrate are not arranged directly below the electrode pads. Because of these limitations on circuit layout on the control substrate, it is difficult to miniaturize the device.

[0003] International Publication No. 2017 / 126319

[0004] The present disclosure provides a photodetector and electronic equipment that can be miniaturized.

[0005] A photodetector according to one embodiment of the present disclosure comprises a first substrate; at least one second substrate stacked below the first substrate; and a third substrate stacked below the second substrate, wherein the first substrate has a first circuit arrangement area in which a photoelectric conversion circuit that photoelectrically converts incident light is arranged, an opening area provided outside the first circuit arrangement area, and electrode pads exposed from the opening area, the second substrate has a second circuit arrangement area facing the first circuit arrangement area and a connection area provided outside the second circuit arrangement area and facing the electrode pads, and the third substrate has a third circuit arrangement area facing the second circuit arrangement area and a fourth circuit arrangement area provided outside the third circuit arrangement area and facing the electrode pads across the connection area.

[0006] An I / O circuit for performing input and output processing of signals may be arranged in the fourth circuit arrangement area.

[0007] A first through electrode that penetrates the second substrate may be provided in the connection region.

[0008] The material of the first through electrode may be copper (Cu) or tungsten (W).

[0009] The first substrate may be provided with a first contact via electrically connected to the electrode pad and a first lower electrode formed integrally with the first contact via, and the second substrate may be provided with a first upper electrode joined to the first lower electrode and a second contact via formed integrally with the first upper electrode and electrically connected to the first through electrode.

[0010] The first substrate may be provided with a first lower electrode electrically connected to the electrode pad, and the second substrate may be provided with a first upper electrode joined to the first lower electrode and electrically connected to the first through electrode.

[0011] The second substrate may be provided with a third contact via electrically connected to the first through electrode and a second lower electrode formed integrally with the third contact via, and the third substrate may be provided with a second upper electrode joined to the second lower electrode and a fourth contact via formed integrally with the second upper electrode.

[0012] The device may further include a wiring layer provided with wiring electrically connected to the electrode pads, and the electrode pads may be disposed on the same layer as the wiring layer.

[0013] The optical fiber may further include a semiconductor layer on which the photoelectric conversion circuit is provided, and the electrode pads may be disposed in the same layer as the semiconductor layer.

[0014] The electrode pad may be disposed above the surface of the semiconductor layer on the light incident surface side of the semiconductor layer on which the photoelectric conversion circuit is provided.

[0015] The pixel element may further include a sampling and holding circuit that holds a pixel signal output from the photoelectric conversion circuit, and the sampling and holding circuit may be arranged in the second circuit arrangement area.

[0016] The sample and hold circuit may include a first capacitance element that holds a pixel signal at a reset level when the photoelectric conversion circuit is initialized, and a second capacitance element that holds a pixel signal at a data level generated by the photoelectric conversion circuit after the initialization.

[0017] The pixel element may further include an ADC (Analog-to-Digital Converter) circuit that digitally converts pixel signals generated by the photoelectric conversion circuit, and the ADC circuit may be arranged in the second circuit arrangement area.

[0018] The second substrate may have an electrically floating silicon region in which an area directly below the electrode pad is surrounded in a frame shape by an element isolation film made of an insulating film.

[0019] The first through electrode may be disposed in a region surrounded by the element isolation film.

[0020] The first through electrode may be disposed outside a region surrounded by the element isolation film.

[0021] The isolation film may include a first isolation film surrounding the region directly below, and a second isolation film adjacent to the first isolation film and surrounding the first through-electrode.

[0022] At least one second through electrode that penetrates the third substrate may be provided in the fourth circuit arrangement region.

[0023] The second through-electrode may be arranged in a central portion of the fourth circuit arrangement region.

[0024] The fourth circuit arrangement region may be rectangular, and parts of the two second through electrodes may be arranged at corners of the fourth circuit arrangement region.

[0025] The fourth circuit arrangement region may be rectangular, and parts of the four second through electrodes may be arranged on sides of the fourth circuit arrangement region.

[0026] Two of the fourth circuit arrangement regions may be arranged along one direction, and two of the second through electrodes, one of which is arranged in each of the two fourth circuit arrangement regions, may be arranged to be offset in a direction perpendicular to the one direction.

[0027] A portion of one of the second through electrodes may extend outside the fourth circuit arrangement region.

[0028] An I / O circuit for performing input and output processing of signals may be arranged in the fourth circuit arrangement area.

[0029] A portion of the second through-electrode may be disposed in the fourth circuit arrangement region, and the I / O circuit may be disposed outside the second through-electrode.

[0030] The I / O circuits may be arranged in two separate areas within the fourth circuit arrangement region, and the second through-electrode may be arranged between the two separate I / O circuits.

[0031] The photodetector may further include dummy wiring arranged in at least one of a region directly below the electrode pad on the first substrate and the connection region.

[0032] The dummy wiring may be arranged in a region surrounded by the second circuit arrangement region and the connection region.

[0033] The dummy wirings may be arranged in layers.

[0034] The dummy wirings may be arranged in a matrix or a staggered pattern.

[0035] The cross-sectional shape of the dummy wiring may be polygonal or circular.

[0036] The pattern of the dummy wiring may be a stripe pattern or a solid pattern.

[0037] The photodetector may further include a wiring group arranged in the fourth circuit arrangement region, the wiring group including a plurality of wirings connected in a mesh pattern.

[0038] A photodetector according to another embodiment of the present disclosure includes a first substrate; a second substrate stacked below the first substrate; and a third substrate stacked below the second substrate, wherein the first substrate has a first circuit arrangement area in which a photoelectric conversion circuit that photoelectrically converts incident light is arranged, and an opening area provided outside the first circuit arrangement area, the second substrate has a second circuit arrangement area facing the first circuit arrangement area, and a connection area provided outside the second circuit arrangement area and including first electrode pads exposed from the opening area and connection switching transistors electrically connected to the first electrode pads, and the third substrate has a third circuit arrangement area facing the second circuit arrangement area, and a fourth circuit arrangement area facing the connection area outside the third circuit arrangement area, in which electrical connection with the first electrode pads is switched by the connection switching transistor.

[0039] The connection switching transistor may be a MOS transistor with a vertical structure including: a first semiconductor region; a second semiconductor region having an opposite conductivity type to that of the first semiconductor region; a third semiconductor region having the same conductivity type as that of the first semiconductor region and facing the first semiconductor region across the second semiconductor region; and a gate electrode arranged between the first semiconductor region and the third semiconductor region via a gate oxide film.

[0040] The semiconductor device may further include a fourth semiconductor region on a back surface side of the first semiconductor region, the fourth semiconductor region having an impurity concentration higher than that of the first semiconductor region.

[0041] The connection switching transistor may be an IGBT (Insulated Gate Bipolar Transistor) including: a first semiconductor region; a second semiconductor region having an opposite conductivity type to the first semiconductor region; a third semiconductor region having the same conductivity type as the first semiconductor region and facing the first semiconductor region across the second semiconductor region; a fifth semiconductor region having an opposite conductivity type to the first semiconductor region and provided on the back surface side of the first semiconductor region; and a gate electrode arranged between the first semiconductor region and the third semiconductor region via a gate oxide film.

[0042] The connection switching transistor may have a trench-type gate electrode.

[0043] The first semiconductor region and the third semiconductor region may have a P-type conductivity, and the second semiconductor region may have an N-type conductivity.

[0044] The fourth semiconductor region is P ＋ It may be a semiconductor region.

[0045] The fifth semiconductor region is N ＋ It may be a semiconductor region.

[0046] The gate electrode may be of a trench type.

[0047] The first electrode pad may include an input electrode pad which is part of a signal path transmitted from the second substrate to the third substrate, and an output electrode pad which is part of a signal path transmitted from the third substrate to the second substrate, and both a first connection switching transistor connected to the input electrode pad and a second connection switching transistor connected to the output electrode pad may be N-channel type, or the first connection switching transistor may be P-channel type and the second connection switching transistor may be N-channel type.

[0048] The second substrate may have a plurality of first electrode pads, some of which may be electrically connected to the connection switching transistor, and the remaining electrode pads may be electrically connected to through electrodes that penetrate the second substrate.

[0049] The second substrate may have a plurality of connection switching transistors, and may further have an element isolation film provided between the plurality of connection switching transistors.

[0050] The semiconductor device may further include a fourth substrate provided between the second substrate and the third substrate, wherein the third substrate has a second electrode pad electrically connected to the connection switching transistor via the fourth substrate, and the fourth substrate has a third electrode pad electrically connected to the first electrode pad via the connection switching transistor, and another connection switching transistor arranged between the second electrode pad and the third electrode pad.

[0051] The second electrode pad may be exposed from the rear surface side of the second substrate.

[0052] The semiconductor device may further include a bump that joins the second electrode pad and the third electrode pad.

[0053] The second substrate may have a plurality of connection switching transistors, and gate electrodes of the plurality of connection switching transistors may be connected to each other.

[0054] Pixels that generate pixel signals by photoelectrically converting incident light from an object may be arranged in the first circuit arrangement area, a signal processing circuit that processes the pixel signals may be arranged in the second circuit arrangement area, and a DNN (Deep Neural Network) circuit that recognizes the object based on the signals processed by the signal processing circuit may be arranged in the third circuit arrangement area.

[0055] An electronic device according to one embodiment of the present disclosure comprises a photodetector device having a first substrate, at least one second substrate stacked below the first substrate, and a third substrate stacked below the second substrate, wherein the first substrate has a first circuit arrangement area in which a photoelectric conversion circuit that photoelectrically converts incident light is arranged, an opening area provided outside the first circuit arrangement area, and electrode pads exposed from the opening area, the second substrate has a second circuit arrangement area facing the first circuit arrangement area and a connection area provided outside the second circuit arrangement area and facing the electrode pads, and the third substrate has a third circuit arrangement area facing the second circuit arrangement area and a fourth circuit arrangement area provided outside the third circuit arrangement area and facing the electrode pads across the connection area.

[0056] 1 is a block diagram illustrating an example of the configuration of a photodetector according to a first embodiment. FIG. 2 is a diagram illustrating an example of the circuit configuration of a pixel. FIG. 3 is a diagram illustrating an example of a stacked structure of a photodetector according to the first embodiment. FIG. 4 is an exploded perspective view enlarging regions R1 to R3 illustrated in FIG. 3. FIG. 5 is a plan view illustrating an example of the positional relationship between an opening region and a through electrode. FIG. 6 is a plan view illustrating another example of the positional relationship between an opening region and a through electrode. FIG. 7 is a plan view illustrating yet another example of the positional relationship between an opening region and a through electrode. FIG. 8 is a diagram illustrating an example of the stacked structure of a photodetector according to a comparative example. FIG. 9 is a diagram illustrating a circuit configuration of a pixel according to a first modified example. FIG. 10 is a diagram illustrating a circuit configuration of a pixel according to a second modified example. FIG. 11 is a diagram illustrating a circuit configuration of a pixel according to a third modified example. FIG. 12 is a diagram illustrating a circuit configuration of a pixel according to a fifth modified example. FIG. 13 is an exploded perspective view of a portion of a photodetector according to a second embodiment. FIG. 14 is an exploded perspective view of a portion of a photodetector according to a third embodiment. FIG. 15 is an exploded perspective view of a portion of a photodetector according to a third embodiment. FIG. 16 is an exploded perspective view of a portion of a photodetector according to a fourth embodiment. FIG. 17 is an exploded perspective view of a portion of a photodetector according to a fifth embodiment. 10. An exploded perspective view of a portion of a photodetector according to a modified example of the seventh embodiment. A plan view of a portion of a photodetector according to the seventh embodiment. A cross-sectional view of a portion of a photodetector according to the seventh embodiment. An exploded perspective view of a portion of a photodetector according to the eighth embodiment. A cross-sectional view of a portion of a photodetector according to the eighth embodiment. A plan view of a portion of a photodetector according to the eighth embodiment. An exploded perspective view of a portion of a photodetector according to the ninth embodiment. A plan view of a portion of a photodetector according to the ninth embodiment. An exploded perspective view of a portion of a photodetector according to the tenth embodiment. A plan view of a portion of a photodetector according to the tenth embodiment. An exploded perspective view of a portion of a photodetector according to the eleventh embodiment. A plan view showing a modified example of a through electrode. A plan view showing another modified example of a through electrode. A plan view showing yet another modified example of a through electrode. A plan view showing yet another modified example of a through electrode. An exploded perspective view of a portion of a photodetector according to the twelfth embodiment. A plan view of a portion of a photodetector according to the twelfth embodiment.14 is a plan view showing a modified example of the layout of the through electrodes and the I / O circuits. FIG. 15 is a cross-sectional view of a portion of the photodetector according to the thirteenth embodiment. FIG. 16 is a cross-sectional view showing another arrangement of dummy wirings. FIG. 17 is a cross-sectional view showing a matrix arrangement of dummy wirings having circular cross-sectional shapes. FIG. 18 is a cross-sectional view showing a staggered arrangement of dummy wirings having circular cross-sectional shapes. FIG. 19 is a cross-sectional view showing a matrix arrangement of dummy wirings having triangular cross-sectional shapes. FIG. 19 is a cross-sectional view showing a staggered arrangement of dummy wirings having triangular cross-sectional shapes. FIG. 19 is a cross-sectional view showing a matrix arrangement of dummy wirings having triangular cross-sectional shapes. FIG. 19 is a cross-sectional view showing a staggered arrangement of dummy wirings having triangular cross-sectional shapes. FIG. 19 is a cross-sectional view showing a matrix arrangement of dummy wirings having hexagonal cross-sectional shapes. FIG. 19 is a cross-sectional view showing a staggered arrangement of dummy wirings having hexagonal cross-sectional shapes. FIG. 19 is a cross-sectional view showing a dummy wiring having one layer. FIG. 19 is a cross-sectional view showing a dummy wiring having two layers. FIG. 19 is a cross-sectional view showing a dummy wiring having three layers. FIG. 19 is a plan view showing dummy wirings formed in a solid pattern. FIG. 19 is a plan view showing that dummy wirings are also formed between the second circuit arrangement region and the connection region. FIG. 19 is a cross-sectional view of a portion of the photodetector according to the fourteenth embodiment. 52. A cross-sectional view showing that dummy wirings are arranged only in the wiring layer of the second substrate. A cross-sectional view showing that dummy wirings are arranged only in the wiring layer of the first substrate. A plan view enlarging a fourth circuit arrangement region of the second substrate of the photodetector according to the fifteenth embodiment. A cross-sectional view of a part of the photodetector according to the sixteenth embodiment. A diagram showing an example of a stacked structure of the photodetector according to the sixteenth embodiment. A cross-sectional view showing the structure of a connection switching transistor according to the sixteenth embodiment. A cross-sectional view of a part of the photodetector according to the seventeenth embodiment. A cross-sectional view showing a part of a manufacturing process of the photodetector according to the seventeenth embodiment. A cross-sectional view showing a manufacturing process next to that of FIG. 52. A cross-sectional view showing a manufacturing process next to that of FIG. 53. A cross-sectional view of a part of the photodetector according to the eighteenth embodiment. A cross-sectional view showing a part of a manufacturing process of the photodetector according to the eighteenth embodiment. A cross-sectional view showing a manufacturing process next to that of FIG. 56. A cross-sectional view showing a manufacturing process next to that of FIG. 57. A cross-sectional view of a part of the photodetector according to the nineteenth embodiment. A cross-sectional view of a part of the photodetector according to the twentieth embodiment. A cross-sectional view of a part of the photodetector according to the twenty-first embodiment.10 is a cross-sectional view showing the structure of a connection switching transistor according to a 22nd embodiment. FIG. 11 is a cross-sectional view showing the structure of a connection switching transistor according to a 23rd embodiment. FIG. 12 is a cross-sectional view showing the structure of a photodetector according to a 24th embodiment. FIG. 13 is a cross-sectional view showing the structure of a photodetector according to a 25th embodiment. FIG. 14 is a cross-sectional view showing the structure of a photodetector according to a 26th embodiment. FIG. 15 is a cross-sectional view showing the structure of a photodetector according to a 27th embodiment. FIG. 16 is a cross-sectional view showing the structure of a photodetector according to a 28th embodiment. FIG. 17 is a schematic plan view of a connection switching transistor according to a 28th embodiment. FIG. 18 is a cross-sectional view showing the structure of a photodetector according to a 29th embodiment. FIG. 19 ...30th embodiment. FIG. 19 is a cross-sectional view showing the structure of a photodetector according to a modified example of the 30th embodiment. FIG. 19 is a block diagram showing an example of the configuration of an electronic device according to a 31st embodiment. FIG. 19 is a block diagram showing an example of the schematic configuration of a vehicle control system. FIG. 19 is an explanatory diagram showing an example of the installation positions of an outside vehicle information detection unit and an imaging unit.

[0057] 1 is a block diagram showing an example of the configuration of a photodetector according to the first embodiment. The photodetector 1 shown in Fig. 1 includes a pixel array unit 10, a vertical drive unit 20, a column processing unit 30, a horizontal drive unit 40, a system control unit 50, a signal processing unit 60, a data storage unit 70, and an I / O circuit 80.

[0058] The pixel array unit 10 has a plurality of pixels arranged two-dimensionally in a matrix. Each pixel generates a pixel signal by photoelectrically converting incident light. The circuit configuration of the pixel will be described later. Furthermore, a pixel drive line 90 is connected to each pixel row in the pixel array unit 10, and a vertical signal line 91 is connected to each pixel column.

[0059] The vertical drive unit 20 is configured with a shift register, an address decoder, etc., and drives each pixel of the pixel array unit 10 in row units, etc. One end of a pixel drive line 90 is connected to an output terminal of the vertical drive unit 20 corresponding to each pixel row.

[0060] The column processing unit 30 has a signal processing circuit for each pixel column of the pixel array unit 10. Each signal processing circuit of the column processing unit 30 performs signal processing such as noise removal processing such as CDS (Correlated Double Sampling) processing and A / D (Analog / Digital) conversion processing on pixel signals output from each pixel of a selected row through a vertical signal line 91. The column processing unit 30 temporarily holds the pixel signals after signal processing.

[0061] The horizontal driving unit 40 is configured with a shift register, an address decoder, etc., and sequentially selects the signal processing circuits of the column processing unit 30. By selective scanning by this horizontal driving unit 40, pixel signals that have been signal-processed by each signal processing circuit of the column processing unit 30 are output to the signal processing unit 60 in sequence.

[0062] The system control unit 50 is composed of a timing generator that generates various timing signals, and controls the vertical drive unit 20, the column processing unit 30, and the horizontal drive unit 40 based on the various timing signals generated by the timing generator.

[0063] The signal processing unit 60 has at least an addition processing function. The signal processing unit 60 performs various signal processing such as addition processing on the pixel signals output from the column processing unit 30. At this time, the signal processing unit 60 stores intermediate results of the signal processing in the data storage unit 70 as necessary and refers to them at the necessary timing. The signal processing unit 60 outputs the pixel signals after signal processing.

[0064] The data storage unit 70 is configured by a dynamic random access memory (DRAM) or a static random access memory (SRAM).

[0065] The I / O circuit 80 is a circuit that performs input / output processing of signals. This input / output processing includes processing of outputting pixel signals that have been input from the signal processing unit 60 and have undergone predetermined signal processing to the outside of the device. This input / output processing also includes processing of outputting signals supplied from an external device to the external device via the signal processing unit 60, the horizontal drive unit 40, etc. This input / output processing also includes processing of supplying power supplied from an external device to the power supply circuit.

[0066] Fig. 2 is a diagram showing an example of a circuit configuration of a pixel. The pixel 11 shown in Fig. 2 has a photoelectric conversion circuit 110, a first source follower circuit 120, a sample-and-hold circuit 130, and a second source follower circuit 140. Each circuit will be described below.

[0067] The photoelectric conversion circuit 110 has a photodiode 111, a transfer transistor 112, a first reset transistor 113, and a discharge transistor 114. The transfer transistor 112, the first reset transistor 113, and the discharge transistor 114 are configured by, for example, an N-channel MOS transistor.

[0068] The photodiode 111 photoelectrically converts incident light to generate an electric charge. The anode of the photodiode 111 is connected to the ground having a reference potential. The cathode of the photodiode 111 is connected to the transfer transistor 112 and the drain transistor 114.

[0069] The transfer transistor 112 transfers electric charges from the photodiode 111 to a floating diffusion (FD) in accordance with a transfer signal TRG input to its gate from the vertical drive unit 20 via a pixel drive line 90. The FD accumulates the electric charges and generates a pixel signal indicated by a voltage corresponding to the amount of the electric charges. The drain of the transfer transistor 112 is connected to the cathode of the photodiode 111, and the source is connected to the FD.

[0070] The first reset transistor 113 performs initialization by extracting charge from the FD in accordance with a first reset signal RST input to its gate from the vertical drive unit 20 through the pixel drive line 90. The drain of the first reset transistor 113 is connected to a power supply line having the potential of the power supply voltage VDD, and the source is connected to the FD.

[0071] The discharge transistor 114 discharges and initializes the charge accumulated in the photodiode 111 in accordance with a discharge signal OFG input to its gate from the vertical drive unit 20 through the pixel drive line 90. The drain of the discharge transistor 114 is connected to the cathode of the photodiode 111 and the drain of the transfer transistor 112. The source of the discharge transistor 114 is connected to the power supply line.

[0072] The first source follower circuit 120 includes a first amplifier transistor 121, a first selection transistor 122, a bias cut transistor 123, and a load transistor 124. The transistors are connected in series between a power supply line having the potential of the power supply voltage VDD and the ground, and are configured, for example, by N-channel MOS transistors.

[0073] The first amplifier transistor 121 amplifies the voltage level of the pixel signal generated by the FD to a voltage V1 and outputs the amplified voltage to the sample-and-hold circuit 130. The gate of the first amplifier transistor 121 is connected to the FD. The drain is connected to the power supply line. The source is connected to the drain of the first selection transistor 122.

[0074] The first selection transistor 122 switches whether or not to transmit the pixel signal amplified by the first amplifier transistor 121 to the sampling and holding circuit 130, in accordance with a switching signal SW input to its gate from the vertical drive unit 20 through the pixel drive line 90. The drain of the first selection transistor 122 is connected to the source of the first amplifier transistor 121, and the source is connected to the sampling and holding circuit 130 and the drain of the bias cut transistor 123.

[0075] The bias cut transistor 123 switches whether or not to supply current from the load transistor 124 in accordance with a bias cut signal PC input to its gate from the vertical drive unit 20 through the pixel drive line 90. The source of the bias cut transistor 123 is connected to the drain of the load transistor 124.

[0076] The load transistor 124 supplies a predetermined current into the first source follower circuit 120 in accordance with a bias signal VB input to its gate from the vertical drive unit 20 through the pixel drive line 90. The source of the load transistor 124 is connected to ground.

[0077] The sample-and-hold circuit 130 includes a first capacitance element 131, a second capacitance element 132, a first sampling transistor 133, a second sampling transistor 134, and a second reset transistor 135. Each transistor is configured, for example, by an N-channel MOS transistor.

[0078] One end of each of the first capacitance element 131 and the second capacitance element 132 is commonly connected to the output terminal of the first source follower circuit 120 (the source of the first selection transistor 122). The other end of the first capacitance element 131 is connected to the drain of the first sampling transistor 133. The other end of the second capacitance element 132 is connected to the drain of the second sampling transistor 134.

[0079] The first sampling transistor 133 switches whether or not to output the pixel signal held in the first capacitance element 131 to the output node 136, in accordance with a first sampling signal SR input to the gate from the vertical drive unit 20 through the pixel drive line 90. The source of the first sampling transistor 133 is connected to the output node 136.

[0080] The second sampling transistor 134 switches whether or not to output the pixel signal held in the second capacitance element 132 to the output node 136, in accordance with a second sampling signal SD input to its gate from the vertical drive unit 20 through the pixel drive line 90. The source of the second sampling transistor 134 is also connected to the output node 136 in common with the source of the first sampling transistor 133.

[0081] The second reset transistor 135 initializes the voltage V2 of the output node 136 to a predetermined voltage VREG in accordance with a second reset signal RB input to its gate from the vertical drive unit 20 through the pixel drive line 90. The voltage VREG is set to a potential lower than the power supply voltage VDD. The drain of the second reset transistor 135 is connected to a voltage wiring having the potential of the voltage VREG, and the source is connected to the output node 136.

[0082] The second source follower circuit 140 is a circuit that selectively reads out and amplifies a signal from the sample-and-hold circuit 130, and includes a second amplifier transistor 141, a second selection transistor 142, and a current source 143. The second amplifier transistor 141 and the second selection transistor 142, which are connected in series with each other, are configured by, for example, N-channel MOS transistors.

[0083] The gate of the second amplifier transistor 141 is connected to the output node 136 of the sample-and-hold circuit 130. The drain is connected to a power supply line having the potential of the power supply voltage VDD. The source is connected to the drain of the second selection transistor 142.

[0084] The second selection transistor 142 switches whether or not to output the pixel signal amplified by the second amplifier transistor 141 to the signal line VSL, in accordance with a second selection signal SEL input to its gate from the vertical drive unit 20 through the pixel drive line 90. The source of the second selection transistor 142 is connected to the signal line VSL and the current source 143.

[0085] The current source 143 is connected in series to the second selection transistor 142. The current source 143 supplies a constant current to the second amplifier transistor 141 and the second selection transistor 142 in accordance with a control signal input to the gate from the vertical drive unit 20 through the pixel drive line 90.

[0086] In the photodetector 1 configured as described above, at the start of exposure, the vertical drive unit 20 supplies a first reset signal RST and a transfer signal TRG of high level to all pixels 11. This initializes the photodiodes 111.

[0087] Next, just before the end of exposure, the vertical drive unit 20 supplies a high-level first reset signal RST over a pulse period while setting the second reset signal RB and the first sampling signal SR to high levels for all pixels 11. This initializes the FD, and a pixel signal corresponding to the voltage level of the FD at that time is held in the first capacitance element 131.

[0088] After that, at the end of exposure, the vertical drive unit 20 supplies a high-level transfer signal TRG for the pulse period while setting the second reset signal RB and the second sampling signal SD to high levels for all pixels 11. As a result, a signal charge according to the amount of exposure is transferred to the FD, and a pixel signal according to the level of the FD at that time is held in the second capacitance element 132.

[0089] This exposure control, in which exposure starts and ends simultaneously for all pixels 11, is called a global shutter system. This exposure control causes the photoelectric conversion circuits 110 of all pixels 11 to generate pixel signals of reset level and data level in sequence. The pixel signals of the reset level are held in the first capacitance element 131, and the pixel signals of the data level are held in the second capacitance element 132.

[0090] After the exposure is completed, the vertical drive unit 20 sequentially selects rows and sequentially outputs pixel signals of the reset level and data level for the selected rows. When outputting pixel signals of the reset level, the vertical drive unit 20 sets the first reset signal RST and second selection signal SEL of the selected row to high level and supplies the first sampling signal SR of high level for a predetermined period. This connects the first capacitance element 131 to the output node 136, and the reset level is read out.

[0091] After reading out the reset level, the vertical drive unit 20 supplies a high-level second reset signal RB for the pulse period while keeping the first reset signal RST and second selection signal SEL for the selected row at a high level. This initializes the voltage level of the output node 136. At this time, the first sampling transistor 133 and the second sampling transistor 134 are both in the off state, so the first capacitive element 131 and the second capacitive element 132 are disconnected from the output node 136.

[0092] After initializing the output node 136, the vertical drive unit 20 supplies a high-level second sampling signal SD for a predetermined period while keeping the first reset signal RST and the second selection signal SEL for the selected row at a high level, thereby connecting the second capacitance element 132 to the output node 136 and reading out a pixel signal at a data level.

[0093] Fig. 3 is a diagram showing an example of the stacked structure of the photodetector 1 according to the first embodiment. Fig. 4A is an exploded perspective view enlarging regions R1 to R3 shown in Fig. 3. As shown in Figs. 3 and 4A, the photodetector 1 according to this embodiment includes a first semiconductor chip 201, a second semiconductor chip 202, and a third semiconductor chip 203. Each semiconductor chip is formed of, for example, a silicon chip.

[0094] The first semiconductor chip 201 is a top chip located in the uppermost layer. The first substrate 210 of the first semiconductor chip 201 has a first circuit arrangement region 211 and an opening region 212. In the first circuit arrangement region 211, for example, the photoelectric conversion circuit 110 and the first amplifier transistor 121 and the first selection transistor 122 of the first source follower circuit 120 are arranged. The opening region 212 is provided on the periphery of the first circuit arrangement region 211. An electrode pad 213 is arranged directly below the opening region 212. The electrode pad 213 is formed using, for example, aluminum. A bonding wire is bonded to the electrode pad 213 through the opening region 212.

[0095] The second semiconductor chip 202 is a middle chip located in the intermediate layer. The second substrate 220 of the second semiconductor chip 202 has a second circuit arrangement region 221 and a connection region 222. The second circuit arrangement region 221 faces the first circuit arrangement region 211 of the first substrate 210 in the stacking direction. The bias cut transistor 123 and the load transistor 124 of the first source follower circuit 120 are arranged in the second circuit arrangement region 221. The sample and hold circuit 130 and the second source follower circuit 140 are also arranged in the second circuit arrangement region 221. Although not shown in FIG. 3 , the pixel drive line 90 and the vertical signal line 91 are also arranged in the second circuit arrangement region 221.

[0096] The connection region 222 faces the electrode pad 213 in the stacking direction. In the connection region 222, the electrode pad 213 and the second substrate 220 are electrically connected by hybrid bonding. Here, an example of the connection between the electrode pad 213 and the second substrate 220 will be described.

[0097] 4A , a first substrate 210 is provided with a first contact via 214 and a first lower electrode 215. The first contact via 214 is electrically connected to an electrode pad 213. The first lower electrode 215 is integrated with the first contact via 214. The first contact via 214 and the first lower electrode 215 can be formed simultaneously by, for example, a dual damascene process using copper.

[0098] On the other hand, the second substrate 220 is provided with a first upper electrode 223 and a second contact via 224. The first upper electrode 223 is bonded to the first lower electrode 215 of the first substrate 210. The second contact via 224 is integrated with the first upper electrode 223. The first upper electrode 223 and the second contact via 224 can also be formed simultaneously by a dual damascene process using copper. In this case, the second substrate 220 is bonded to the first substrate 210 by so-called Cu-Cu bonding.

[0099] The connection region 222 also has a through electrode 225 (first through electrode) that penetrates the second substrate 220 in the stacking direction. The through electrode 225 is, for example, a through-silicon via (TSV). The first substrate 210 and the third substrate 230 are electrically connected via this through electrode 225. The through electrode 225 can be formed using copper or tungsten (W). For example, when tungsten (W) is used, the through electrode 225 can be formed so that the via diameter of the TSV is 50 nm to 1 μm (preferably 150 nm).

[0100] In this embodiment, the second semiconductor chip 202 has one second substrate 220. However, there is no particular limitation on the number of second substrates 220, and multiple second substrates 220 may be stacked. In other words, it is sufficient that there is at least one second substrate 220.

[0101] The third semiconductor chip 203 is a bottom chip located in the lowest layer. The third substrate 230 of the third semiconductor chip 203 has a third circuit arrangement area 231 and a fourth circuit arrangement area 232. The third circuit arrangement area 231 faces the second circuit arrangement area 221 of the second substrate 220 in the stacking direction. The third circuit arrangement area 231 is equipped with a vertical drive unit 20, a column processing unit 30, a horizontal drive unit 40, a system control unit 50, a signal processing unit 60, and a data storage unit. The third circuit arrangement area 231 may also be equipped with a power supply circuit such as a PLL (Phase Locked Loop) or an electronic circuit such as a DAC (Digital to Analog Converter).

[0102] The fourth circuit arrangement region 232 faces the connection region 222 of the second substrate 220 in the stacking direction. At least a portion of the I / O circuit 80 is arranged in the fourth circuit arrangement region 232. Furthermore, in the fourth circuit arrangement region 232, the second substrate 220 and the third substrate 230 are electrically connected by hybrid bonding. Here, an example of the connection between the second substrate 220 and the third substrate 230 will be described.

[0103] 4A , a through electrode 225, wiring, a wiring interlayer film, a third contact via 226, and a second lower electrode 227 are provided on the back surface side (lower substrate surface) of the second substrate 220. The third contact via 226 is electrically connected to the through electrode 225 via wiring, and a wiring 228 may be present between the through electrode 225 and the third contact via 226. The second lower electrode 227 is integrated with the third contact via 226. The third contact via 226 and the second lower electrode 227 can be formed simultaneously by, for example, a dual damascene process using copper.

[0104] On the other hand, the third substrate 230 is provided with a second upper electrode 233 and a fourth contact via 234. The second upper electrode 233 is bonded to the second lower electrode 227 of the second substrate 220. The fourth contact via 234 is integrated with the second upper electrode 233. The second upper electrode 233 and the third contact via 226 can also be formed simultaneously by a dual damascene process using copper. In this case, the third substrate 230 is bonded to the second substrate 220 by so-called Cu-Cu bonding.

[0105] 4B is a plan view showing an example of the positional relationship between the opening region 212 and the through electrodes 225. In Fig. 4B, the plurality of through electrodes 225 are arranged along the outer periphery of the opening region 212, with portions of the through electrodes 225 overlapping the opening region 212.

[0106] 4C is a plan view showing another example of the positional relationship between the opening region 212 and the through electrodes 225. In FIG. 4C, some of the plurality of through electrodes 225 are aligned along the periphery of the opening region 212 while overlapping the opening region 212. Furthermore, the remainder of the plurality of through electrodes 225, excluding the aforementioned portion, are located completely inside the opening region 212. By arranging the through electrodes 225 in this manner, it is possible to achieve low resistance in the opening region 212.

[0107] 4D is a plan view showing yet another example of the positional relationship between the opening region 212 and the through electrodes 225. In FIG. 4D, at least one through electrode 225 is located completely inside the opening region 212. In other words, the through electrodes 225 are not arranged along the outer periphery of the opening region 212. By arranging the through electrodes 225 in this manner, it is possible to reduce the capacitance of the opening region 212.

[0108] Here, the present embodiment and a comparative example will be described with reference to Fig. 5. Fig. 5 is a diagram showing an example of a layered structure of a photodetector 100 according to the comparative example. Note that components similar to those in the photodetector 1 according to the first embodiment described above are given the same reference numerals, and detailed description thereof will be omitted.

[0109] 5 has a two-layer structure in which a first semiconductor chip 201a and a second semiconductor chip 202a are stacked. A first substrate 210a of the first semiconductor chip 201a has a first circuit arrangement region 211 and an opening region 212. The pixel array unit 10 is arranged in the first circuit arrangement region 211. Electrode pads 213 are arranged in the opening region 212.

[0110] On the second substrate 220a of the second semiconductor chip 202a, circuits are not arranged in the area directly below the electrode pads 213 to avoid damage during wire bonding. Therefore, the I / O circuit 80 is arranged in the second circuit arrangement area 221, similar to the vertical drive unit 20 to the data storage unit 70. As such, in this comparative example, the area directly below the electrode pads 213 on the second substrate 220a cannot be used as a circuit arrangement area. Therefore, in order to secure an area for the arrangement of the I / O circuit 80, the size of the second substrate 220a becomes larger.

[0111] In contrast, in the photodetector 1 according to this embodiment, as described above, the second substrate 220 is inserted between the electrode pads 213 and the I / O circuit 80. This increases the distance from the electrode pads 213 to the I / O circuit 80 compared to the comparative example, and the second substrate 220 functions as a buffer during wire bonding. This reduces damage during wire bonding. As a result, at least a portion of the I / O circuit 80 can be disposed in the fourth circuit arrangement region 232, which is the region directly below the electrode pads 213, making it possible to reduce the chip size. This allows the photodetector 1 to be miniaturized.

[0112] Furthermore, in this embodiment, the joints between the first substrate 210 and the second substrate 220 and the joints between the second substrate 220 and the third substrate 230 are also disposed inside the regions directly below the electrode pads 213. This makes it possible to further reduce the chip size.

[0113] (First Modification) Fig. 6 is a diagram showing the circuit configuration of a pixel according to a first modification. In Fig. 6, the same circuit elements as those of the pixel 11 according to the first embodiment are denoted by the same reference numerals. The pixel 11a shown in Fig. 6 has a photoelectric conversion circuit 110a, a first source follower circuit 120a, a sample-and-hold circuit 130a, and a second source follower circuit 140a.

[0114] The photoelectric conversion circuit 110a has a photodiode 111, a transfer transistor 112, and a first reset transistor 113. These circuit elements have been described in the first embodiment, so detailed description thereof will be omitted.

[0115] The first source follower circuit 120a has a first amplifier transistor 121 and a bias cut transistor 123. These circuit elements have also been described in the first embodiment, so detailed description thereof will be omitted.

[0116] The sample-and-hold circuit 130a includes a first capacitance element 131, a second capacitance element 132, a first sampling transistor 133, and a second sampling transistor 134. In the sample-and-hold circuit 130a, one end of each of the first capacitance element 131 and the second capacitance element 132 is connected to a power supply line having the potential of the power supply voltage VDD. The other end of the first capacitance element 131 is connected to the source of the first sampling transistor 133. The other end of the second capacitance element 132 is connected to the source of the second sampling transistor 134.

[0117] The first sampling transistor 133 switches whether or not to hold the pixel signal amplified by the first source follower circuit 120a in the first capacitance element 131, in accordance with a first sampling signal SR input to its gate from the vertical drive unit 20 through the pixel drive line 90. On the other hand, the second sampling transistor 134 switches whether or not to hold the pixel signal amplified by the first source follower circuit 120a in the second capacitance element 132, in accordance with a second sampling signal SD input to its gate from the vertical drive unit 20 through the pixel drive line 90. The drains of the sampling transistors are commonly connected to the output terminal of the first source follower circuit 120a.

[0118] The second source follower circuit 140a includes a second amplifier transistor 141, a second selection transistor 142, and a current source 143. In the second source follower circuit 140a, these circuit elements are connected to the first capacitance element 131 and the second capacitance element 132, respectively, to form a pair.

[0119] In the pixel 11a configured as described above, for example, the photoelectric conversion circuit 110a and the first amplifier transistor 121 of the first source follower circuit 120a are arranged on the first substrate 210. Furthermore, the bias cut transistor 123 of the first source follower circuit 120a, the sampling and holding circuit 130a, and the second source follower circuit 140a are arranged on the second substrate 220. However, the arrangement of the pixel 11a on the first substrate 210 and the second substrate 220 is not limited to the arrangement described above.

[0120] In this modification, as in the first embodiment described above, the I / O circuit 80 is arranged in the fourth circuit arrangement region 232 of the third substrate 230, which is the region directly below the electrode pads 213. This allows the chip size to be reduced, thereby enabling the device to be miniaturized.

[0121] (Second Modification) Fig. 7 is a diagram showing the circuit configuration of a pixel according to a second modification. In Fig. 7, the same circuit elements as those of the pixel 11 according to the first embodiment are denoted by the same reference numerals. The pixel 11b shown in Fig. 7 has a photoelectric conversion circuit 110b, a first source follower circuit 120b, a sample-and-hold circuit 130b, and a second source follower circuit 140b.

[0122] The photoelectric conversion circuit 110b has a photodiode 111, a transfer transistor 112, and a first reset transistor 113. These circuit elements have been described in the first embodiment, so detailed description thereof will be omitted.

[0123] The first source follower circuit 120b has a first amplifier transistor 121 and a bias cut transistor 123. These circuit elements have also been described in the first embodiment, and therefore detailed description thereof will be omitted.

[0124] The sample-and-hold circuit 130b includes a first capacitance element 131, a second capacitance element 132, a first sampling transistor 133, and a second sampling transistor 134. In the sample-and-hold circuit 130b, one end of the first capacitance element 131 is connected to a power supply line having the potential of the power supply voltage VDD. The other end of the first capacitance element 131 is connected to the source of the first sampling transistor 133 and one end of the second capacitance element 132. The other end of the second capacitance element 132 is connected to an output node 136.

[0125] The first sampling transistor 133 switches whether or not to hold the pixel signal amplified by the first source follower circuit 120a in the first capacitance element 131 and the second capacitance element 132, in accordance with a first sampling signal SR input to its gate from the vertical drive unit 20 through the pixel drive line 90. The drains of the first sampling transistor 133 are commonly connected to the output terminal of the first source follower circuit 120a.

[0126] The second sampling transistor 134 resets the potential of the output node 136 in accordance with a second sampling signal SD input to its gate from the vertical drive unit 20 through the pixel drive line 90. The drain of the second sampling transistor 134 is connected to the power supply line, and the source is connected to the output node 136.

[0127] The second source follower circuit 140b has a second amplifier transistor 141, a second selection transistor 142, and a current source 143. These circuit elements have been described in the first embodiment, so detailed description thereof will be omitted.

[0128] In the pixel 11b configured as described above, for example, the photoelectric conversion circuit 110b and the first amplifier transistor 121 of the first source follower circuit 120b are arranged on the first substrate 210. Furthermore, the bias cut transistor 123 of the first source follower circuit 120b, the sampling and holding circuit 130b, and the second source follower circuit 140b are arranged on the second substrate 220. However, the arrangement of the pixel 11b on the first substrate 210 and the second substrate 220 is not limited to the arrangement described above.

[0129] In this modification, as in the first embodiment described above, the I / O circuit 80 is arranged in the fourth circuit arrangement region 232 of the third substrate 230, which is the region directly below the electrode pads 213. This allows the chip size to be reduced, thereby enabling the device to be miniaturized.

[0130] (Third Modification) Fig. 8 is a diagram showing the circuit configuration of a pixel according to a third modification. In Fig. 8, the same circuit elements as those of the pixel 11 according to the first embodiment are denoted by the same reference numerals. The pixel 11c shown in Fig. 8 has a photoelectric conversion circuit 110c, a first source follower circuit 120c, a sample-and-hold circuit 130c, and a second source follower circuit 140c.

[0131] The photoelectric conversion circuit 110c has a photodiode 111, a transfer transistor 112, and a first reset transistor 113. These circuit elements have been described in the first embodiment, so detailed description thereof will be omitted.

[0132] The first source follower circuit 120c has a first amplifier transistor 121, a bias cut transistor 123, and a load transistor 124. These circuit elements have also been described in the first embodiment, so detailed description thereof will be omitted.

[0133] The sample-and-hold circuit 130c includes a first capacitance element 131, a second capacitance element 132, a first sampling transistor 133, a second sampling transistor 134, and a switching transistor 137. In the sample-and-hold circuit 130c, one end of each of the first capacitance element 131 and the second capacitance element 132 is connected to a power supply line having the potential of the power supply voltage VDD. The other end of the first capacitance element 131 is connected to the drain of the first sampling transistor 133. The other end of the second capacitance element 132 is connected to the drain of the second sampling transistor 134.

[0134] The first sampling transistor 133 switches whether to output the pixel signal held in the first capacitance element 131 to the second source follower circuit 140c in accordance with a first sampling signal SR input to its gate from the vertical drive unit 20 through the pixel drive line 90. The source of the first sampling transistor 133 is connected to the source of the switching transistor 137 and the output node 136.

[0135] The second sampling transistor 134 switches whether to output the pixel signal held in the second capacitance element 132 to the second source follower circuit 140c in accordance with a second sampling signal SD input to its gate from the vertical drive unit 20 through the pixel drive line 90. The source of the second sampling transistor 134 is connected to the source of the switching transistor 137 and the output node 136.

[0136] The switching transistor 137 is composed of an N-channel MOS transistor. A switching signal SH is input to the gate of the switching transistor 137 from the vertical drive unit 20 through the pixel drive line 90. When the switching transistor 137 is turned on based on the switching signal SH, the signal amplified by the first source follower circuit 120c is held in the first capacitance element 131 or the second capacitance element 132.

[0137] The second source follower circuit 140c has a second amplifier transistor 141, a second selection transistor 142, and a current source 143. These circuit elements have been described in the first embodiment, so detailed description thereof will be omitted.

[0138] In the pixel 11c configured as described above, for example, the photoelectric conversion circuit 110c and the first amplifier transistor 121 of the first source follower circuit 120c are arranged on the first substrate 210. Furthermore, the bias cut transistor 123 and the load transistor 124 of the first source follower circuit 120c, the sample and hold circuit 130b, and the second source follower circuit 140b are arranged on the second substrate 220. However, the arrangement of the pixel 11c on the first substrate 210 and the second substrate 220 is not limited to the arrangement described above.

[0139] In this modification, as in the first embodiment described above, the I / O circuit 80 is arranged in the fourth circuit arrangement region 232 of the third substrate 230, which is the region directly below the electrode pads 213. This allows the chip size to be reduced, thereby enabling the device to be miniaturized.

[0140] (Fourth Modification) Fig. 9 is a diagram showing the circuit configuration of a pixel according to a fourth modification. Note that in Fig. 9, the same circuit elements as those of the pixel 11 according to the first embodiment described above are denoted by the same reference numerals. The pixel 11d shown in Fig. 9 has a photoelectric conversion circuit 110d, a first source follower circuit 120d, a sample-and-hold circuit 130d, and a second source follower circuit 140d.

[0141] The photoelectric conversion circuit 110d has a photodiode 111, a transfer transistor 112, a first reset transistor 113, a switching transistor 116, and a capacitance element 117. The switching transistor 116 is configured as an N-channel MOS transistor and is arranged between the first reset transistor 113 and the FD. One end of the capacitance element 117 is connected to the drain of the switching transistor 116, and the other end is grounded. A drive signal FDG is input to the gate of the switching transistor 116 from the vertical drive unit 20. When the switching transistor 116 is turned on based on the drive signal FDG, the charge held in the capacitance element 117 is transferred to the FD.

[0142] The circuit configurations of the first source follower circuit 120d, the sampling and holding circuit 130d, and the second source follower circuit 140d are the same as those in the first embodiment, and therefore description thereof will be omitted. However, in this modification, the second reset transistor 135 of the sampling and holding circuit 130d and the second source follower circuit 140d are shared by four pixels 11d.

[0143] In this modification, of the pixel 11d, the photoelectric conversion circuit 110d and the first amplifier transistor 121 and the first selection transistor 122 of the first source follower circuit 120d are arranged on the first substrate 210. The remaining circuit elements of the pixel 11d are arranged on the second substrate 220. However, the arrangement of the pixel 11d on the first substrate 210 and the second substrate 220 is not limited to the above arrangement.

[0144] In the pixel 11d configured as described above, as in the first embodiment described above, the I / O circuit 80 is arranged in the fourth circuit arrangement region 232 of the third substrate 230, which is the region directly below the electrode pad 213. This allows the chip size to be reduced, thereby enabling the device to be miniaturized.

[0145] (Fifth Modification) Fig. 10 is a diagram showing the circuit configuration of a pixel according to a fifth modification. In Fig. 10, the same circuit elements as those of the pixel 11 according to the first embodiment are denoted by the same reference numerals. The pixel 11e shown in Fig. 10 has a photoelectric conversion circuit 110e, a first source follower circuit 120e, a sample-and-hold circuit 130e, and a second source follower circuit 140e.

[0146] The photoelectric conversion circuit 110e has a photodiode 111, a transfer transistor 112, a first reset transistor 113, a drain transistor 114, a switching transistor 116, and a capacitance element 117. That is, the photoelectric conversion circuit 110e according to this modification has a configuration that includes the circuit elements of the photoelectric conversion circuit 110d according to the fourth modification, as well as a drain transistor 114. The drain transistor 114 is the same as in the first embodiment, and therefore a description thereof will be omitted.

[0147] Furthermore, the circuit configurations of the first source follower circuit 120e, the sample-and-hold circuit 130e, and the second source follower circuit 140e are also similar to those in the first embodiment, and therefore description thereof will be omitted.

[0148] In this modification, of the pixels 11e, the first amplifier transistor 121 and the first selection transistor 122 of the photoelectric conversion circuit 110e and the first source follower circuit 120e are arranged on the first substrate 210. The remaining circuit elements of the pixels 11e are arranged on the second substrate 220. However, the arrangement of the pixels 11e on the first substrate 210 and the second substrate 220 is not limited to the arrangement described above.

[0149] In the pixel 11e configured as described above, as in the first embodiment described above, the I / O circuit 80 is arranged in the fourth circuit arrangement region 232 of the third substrate 230, which is the region directly below the electrode pad 213. This allows the chip size to be reduced, thereby enabling the device to be miniaturized.

[0150] Second Embodiment Fig. 11 is an exploded perspective view of a portion of a photodetector 2 according to a second embodiment. Fig. 12 is a cross-sectional view of a portion of a photodetector 2 according to the second embodiment. In Figs. 11 and 12, the same components as those in the first embodiment described above are denoted by the same reference numerals, and detailed description thereof will be omitted.

[0151] 12, the first semiconductor chip 201 of the photodetector 2 according to this embodiment includes a stack of a light collection layer 301, a semiconductor layer 302, and a wiring layer 303. The light collection layer 301 and the wiring layer 303 face each other with the semiconductor layer 302 sandwiched therebetween.

[0152] On-chip microlenses 311, color filters 312, and the like are formed on the light collection layer 301. Incident light incident on the upper surface of the light collection layer 301 is collected by the on-chip microlenses 311 onto photodiodes 111 (not shown) formed on the semiconductor layer 302.

[0153] Although not shown, the semiconductor layer 302 is provided with semiconductor elements of the photoelectric conversion circuit 110 including the photodiode 111. Also, an electrode pad 213 is provided in the same layer as the semiconductor layer 302. The electrode pad 213 is formed, for example, in a front end of line (FEOL) process.

[0154] The wiring layer 303 is provided with wirings electrically connected to the electrode pad 213, such as a through electrode 217, a first contact via 214, and a first lower electrode 215. The through electrode 217 is formed using, for example, copper. One end of the through electrode 217 is electrically connected to the electrode pad 213, and the other end is connected to the first contact via 214. The first contact via 214 and the first lower electrode 215 are integrally formed by a dual damascene process, as in the first embodiment.

[0155] 11 , in this embodiment, the I / O circuit 80 is arranged in a fourth circuit arrangement region 232 of the third substrate 230, which is an area directly below the electrode pads 213. This allows the chip size to be reduced, and therefore the photodetector 2 can be made smaller.

[0156] Third Embodiment Fig. 13 is an exploded perspective view of a portion of a photodetector 3 according to a third embodiment. Fig. 14 is a cross-sectional view of a portion of a photodetector 3 according to the third embodiment. In Figs. 13 and 14, the same components as those in the second embodiment described above are denoted by the same reference numerals, and detailed description thereof will be omitted. In the photodetector 2 according to the second embodiment described above, the electrode pad 213 is provided on the semiconductor layer 302.

[0157] On the other hand, in the photodetector 3 according to this embodiment, the electrode pad 213 is provided on the wiring layer 303. The electrode pad 213 is formed, for example, by a reverse end of line (REOL) process. In the wiring layer 303, the electrode pad 213 is electrically connected to an upper end of the through electrode 217. A lower end of the through electrode 217 is electrically connected to the first lower electrode 215 via a first contact via 214. The first contact via 214 and the first lower electrode 215 are integrally formed by a dual damascene process, as in the second embodiment.

[0158] In this embodiment, as in the first and second embodiments described above, the I / O circuit 80 is arranged in the fourth circuit arrangement region 232 of the third substrate 230, which is the region directly below the electrode pad 213. This allows the chip size to be reduced in this embodiment as well, making it possible to miniaturize the photodetector 3.

[0159] 15 is an exploded perspective view of a portion of a photodetector 4 according to a fourth embodiment. In FIG. 15, components similar to those in the first embodiment described above are denoted by the same reference numerals, and detailed description thereof will be omitted. In the photodetector 1 according to the first embodiment described above, the first lower electrode 215 is formed integrally with the first contact via 214 by a dual damascene process, and the first upper electrode 223 is formed integrally with the second contact via 224.

[0160] On the other hand, in the photodetector 4 according to this embodiment, the first lower electrode 215 and the first upper electrode 223 are formed by a single damascene process. Therefore, as shown in Fig. 15, the first lower electrode 215 is not integrally formed with the first contact via 214, and the first upper electrode 223 is not integrally formed with the second contact via 224. That is, in this embodiment, the single first lower electrode 215 and the single first upper electrode 223 are joined together.

[0161] In this embodiment, as in the first to third embodiments described above, the I / O circuit 80 is arranged in the fourth circuit arrangement region 232 of the third substrate 230, which is the region directly below the electrode pads 213. This allows the chip size to be reduced in this embodiment as well, thereby enabling the photodetector 4 to be miniaturized.

[0162] Fifth Embodiment Fig. 16 is an exploded perspective view of a part of a photodetector 5 according to a fifth embodiment. In Fig. 16, the same components as those in the first embodiment described above are denoted by the same reference numerals, and detailed description thereof will be omitted.

[0163] In the photodetector 5 according to this embodiment, the second substrate 220 of the photodetector 1 according to the first embodiment is inverted by 180 degrees. That is, in this embodiment, the through electrode 225 is electrically connected to the first upper electrode 223 through the second contact via 224.

[0164] In this embodiment, as in the first embodiment described above, the I / O circuit 80 is arranged in the fourth circuit arrangement region 232 of the third substrate 230, which is the region directly below the electrode pad 213. This allows the chip size to be reduced in this embodiment as well, thereby enabling the photodetector 5 to be miniaturized.

[0165] Sixth Embodiment Fig. 17 is an exploded perspective view of a part of a photodetector 6 according to a sixth embodiment. In Fig. 17, the same components as those in the first embodiment described above are denoted by the same reference numerals, and detailed description thereof will be omitted.

[0166] In the photodetector 6 according to this embodiment, an ADC (Analog-to-Digital Converter) circuit arrangement region 221a is provided in the second circuit arrangement region 221 of the second substrate 220. A plurality of ADC circuits are arranged in the ADC circuit arrangement region 221a, one for each pixel 11. Here, the ADC circuits will be described with reference to FIG. 18 .

[0167] Fig. 18 is a diagram showing an example of the configuration of an ADC circuit. The ADC circuit 320 shown in Fig. 18 is a circuit for converting the result of comparison between an analog pixel signal input from the pixel 11 via the signal line VSL and a reference voltage REF into a digital pixel signal. Note that the ADC circuit may have any configuration as long as it has such a digital conversion function, and is not limited to the circuit configuration shown in Fig. 18.

[0168] This ADC circuit 320 has a pair of capacitive elements 321 and 322, an input transistor 323 and an output transistor 324 each configured as a pair of N-channel MOS transistors, a pair of switches 325 and 326, transistors 327 and 328 each configured as a pair of P-channel MOS transistors, and a current source 329.

[0169] In the ADC circuit 320, a pixel signal is input to the gate of the input transistor 323 via a capacitance element 321. Meanwhile, a reference voltage REF is input to the gate of the output transistor 324 via a second capacitance element 132. Furthermore, when the switches 325 and 326 are in the on state, the gate potentials of the input transistor 323 and the output transistor 324 are reset and enter an auto-zero state. Furthermore, the sources of the input transistor 323 and the output transistor 324 are commonly connected to a current source 329.

[0170] Furthermore, the transistors 327 and 328 function as a current mirror circuit that performs current control such that the same current flows through the input transistor 323 and the output transistor 324. The gates of the transistors 327 and 328 are connected to each other. The sources are commonly connected to a power supply that supplies the voltage VDDCM. The drain of the switching transistor 137 is connected to the drain of the input transistor 323, and the drain of the transistor 138 is connected to the drain of the output transistor 324. In the ADC circuit 320 configured as described above, when the voltage of the pixel signal matches, or in other words crosses, the comparison voltage VCO, which indicates the comparison result, is inverted.

[0171] In this embodiment, the ADC circuit 320 is provided for each pixel 11, thereby realizing a global shutter function.

[0172] Furthermore, in this embodiment, similarly to the first embodiment described above, the I / O circuit 80 is arranged in the fourth circuit arrangement region 232 of the third substrate 230, which is the region directly below the electrode pad 213. This allows the chip size to be reduced in this embodiment as well, thereby enabling the photodetector to be miniaturized.

[0173] Seventh Embodiment Fig. 19A is an exploded perspective view of a portion of a photodetector 7 according to the seventh embodiment. Fig. 19B is an exploded perspective view of a portion of a photodetector 7 according to a modified example of the seventh embodiment. Fig. 20 is a plan view of a portion of a photodetector 7 according to the seventh embodiment. Fig. 21 is a cross-sectional view of a portion of a photodetector 7 according to the seventh embodiment. In Figs. 19A to 21, components similar to those in the first embodiment described above are denoted by the same reference numerals, and detailed description thereof will be omitted.

[0174] In the photodetector 7 according to this embodiment, similarly to the first embodiment, the second substrate 220 is inserted between the electrode pads 213 and the I / O circuit 80. This increases the distance from the electrode pads 213 to the I / O circuit 80, so that the second substrate 220 functions as a buffer material during wire bonding, thereby reducing damage during wire bonding.

[0175] As a result, at least a part of the I / O circuit 80 can be arranged in the fourth circuit arrangement region 232, which is the region directly below the electrode pad 213. This makes it possible to reduce the chip size. On the other hand, an electrode pad capacitance C10 exists below the electrode pad 213.

[0176] Therefore, in this embodiment, an element isolation film 240 is formed in the second semiconductor chip 202. As shown in Figures 19A and 19B, the element isolation film 240 is provided in the second substrate 220. Furthermore, as shown in Figures 19A and 20, the element isolation film 240 is formed in a frame shape that single-layer surrounds at least a portion of the region directly below the opening region 212 of the first substrate 210.

[0177] The element isolation film 240 is a silicon oxide film (SiO ２ The isolation film 240 is a back side alignment (BSA) film or a full trench isolation (FFTI) film made of an insulating film such as a silicon nitride (SiN) film or a polysilicon film. Therefore, the potential of the region surrounded by the isolation film 240 in the second substrate 220 is floated. An electrode pad 213 is disposed directly above the region surrounded by the isolation film 240.

[0178] As shown in FIG. 21, the pad capacitance provided between the electrode pad 213 and the second substrate 220 includes a pad capacitance Cp5 that occurs between the wiring 229 electrically connected to the electrode pad 213 and the second substrate 220.

[0179] There is also a combined capacitance of the pad capacitances Cp3 and Cp4, Cp34=1 / (1 / Cp3+1 / Cp4). Here, the pad capacitance Cp3 is a capacitance generated between the second substrate 220, which is made floating by the through electrode 225 and the element isolation film 240, and the through electrode 225. On the other hand, the pad capacitance Cp4 is a capacitance generated between the second substrates 220, which are made floating, and the second substrates 220.

[0180] The capacitance generated between the through electrode 225 and the second substrate 220 can be large because the thickness of the film insulating the through electrode 225 and the second substrate 220 is thin, about 0.05 to 0.5 μm. However, by dividing the second substrate 220 into a floating region and a region at, for example, a power supply potential or a ground potential, using the element isolation film 240, it is possible to divide the capacitance and reduce the pad capacitance.

[0181] 19B, the element isolation film 240 may be formed in a double or more multi-frame shape. The planar shape of the element isolation film 240 is not limited to a rectangle, and may be a polygon such as an octagon formed by cutting out four vertices of a rectangle.

[0182] According to the embodiment described above, it is possible to achieve both a shrink in chip size and a reduction in capacitance under the electrode pad 213. Stress strain occurs in silicon, the material of the semiconductor substrate, during TSV formation. This stress strain increases the closer the distance from the TSV. Therefore, if an element is formed in a silicon region where the stress strain is significant, the stress strain may change the mobility of electrons and holes in the silicon. Therefore, it is necessary to avoid a layout in which elements are located near the TSV. Therefore, in this embodiment, by surrounding the TSV with the element isolation film 240 in a frame shape, the effects of stress strain caused by TSV formation can be limited to the area surrounded by the element isolation film 240. This allows elements to be located closer to the TSV than in conventional devices. As a result, the distance between the elements located on the second substrate 220 and the PAD region can be reduced, thereby reducing the chip size.

[0183] Additionally, in this embodiment, the through electrode 225 is present in the region surrounded by the element isolation film 240. Therefore, the electrode capacitance C20 of the through electrode 225 can also be reduced.

[0184] Eighth Embodiment Fig. 22A is an exploded perspective view of a portion of a light-detecting device 8 according to an eighth embodiment. Fig. 22B is a cross-sectional view of a portion of a light-detecting device 8 according to the eighth embodiment.

[0185] The pad capacitance generated between the electrode pad 213 and the second substrate 220 in this embodiment includes a pad capacitance Cp3′ generated between the through electrode 225 and the second substrate 220 that is floating by the element isolation film 240.

[0186] There is also a combined capacitance of the pad capacitances Cp5' and Cp4', Cp4'5'=1 / (1 / Cp4'+1 / Cp5')+Cp3'. The pad capacitance Cp5' is the pad capacitance generated between the wiring 229 electrically connected to the electrode pad 213 and the floating second substrate 220. On the other hand, the pad capacitance Cp4' is the pad capacitance generated between the floating second substrates 220. By separating the second substrate 220 into a floating region and a region at, for example, a power supply potential or a ground potential using the element isolation film 240, it is possible to divide the capacitance and reduce the pad capacitance.

[0187] 23 is a plan view of a part of a photodetector 8 according to the eighth embodiment. Here, the differences from the seventh embodiment will be mainly described.

[0188] In the photodetector 8 according to this embodiment, the range of the region surrounded by the element isolation film 240 is different from that of the photodetector 7 according to the seventh embodiment. In the photodetector 7 according to the seventh embodiment, the through electrode 225 is present in the region surrounded by the element isolation film 240.

[0189] On the other hand, in the photodetector 8 according to this embodiment, the through electrode 225 does not exist within the region surrounded by the element isolation film 240. In other words, the through electrode 225 exists outside the region surrounded by the element isolation film 240. However, the region surrounded by the element isolation film 240 is included in the region directly below the electrode pad 213.

[0190] Therefore, according to this embodiment, similarly to the seventh embodiment, it is possible to realize both a shrink in chip size and a reduction in capacitance below the electrode pad 213 .

[0191] Ninth Embodiment Fig. 24 is an exploded perspective view of a part of a photodetector 9 according to a ninth embodiment. Fig. 25 is a plan view of a part of a photodetector 9 according to the ninth embodiment. Here, differences from the seventh embodiment will be mainly described.

[0192] The photodetector 9 according to this embodiment differs from the photodetector 7 according to the seventh embodiment in the structure of the element isolation film 240. In the photodetector 7 according to the seventh embodiment, the region directly below the electrode pad 213 and the through electrode 225 are surrounded by a single element isolation film 240.

[0193] On the other hand, in the photodetector 9 according to this embodiment, the element isolation film 240 has a first element isolation film 240a and a second element isolation film 240b. The first element isolation film 240a surrounds the region directly below the electrode pad 213. The second element isolation film 240b is adjacent to the first element isolation film 240a and surrounds the through electrode 225. That is, the element isolation film 240 according to this embodiment surrounds the region directly below the electrode pad 213 and the through electrode 225 individually with the first element isolation film 240a and the second element isolation film 240b.

[0194] According to this embodiment, the first element isolation film 240a can realize both a shrink of the chip size and a reduction in the capacitance below the electrode pad 213. In addition, the second element isolation film 240b can reduce the electrode capacitance C20 of the through electrode 225.

[0195] Tenth Embodiment Fig. 26 is an exploded perspective view of a portion of a photodetector according to a tenth embodiment. Fig. 27 is a plan view of a portion of a photodetector according to the tenth embodiment. Here, differences from the first embodiment will be mainly described.

[0196] In the photodetector 1010 according to this embodiment, the I / O circuit 80 is disposed in a third circuit arrangement region 231 of the third substrate 230, and a through electrode 235 (second through electrode) is provided in a fourth circuit arrangement region 232 of the third substrate 230. The through electrode 235 is a so-called CSP (Chip Size Package)-TSV.

[0197] 27, the through electrode 235 is disposed in the center of the fourth circuit arrangement region 232. As shown in FIG. 26, the upper end of the through electrode 235 is located below the fourth contact via 234 in the fourth circuit arrangement region 232. The lower end of the through electrode 235 is located on the back surface of the third substrate 230. That is, the through electrode 235 is an electrode that penetrates from the back surface of the third substrate 230 to partway through the third substrate 230. On the back surface of the third substrate 230, a rewiring layer 236 is formed around the opening at the lower end of the through electrode 235. Solder balls 237 are formed on the rewiring layer 236. That is, the photodetector 1010 according to this embodiment has a BGA (Ball Grid Array) structure.

[0198] According to this embodiment, the I / O circuit 80 is arranged in the third circuit arrangement region 231, while the through electrodes 235 electrically connected to the solder balls 237 via the rewiring layer 236 are formed in the fourth circuit arrangement region 232. In this way, by arranging the through electrodes 235 for the CSP in the fourth circuit arrangement region 232, which is the region directly below the electrode pads 213, it is possible to reduce the chip size. Therefore, it is possible to miniaturize the photodetector 1010.

[0199] 28 is an exploded perspective view of a part of a photodetector according to an eleventh embodiment. The following description will focus on the differences from the above-described tenth embodiment.

[0200] 28 , the photodetector 1011 according to this embodiment does not include solder balls 237. That is, the photodetector 1011 according to this embodiment has a land grid array (LGA) structure. In this LGA structure, a part of the redistribution layer 236 electrically connected to the through electrode 235 functions as a flat pad (not shown), or a so-called land.

[0201] In this embodiment, as in the tenth embodiment, the through electrode 235 is formed in the fourth circuit arrangement region 232. This makes it possible to reduce the chip size, and therefore the photodetector 1011 can be made smaller.

[0202] In the above-described tenth and eleventh embodiments, one through electrode 235 is entirely disposed in the center of the fourth circuit arrangement region 232, but there are no particular limitations on the number of through electrodes 235 and their layout within the fourth circuit arrangement region 232. Here, modified examples of the through electrode 235 will be described with reference to Figures 29A and 29B.

[0203] 29A is a plan view showing a modified example of the through electrodes 235. In Fig. 29A, two through electrodes 235 are arranged in the fourth circuit arrangement region 232. In this modified example, the fourth circuit arrangement region 232 is rectangular, and the two through electrodes 235 are arranged at two corners facing each other. In addition, only a portion of each through electrode 235 is arranged in the fourth circuit arrangement region 232, rather than the entirety thereof.

[0204] 29B is a plan view showing another modified example of the through electrodes 235. In Fig. 29B, four through electrodes 235 are arranged in the fourth circuit arrangement region 232. In this modified example, the fourth circuit arrangement region 232 is also rectangular, and the four through electrodes 235 are arranged on four sides of the fourth circuit arrangement region 232. Furthermore, not the entire through electrodes 235 but only a portion of them is arranged in the fourth circuit arrangement region 232.

[0205] 29C is a plan view showing yet another modified example of the through electrodes 235. In FIG. 29C, two fourth circuit arrangement regions 232 arranged in one direction are provided on the third substrate 230, and one through electrode 235 is arranged in each of the fourth circuit arrangement regions 232. The two through electrodes 235 are also arranged so as to be offset in a direction perpendicular to the arrangement direction of the fourth circuit arrangement regions 232. That is, in this modified example, the two through electrodes 235 are arranged in a staggered manner. Furthermore, only a portion of each through electrode 235 is arranged in the fourth circuit arrangement region 232, rather than the entirety of it.

[0206] 29D is a plan view showing yet another modified example of the through electrode 235. In Fig. 29D, a portion of one through electrode 235 protrudes outside the fourth circuit arrangement region 232. Specifically, the outer periphery of the through electrode 235 protrudes outside the fourth circuit arrangement region 232.

[0207] 29A to 29D, it is possible to reduce the chip size by arranging part of the through electrode 235 in the fourth circuit arrangement region 232, which is the region directly below the electrode pad 213. Therefore, it is possible to reduce the size of the photodetector devices 1010 and 1011.

[0208] 29A and 29B provide greater flexibility in the layout of the through electrodes 235 and the rewiring formed in the rewiring layer 236. Furthermore, the layout shown in Fig. 29C allows for a larger pitch between the through electrodes 235. Furthermore, the layout shown in Fig. 29D allows for at least a portion of the through electrodes 235 to be disposed within the fourth circuit arrangement region 232, even if the area of ​​the fourth circuit arrangement region 232 becomes smaller as the area of ​​the opening region 212 of the first substrate 210 becomes smaller.

[0209] Twelfth Embodiment Fig. 30 is an exploded perspective view of a part of a photodetector according to a twelfth embodiment. Fig. 31 is a plan view of a part of a photodetector according to the twelfth embodiment. Here, differences from the above-described tenth embodiment will be mainly described.

[0210] In the photodetector 1012 according to this embodiment, as shown in Fig. 31 , not only the through electrodes 235 but also the I / O circuits 80 are arranged in a fourth circuit arrangement region 232 of the third substrate 230. In Fig. 31 , a portion of the through electrodes 235 is arranged in the fourth circuit arrangement region 232, and the I / O circuits 80 are arranged outside the through electrodes 235. However, the layout of the through electrodes 235 and the I / O circuits 80 in the fourth circuit arrangement region 232 is not limited to the example shown in Fig. 31 .

[0211] 32 is a plan view showing a modified layout of the through electrodes 235 and the I / O circuits 80. In Fig. 32, the I / O circuits 80 are arranged in two separate areas within the fourth circuit arrangement area 232. The through electrodes 235 are arranged between the two separate I / O circuits 80.

[0212] According to the present embodiment described above, in addition to the through electrodes 235, the I / O circuit 80 is arranged in the fourth circuit arrangement region 232. Compared to the tenth and eleventh embodiments, the area of ​​the third substrate 230 is reduced, which makes it possible to further miniaturize the photodetector.

[0213] 33 is a cross-sectional view of a portion of a photodetector according to a thirteenth embodiment. In Fig. 33, the same components as those in the photodetector 8 according to the eighth embodiment shown in Fig. 8 are denoted by the same reference numerals, and redundant explanations will be omitted.

[0214] In the photodetector 1013 according to this embodiment, dummy wiring 250 is provided in the second semiconductor chip 202. The dummy wiring 250 is arranged in a connection region 222 in a wiring layer 251 of the second substrate 220. The dummy wiring 250 is not connected to other wiring provided in the wiring layer 251, and is a floating wiring in terms of potential. The dummy wiring 250 can protect the region directly below the connection region 222, i.e., the I / O circuit 80 arranged in the fourth circuit arrangement region 232 of the third substrate 230.

[0215] The material of the dummy wiring 250 may be the same as or different from the material of the other wirings. When the material of the dummy wiring 250 is the same as the material of the other wirings, for example, metal and polysilicon are used. For example, copper (Cu), titanium (Ti), tungsten (W), aluminum (Al), silver (Ag), gold (Au), cobalt (Co), etc. are used as this metal. In this case, the dummy wiring 250 can be formed using the same manufacturing process as the other wirings.

[0216] On the other hand, when the material of the dummy wiring 250 is different from the material of the other wirings, for example, a metal oxide film, a carbon-based material, an organic material such as a resist, an electrochromic material such as tungsten trioxide, etc. is used. In this case, for example, by selecting a material with higher rigidity than the material of the other wirings, the dummy wiring 250 can be optimized for protecting the I / O circuit 80.

[0217] In this embodiment, a plurality of dummy wirings 250 are arranged in a line in a plurality of layers along the stacking direction. That is, when viewed in a cross section in the stacking direction, the dummy wirings 250 are arranged in a two-dimensional matrix. However, the arrangement of the dummy wirings 250 is not limited to a matrix.

[0218] 34 is a cross-sectional view showing another arrangement of the dummy wirings 250. In FIG. 34, rows of dummy wirings 250 adjacent to each other in the stacking direction are arranged with a staggered arrangement. That is, when viewed in cross section in the stacking direction, the dummy wirings 250 are arranged in a staggered arrangement. In this case, the length of the gaps between the dummy wirings 250 in the stacking direction is shorter than in the matrix arrangement. Therefore, damage to the I / O circuit 80 from the electrode pads 213 can be further reduced.

[0219] Furthermore, the cross-sectional shape of the dummy wiring 250 is not limited to the rectangular shape shown in FIGS. 33 and 34, and may be other shapes.

[0220] For example, as shown in Fig. 35A, the dummy wirings 250 may have a circular cross-sectional shape. Furthermore, the dummy wirings 250 may be arranged in a matrix as shown in Fig. 35A, or in a staggered arrangement as shown in Fig. 35B.

[0221] 36A, the dummy wirings 250 may have a triangular cross-sectional shape. In this cross-sectional shape, triangles and inverted triangles are alternately arranged in a row of the dummy wirings 250. Furthermore, the dummy wirings 250 may be arranged in a matrix as shown in FIG. 36A, or in a staggered arrangement as shown in FIG. 36B.

[0222] 37A, in the dummy wiring 250 having a triangular cross section, triangles and inverted triangles may be alternately arranged in the stacking direction. Furthermore, the dummy wiring 250 may be arranged in a matrix as shown in FIG. 37A, or in a staggered arrangement as shown in FIG. 37B.

[0223] 38A, the dummy wirings 250 may have a hexagonal cross section. Furthermore, the dummy wirings 250 may be arranged in a matrix as shown in FIG. 36A, or in a staggered arrangement as shown in FIG. 38B.

[0224] Furthermore, in the photodetector 1013 according to this embodiment, four layers of dummy wirings 250 are formed in the connection region 222, but the number of layers of the dummy wirings 250 is not particularly limited. The number of layers of the dummy wirings 250 may be, for example, one as shown in Fig. 39, two as shown in Fig. 40, or three as shown in Fig. 41. The number of layers of the dummy wirings 250 may be five or more depending on the number of wiring layers 251.

[0225] Furthermore, in the photodetector 1013 according to this embodiment, the dummy wiring 250 is formed in a striped pattern, but the wiring pattern is not particularly limited. For example, as shown in Fig. 42, the dummy wiring 250 may be formed in a solid pattern. In this case, the area of ​​the dummy wiring 250 is larger than that of a striped pattern, thereby enhancing protection of the I / O circuit 80.

[0226] Furthermore, in this embodiment, the dummy wiring 250 may be arranged in other regions in addition to the connection region 222. For example, as shown in Fig. 43, in the second substrate 220, the dummy wiring 250 may be arranged in a region surrounded by the second circuit arrangement region 221 and the connection region 222. In this case, the second substrate 220 can be planarized.

[0227] According to the present embodiment described above, similarly to the first embodiment, the I / O circuit 80 is arranged in the fourth circuit arrangement region 232 of the third substrate 230, which is the region directly below the electrode pad 213. This allows the chip size to be reduced in this embodiment as well, thereby enabling the photodetector to be miniaturized.

[0228] 44 is a cross-sectional view of a portion of a photodetector according to a fourteenth embodiment. In FIG. 44, the same components as those in the photodetector 1013 according to the thirteenth embodiment shown in FIG. 33 are denoted by the same reference numerals, and redundant description will be omitted. In the photodetector 1013 according to the thirteenth embodiment, electrode pads 213 are provided on the underside of the first substrate 210. Furthermore, dummy wiring 250 is arranged only on the second substrate 220.

[0229] In contrast, in the photodetector 1014 according to this embodiment, the electrode pads 213 are arranged on the upper side of the first substrate 210. Furthermore, the dummy wirings 250 are arranged not only in the wiring layer 251 of the second substrate 220 but also in the wiring layer 252 of the first substrate 210. In the wiring layer 252, the dummy wirings 250 are arranged in the region directly below the opening region 212. However, in this embodiment, the dummy wirings 250 do not need to be arranged on both the first substrate 210 and the second substrate 220.

[0230] For example, as shown in Fig. 45, the dummy wiring 250 may be arranged only in the wiring layer 251 of the second substrate 220. Alternatively, as shown in Fig. 46, the dummy wiring 250 may be arranged only in the wiring layer 252 of the first substrate 210.

[0231] In this embodiment, as in the thirteenth embodiment, the cross-sectional shape of the dummy wirings 250 is not limited to a rectangle, but may be a polygonal shape such as a triangle or a hexagon, or may be a circle. The dummy wirings 250 may be arranged in a matrix or a staggered pattern.

[0232] The number of layers of the dummy wiring 250 is not limited to four, and may be more or less than four. The pattern of the dummy wiring 250 may be a striped pattern or a solid pattern. Furthermore, the dummy wiring 250 may be arranged in a region surrounded by the second circuit arrangement region 221 and the connection region 222 on the second substrate 220.

[0233] According to the present embodiment described above, similarly to the thirteenth embodiment, the I / O circuit 80 is arranged in the fourth circuit arrangement region 232 of the third substrate 230, which is the region directly below the electrode pad 213. This allows the chip size to be reduced in this embodiment as well, thereby enabling the photodetector to be miniaturized.

[0234] 47 is an enlarged plan view of a fourth circuit arrangement region of a second substrate of a photodetector according to a fifteenth embodiment. In this embodiment, a wiring group 238 in which a plurality of wirings are connected in a mesh pattern is arranged in the fourth circuit arrangement region 232 of the second substrate 220. The wiring group 238 may be connected to the I / O circuit 80, or may be connected to a circuit arranged in the third circuit arrangement region 231.

[0235] In the wiring group 238, even if some of the wiring is broken due to damage during wire bonding, the remaining conductive parts can still function as wiring. In other words, the wiring group 238 has redundant wiring. Therefore, even if damage occurs during wire bonding, it is possible to maintain operation of the circuits connected to the wiring group 238.

[0236] According to the present embodiment described above, similarly to the first embodiment, the I / O circuit 80 is arranged in the fourth circuit arrangement region 232 of the third substrate 230, which is the region directly below the electrode pad 213. This allows the chip size to be reduced in this embodiment as well, thereby enabling the photodetector to be miniaturized.

[0237] 48 is a cross-sectional view of a portion of a photodetector according to a sixteenth embodiment. Also, Fig. 49 is a diagram showing an example of a layered structure of the photodetector according to the sixteenth embodiment. In Figs. 48 and 49, the same components as those in the photodetector 1 according to the first embodiment described above are designated by the same reference numerals, and redundant description will be omitted.

[0238] 49 , in the photodetector 1016 according to this embodiment, the second semiconductor chip 202 has connection regions 222a and 222b. An input electrode pad 213a is arranged in the connection region 222a, and an output electrode pad 213b is arranged in the connection region 222b. The input electrode pad 241a and the output electrode pad 241b are also referred to as first electrode pads.

[0239] The plane area of ​​each of the input electrode pad 213a and the output electrode pad 213b is 100 μm ２ (10μm×10μm)~10000μm ２ (100 μm×100 μm). The input electrode pad 213 a is part of a signal path transmitted from the second substrate 220 to the third substrate 230. On the other hand, the output electrode pad 213 b is part of a signal path transmitted from the third substrate 230 to the second substrate 220.

[0240] Furthermore, in the photodetector device 1016 according to this embodiment, a connection switching transistor Q1 is formed in each of the connection regions 222a and 222b. The connection switching transistor Q1 formed in the connection region 222a is electrically connected to the input electrode pad 213a. The connection switching transistor Q1 formed in the connection region 222b is electrically connected to the output electrode pad 213b. The thickness of the second substrate 220 is, for example, 1 μm to 10 μm. Here, the structure of the connection switching transistor Q1 will be described with reference to FIG. 50 .

[0241] 50 is a cross-sectional view showing the structure of a connection switching transistor according to the sixteenth embodiment. The connection switching transistor Q1 shown in Fig. 50 is an N-channel MOS transistor with a vertical structure. Specifically, the connection switching transistor Q1 has a first semiconductor region 2201, a second semiconductor region 2202, a third semiconductor region 2203, a gate electrode 2204, and a gate oxide film 2205.

[0242] The first semiconductor region 2201 is a drain region made of an N-type semiconductor. The second semiconductor region 2202 is a P-type semiconductor region provided between the first semiconductor region 2201 and the third semiconductor region 2203. The third semiconductor region 2203 is made of an N-type semiconductor. ＋The third semiconductor region 2203 is a source region made of a type semiconductor. The third semiconductor region 2203 is electrically connected to the input electrode pad 213a or the output electrode pad 213b via the wiring layer 2200. The gate electrode 2204 is disposed between the first semiconductor region 2201 and the third semiconductor region 2203 via a gate oxide film 2205. For example, the gate electrode 2204 is made of polysilicon. The thickness of the gate oxide film 2205 is 4 nm to 15 nm. The impurity concentration of the first semiconductor region 2201 is 10 １８ ~10 １９ / cm ３ The impurity concentration of the second semiconductor region 2202 is 10 １６ ~10 １７ / cm ３ Furthermore, the impurity concentration of the third semiconductor region 2203 is 10 ２０ / cm ３ That's about it.

[0243] In the photodetector 1016 according to this embodiment, as shown in FIG. 49 , the third semiconductor chip 203 has fourth circuit arrangement regions 232a and 232b. An input electrode pad 239a is arranged in the fourth circuit arrangement region 232a, and an output electrode pad 239b is arranged in the fourth circuit arrangement region 232b. The input electrode pad 239a and the output electrode pad 239b are each electrically connected to the connection switching transistor Q1. The input electrode pad 239a and the output electrode pad 239b are also referred to as second electrode pads. The areas of the input electrode pad 239a and the output electrode pad 213b are the same as those of the input electrode pad 213a and the output electrode pad 213b, respectively.

[0244] In the photodetector device 1016 according to this embodiment, the first circuit region 211 is provided with pixels 11 that generate pixel signals by photoelectrically converting incident light from an object. The second circuit region 221 is provided with signal processing circuits 2210 that process the pixel signals from the pixels 11. The signal processing circuit 2210 includes, for example, an ADC that digitally converts the pixel signals. The third circuit region 231 is provided with a deep neural network (DNN) circuit 2310 that recognizes the object based on the pixel signals processed by the signal processing circuit 2210. In this case, if the connection switching transistor Q1 is not provided, the second substrate 220 and the third substrate 230 would always be electrically connected. Therefore, for example, when processing is performed in which only the signal processing circuit 2210 is driven without driving the DNN circuit 2310, power is also supplied to the DNN circuit 2310, leaving room for improvement in terms of circuit operating speed and power consumption.

[0245] Therefore, in this embodiment, for example, when the voltage input to the gate electrode 2204 from the signal processing unit 60 is lower than the threshold voltage, the connection switching transistor Q1 is turned off. In this case, the electrical connection between the input electrode pad 213a and the input electrode pad 239a is cut off, and the electrical connection between the output electrode pad 213b and the output electrode pad 239b is also cut off. As a result, the electrical connection between the second substrate 220 and the third substrate 230 is cut off. This allows the signal processing circuit 2210 to be driven without driving the DNN circuit 2310, thereby improving the circuit operating speed and reducing power consumption.

[0246] On the other hand, connection switching transistor Q1 turns on when a voltage higher than the threshold voltage is applied to gate electrode 2204. In this case, the input and output electrode pads are electrically connected to each other, making it possible to perform processing that operates both the circuit arranged in third circuit arrangement region 231 and the circuit arranged in second circuit arrangement region 221.

[0247] In this embodiment, the connection switching transistor Q1 is formed by implanting P-type or N-type impurities or by polysilicon. Therefore, even if the connection switching transistor Q1 is disposed in the connection regions 222a and 222b of the second substrate 220, it is less susceptible to damage during bonding to the electrode pads. Therefore, according to this embodiment, as in the first embodiment described above, the I / O circuit 80 can be disposed in the fourth circuit arrangement region 232. As a result, in this embodiment as well, the chip size can be reduced, thereby enabling the miniaturization of the photodetector device.

[0248] 51 is a cross-sectional view of a portion of a photodetector according to a seventeenth embodiment. Here, differences from the sixteenth embodiment will be mainly described, and redundant explanations will be omitted. In a photodetector 1017 according to this embodiment, the structure of the connection switching transistor Q1 differs from that of the sixteenth embodiment.

[0249] The connection switching transistor Q1 according to this embodiment further includes a fourth semiconductor region 2206. The fourth semiconductor region 2206 is an N-type semiconductor region formed on the back surface (the surface on the third substrate 230 side) of the first semiconductor region 2201. ＋ It is a type semiconductor region.

[0250] Hereinafter, a general manufacturing process for the photodetector 1017 according to this embodiment will be described with reference to FIGS.

[0251] First, as shown in FIG. 52, a N ＋ A semiconductor layer 2206a is formed. ＋ The semiconductor layer 2206a can be formed by, for example, epitaxial growth. Subsequently, a first semiconductor region 2201, a second semiconductor region 2202, a third semiconductor region 2203, a gate electrode 2204, a gate oxide film 2205 (not shown in FIG. 52 ), and a wiring layer 2200 are formed in this order on the second substrate 200.

[0252] 53, the second substrate 220 is inverted and attached to the first substrate 210. Subsequently, the silicon bulk layer 2020 is thinned, and N ＋The semiconductor layer 2206a is patterned into the fourth semiconductor region 2206. This completes the connection switching transistor Q1.

[0253] 54 , the thinned second substrate 220 is covered with an oxide film 2021, and contact vias 2022 and bonding pads 2023 are formed in the oxide film 2021. Subsequently, a third substrate 230, on which input electrode pads 239 a and output electrode pads 239 b are formed, is attached to the second substrate 220.

[0254] Finally, returning to FIG. 51, the bonded first substrate 210 to third substrate 230 are inverted, and opening regions are formed in the first substrate 210 to expose the input electrode pads 213a and the output electrode pads 213b.

[0255] According to the present embodiment described above, similarly to the sixteenth embodiment, the second substrate 220 is provided with a connection switching transistor Q1 that switches whether or not the second substrate 220 and the third substrate 230 are electrically connected. Therefore, when performing a process that does not require the third substrate 230, the electrical connection between the second substrate 220 and the third substrate 230 is cut off, thereby making it possible to improve the circuit operating speed and reduce power consumption.

[0256] Additionally, in the connection switching transistor Q1 according to this embodiment, a fourth semiconductor region 2206 having an impurity concentration higher than that of the first semiconductor region 2201 is formed on the back surface side of the first semiconductor region 2201. This makes it possible to reduce the contact resistance of the connection switching transistor Q1.

[0257] 55 is a cross-sectional view of a portion of a photodetector according to an eighteenth embodiment. Here, differences from the sixteenth embodiment will be mainly described, and redundant explanations will be omitted. In a photodetector 1018 according to this embodiment, the structure of the connection switching transistor Q1 differs from that of the sixteenth embodiment.

[0258] The connection switching transistor Q1 according to this embodiment further includes a fifth semiconductor region 2207. The fifth semiconductor region 2207 is a P ＋That is, the connection switching transistor Q1 is an insulated gate bipolar transistor (IGBT).

[0259] Hereinafter, a general manufacturing process for the photodetector 1018 according to this embodiment will be described with reference to FIGS.

[0260] First, as shown in FIG. 56, a P ＋ A semiconductor layer 2207a is formed. ＋ The semiconductor layer 2207a can be formed by, for example, epitaxial growth. Subsequently, a first semiconductor region 2201, a second semiconductor region 2202, a third semiconductor region 2203, a gate electrode 2204, a gate oxide film 2205 (not shown in FIG. 56 ), and a wiring layer 2200 are formed in this order on the second substrate 200.

[0261] 57, the second substrate 220 is inverted and attached to the first substrate 210. Subsequently, the silicon bulk layer 2020 is thinned, and P ＋ The semiconductor layer 2207a is patterned into a fifth semiconductor region 2207. This completes the connection switching transistor Q1.

[0262] 58 , the thinned second substrate 220 is covered with an oxide film 2021, and contact vias 2022 and bonding pads 2023 are formed in the oxide film 2021. Subsequently, a third substrate 230, on which input electrode pads 239 a and output electrode pads 239 b are formed, is attached to the second substrate 220.

[0263] Finally, returning to FIG. 55, the bonded first to third substrates 210 to 230 are inverted, and opening regions are formed in the first substrate 210 to expose the input electrode pads 213a and the output electrode pads 213b.

[0264] According to the present embodiment described above, similarly to the sixteenth embodiment, the second substrate 220 is provided with a connection switching transistor Q1 that switches whether or not the second substrate 220 and the third substrate 230 are electrically connected. Therefore, when performing a process that does not require the third substrate 230, the electrical connection between the second substrate 220 and the third substrate 230 is cut off, thereby making it possible to improve the circuit operating speed and reduce power consumption.

[0265] 59 is a cross-sectional view of a portion of a photodetector according to the 19th embodiment. Here, differences from the above-described 16th embodiment will be mainly described, and overlapping descriptions will be omitted. In the photodetector 1019 according to this embodiment, the conductivity type of the connection switching transistor is opposite to that of the 16th embodiment.

[0266] The connection switching transistor Q1 according to the sixteenth embodiment is an N-channel MOS transistor, whereas the connection switching transistor Q2 according to this embodiment is a P-channel MOS transistor. Specifically, the connection switching transistor Q2 includes a first semiconductor region 2211, a second semiconductor region 2212, and a third semiconductor region 2213.

[0267] The first semiconductor region 2211 is a P-type semiconductor region. The second semiconductor region 2212 is an N-type semiconductor region. The third semiconductor region 2213 is a P-type semiconductor region. ＋ It is a type semiconductor region.

[0268] In the connection switching transistor Q2 configured as described above, when the voltage input to the gate electrode 2204 is lower than the threshold voltage, the connection switching transistor Q2 turns on. In this case, the second substrate 220 and the third substrate 230 are electrically connected. Furthermore, when the voltage input to the gate electrode 2204 is higher than the threshold voltage, the connection switching transistor Q2 turns off. In this case, the electrical connection between the second substrate 220 and the third substrate 230 is cut off.

[0269] Therefore, according to this embodiment, the connection switching transistor Q2, which is configured using a P-channel MOS transistor, can switch the electrical connection between the second substrate 220 and the third substrate 230. Therefore, when performing a process that does not require the third substrate 230, the connection switching transistor Q2 cuts off the electrical connection between the second substrate 220 and the third substrate 230, thereby improving the circuit operating speed and reducing power consumption.

[0270] 60 is a cross-sectional view of a portion of a photodetector according to the twentieth embodiment. Here, differences from the above-described seventeenth embodiment will be mainly described, and overlapping descriptions will be omitted. In a photodetector 1020 according to this embodiment, the conductivity type of the connection switching transistor is opposite to that of the seventeenth embodiment.

[0271] The connection switching transistor Q1 according to the seventeenth embodiment is an N-channel MOS transistor, whereas the connection switching transistor Q2 according to this embodiment is a P-channel MOS transistor. Specifically, the connection switching transistor Q2 is provided with a first semiconductor region 2211, a second semiconductor region 2212, a third semiconductor region 2213, and a fourth semiconductor region 2216.

[0272] The first semiconductor region 2211 is a P-type semiconductor region. The second semiconductor region 2212 is an N-type semiconductor region. The third semiconductor region 2213 and the fourth semiconductor region 2216 are P-type semiconductor regions. ＋ It is a type semiconductor region.

[0273] In the connection switching transistor Q2 configured as described above, when the voltage input to the gate electrode 2204 is lower than the threshold voltage, the connection switching transistor Q2 turns on. In this case, the second substrate 220 and the third substrate 230 are electrically connected. Furthermore, when the voltage input to the gate electrode 2204 is higher than the threshold voltage, the connection switching transistor Q2 turns off. In this case, the electrical connection between the second substrate 220 and the third substrate 230 is cut off.

[0274] Therefore, according to this embodiment, the connection switching transistor Q2, which is configured using a P-channel MOS transistor, can switch the electrical connection between the second substrate 220 and the third substrate 230. Therefore, when performing a process that does not require the third substrate 230, the connection switching transistor Q2 cuts off the electrical connection between the second substrate 220 and the third substrate 230, thereby improving the circuit operating speed and reducing power consumption.

[0275] Additionally, in the connection switching transistor Q2 according to this embodiment, a fourth semiconductor region 2216 having an impurity concentration higher than that of the first semiconductor region 2211 is formed on the back surface side of the first semiconductor region 2211. This makes it possible to reduce the contact resistance of the connection switching transistor Q2.

[0276] 61 is a cross-sectional view of a portion of a photodetector according to the 21st embodiment. Here, differences from the 18th embodiment will be mainly described, and overlapping descriptions will be omitted. In a photodetector 1020 according to this embodiment, the conductivity type of the connection switching transistor is opposite to that of the 18th embodiment.

[0277] The connection switching transistor Q1 according to the eighteenth embodiment is an N-channel IGBT, whereas the connection switching transistor Q2 according to this embodiment is a P-channel IGBT. Specifically, the connection switching transistor Q2 is provided with a first semiconductor region 2211, a second semiconductor region 2212, a third semiconductor region 2213, and a fifth semiconductor region.

[0278] The first semiconductor region 2211 is a P-type semiconductor region. The second semiconductor region 2212 is an N-type semiconductor region. The third semiconductor region 2213 is a P-type semiconductor region. ＋ The fifth semiconductor region 2217 is an N-type semiconductor region. ＋ It is a type semiconductor region.

[0279] In the connection switching transistor Q2 configured as described above, when the voltage input to the gate electrode 2204 is lower than the threshold voltage, the connection switching transistor Q2 turns on. In this case, the second substrate 220 and the third substrate 230 are electrically connected. Furthermore, when the voltage input to the gate electrode 2204 is higher than the threshold voltage, the connection switching transistor Q2 turns off. In this case, the electrical connection between the second substrate 220 and the third substrate 230 is cut off.

[0280] Therefore, according to this embodiment, the connection switching transistor Q2 formed of a P-channel IGBT can switch the electrical connection between the second substrate 220 and the third substrate 230. Therefore, when performing a process that does not require the third substrate 230, the connection switching transistor Q2 cuts off the electrical connection between the second substrate 220 and the third substrate 230, thereby improving the circuit operating speed and reducing power consumption.

[0281] 62 is a cross-sectional view showing the structure of a connection switching transistor according to the 22nd embodiment. In this embodiment, the structure of the gate electrode 2204 of the connection switching transistor Q1 differs from that of the 16th embodiment. The connection switching transistor Q1 according to the 16th embodiment has a planar gate electrode 2204.

[0282] On the other hand, the connection switching transistor Q1 according to this embodiment has a trench-type gate electrode 2204. The depth of the trench extending from the surface toward the inside of the second substrate 220 is, for example, 0.2 μm to 0.5 μm. By forming the gate electrode 2204 in a trench shape in this way, the on-resistance of the connection switching transistor Q1 can be reduced.

[0283] According to the present embodiment described above, similarly to the sixteenth embodiment, the second substrate 220 is provided with a connection switching transistor Q1 that switches whether or not the second substrate 220 and the third substrate 230 are electrically connected. Therefore, when performing a process that does not require the third substrate 230, the electrical connection between the second substrate 220 and the third substrate 230 is cut off, thereby making it possible to improve the circuit operating speed and reduce power consumption.

[0284] Additionally, in the connection switching transistor Q1 according to this embodiment, the trench-type gate electrode 2204 reduces the on-resistance, making it possible to suppress the heat generation temperature associated with current flow.

[0285] 63 is a cross-sectional view showing the structure of a connection switching transistor according to the 23rd embodiment. In this embodiment, the conductivity type of the connection switching transistor differs from that of the 21st embodiment. The connection switching transistor Q1 according to the 21st embodiment is an N-channel MOS transistor having a trench-type gate electrode 2204.

[0286] On the other hand, the connection switching transistor Q2 according to this embodiment is a P-channel MOS transistor having a trench-type gate electrode 2204. In the connection switching transistor Q2, the depth of the trench is, for example, 0.2 μm to 0.5 μm.

[0287] According to the present embodiment described above, the second substrate 220 is provided with a connection switching transistor Q2 that switches whether or not the second substrate 220 and the third substrate 230 are electrically connected. Therefore, when performing a process that does not require the third substrate 230, the electrical connection between the second substrate 220 and the third substrate 230 is cut off, thereby making it possible to improve the circuit operating speed and reduce power consumption.

[0288] In this embodiment, the gate electrode 2204 is of a trench type, as in the twenty-first embodiment, which reduces the on-resistance and makes it possible to suppress the heat generation temperature caused by energization.

[0289] 24th Embodiment FIG. 64 is a cross-sectional view showing the structure of a photodetector according to the 24th embodiment. The photodetector 1024 according to this embodiment further includes an element isolation film 2220 in addition to the components of the photodetector 1016 according to the 16th embodiment. The element isolation film 2220 is provided between a plurality of connection switching transistors Q1 provided on the second substrate 220. The element isolation film 2220 is made of, for example, a silicon oxide film or a silicon nitride film. The plurality of connection switching transistors Q1 are electrically insulated from one another by the element isolation film 2220. This allows each transistor to be driven and controlled individually.

[0290] Furthermore, according to this embodiment, the connection switching transistor Q1 can switch the electrical connection between the second substrate 220 and the third substrate 230, and therefore, by cutting off the electrical connection between the second substrate 220 and the third substrate 230, it is possible to improve the circuit operating speed and reduce power consumption.

[0291] 65 is a cross-sectional view showing the structure of a photodetector according to the 25th embodiment. In a photodetector 1025 according to this embodiment, a fourth semiconductor chip 204 is stacked between a second semiconductor chip 202 and a third semiconductor chip 203. In the fourth semiconductor chip 204, input electrode pads 241a and output electrode pads 241b are provided on a second substrate 220. The input electrode pads 241a and output electrode pads 241b are also referred to as third electrode pads.

[0292] The input electrode pad 241a faces the input electrode pad 213a via the connection switching transistor Q1, and the output electrode pad 241b faces the output electrode pad 213b via the connection switching transistor Q1.

[0293] Furthermore, a connection switching transistor Q3 is formed within the second substrate 220. The connection switching transistor Q3 is disposed between the input electrode pad 241a and the third substrate 230, and is also disposed between the output electrode pad 241b and the third substrate 230. The structure of the connection switching transistor Q3 is the same as that of the connection switching transistor Q1 provided in the second semiconductor chip 202, and therefore a description thereof will be omitted.

[0294] When the connection switching transistor Q3 is turned on, the input electrode pads 213 a, 239 a, and 241 a are electrically connected, and the output electrode pads 213 b, 239 b, and 241 b are electrically connected. On the other hand, when the connection switching transistor Q3 is turned off, the electrical connection between the input electrode pads and the electrical connection between the output electrode pads are cut off.

[0295] Therefore, according to this embodiment, the connection switching transistor Q3 can switch the electrical connection between the fourth substrate 2400 and the third substrate 230, and by cutting off the electrical connection between the fourth substrate 2400 and the third substrate 230, it is possible to improve the circuit operating speed and reduce power consumption.

[0296] 66 is a cross-sectional view showing the structure of a photodetector according to the 26th embodiment. In a photodetector 1026 according to this embodiment, as in the above-described 24th embodiment, a fourth semiconductor chip 204 is stacked between a second semiconductor chip 202 and a third semiconductor chip 203. In the fourth semiconductor chip 204, an input electrode pad 241a and an output electrode pad 241b are provided on a second substrate 220, and a connection switching transistor Q3 is formed within the second substrate 220. On the other hand, in a photodetector 1025 according to this embodiment, an input electrode pad 239a and an output electrode pad 239b provided on the third semiconductor chip 203 are exposed from the rear surface side of a fourth substrate 2400.

[0297] In the photodetector 1026 according to this embodiment configured as described above, when the connection switching transistor Q3 is turned on, the input electrode pads 213 a, 239 a, and 241 a are electrically connected, and the output electrode pads 213 b, 239 b, and 241 b are electrically connected, as in the 24th embodiment. On the other hand, when the connection switching transistor Q3 is turned off, the electrical connection between the input electrode pads and the electrical connection between the output electrode pads are cut off.

[0298] Therefore, in this embodiment as well, the connection switching transistor Q3 can switch the electrical connection between the fourth substrate 2400 and the third substrate 230, and by cutting off the electrical connection between the fourth substrate 2400 and the third substrate 230, it is possible to improve the circuit operating speed and reduce power consumption.

[0299] 67 is a cross-sectional view showing the structure of a photodetector according to the 26th embodiment. In a photodetector 1027 according to this embodiment, a fourth semiconductor chip 204 is stacked on the back surface side of a second semiconductor chip 202. In the fourth semiconductor chip 204, input electrode pads 241 a and output electrode pads 241 b are exposed from the back surface side of the second substrate 220.

[0300] In the third semiconductor chip 203, the input electrode pads 239a and the output electrode pads 239b are exposed from the front surface side of the third substrate 230. The input electrode pads 239a are bonded to the input electrode pads 241a via bumps 242. The output electrode pads 239b are bonded to the output electrode pads 241b via bumps 242.

[0301] In the photodetector 1027 according to this embodiment configured as described above, when the connection switching transistor Q1 is turned on, the input electrode pads 213 a, 239 a, and 241 a are electrically connected, and the output electrode pads 213 b, 239 b, and 241 b are electrically connected. On the other hand, when the connection switching transistor Q1 is turned off, the electrical connection between the input electrode pads and the electrical connection between the output electrode pads are cut off.

[0302] Therefore, according to this embodiment, the connection switching transistor Q1 can switch the electrical connection between the second substrate 220 and the third substrate 230, and by cutting off the electrical connection between the second substrate 220 and the third substrate 230, it is possible to improve the circuit operating speed and reduce power consumption.

[0303] 28th Embodiment Fig. 68 is a cross-sectional view showing the structure of a photodetector according to the 28th embodiment, and Fig. 69 is a schematic plan view of a connection switching transistor Q1 according to the 28th embodiment.

[0304] In the photodetector device 1028 according to this embodiment, the gate electrodes 2204 of the multiple connection switching transistors Q1 arranged side by side in one direction are electrically connected to each other, so that these connection switching transistors Q1 can be switched on and off simultaneously.

[0305] When the connection switching transistors Q1 are simultaneously turned on, the input electrode pads 213 a and 239 a are electrically connected and the output electrode pads 213 b and 239 b are electrically connected. On the other hand, when the connection switching transistor Q1 is turned off, the electrical connection between the input electrode pads and the electrical connection between the output electrode pads are cut off.

[0306] Therefore, according to this embodiment, the connection switching transistor Q1 can switch the electrical connection between the second substrate 220 and the third substrate 230, and by cutting off the electrical connection between the second substrate 220 and the third substrate 230, it is possible to improve the circuit operating speed and reduce power consumption.

[0307] 70 and 71 are cross-sectional views showing the structure of a photodetector according to a 29th embodiment. Fig. 70 shows a cross section of connection region 222a and fourth circuit arrangement region 232a, i.e., the input side. On the other hand, Fig. 71 shows a cross section of connection region 222b and fourth circuit arrangement region 232b, i.e., the output side.

[0308] 70, the input electrode pad 213a and the input electrode pad 239a are electrically connected via a connection switching transistor Q2 configured by a P-channel MOS transistor. ＋ A fourth semiconductor region 2216, which is a P-type semiconductor region, may be provided on the back surface of the first semiconductor region 2211. The connection switching transistor Q2 may be the P-channel IGBT described in the twenty-first embodiment.

[0309] On the other hand, the output electrode pad 213b and the output electrode pad 239b are electrically connected to each other via a connection switching transistor Q1 made up of an N-channel MOS transistor, as shown in FIG. ＋ A fourth semiconductor region 2206, which is a type semiconductor region, may be provided on the back surface of the first semiconductor region 2201. The connection switching transistor Q1 may be the N-channel IGBT described in the eighteenth embodiment.

[0310] According to the present embodiment described above, the conductivity type of the connection switching transistor Q2, which switches the electrical connection between the input electrode pad 213a and the input electrode pad 239a, is opposite to the conductivity type of the connection switching transistor Q1, which switches the electrical connection between the output electrode pad 213b and the output electrode pad 239b. Even when connection switching transistors of opposite conductivity types are used, the electrical connection between the second substrate 220 and the third substrate 230 can be switched. Therefore, by cutting off the electrical connection between the second substrate 220 and the third substrate 230, it is possible to improve the circuit operating speed and reduce power consumption.

[0311] 72 is a cross-sectional view showing the structure of a photodetector according to the 30th embodiment. In a photodetector 1030 according to this embodiment, some of the multiple input / output electrode pads are electrically connected to a connection switching transistor Q1, and the remaining input / output electrode pads are electrically connected to a through electrode 2024 that penetrates the second substrate 220. The sidewall of the through electrode 2024 is covered with a sidewall insulating film 2025. As a result, the through electrode 2024 is electrically insulated from the second semiconductor region 2202.

[0312] In the photodetector 1030 configured as described above, the connection switching transistor Q1 can switch the electrical connection between some of the input / output electrode pads and the second substrate 220 and the third substrate 230. Therefore, by cutting off the electrical connection between the second substrate 220 and the third substrate 230, it is possible to improve the circuit operation speed and reduce power consumption.

[0313] Fig. 73 is a cross-sectional view showing the structure of a photodetector according to a modified example of the 30th embodiment. In a photodetector 1030a shown in Fig. 73, among the electrical connection points between the second substrate 220 and the third substrate 230, the input / output electrode pads are connected to each other via a connection switching transistor Q1, and the wiring is connected to each other via a through electrode 2024. For example, the wiring 2026 shown in Fig. 73 is located in the same layer as the input electrode pad 213a or the output electrode pad 213b on the second substrate 220. Furthermore, the wiring 2027 shown in Fig. 73 is located in the same layer as the input electrode pad 239a or the output electrode pad 239b on the third substrate 230.

[0314] According to the photodetector device 1030a configured as described above, the connection switching transistor Q1 can switch the electrical connection between the second substrate 220 and the third substrate 230, and therefore, by cutting off the electrical connection between the second substrate 220 and the third substrate 230, it is possible to improve the circuit operating speed and reduce power consumption.

[0315] Thirty-first embodiment FIG. 74 is a block diagram showing an example of the configuration of an electronic device according to a thirty-first embodiment.

[0316] 74 is a video camera, a digital still camera, or the like. Electronic device 1000 includes a lens group 1001, a solid-state image sensor 1002, a DSP circuit 1003, a frame memory 1004, a display unit 1005, a recording unit 1006, an operation unit 1007, and a power supply unit 1008. DSP circuit 1003, frame memory 1004, display unit 1005, recording unit 1006, operation unit 1007, and power supply unit 1008 are interconnected via a bus line 1009.

[0317] The lens group 1001 takes in incident light (image light) from a subject and forms an image on the imaging surface of the solid-state imaging device 1002 .

[0318] The solid-state imaging device 1002 is any one of the photodetector devices according to the above-described embodiments. The solid-state imaging device 1002 converts the amount of incident light that is imaged on the imaging surface by the lens group 1001 into an electrical signal on a pixel-by-pixel basis and supplies the pixel signal to the DSP circuit 1003.

[0319] The DSP circuit 1003 performs predetermined image processing on the pixel signals supplied from the solid-state image sensor 1002, and supplies the processed image signals to a frame memory 1004 on a frame-by-frame basis for temporary storage.

[0320] The display unit 1005 is formed of a panel display device such as a liquid crystal panel or an organic EL (Electro Luminescence) panel, and displays an image based on pixel signals in frame units that are temporarily stored in the frame memory 1004 .

[0321] The recording unit 1006 is made up of a DVD (Digital Versatile Disk), a flash memory, or the like, and reads out and records the pixel signals in units of frames that are temporarily stored in the frame memory 1004 .

[0322] An operation unit 1007, under user operation, issues operation commands for various functions of the electronic device 1000. A power supply unit 1008 supplies power to the DSP circuit 1003, frame memory 1004, display unit 1005, recording unit 1006, and operation unit 1007.

[0323] The electronic device to which this technology can be applied may be any device that uses a photodetector in the image capture section (photoelectric conversion section), and in addition to the electronic device 1000, includes a portable terminal device with an imaging function and a copier that uses a photodetector in the image reading section.

[0324] The electronic device 1000 according to the present embodiment described above is equipped with any one of the photodetector devices according to the above-described embodiments as the solid-state imaging element 1002. This allows the chip size of the solid-state imaging element 1002 to be reduced, thereby enabling the electronic device 1000 to be miniaturized.

[0325] <Application to a Mobile Body> The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure may be realized as a device mounted on any type of mobile body, such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, personal mobility, an airplane, a drone, a ship, or a robot.

[0326] FIG. 75 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile object control system to which the technology of the present disclosure can be applied.

[0327] The vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001. In the example shown in Fig. 75, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside-vehicle information detection unit 12030, an inside-vehicle information detection unit 12040, and an integrated control unit 12050. Also shown as functional components of the integrated control unit 12050 are a microcomputer 12051, an audio / video output unit 12052, and an in-vehicle network I / F (interface) 12053.

[0328] The drivetrain control unit 12010 controls the operation of devices related to the drivetrain of the vehicle in accordance with various programs. For example, the drivetrain control unit 12010 functions as a control device for a drive force generating device for generating a drive force of the vehicle, such as an internal combustion engine or a drive motor, a drive force transmission mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, and a braking device for generating a braking force of the vehicle.

[0329] The body system control unit 12020 controls the operation of various devices equipped in the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various lamps such as headlamps, backup lamps, brake lamps, turn signals, and fog lamps. In this case, radio waves transmitted from a portable device that serves as a key or signals from various switches can be input to the body system control unit 12020. The body system control unit 12020 receives these radio waves or signals and controls the vehicle's door lock device, power window device, lamps, etc.

[0330] The outside-vehicle information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the outside-vehicle information detection unit 12030. The outside-vehicle information detection unit 12030 causes the imaging unit 12031 to capture images outside the vehicle and receives the captured images. The outside-vehicle information detection unit 12030 may perform object detection processing or distance detection processing for people, cars, obstacles, signs, characters on the road surface, etc. based on the received images.

[0331] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as an image or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

[0332] The in-vehicle information detection unit 12040 detects information inside the vehicle. For example, a driver state detection unit 12041 that detects the state of the driver is connected to the in-vehicle information detection unit 12040. The driver state detection unit 12041 includes, for example, a camera that captures an image of the driver, and the in-vehicle information detection unit 12040 may calculate the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 12041, or may determine whether the driver is dozing off.

[0333] The microcomputer 12051 can calculate control target values ​​for the driving force generating device, steering mechanism, or braking device based on the information inside and outside the vehicle acquired by the outside-vehicle information detection unit 12030 or the inside-vehicle information detection unit 12040, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing the functions of an ADAS (Advanced Driver Assistance System), including vehicle collision avoidance or impact mitigation, following driving based on the inter-vehicle distance, vehicle speed maintenance driving, vehicle collision warning, vehicle lane departure warning, etc.

[0334] In addition, the microcomputer 12051 can perform cooperative control for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on driver operation, by controlling the driving force generating device, steering mechanism, braking device, etc. based on information about the surroundings of the vehicle obtained by the outside vehicle information detection unit 12030 or the inside vehicle information detection unit 12040.

[0335] Furthermore, the microcomputer 12051 can output a control command to the body system control unit 12020 based on the information outside the vehicle acquired by the outside information detection unit 12030. For example, the microcomputer 12051 can control the headlamps according to the position of a preceding vehicle or an oncoming vehicle detected by the outside information detection unit 12030, and perform cooperative control aimed at preventing glare, such as switching from high beams to low beams.

[0336] The audio / video output unit 12052 transmits at least one of audio and video output signals to an output device capable of visually or audibly notifying the passengers of the vehicle or the outside of the vehicle of information. In the example of Fig. 75, the output devices are exemplified by an audio speaker 12061, a display unit 12062, and an instrument panel 12063. The display unit 12062 may include, for example, at least one of an on-board display and a head-up display.

[0337] FIG. 76 is a diagram showing an example of the installation position of the imaging unit 12031.

[0338] In FIG. 76, a vehicle 12100 has imaging units 12101, 12102, 12103, 12104, and 12105 as the imaging unit 12031.

[0339] The imaging units 12101, 12102, 12103, 12104, and 12105 are provided, for example, at positions such as the front nose, side mirrors, rear bumper, back door, and the top of the windshield inside the vehicle cabin of the vehicle 12100. The imaging unit 12101 provided on the front nose and the imaging unit 12105 provided on the top of the windshield inside the vehicle cabin mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 provided on the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 provided on the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The forward images acquired by the imaging units 12101 and 12105 are mainly used to detect preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, lanes, etc.

[0340] 76 shows an example of the imaging ranges of the imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of the imaging unit 12101 provided on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided on the side mirrors, respectively, and imaging range 12114 indicates the imaging range of the imaging unit 12104 provided on the rear bumper or back door. For example, by overlaying the image data captured by the imaging units 12101 to 12104, an overhead image of the vehicle 12100 viewed from above can be obtained.

[0341] At least one of the image capturing units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the image capturing units 12101 to 12104 may be a stereo camera made up of multiple image capturing elements, or may be an image capturing element having pixels for phase difference detection.

[0342] For example, based on the distance information obtained from the imaging units 12101 to 12104, the microcomputer 12051 can calculate the distance to each three-dimensional object within the imaging ranges 12111 to 12114 and the change in this distance over time (relative speed with respect to the vehicle 12100), thereby extracting as a preceding vehicle, in particular, the three-dimensional object that is the closest three-dimensional object on the path of the vehicle 12100 and traveling in approximately the same direction as the vehicle 12100 at a predetermined speed (e.g., 0 km / h or higher). Furthermore, the microcomputer 12051 can set a vehicle-to-vehicle distance to be maintained in advance in front of the preceding vehicle, and perform automatic braking control (including follow-up stop control), automatic acceleration control (including follow-up start control), etc. In this way, cooperative control can be performed for the purpose of autonomous driving, which runs autonomously without relying on driver operation.

[0343] For example, the microcomputer 12051 classifies and extracts three-dimensional object data regarding three-dimensional objects into two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects based on distance information obtained from the imaging units 12101 to 12104, and can use the data for automatic obstacle avoidance. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. The microcomputer 12051 then determines a collision risk that indicates the risk of collision with each obstacle, and when the collision risk is equal to or greater than a set value and a collision is possible, the microcomputer 12051 can provide driving assistance for collision avoidance by outputting an alarm to the driver via the audio speaker 12061 or the display unit 12062, or by performing forced deceleration or avoidance steering via the drive system control unit 12010.

[0344] At least one of the image capturing units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can recognize a pedestrian by determining whether a pedestrian is present in the images captured by the image capturing units 12101 to 12104. Such pedestrian recognition is performed, for example, by extracting feature points from the images captured by the image capturing units 12101 to 12104 as infrared cameras and performing pattern matching on a series of feature points that indicate the outline of an object to determine whether the object is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the images captured by the image capturing units 12101 to 12104 and recognizes the pedestrian, the audio / image output unit 12052 controls the display unit 12062 to superimpose a rectangular outline on the recognized pedestrian for emphasis. The audio / image output unit 12052 may also control the display unit 12062 to display an icon or the like indicating the pedestrian at a desired position.

[0345] An example of a vehicle control system to which the technology according to the present disclosure can be applied has been described above. The technology according to the present disclosure can be applied to, for example, the image capture unit 12031 of the above-described configuration. Specifically, the image capture unit 12031 can be equipped with any of the photodetector devices according to the above-described embodiments. By applying the technology according to the present disclosure to the image capture unit 12031, the chip size can be reduced. As a result, the vehicle 12100 can be made smaller.

[0346] Note that the above-described embodiments are examples for realizing the present technology, and the matters in the embodiments correspond to the matters specifying the invention in the claims. Similarly, the matters specifying the invention in the claims correspond to the matters in the embodiments of the present technology having the same names. However, the present technology is not limited to the embodiments, and can be realized by applying various modifications to the embodiments within the scope of the gist of the present technology.

[0347] The present technology can be configured as follows:

[0348] (1) A photodetector device comprising: a first substrate; at least one second substrate stacked below the first substrate; and a third substrate stacked below the second substrate, wherein the first substrate has a first circuit arrangement area in which a photoelectric conversion circuit that photoelectrically converts incident light is arranged, an opening area provided outside the first circuit arrangement area, and electrode pads exposed from the opening area, the second substrate has a second circuit arrangement area facing the first circuit arrangement area and a connection area provided outside the second circuit arrangement area and facing the electrode pads, and the third substrate has a third circuit arrangement area facing the second circuit arrangement area and a fourth circuit arrangement area provided outside the third circuit arrangement area and facing the electrode pads across the connection area.

[0349] (2) The photodetector according to (1), wherein an I / O circuit that performs input / output processing of signals is arranged in the fourth circuit arrangement region.

[0350] (3) The photodetector according to (1) or (2), wherein a first through electrode that penetrates the second substrate is provided in the connection region.

[0351] (4) The photodetector according to (3), wherein the material of the first through electrode is copper (Cu) or tungsten (W).

[0352] (5) A photodetector device as described in (3), wherein the first substrate is provided with a first contact via electrically connected to the electrode pad and a first lower electrode formed integrally with the first contact via, and the second substrate is provided with a first upper electrode joined to the first lower electrode and a second contact via formed integrally with the first upper electrode and electrically connected to the first through electrode.

[0353] (6) The photodetector according to (3) or (4), wherein the first substrate is provided with a first lower electrode electrically connected to the electrode pad, and the second substrate is provided with a first upper electrode joined to the first lower electrode and electrically connected to the first through electrode.

[0354] (7) A photodetector device according to (3) or (4), wherein the second substrate is provided with a third contact via electrically connected to the first through electrode and a second lower electrode formed integrally with the third contact via, and the third substrate is provided with a second upper electrode joined to the second lower electrode and a fourth contact via formed integrally with the second upper electrode.

[0355] (8) The photodetector according to any one of (1) to (7), further comprising a wiring layer provided with wiring electrically connected to the electrode pads, the electrode pads being disposed in the same layer as the wiring layer.

[0356] (9) The photodetector according to any one of (1) to (8), further comprising a semiconductor layer in which the photoelectric conversion circuit is provided, and the electrode pads are disposed in the same layer as the semiconductor layer.

[0357] (10) The photodetector according to any one of (1) to (9), wherein the electrode pad is disposed above the surface of the semiconductor layer on the light incident surface side of the semiconductor layer on which the photoelectric conversion circuit is provided.

[0358] (11) The photodetector according to any one of (1) to (10), further comprising a sampling and holding circuit that holds a pixel signal output from the photoelectric conversion circuit, wherein the sampling and holding circuit is arranged in the second circuit arrangement area.

[0359] (12) The photodetector according to (11), wherein the sample-and-hold circuit includes: a first capacitance element that holds a pixel signal at a reset level when the photoelectric conversion circuit is initialized; and a second capacitance element that holds a pixel signal at a data level generated by the photoelectric conversion circuit after the initialization.

[0360] (13) The photodetector according to any one of (1) to (12), further comprising an ADC (Analog-to-Digital Converter) circuit that digitally converts pixel signals generated by the photoelectric conversion circuit, wherein the ADC circuit is disposed in the second circuit arrangement area.

[0361] (14) The photodetector according to (3), wherein the second substrate has a silicon region of the second substrate that is surrounded in a frame shape by an element isolation film made of an insulating film in an area directly below the electrode pad, and is electrically floating.

[0362] (15) The photodetector according to (14), wherein the first through electrode is disposed in a region surrounded by the element isolation film.

[0363] (16) The photodetector according to (14), wherein the first through electrode is disposed outside a region surrounded by the element isolation film.

[0364] (17) The photodetector according to (14), wherein the element isolation film includes a first element isolation film surrounding the region directly below, and a second element isolation film adjacent to the first element isolation film and surrounding the first through electrode.

[0365] (18) The photodetector according to (3), wherein at least one second through electrode that penetrates the third substrate is provided in the fourth circuit placement region.

[0366] (19) The photodetector according to (18), wherein the second through electrode is disposed in a central portion of the fourth circuit arrangement region.

[0367] (20) The photodetector according to (18), wherein the fourth circuit arrangement region is rectangular, and portions of the two second through electrodes are arranged at corners of the fourth circuit arrangement region.

[0368] (21) The photodetector according to (18), wherein the fourth circuit arrangement region is rectangular, and portions of the four second through electrodes are arranged on sides of the fourth circuit arrangement region.

[0369] (22) The photodetector device according to (18), wherein two of the fourth circuit arrangement regions are arranged along one direction, and two of the second through electrodes arranged one in each of the two fourth circuit arrangement regions are arranged so as to be offset in a direction perpendicular to the one direction.

[0370] (23) The photodetector according to (18), wherein a portion of one of the second through electrodes protrudes outside the fourth circuit arrangement region.

[0371] (24) The photodetector according to (18), wherein an I / O circuit that performs input / output processing of signals is arranged in the fourth circuit arrangement region.

[0372] (25) The photodetector according to (24), wherein a portion of the second through-electrode is disposed in the fourth circuit arrangement region, and the I / O circuit is disposed outside the second through-electrode.

[0373] (26) The photodetector device according to (24), wherein the I / O circuit is arranged in two separate areas within the fourth circuit arrangement region, and the second through electrode is arranged between the two separate I / O circuits.

[0374] (27) The photodetector according to (1), further comprising dummy wiring arranged in at least one of the region directly below the electrode pad on the first substrate and the connection region.

[0375] (28) The photodetector according to (27), wherein the dummy wiring is arranged in a region surrounded by the second circuit arrangement region and the connection region.

[0376] (29) The photodetector according to (27) or (28), wherein the dummy wirings are arranged in layers.

[0377] (30) The photodetector according to (29), wherein the dummy wirings are arranged in a matrix or a staggered pattern.

[0378] (31) The photodetector according to any one of (27) to (30), wherein the cross-sectional shape of the dummy wiring is polygonal or circular.

[0379] (32) The photodetector according to any one of (27) to (31), wherein the pattern of the dummy wiring is a stripe pattern or a solid pattern.

[0380] (33) The photodetector according to (1), further comprising a wiring group arranged in the fourth circuit arrangement region, in which a plurality of wirings are connected in a mesh pattern.

[0381] (34) A photodetector device comprising: a first substrate; a second substrate stacked below the first substrate; and a third substrate stacked below the second substrate, wherein the first substrate has a first circuit arrangement area in which a photoelectric conversion circuit that photoelectrically converts incident light is arranged, and an opening area provided outside the first circuit arrangement area; the second substrate has a second circuit arrangement area facing the first circuit arrangement area, and a connection area provided outside the second circuit arrangement area, in which first electrode pads exposed from the opening area and connection switching transistors electrically connected to the first electrode pads are provided; and the third substrate has a third circuit arrangement area facing the second circuit arrangement area, and a fourth circuit arrangement area facing the connection area outside the third circuit arrangement area, in which electrical connection with the first electrode pads is switched by the connection switching transistor.

[0382] (35) The photodetector according to (34), wherein the connection switching transistor is a MOS transistor having a vertical structure, including: a first semiconductor region; a second semiconductor region having an opposite conductivity type to the first semiconductor region; a third semiconductor region having the same conductivity type as the first semiconductor region and facing the first semiconductor region across the second semiconductor region; and a gate electrode arranged between the first semiconductor region and the third semiconductor region via a gate oxide film.

[0383] (36) The photodetector according to (35), further including a fourth semiconductor region on a back surface side of the first semiconductor region, the fourth semiconductor region having an impurity concentration higher than that of the first semiconductor region.

[0384] (37) The photodetector according to (34), wherein the connection switching transistor is an IGBT (Insulated Gate Bipolar Transistor), including: a first semiconductor region; a second semiconductor region having an opposite conductivity type to the first semiconductor region; a third semiconductor region having the same conductivity type as the first semiconductor region and facing the first semiconductor region across the second semiconductor region; a fifth semiconductor region having an opposite conductivity type to the first semiconductor region and provided on the back surface side of the first semiconductor region; and a gate electrode arranged between the first semiconductor region and the third semiconductor region via a gate oxide film.

[0385] (38) The photodetector according to any one of (34) to (37), wherein the connection switching transistor has a trench-type gate electrode.

[0386] (39) The photodetector according to (35), wherein the conductivity type of the first semiconductor region and the third semiconductor region is P-type, and the conductivity type of the second semiconductor region is N-type.

[0387] (40) The fourth semiconductor region is P ＋ The photodetector according to (36), wherein the region is a semiconductor region.

[0388] (41) The fifth semiconductor region is N ＋ The photodetector according to (37), wherein the region is a semiconductor region.

[0389] (42) The photodetector according to (37), wherein the gate electrode is of a trench type.

[0390] (43) The photodetector device according to any one of (34) to (42), wherein the first electrode pad includes an input electrode pad that is part of a signal path transmitted from the second substrate to the third substrate, and an output electrode pad that is part of a signal path transmitted from the third substrate to the second substrate, and wherein both the first connection switching transistor connected to the input electrode pad and the second connection switching transistor connected to the output electrode pad are N-channel type, or the first connection switching transistor is P-channel type and the second connection switching transistor is N-channel type.

[0391] (44) The photodetector device according to any one of (34) to (43), wherein the second substrate has a plurality of first electrode pads, some of the plurality of first electrode pads being electrically connected to the connection switching transistor, and the remaining electrode pads being electrically connected to through electrodes that pass through the second substrate.

[0392] (45) The photodetector according to any one of (34) to (44), wherein the second substrate has a plurality of connection switching transistors and further has an element isolation film provided between the plurality of connection switching transistors.

[0393] (46) A photodetector device according to any one of (34) to (44), further comprising a fourth substrate provided between the second substrate and the third substrate, wherein the third substrate has a second electrode pad electrically connected to the connection switching transistor via the fourth substrate, and the fourth substrate has a third electrode pad electrically connected to the first electrode pad via the connection switching transistor, and another connection switching transistor arranged between the second electrode pad and the third electrode pad.

[0394] (47) The light detection device according to (46), wherein the second electrode pad is exposed from the rear surface side of the second substrate.

[0395] (48) The photodetector according to (46), further comprising a bump that joins the second electrode pad and the third electrode pad.

[0396] (49) The photodetector according to (35), wherein the second substrate has a plurality of connection switching transistors, and gate electrodes of the plurality of connection switching transistors are connected to each other.

[0397] (50) A photodetection device described in any one of (34) to (49), wherein pixels that generate pixel signals by photoelectrically converting incident light from an object are arranged in the first circuit arrangement area, a signal processing circuit that processes the pixel signals is arranged in the second circuit arrangement area, and a DNN (Deep Neural Network) circuit that recognizes the object based on the signal processed by the signal processing circuit is arranged in the third circuit arrangement area.

[0398] (51) An electronic device comprising a photodetector having a first substrate, at least one second substrate stacked below the first substrate, and a third substrate stacked below the second substrate, wherein the first substrate has a first circuit arrangement area in which a photoelectric conversion circuit that photoelectrically converts incident light is arranged, an opening area provided outside the first circuit arrangement area, and electrode pads exposed from the opening area, the second substrate has a second circuit arrangement area facing the first circuit arrangement area and a connection area provided outside the second circuit arrangement area and facing the electrode pads, and the third substrate has a third circuit arrangement area facing the second circuit arrangement area and a fourth circuit arrangement area provided outside the third circuit arrangement area and facing the electrode pads with the connection area in between.

[0399] 1 to 9: Photodetector 80: I / O circuit 110: Photoelectric conversion circuit 130: Sampling and holding circuit 131: First capacitance element 132: Second capacitance element 210: First substrate 211: First circuit arrangement area 212: Opening area 213: Electrode pads 213a, 239a, 241a: Input electrode pads 213b, 239b, 241b: Output electrode pads 214: First contact via 215: First lower electrode 220: Second substrate 221: Second circuit arrangement area 222: Connection area 223: First upper electrode 224: Second contact via 225: Through electrode 226: Third contact via 227: Second lower electrode 230: Third substrate 231: Third circuit arrangement area 232: Fourth circuit arrangement area 233: Second upper electrode 234: Fourth contact via 238: Wiring group 240: Element isolation film 240a: First element isolation film 240b: Second element isolation film 242: Bump 250: Dummy wiring 302: Semiconductor layer 303: Wiring layer 320: ADC circuit 1000: Electronic device 2201, 2211: First semiconductor region 2202, 2212: Second semiconductor region 2203, 2213: Third semiconductor region 2204: Gate electrode 2205: Gate oxide film 2206, 2216: Fourth semiconductor region 2207, 2217: Fifth semiconductor region 2210: Signal processing circuit 2220: Element isolation film 2310: DNN circuit 2400: Fourth substrate Q1 to Q3: Connection switching transistor

Claims

1. A photodetector comprising: a first substrate; at least one second substrate stacked below the first substrate; and a third substrate stacked below the second substrate, wherein the first substrate has a first circuit arrangement area in which a photoelectric conversion circuit that photoelectrically converts incident light is arranged, an opening area provided outside the first circuit arrangement area, and electrode pads exposed from the opening area, the second substrate has a second circuit arrangement area facing the first circuit arrangement area and a connection area provided outside the second circuit arrangement area and facing the electrode pads, and the third substrate has a third circuit arrangement area facing the second circuit arrangement area and a fourth circuit arrangement area provided outside the third circuit arrangement area and facing the electrode pads with the connection area in between.

2. The photodetector device according to claim 1, wherein an I / O circuit for performing input / output processing of signals is arranged in the fourth circuit arrangement region.

3. The photodetector according to claim 1, wherein a first through electrode that penetrates through the second substrate is provided in the connection region.

4. The photodetector device according to claim 3, wherein the material of the first through electrode is copper (Cu) or tungsten (W).

5. The photodetector device of claim 3, wherein the first substrate is provided with a first contact via electrically connected to the electrode pad and a first lower electrode formed integrally with the first contact via, and the second substrate is provided with a first upper electrode joined to the first lower electrode and a second contact via formed integrally with the first upper electrode and electrically connected to the first through electrode.

6. The photodetector device according to claim 3, wherein the first substrate is provided with a first lower electrode electrically connected to the electrode pad, and the second substrate is provided with a first upper electrode joined to the first lower electrode and electrically connected to the first through electrode.

7. The photodetector device described in claim 3, wherein the second substrate is provided with a third contact via electrically connected to the first through electrode and a second lower electrode formed integrally with the third contact via, and the third substrate is provided with a second upper electrode joined to the second lower electrode and a fourth contact via formed integrally with the second upper electrode.

8. The photodetector according to claim 1, further comprising a wiring layer provided with wiring electrically connected to said electrode pads, said electrode pads being disposed in the same layer as said wiring layer.

9. The photodetector according to claim 1, further comprising a semiconductor layer in which the photoelectric conversion circuit is provided, and the electrode pads are disposed in the same layer as the semiconductor layer.

10. The photodetector according to claim 1, wherein the electrode pad is disposed above the surface of the semiconductor layer on the light incident surface side of the semiconductor layer on which the photoelectric conversion circuit is provided.

11. The photodetector device according to claim 1, further comprising a sampling and holding circuit that holds a pixel signal output from said photoelectric conversion circuit, said sampling and holding circuit being arranged in said second circuit arrangement area.

12. The photodetector device according to claim 11, wherein the sample-and-hold circuit includes: a first capacitance element that holds a pixel signal at a reset level when the photoelectric conversion circuit is initialized; and a second capacitance element that holds a pixel signal at a data level generated by the photoelectric conversion circuit after the initialization.

13. The photodetector device according to claim 1, further comprising an ADC (Analog-to-Digital Converter) circuit that digitally converts pixel signals generated by the photoelectric conversion circuit, the ADC circuit being arranged in the second circuit arrangement area.

14. The photodetector device according to claim 3, wherein the second substrate has a silicon region directly below the electrode pad surrounded by a frame-like element isolation film made of an insulating film, and the silicon region of the second substrate is electrically floating.

15. The photodetector according to claim 14, wherein the first through electrode is disposed within a region surrounded by the element isolation film.

16. The photodetector according to claim 14, wherein the first through electrode is disposed outside the region surrounded by the element isolation film.

17. The photodetector according to claim 14, wherein the element isolation film comprises a first element isolation film surrounding the region directly below, and a second element isolation film adjacent to the first element isolation film and surrounding the first through electrode.

18. The photodetector device according to claim 3, wherein at least one second through electrode that penetrates through the third substrate is provided in the fourth circuit placement region.

19. The photodetector device according to claim 18, wherein the second through-electrode is disposed in a central portion of the fourth circuit arrangement region.

20. The photodetector device according to claim 18, wherein the fourth circuit arrangement region is rectangular, and portions of the two second through electrodes are arranged at corners of the fourth circuit arrangement region.

21. The photodetector device according to claim 18, wherein the fourth circuit arrangement region is rectangular, and portions of the four second through electrodes are arranged on the sides of the fourth circuit arrangement region.

22. The photodetector device according to claim 18, wherein two of the fourth circuit arrangement regions are arranged along one direction, and two of the second through electrodes arranged in each of the two fourth circuit arrangement regions are arranged so as to be offset in a direction perpendicular to the one direction.

23. The photodetector device according to claim 18, wherein a portion of one of the second through electrodes extends outside the fourth circuit placement area.

24. The photodetector device according to claim 18, wherein an I / O circuit for performing input / output processing of signals is arranged in the fourth circuit arrangement region.

25. The photodetector device according to claim 24, wherein a portion of the second through-electrode is disposed in the fourth circuit placement area, and the I / O circuit is disposed outside the second through-electrode.

26. The photodetector device according to claim 24, wherein the I / O circuit is arranged in two separate areas within the fourth circuit arrangement region, and the second through-electrode is arranged between the two separate I / O circuits.

27. The photodetector according to claim 1, further comprising dummy wiring arranged in at least one of the region directly below the electrode pad on the first substrate and the connection region.

28. The photodetector device according to claim 27, wherein the dummy wiring is arranged within an area surrounded by the second circuit arrangement area and the connection area.

29. The photodetector device according to claim 27, wherein the dummy wirings are arranged in layers.

30. The photodetector device according to claim 29, wherein the dummy wirings are arranged in a matrix or a staggered pattern.

31. The photodetector according to claim 27, wherein the cross-sectional shape of the dummy wiring is polygonal or circular.

32. The photodetector according to claim 27, wherein the pattern of the dummy wiring is a stripe pattern or a solid pattern.

33. The photodetector device according to claim 1, further comprising a wiring group arranged in the fourth circuit arrangement region, the wiring group including a plurality of wirings connected in a mesh pattern.

34. A photodetector device comprising: a first substrate; a second substrate stacked below the first substrate; and a third substrate stacked below the second substrate, wherein the first substrate has a first circuit arrangement area in which a photoelectric conversion circuit that photoelectrically converts incident light is arranged, and an opening area provided outside the first circuit arrangement area; the second substrate has a second circuit arrangement area facing the first circuit arrangement area, and a connection area provided outside the second circuit arrangement area and including first electrode pads exposed from the opening area and connection switching transistors electrically connected to the first electrode pads; and the third substrate has a third circuit arrangement area facing the second circuit arrangement area, and a fourth circuit arrangement area facing the connection area outside the third circuit arrangement area, where the electrical connection with the first electrode pads is switched by the connection switching transistor.

35. The photodetector device according to claim 34, wherein the connection switching transistor is a MOS transistor with a vertical structure, including: a first semiconductor region; a second semiconductor region having an opposite conductivity type to that of the first semiconductor region; a third semiconductor region having the same conductivity type as that of the first semiconductor region and facing the first semiconductor region across the second semiconductor region; and a gate electrode arranged between the first semiconductor region and the third semiconductor region via a gate oxide film.

36. The photodetector device according to claim 35, further comprising a fourth semiconductor region on the back surface side of said first semiconductor region, said fourth semiconductor region having an impurity concentration higher than that of said first semiconductor region.

37. The photodetector device according to claim 34, wherein the connection switching transistor is an IGBT (Insulated Gate Bipolar Transistor) including: a first semiconductor region; a second semiconductor region having an opposite conductivity type to that of the first semiconductor region; a third semiconductor region having the same conductivity type as that of the first semiconductor region and facing the first semiconductor region across the second semiconductor region; a fifth semiconductor region having an opposite conductivity type to that of the first semiconductor region and provided on the back surface side of the first semiconductor region; and a gate electrode arranged between the first semiconductor region and the third semiconductor region via a gate oxide film.

38. The photodetector device of claim 34, wherein the connection switching transistor has a trench-type gate electrode.

39. The photodetector device according to claim 35, wherein the conductivity types of the first semiconductor region and the third semiconductor region are P-type, and the conductivity type of the second semiconductor region is N-type.

40. The fourth semiconductor region is P ＋ 37. The photodetector of claim 36, wherein the photodetector is a semiconductor region.

41. The fifth semiconductor region is N ＋ 38. The photodetector of claim 37, wherein the photodetector is a semiconductor region.

42. The photodetector device of claim 37, wherein the gate electrode is trench-type.

43. The photodetector device described in claim 34, wherein the first electrode pad includes an input electrode pad that is part of a signal path transmitted from the second substrate to the third substrate, and an output electrode pad that is part of a signal path transmitted from the third substrate to the second substrate, and wherein both the first connection switching transistor connected to the input electrode pad and the second connection switching transistor connected to the output electrode pad are N-channel type, or the first connection switching transistor is P-channel type and the second connection switching transistor is N-channel type.

44. The photodetector device described in claim 34, wherein the second substrate has a plurality of first electrode pads, some of the plurality of first electrode pads being electrically connected to the connection switching transistor, and the remaining electrode pads being electrically connected to through electrodes that penetrate the second substrate.

45. The photodetector device according to claim 34, wherein the second substrate has a plurality of connection switching transistors, and further has an element isolation film provided between the plurality of connection switching transistors.

46. ​​The photodetector device of claim 34, further comprising a fourth substrate provided between the second substrate and the third substrate, the third substrate having a second electrode pad electrically connected to the connection switching transistor via the fourth substrate, and the fourth substrate having a third electrode pad electrically connected to the first electrode pad via the connection switching transistor, and another connection switching transistor disposed between the second electrode pad and the third electrode pad.

47. The photodetector device of claim 46, wherein the second electrode pad is exposed from the back surface side of the second substrate.

48. The photodetector device of claim 46, further comprising a bump that joins the second electrode pad and the third electrode pad.

49. The photodetector device according to claim 35, wherein the second substrate has a plurality of connection switching transistors, and the gate electrodes of the plurality of connection switching transistors are connected to each other.

50. A photodetector device as described in claim 34, wherein pixels that generate pixel signals by photoelectrically converting incident light from an object are arranged in the first circuit arrangement area, a signal processing circuit that processes the pixel signals is arranged in the second circuit arrangement area, and a DNN (Deep Neural Network) circuit that recognizes the object based on the signals processed by the signal processing circuit is arranged in the third circuit arrangement area.

51. An electronic device comprising a photodetector device having a first substrate, at least one second substrate stacked below the first substrate, and a third substrate stacked below the second substrate, wherein the first substrate has a first circuit arrangement area in which a photoelectric conversion circuit that photoelectrically converts incident light is arranged, an opening area provided outside the first circuit arrangement area, and electrode pads exposed from the opening area, the second substrate has a second circuit arrangement area facing the first circuit arrangement area and a connection area provided outside the second circuit arrangement area and facing the electrode pads, and the third substrate has a third circuit arrangement area facing the second circuit arrangement area and a fourth circuit arrangement area provided outside the third circuit arrangement area and facing the electrode pads with the connection area in between.

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