High-speed wafer defect measurement system having twin stages and high-speed wafer defect measurement method using same

Abstract

The present invention relates to a high-speed wafer defect measurement system that has inspection stages configured in a twin structure to increase inspection yield and realizes reduction of footprint, which is a space occupied by equipment, and to a high-speed wafer defect measurement method using same, wherein the high-speed wafer defect measurement system comprises: a first wafer defect measurement apparatus that performs surface detection and defect depth detection of a first wafer transferred by a robot arm; and a second wafer defect measurement apparatus that performs surface detection and defect depth detection of a second wafer transferred by the robot arm, wherein the first wafer defect measurement apparatus and the second wafer defect measurement apparatus may be positioned within a stroke area of the robot arm, thereby continuously inspecting defects in a plurality of wafers at high speed.

Description

High-speed wafer defect measurement system equipped with twin stage and high-speed wafer defect measurement method using the same

[0001] The present invention relates to a high-speed wafer defect measurement system equipped with a twin stage and a high-speed wafer defect measurement method using the same, and more particularly, to a high-speed wafer defect measurement system equipped with a twin stage, which increases the inspection yield by configuring the inspection stage as twin, realizes a reduction in the footprint, which is the space occupied by the equipment, and thus enables high-speed and precise detection of the surface of a plurality of wafers and the depth of defects, and can continuously and sequentially inspect the type of defect, the size of the defect, the depth of the defect, and the image of the defect, and a high-speed wafer defect measurement method using the same.

[0002] Typically, semiconductor devices are manufactured by performing several unit processes on a silicon wafer used as a semiconductor wafer to form an electrical circuit including electrical devices on the silicon wafer.

[0003] Recently, as the integration of semiconductor devices increases, the yield and reliability of semiconductor devices are significantly affected by the quality of the wafers on which they are manufactured. Wafer quality is determined by the number of defects generated throughout the entire wafer fabrication process, known as wafering, during crystal growth.

[0004] These wafer defects can be divided into crystal defects that occur during ingot growth and defects caused by external contaminants. Among these, external contaminants such as dust are easily removed through etching or cleaning processes, but crystal defects such as COP (Crystal Originated Particles), FPD (Flow Pattern Defect), OiSF (Oxygen Induced Stacking Fault), BMD (Bulk Micro Defect), and LDP (Large Dislocation Pit) are not removed by cleaning processes and remain, affecting the yield and quality of semiconductor devices. Therefore, their occurrence must be suppressed during the wafer manufacturing process. Therefore, confirming and inspecting the exact distribution and density of these defects before implementing semiconductor devices on the wafer is very important from the perspective of yield management.

[0005] That is, the wafers used in the manufacture of semiconductor devices, etc. are made by thinly slicing silicon ingots, and when the ingots are grown, impurities are mixed in due to the high growth temperature, and oxygen is absorbed by the quartz crucible at a rate of 10 7 ~10 8 They exist together in a single crystal of atom / cm3. During the growth of such ingots, air pockets are created due to voids or crystal defects where silicon atoms are absent, depending on the rotation speed or the amount of oxygen, and these air pockets are transferred to the wafers from which the ingot is sliced. Wafers with defects such as air pockets are mostly discarded. In addition, the wafers are subjected to thermal or physical stress while going through multiple processes. At this time, if there is even a small defect such as a crack in the wafer, new cracks may occur due to thermal or physical stress during the process, or defects in semiconductor devices may occur, resulting in a decrease in yield.

[0006] A wafer defect inspection device for inspecting defects on the surface or interior of a wafer, as described above, is known. Such an inspection device, for example, irradiates light from one side of the wafer's main surface, captures an image of the wafer from the other side, and analyzes the captured image to inspect for defects in the wafer.

[0007] The above wafer defects may include air pockets (hereinafter referred to as “pinholes”) existing on the surface or inside of the wafer, as well as hole defects (hereinafter referred to as “through holes”) that completely penetrate the wafer in the thickness direction of the wafer.

[0008] In addition, wafer defect inspection equipment usually operates in cassette units as receiving containers, and various types of wafers with different resistivity value ranges of 10 to 25 sheets are received in one cassette.

[0009] The above wafer defect inspection device typically utilizes a highly sensitive camera with a wide sensor dynamic range (DV) based on light source transmittance. Therefore, if the wafer contains through-holes, strong light will pass through them. In this case, a highly sensitive camera will experience smearing due to the strong light, making it difficult to accurately identify the defect.

[0010] In addition, in the wafer defect inspection device, it is basically configured as a single inspection device by mounting it on a single device that only performs inspection, but the single inspection device had room for improvement in terms of throughput.

[0011] Examples of such technologies are disclosed in patent documents 1 to 4 below.

[0012] For example, Patent Document 1 (Korean Patent Laid-Open Publication No. 2022-0007018, published on January 18, 2022) discloses a substrate receiving apparatus having a first placement section and a second placement section in which receiving containers for receiving substrates are respectively placed, a first inspection section and a second inspection section each having an imaging unit for taking images of the substrate for inspecting the substrate, a first transfer area provided with a first transfer mechanism that performs a first transfer operation for transferring the substrate between the receiving container placed in the first placement section and the first inspection section, and a second transfer area provided with a second transfer mechanism that performs a second transfer operation for transferring the substrate between the receiving container placed in the second placement section and the second inspection section, wherein the first placement section and the second placement section are provided at positions that do not overlap each other when viewed from a planar view, the first inspection section and the second inspection section are provided at positions that do not overlap each other when viewed from a planar view, and the first transfer area and the second transfer mechanism The region is disclosed for an inspection device which is provided at different positions when viewed from a plane so that the first return operation and the second return operation can be performed in parallel.

[0013] In addition, Patent Document 2 (Korean Patent Laid-Open No. 2023-0111273, published on July 25, 2027) discloses a substrate processing system comprising: an inspection device provided adjacent to a cassette station, which captures images of a substrate before being processed in a liquid processing device and a substrate after being processed in the liquid processing device; a feature extraction unit which extracts a predetermined feature from a substrate image of the substrate before being processed in the liquid processing device; a storage unit which stores a plurality of inspection recipes, each of which is set to correspond to a feature in a different range and includes an imaging condition when capturing an image in the inspection device; a recipe selection unit which selects an inspection recipe including an imaging condition corresponding to the feature extracted by the feature extraction unit from the inspection recipes stored in the storage unit; and a defect determination unit which acquires a substrate image of a substrate after being processed in the same liquid processing device as a substrate from which a feature is extracted from the substrate image before being processed in the liquid processing device according to the selected inspection recipe, and determines the presence or absence of a defect in the substrate image of the substrate after being processed in the liquid processing device.

[0014] In addition, Patent Document 3 (Korean Patent Publication No. 2013-0039880, published on April 23, 2013) discloses an inspection method for a wafer processing device, including the steps of: determining an idle time for waiting until performing a second process subsequent to the first process when a process performing a first process in at least one process chamber among a plurality of process chambers of a wafer processing device is completed; loading a test wafer into the process chamber in which the first process is completed when the idle time of the process chamber in which the first process is completed is equal to or greater than a preset reference time; and performing an inspection process on the process chamber in which the test wafer is loaded.

[0015] Meanwhile, Patent Document 4 (Korean Patent Publication No. 10-0963131, registered on June 4, 2010) discloses a wafer defect inspection method including (a) a step of performing automatic defect measurement after adjusting the microscope auto-focus at the first measurement point of the sample, (b) a step of automatically storing and aligning the measurement result value and the measurement image, (c) a step of moving the sample by a predetermined interval and performing automatic defect measurement after adjusting the microscope auto-focus, (d) a step of automatically storing and aligning the measurement result value and the measurement image, and (e) a step of sequentially repeating steps (c) and (d) until the measurement at the final measurement point is completed.

[0016] As described above, Patent Document 1 discloses a technology for improving throughput in an inspection device that inspects a substrate by providing a first placement unit, a second placement unit, a first inspection unit, and a second inspection unit, and Patent Document 2 is a structure in which a wafer transfer device that can move along a transfer path extending in the X direction is provided and can move up and down and around a vertical axis, and transfers wafers between a cassette on each cassette placement plate and a receiving device of a processing station, and Patent Document 3 is a structure in which multiple transfer units are provided to solve the problem that the overall facility operation rate is lowered because the wafer processing device must be stopped in order to load a test FOUP when all of the load ports of the wafer processing device are in operation, and there was a problem in that the foot print increased because a space for the movement of the wafer transfer device was provided.

[0017] Meanwhile, the above patent document 4 discloses a technology for evaluating the location, distribution, density, etc. of crystal defects existing on the surface and in the bulk of a wafer, but the semiconductor wafer defect measuring device disclosed in the above patent document, etc., was mainly capable of measuring only the x, y coordinates, and a separate measuring device had to be used for the z coordinate, so there was a problem that it was difficult to accurately measure the x, y, and z coordinates of the defect.

[0018] Additionally, there was a problem that production yield was reduced when inspecting up to the x, y and z coordinates for a single stage.

[0019] The purpose of the present invention is to solve the above-described problems, and to provide a high-speed wafer defect measurement system equipped with a twin stage that can inspect the x, y and z coordinates of the wafer to accurately identify the coordinates of defects on the wafer, thereby preventing problems that may occur in the semiconductor process and increasing production volume, and a high-speed wafer defect measurement method using the same.

[0020] Another object of the present invention is to provide a high-speed wafer defect measurement system equipped with a twin stage that can operate flexibly on each stage and ensure productivity when a problem occurs in the measurement equipment, and a high-speed wafer defect measurement method using the same.

[0021] Another object of the present invention is to provide a high-speed wafer defect measurement system equipped with a twin stage that has less impact on throughput than a single stage when inspection defects increase, and a high-speed wafer defect measurement method using the same.

[0022] In order to achieve the above object, the high-speed wafer defect measurement system according to the present invention is a high-speed wafer defect measurement system equipped with a twin stage for measuring defects in a wafer transported by a robot arm, the system including a wafer load module provided for inspecting and storing wafers, a wafer transfer module for transporting a wafer of the wafer load module to a robot arm, a wafer edge area inspection module for inspecting an edge area of ​​a wafer transported by the robot arm, a first wafer defect measurement device for performing surface detection and defect depth detection of a first wafer transported by the robot arm, and a second wafer defect measurement device for performing surface detection and defect depth detection of a second wafer transported by the robot arm, wherein the first wafer defect measurement device and the second wafer defect measurement device are characterized in that they are located within a stroke area of ​​the robot arm.

[0023] In addition, in the high-speed wafer defect measurement system according to the present invention, the first wafer defect measurement device includes a first surface detection module for detecting a surface state of the first wafer and a first defect depth detection module for detecting a defect depth of the first wafer, and the second wafer defect measurement device includes a second surface detection module for detecting a surface state of the second wafer and a second defect depth detection module for detecting a defect depth of the second wafer.

[0024] In addition, in the high-speed wafer defect measurement system according to the present invention, the first surface detection module and the first defect depth detection module are arranged parallel along the X-axis, and the second surface detection module and the second defect depth detection module are arranged parallel along the X-axis.

[0025] In addition, in the high-speed wafer defect measurement system according to the present invention, the first wafer defect measurement device further includes a first gantry as a structure provided on the first body and having the first surface detection module and the first defect depth detection module mounted therein, and the second wafer defect measurement device further includes a second gantry as a structure provided on the second body and having the second surface detection module and the second defect depth detection module mounted therein, and the first body and the second body are provided to be in contact with each other on the same plane, and the first gantry and the second gantry are provided to be in contact with each other.

[0026] In addition, in a high-speed wafer defect measurement system according to the present invention, a first linear servo and a first LM guide are mounted on both sides of the first main body, a first main table is mounted on the upper side of the first linear servo and the first LM guide so as to be movable in the Y-axis, a second linear servo and a second LM guide are mounted on both sides of the second main body, and a second main table is mounted on the upper side of the second linear servo and the second LM guide so as to be movable in the Y-axis.

[0027] In addition, in the high-speed wafer defect measurement system according to the present invention, a first line camera lighting unit and a first depth measurement lighting unit are provided between the first linear servo and the first LM guide, and a second line camera lighting unit and a second depth measurement lighting unit are provided between the second linear servo and the second LM guide.

[0028] In addition, in the high-speed wafer defect measurement system according to the present invention, the first main body is equipped with a first line lighting unit, the first line lighting unit includes an LED lamp or a halogen lamp, and the second main body is equipped with a second line lighting unit, the second line lighting unit includes an LED lamp or a halogen lamp.

[0029] In addition, in the high-speed wafer defect measurement system according to the present invention, the center line of the first wafer defect measurement device and the center line of the second wafer defect measurement device are located within the stroke area of ​​the robot arm.

[0030] In addition, in the high-speed wafer defect measurement system according to the present invention, a square-shaped first line camera bracket is coupled to the inside of the upper plate of the first gantry, a first Z-axis drive camera bracket is coupled to a side of the first line camera bracket, the first surface detection module is mounted inside the first line camera bracket, and the first defect depth detection module is mounted on the first Z-axis drive camera bracket, and a square-shaped second line camera bracket is coupled to the inside of the upper plate of the second gantry, a second Z-axis drive camera bracket is coupled to a side of the second line camera bracket, the second surface detection module is mounted inside the second line camera bracket, and the second defect depth detection module is mounted on the second Z-axis drive camera bracket.

[0031] In addition, in the high-speed wafer defect measurement system according to the present invention, the center line of the inspection load part of the load module and the center line of the storage load part of the load module are located within the stroke area of ​​the robot arm.

[0032] In addition, a high-speed measurement method of a wafer defect according to the present invention is a method of high-speed measuring a wafer defect using twin stages of a first stage and a second stage, characterized by comprising the steps of (a) taking out a wafer from a FOUP (Front Opening Unified Pod) provided in an inspection load unit, (b) seating the wafer taken out in step (a) on a wafer edge area inspection module, and inspecting a crack defect or a damage defect in the edge area of ​​the wafer and aligning a notch, (c) seating the wafer, whose notch position is aligned in step (b), on a first wafer defect measurement device of the first stage, and detecting a surface defect and measuring a defect depth, (d) seating the wafer, whose notch position is aligned in step (b), on a second wafer defect measurement device of the second stage, and detecting a surface defect and measuring a defect depth, (e) taking out the wafer, whose defect is measured in step (c) or step (d), and mounting it on a storage load unit.

[0033] In addition, in the high-speed wafer defect measurement method according to the present invention, it is characterized in that the control module determines the progress from step (b) to step (c) or the progress from step (b) to step (d) according to the inspection time in the first wafer defect measurement device and / or the second wafer defect measurement device.

[0034] In addition, in the high-speed measurement method for wafer defects according to the present invention, it is characterized in that the withdrawal and placement of the wafer in steps (a) to (e) are sequentially and continuously performed by a single robot arm.

[0035] In addition, in the high-speed wafer defect measurement method according to the present invention, it is characterized in that the wafer surface defect detection and defect depth measurement in the first wafer defect measurement device and the wafer surface defect detection and defect depth measurement in the second wafer defect measurement device are performed simultaneously.

[0036] In addition, in the high-speed measurement method for wafer defects according to the present invention, the single robot arm is provided on the main body of a wafer transfer module fixed within the system, and is characterized in that it is provided to be able to move up and down on the main body and to move forward and backward left and right within a stroke area.

[0037] In addition, in the high-speed measurement method for wafer defects according to the present invention, the withdrawal and placement of the wafer in steps (a) to (b) are sequentially and continuously performed by a first robot arm, and the withdrawal and placement of the wafer in steps (c) to (e) are sequentially and continuously performed by a second robot arm.

[0038] As described above, according to the high-speed wafer defect measurement system equipped with a twin stage according to the present invention and the high-speed wafer defect measurement method using the same, the first wafer defect measurement device and the second wafer defect measurement device are positioned within the stroke area of ​​the robot arm, thereby obtaining the effect of increasing production while maintaining the same inspection performance as the existing defect measurement device.

[0039] In addition, according to the high-speed wafer defect measurement system equipped with a twin stage according to the present invention and the high-speed wafer defect measurement method using the same, since the first wafer defect measurement device and / or the second wafer defect measurement device can sequentially and simultaneously inspect the wafer for defects, the effect of being able to continuously perform defect inspections on a plurality of wafers at high speed is also obtained.

[0040] Figure 1 is a block diagram of a high-speed wafer defect measurement system equipped with a twin stage according to the present invention;

[0041] Figure 2 is a configuration diagram of the high-speed wafer defect measurement system illustrated in Figure 1;

[0042] Figure 3 is a front perspective view of a first wafer defect measurement device and a second wafer defect measurement device as a twin stage according to the present invention;

[0043] Figure 4 is a rear perspective view of a first wafer defect measurement device and a second wafer defect measurement device as twin stages according to the present invention;

[0044] Figure 5 is a front perspective view of the first wafer defect measurement device illustrated in Figure 3;

[0045] Figure 6 is a rear perspective view of the first wafer defect measurement device illustrated in Figure 3;

[0046] Figure 7 is a plan view of the first wafer defect measurement device and the second wafer defect measurement device shown in Figure 3;

[0047] Figure 8 is a front cross-sectional view of the first wafer defect measurement device and the second wafer defect measurement device shown in Figure 3;

[0048] Figure 9 is a flow chart for explaining a high-speed measurement method of wafer defects using a twin stage according to the present invention.

[0049] FIG. 10 is a drawing showing a state in which a robot arm according to one embodiment of the present invention has moved to an inspection load section;

[0050] Figure 11 is a drawing showing a state in which the robot arm has moved to the wafer edge area inspection module.

[0051] Figure 12 is a drawing showing a state in which the robot arm has moved to the first wafer defect measurement device.

[0052] Figure 13 is a drawing showing a state in which the robot arm has moved to the second wafer defect measurement device.

[0053] Figure 14 is a drawing showing a state in which the robot arm has moved to the storage load section.

[0054] FIG. 15 is a drawing showing a state in which a robot arm according to another embodiment of the present invention has moved to a second wafer defect measurement device.

[0055] The above and other objects and novel features of the present invention will become more apparent with the description of this specification and the accompanying drawings.

[0056] In the description of the present invention, when it is said that a part "includes" a certain component, this does not mean that other components are excluded, but rather that other components can be included, unless specifically stated otherwise.

[0057] In addition, the term "member," "module," or "part" used herein performs at least one function or operation, and may be implemented as hardware or software consisting of a mechanical configuration or an electrical / electronic configuration, or may be implemented as a combination of hardware and software, and a plurality of "members," "modules," or a plurality of "parts" may be integrated into at least one module and implemented as at least one processor, except for a "member," "module," or "part" that needs to be implemented as a specific hardware.

[0058] In addition, as a term used herein, "left-right direction and front-back direction" means the X-axis and Y-axis directions as directions parallel to the surface on which the wafer applied to the present invention is mounted, and "up-down direction" means the Z-axis direction as a direction perpendicular to the horizontal direction formed by the X-axis and Y-axis, and as a term used herein, "wafer defect" may include defects such as cracks, defects, or damage in the edge region of the wafer, defects in the surface of the wafer, and the like, and "wafer defect measurement" may include the measurement of the type of defect, the size of the defect, the depth of the defect, and the image of the defect according to inspection of the edge region of the wafer, detection of the surface of the wafer, and detection of the depth of the defect.

[0059] Meanwhile, a small footprint is crucial for semiconductor equipment. While converting a single device into a twin device typically requires at least 1.5 times the space, the present invention optimizes the unit shape and layout, enabling the application of a high-speed wafer defect measurement system equipped with a twin stage in approximately 1.16 times the space.

[0060] In addition, the size and thickness of each component shown in the description and drawings of the present invention are arbitrarily shown for convenience of explanation, and therefore the present invention is not necessarily limited to what is shown.

[0061] Hereinafter, embodiments of the present invention will be described with reference to the drawings.

[0062] FIG. 1 is a block diagram of a high-speed wafer defect measurement system equipped with a twin stage according to the present invention, and FIG. 2 is a configuration diagram of the high-speed wafer defect measurement system illustrated in FIG. 1.

[0063] The high-speed wafer defect measurement system illustrated in FIGS. 1 and 2 may include a first wafer defect measurement device (100), a second wafer defect measurement device (100'), a wafer load module (200) provided for inspecting and storing wafers, a wafer transfer module (300) for transferring a wafer (W) of the wafer load module with a single robot arm (310), a wafer edge area inspection module (400) for inspecting an edge area of ​​a wafer (W) transferred by the single robot arm (310), and a control module (500) for controlling the operation of each device and module of the high-speed wafer defect measurement system.

[0064] Therefore, in the high-speed wafer defect measurement system equipped with a twin stage according to the present invention, the inspection of the edge area of ​​the wafer (W), detection of the surface of the wafer, and measurement of the type of defect, size of the defect, depth of the defect, and defect image according to the detection of the depth of the defect can be performed simultaneously or sequentially. That is, in Fig. 2, for convenience of explanation, a state in which the wafer (W) is seated on each of the first wafer defect measurement device (100), the second wafer defect measurement device (100'), the wafer load module (200), and the wafer edge area inspection module (400) is shown.

[0065] The first wafer defect measurement device (100), the second wafer defect measurement device (100'), the wafer load module (200), and the wafer edge area inspection module (400) may be positioned within a stroke area of ​​a single robot arm (310) of the wafer transfer module (300). That is, the main body of the wafer transfer module (300) may move left and right within the system along a rail (320), and the single robot arm (310) provided on the main body may move up and down within the main body, and may be provided to move left and right, forward and backward within the stroke area for the first wafer defect measurement device (100), the second wafer defect measurement device (100'), the wafer load module (200), and the wafer edge area inspection module (400) to transport the wafer (W).

[0066] The first wafer defect measurement device (100) and the second wafer defect measurement device (100') are described with reference to FIGS. 3 and 4.

[0067] FIG. 3 is a front perspective view of a first wafer defect measurement device and a second wafer defect measurement device as twin stages according to the present invention, and FIG. 4 is a rear perspective view of a first wafer defect measurement device and a second wafer defect measurement device as twin stages according to the present invention.

[0068] The first wafer defect measurement device (100) and the second wafer defect measurement device (100') can simultaneously or sequentially measure defects of the first wafer (1) and the second wafer (1') as substrates transported by a single robot arm (310), as shown in FIGS. 3 and 4.

[0069] Meanwhile, the expressions 'first' and 'second' may be used for the respective identical components of the first wafer defect measurement device (100) and the second wafer defect measurement device (100'). That is, the first wafer defect measurement device (100) may include a first main body (10) and a first gantry (20) as a structure for installing a measurement device such as a camera on the first main body (10), and the second wafer defect measurement device (100') may include a second main body (10') and a second gantry (20') as a structure on the second main body (10').

[0070] In addition, as illustrated in FIGS. 2 to 4, the first wafer defect measurement device (100) may include a first surface detection module (110) for detecting the surface state of the first wafer (1) and a first defect depth detection module (120) for detecting the defect depth of the first wafer (1), and the second wafer defect measurement device (100') may include a second surface detection module (110') for detecting the surface state of the second wafer (1') and a second defect depth detection module (120') for detecting the defect depth of the second wafer (1').

[0071] The first body (10) and the second body (10') may be formed, for example, with an aluminum plate, and may be formed to contact each other on the same plane, as illustrated in FIGS. 2 to 4. That is, the first body (10) and the second body (10') may be formed as twin stages.

[0072] The first gantry (20) and the second gantry (20') are provided in the shape of first and second support plates on each of the two sides of the first main body (10) and the second main body (10'), respectively, as illustrated in FIGS. 3 and 4, and may be formed as an upper plate connecting the upper portions of the first and second support plates. That is, the first gantry (20) and the second gantry (20') may be provided in an approximately "ㄷ" shape when viewed in plan from above.

[0073] A square-shaped first line camera bracket (21) is coupled to the inside of the upper plate of the first gantry (20), and a first Z-axis drive camera bracket (22) is coupled to a side of the first line camera bracket (21), and a first surface detection module (110) for detecting the surface state of the first wafer (1) is mounted inside the first line camera bracket (21), and a first defect depth detection module (120) for detecting the defect depth of the first wafer (1) can be mounted on the first Z-axis drive camera bracket (22).

[0074] In addition, a square-shaped second line camera bracket (21') is coupled to the inside of the upper plate of the second gantry (20'), a second Z-axis drive camera bracket (22') is coupled to a side of the second line camera bracket (21'), a second surface detection module (110') for detecting the surface state of the second wafer (1') may be mounted inside the second line camera bracket (21'), and a second defect depth detection module (120') for detecting the defect depth of the second wafer (1') may be mounted in the second Z-axis drive camera bracket (22'). In addition, as illustrated in FIGS. 3 and 4, the first gantry (20) and the second gantry (20') may be arranged to be in contact with each other.

[0075] As described above, in the high-speed wafer defect measurement system equipped with a twin stage according to the present invention, the surface detection module (110, 110') for detecting the surface state of the wafer (W, 1, 1') and the defect depth detection module (120, 120') for detecting the defect depth of the wafer (1, 1') are arranged in parallel along the X-axis as shown in FIGS. 3 and 4, thereby realizing reduction of the footprint, which is the space occupied by the twin stage equipment.

[0076] The specific structures of each of the first wafer defect measurement device (100) and the second wafer defect measurement device (100') described above will be described with reference to FIGS. 5 and 6.

[0077] Fig. 5 is a front perspective view of the first wafer defect measurement device illustrated in Fig. 3, and Fig. 6 is a rear perspective view of the first wafer defect measurement device illustrated in Fig. 3.

[0078] In addition, since the first wafer defect measurement device (100) and the second wafer defect measurement device (100') have the same configuration, only the configuration of the first wafer defect measurement device (100) is described for convenience of explanation, as shown in FIGS. 5 and 6, but the same can be applied to the configuration of the second wafer defect measurement device (100').

[0079] As shown in FIGS. 5 and 6, a first gantry (20) having a roughly 'ㄷ' shape is provided in the first main body (10) of the first wafer defect measurement device (100), a first main table (30) that can move in the Y-axis is provided on the upper part of the first main body (10), and a first sub-table (40) that can move in the X-axis is provided on the upper part of the first main table (30).

[0080] In addition, a first screen plate (50) formed in a roughly circular shape is mounted on the first sub-table (40) to block light that may be applied from the outside of the first wafer (1) when inspecting the first wafer (1), and a plurality of first wafer supports (60) that support the first wafer (1) can be mounted along the periphery of the first screen plate (50).

[0081] On both sides of the first main body (10), a first linear servo (70) and a first LM guide (71) are provided between the first and second support plates of the first gantry (20) to support the first main table (30) so that the first main table (30) can move in the Y-axis. That is, the first linear servo (70) is provided to drive the first main table (30) in the Y-axis, and the first LM guide (71) is provided to support the first main table (30) that can move in the Y-axis. That is, a first linear servo (70) and a first LM guide (71) are mounted on both sides of the first main body (10), and a first main table (30) is mounted on the upper side of the first linear servo (70) and the first LM guide (71) so as to be movable in the Y-axis, and a second linear servo (70') and a second LM guide (71') are mounted on both sides of the second main body (10'), and a second main table (30') can be mounted on the upper side of the second linear servo (70) and the second LM guide (71') so as to be movable in the Y-axis.

[0082] As described above, in the high-speed wafer defect measurement system equipped with a twin stage according to the present invention, the first linear servo (70) and the first LM guide (71) are provided at the bottom of the first main table (30) so that the first main table (30) can move in the Y-axis inside the first gantry (20), and the second linear servo (70') and the second LM guide (71') are provided at the bottom of the second main table (30') so that the second main table (30') can move in the Y-axis inside the second gantry (20'), thereby reducing the size of the first wafer defect measurement device (100) and the second wafer defect measurement device (100').

[0083] The first sub-table (40) is provided to be movable in the X-axis by being driven by a first servo actuator (80), as shown in FIG. 6, and the first servo actuator (80) can be operated by being coupled to a first clean cable bearer (81) used as a pneumatic tube and wire passage.

[0084] The first screen plate (50) may be provided to be able to move up and down on the first sub-table (40) by a first up-and-down cylinder (90) that may be operated by pneumatic or hydraulic pressure. Accordingly, the first screen plate (50) may be provided to be able to move up and down on the inside of a plurality of first wafer supports (60) in order to block light that may be applied from the outside during the inspection process for the first wafer (1). To this end, a cut-out portion for movement of the first screen plate (50) may be provided on the inside of the plurality of first wafer supports (60).

[0085] The above-described plurality of first wafer supports (60) are provided in a structure in which three are arranged at 120-degree intervals as shown in FIGS. 5 and 6, but are not limited thereto and may be provided in a structure of four or more depending on the type of wafer.

[0086] The above first surface detection module (110) is provided for surface inspection to check the size, position, and dimensions of the wafer and whether there are microcracks, pinholes, stains (foreign substances), etc. on the surface or back surface of the wafer, and may include a first line camera adjustment unit (111), three first line scan cameras (112), a first lens (113) for the line scan camera, a first line camera lighting unit (114), and a line lighting unit (115) composed of near-infrared (NIR) light, as shown in FIGS. 5 and 6.

[0087] That is, the first surface detection module (110) can detect defects such as foreign substances, cracks, scratches, pinholes, etc. existing on the surface or inside of the first wafer (1) by obtaining an image through three first line scan cameras (112) having imaging elements arranged in a band shape using transmitted light, for example, infrared light of 1050 nm to 1100 nm, which passes through the first wafer (1), and can irradiate visible light that does not pass through the wafer, for example, visible light with a wavelength of 400 nm to 700 nm, toward the first wafer (1), obtain an image of the first wafer (1) using a through-hole camera on the other side of the first wafer (1), and inspect the through-hole of the first wafer (1) by determining whether light is transmitted, and re-acquire an image of the defect through a review camera at the defect location detected through the first line scan camera (112) to re-judge whether there is a defect. In addition, in the first surface detection module (110), the size of the line lighting unit (115) can be reduced by applying a halogen lamp or an LED lamp.

[0088] The first defect depth detection module (120) includes a depth detection camera that detects the location (hereinafter referred to as “depth”) of the defect detected through the first surface detection module (110) with respect to the thickness of the wafer, and a first depth measurement lighting unit (121). The depth detection camera is designed to have a relatively smaller depth of focus than the thickness of the wafer, so that it can accurately measure defects of 1 μm to 3000 μm in size existing in the wafer. That is, the first defect depth detection module (120) can automatically find the surface of the wafer (1) and detect the location of the defect in the wafer (1) by taking pictures 30 times at intervals of 25 μm in the depth direction, for example.

[0089] Next, the reduction of the footprint according to the high-speed wafer defect measurement system equipped with a twin stage according to the present invention is described with reference to FIGS. 7 and 8.

[0090] Fig. 7 is a plan view of the first wafer defect measurement device and the second wafer defect measurement device illustrated in Fig. 3, and Fig. 8 is a front cross-sectional view of the first wafer defect measurement device and the second wafer defect measurement device illustrated in Fig. 3.

[0091] As shown in FIG. 7, the first surface detection module (110) and the first defect depth detection module (120) of the first wafer defect measurement device (100) according to the present invention are arranged parallel along the X-axis inside the first gantry (20), and the first defect depth detection module (120) is provided within the width direction region of the first surface detection module (110) at the rear of the first surface detection module (110), as shown in the horizontal region A for the camera inspection of the wafer, and the second surface detection module (110') and the second defect depth detection module (120') of the second wafer defect measurement device (100') are arranged parallel along the X-axis inside the second gantry (20'), and the second defect depth detection module (120') is provided within the width direction region of the second surface detection module (110') at the rear of the second surface detection module (110'). It is provided so that the inspection area of ​​the camera inspection can be minimized.

[0092] In addition, as shown in FIGS. 7 and 8, a first linear servo (70) and a first LM guide (71) are provided inside between the first and second support plates of the first gantry (20), and a second linear servo (70') and a second LM guide (71') are provided inside between the first and second support plates of the second gantry (20'), and the first linear servo (70) and the first LM guide (71) are mounted on the lower portion of the first main table (30) to support the first main table (30), and the second linear servo (70') and the second LM guide (71') are mounted on the lower portion of the second main table (30') to support the second main table (30'), so that a reduction in the footprint can be realized in a high-speed wafer defect measurement system equipped with a twin stage.

[0093] The wafer load module (200) may include an inspection load unit (210) and a storage load unit (220), each having a wafer receiving container and a load port for vertically stacking and receiving each wafer (W), as illustrated in FIGS. 1 and 2. That is, in the inspection load unit (210), an inspection wafer receiving container having a plurality of wafers to be inspected in the high-speed wafer defect measurement system according to the present invention, for example, 25 wafers (W), mounted thereon may be mounted on a first load port, and in the storage load unit (220), a storage wafer receiving container having a plurality of wafers, for example, 25 wafers, on which inspection of the wafers (W) has been completed according to the present invention, may be mounted on a second load port. As the wafer receiving container, for example, a FOUP (Front Opening Unified Pod) transported from an OHT (Overhead Hoist Transport) may be applied.

[0094] The above wafer transfer module (300) is equipped with a robot arm (310) that is mounted on the inspection load section (210) of the wafer load module (200) to load and unload the wafer (W) to be inspected to the wafer edge area inspection module (400) and the first wafer defect measurement device (100) and the second wafer defect measurement device (100'). The robot arm (310) may be provided with an edge grip section for holding the wafer or a vacuum suction section such as a vacuum chuck.

[0095] The above robot arm (310) is provided with a plurality of joints and can be deployed in a horizontal direction and can move left and right or forward and backward within a single robot driving stroke range. That is, since the center line of the first wafer defect measurement device (100), the center line of the second wafer defect measurement device (100'), the center line of the inspection load unit (210), and the center line of the storage load unit (220) are within the robot driving stroke range of the wafer transfer module (300), handling of the wafer is possible within the entire system by the wafer transfer module (300), thereby minimizing the inspection stage.

[0096] The above wafer edge area inspection module (400) may be provided as a device for inspecting the edge area of ​​a wafer for defects such as cracks, defects, or damage and for inspecting the edge area of ​​a wafer for aligning notches.

[0097] The above control module (500) may include a microprocessor for controlling the operation of the first wafer defect measurement device (100), the second wafer defect measurement device (100'), the wafer load module (200), the wafer transfer module (300), and the wafer edge area inspection module (400), and a memory for storing information on the above-described operation.

[0098] As described above, the high-speed wafer defect measurement system according to the present invention can be applied to a target wafer, for example, a 300 mm silicon wafer (polished), in which the minimum detectable size is 8 ㎛, the measurement items are pinholes, through holes, etc., the throughput is 200 wfr / h, the depth repeatability is < ±3 ㎛, the wafer handling is a single-arm robot (edge ​​clamp), and the installation area (mm) is 1,800 (W) x 2,530 (D) x 2,000 (H).

[0099] Next, a method for measuring wafer defects at high speed by applying a high-speed wafer defect measurement system as described above will be described with reference to FIGS. 9 to 14.

[0100] FIG. 9 is a flowchart for explaining a high-speed method for measuring wafer defects using a twin stage according to the present invention.

[0101] First, when the FOUP transferred from the OHT is mounted on the load port and the cover of the FOUP is opened, the robot arm (310) can move to the inspection load unit (210) and take out the wafer (W) to be inspected (S10) as shown in FIG. 10 by the control of the control module (500). FIG. 10 is a drawing showing a state in which the robot arm according to one embodiment of the present invention has moved to the inspection load unit. In addition, a unique ID is assigned to each of a plurality of wafers accommodated in the FOUP, for example, 25 wafers, so that the wafers to be inspected can be identified. In this way, information on the wafers assigned with unique IDs can be transmitted from a separately provided host controller to the control module (500) of the high-speed wafer defect measurement system and stored in the memory.

[0102] The wafer (W) withdrawn in the above step S10 is placed on the wafer edge area inspection module (400) by the robot arm (310) moving along the rail (320), as shown in FIG. 11, and the wafer edge area inspection module (400) can inspect the edge area of ​​the wafer for defects such as cracks, defects, or damage, and align the notch (S20). The above steps S10 to S20 can be executed sequentially and continuously. FIG. 11 is a drawing showing a state in which the robot arm has moved to the wafer edge area inspection module.

[0103] When the notch position of the wafer (W) is aligned in the above step S20, the control module (500) determines whether a defect measurement operation of the wafer (W) is executed in the first wafer defect measurement device (100) and / or the second wafer defect measurement device (100') (S30). In the initial state of the high-speed wafer defect measurement system equipped with a twin stage according to the present invention, the wafer (W) with the notch aligned in the wafer edge area inspection module (400) may be sequentially seated in the first wafer defect measurement device (100), which is the first stage, and subsequently, the wafer (W) with the notch aligned in the wafer edge area inspection module (400) may be seated in the second wafer defect measurement device (100'), which is the second stage.

[0104] That is, the wafer (W) whose notch position is aligned in the wafer edge area inspection module (400) according to the judgment in the above step S30 is placed on the first wafer defect measurement device (100) by the robot arm (310) as shown in FIG. 12, and the presence or absence of a defect is inspected by the first line scan camera (112) (S40). FIG. 12 is a drawing showing a state in which the robot arm has moved to the first wafer defect measurement device.

[0105] In addition, the wafer (W) whose notch position is aligned in the wafer edge area inspection module (400) according to the judgment in the above step S30 is placed on the second wafer defect measurement device (100') by the robot arm (310) moving along the rail (320), as shown in FIG. 13, and the presence or absence of a defect is inspected by the second line scan camera (S80). FIG. 13 is a drawing showing a state in which the robot arm has moved to the second wafer defect measurement device.

[0106] In the above step S40, if it is determined that there is a defect by the first line scan camera (112) of the first surface detection module (110) provided in the first wafer defect measurement device (100) (S50), the defect location of the wafer (W) can be detected by taking pictures 30 times at 25 μm intervals in the depth direction by the depth detection camera of the first defect depth detection module (120) (S60).

[0107] Information about the wafer (W) inspected in the above step S60, for example, normal information or defect information of the wafer (W), may be transmitted to the control module (500) and sent to a separately provided host controller. In addition, the wafer (W) inspected in the above step S60 may be mounted on the storage load unit (220) by the robot arm (310), as illustrated in FIG. 14 (S70). FIG. 14 is a drawing showing a state in which the robot arm has moved to the storage load unit.

[0108] In addition, in the step S80, if it is determined that there is a defect by the second line scan camera of the second surface detection module provided in the second wafer defect measurement device (100') (S90), the depth detection camera of the second defect depth detection module (120') can take pictures 30 times at 25 μm intervals in the depth direction to detect the location of the defect in the wafer (W) (S100). The wafer (W) for which the inspection is completed in the step S100 can be mounted on the storage load unit (220) by the robot arm (310), as illustrated in FIG. 14 (S70).

[0109] Meanwhile, if no defect is found in the wafer (W) in step S50, the process proceeds to step S70, where the robot arm (310) can take out the wafer (W) from the first wafer defect measurement device (100) and mount it on the storage load unit (220). In addition, if no defect is found in the wafer (W) in step S90, the process proceeds to step S70, where the robot arm (310) can take out the wafer (W) from the second wafer defect measurement device (100') and mount it on the storage load unit (220).

[0110] That is, each wafer mounted on the FOUP of the storage load unit (220) can be mounted according to the position corresponding to the unique ID assigned to each wafer in the FOUP provided in the inspection load unit (210), regardless of the inspection order. Information on each wafer (W) mounted on the FOUP of the storage load unit (220) is transmitted to the host controller through the control module (500), and each wafer (W) can be separated through separate sorting equipment. However, it is not limited thereto, and a structure may be provided in which a normal wafer (W) inspected in step S50 or S90 is stored in the FOUP of the inspection load unit (210), and a defective wafer (W) inspected in step S60 or S100 is stored in the FOUP of the storage load unit (220).

[0111] After the above step S70, the process can proceed to the above step S10 and repeat the above-described process.

[0112] As described above, in the high-speed wafer defect measurement method using a twin stage according to the present invention, since the first wafer defect measurement device (100) and / or the second wafer defect measurement device (100') continuously performs wafer defect inspection, it is possible to inspect wafer defects at a speed at least twice as fast as in the conventional technology using a single wafer defect measurement device.

[0113] Meanwhile, in the process of repetitive defect inspection for a plurality of wafers, the inspection time in the first wafer defect measurement device (100) and / or the second wafer defect measurement device (100') may be different. That is, in the actual defect inspection process, most of the wafers (W) do not have defects, but one or more defects may occur in the wafers (W). Therefore, since the inspection time in the first wafer defect measurement device (100) and / or the second wafer defect measurement device (100') is different depending on the presence or absence of defects or the number of defects in the wafers (W), the control module (500) determines the defect measurement operation status in the first wafer defect measurement device (100) and the second wafer defect measurement device (100').

[0114] For example, when the first wafer defect measurement device (100) continuously performs a defect measurement task of the wafer (W), and the second wafer defect measurement device (100') completes a defect inspection of the wafer (W), the robot arm (310) can take out the wafer (W) from the second wafer defect measurement device (100') and mount it on the storage load unit (220) under the control of the control module (500) based on the judgment in step S30, and can place the wafer (W) with the notch aligned in the wafer edge area inspection module (400) on the second wafer defect measurement device (100').

[0115] As described above, in the high-speed wafer defect measurement method using a twin stage according to the present invention, defect inspection of wafers can be performed sequentially and simultaneously in the first wafer defect measurement device (100) and / or the second wafer defect measurement device (100'), so that defect inspection of a plurality of wafers can be performed continuously and at high speed.

[0116] In addition, although the above description describes a process in which the main body of the wafer transfer module (300) is moved along the rail (320) to retrieve and place the wafer (W), it is not limited thereto. For example, as shown in FIG. 15, a structure may be provided in which the main body of the wafer transfer module (300) fixed within the system is provided with a single robot arm (310) that can move up and down on the main body and move forward and backward left and right within the stroke region, so that the wafer (W) can be retrieved and placed by the first wafer defect measurement device (100), the second wafer defect measurement device (100'), the wafer load module (200) provided for inspecting and storing the wafer, and the wafer edge area inspection module (400). FIG. 15 is a drawing showing a state in which a robot arm according to another embodiment of the present invention has moved to the second wafer defect measurement device.

[0117] In addition, although the above description describes a process in which the withdrawal and settling of the wafer (W) is performed by a single robot arm, it is not limited thereto. For example, a configuration of a pair of robot arms may be applied so that the wafer transfer in the wafer load module (200) and the wafer edge area inspection module (400) is performed by the first robot arm, and the wafer transfer from the edge area inspection module (400) to the first wafer defect measurement device (100) and / or the second wafer defect measurement device (100') may be performed by the second robot arm. That is, the main body of the wafer transfer module (300) may be fixed within the system, and the first robot arm and the second robot arm may be provided on the main body to be able to independently move up and down on the main body, and to be able to move left, right, forward, and backward within the stroke region.

[0118] Although the invention made by the present inventor has been specifically described according to the above embodiments, the present invention is not limited to the above embodiments and can be modified in various ways without departing from the spirit thereof.

[0119] By using a high-speed wafer defect measurement system equipped with a twin stage according to the present invention and a high-speed wafer defect measurement method using the same, defect inspection for a plurality of wafers can be performed continuously and at high speed.

Claims

1. A high-speed wafer defect measurement system equipped with a twin stage that measures defects in wafers transported by a robot arm. A wafer load module provided for inspection and storage of wafers; A wafer transfer module that transfers wafers from the wafer load module using a robot arm, A wafer edge area inspection module that inspects the edge area of ​​a wafer transported by the above robot arm, A first wafer defect measurement device that performs surface detection and defect depth detection of a first wafer transported by the above robot arm, A second wafer defect measurement device is included that performs surface detection and defect depth detection of a second wafer transported by the robot arm. A high-speed wafer defect measurement system, characterized in that the first wafer defect measurement device and the second wafer defect measurement device are located within the stroke area of ​​the robot arm.

2. In paragraph 1, The first wafer defect measurement device includes a first surface detection module for detecting a surface condition of the first wafer and a first defect depth detection module for detecting a defect depth of the first wafer, A high-speed wafer defect measurement system, characterized in that the second wafer defect measurement device includes a second surface detection module for detecting a surface condition of the second wafer and a second defect depth detection module for detecting a defect depth of the second wafer.

3. In paragraph 2, The first surface detection module and the first defect depth detection module are arranged parallel along the X-axis, A high-speed wafer defect measurement system, characterized in that the second surface detection module and the second defect depth detection module are arranged parallel along the X-axis.

4. In paragraph 3, The first wafer defect measurement device further includes a first gantry as a structure provided on the first body and having the first surface detection module and the first defect depth detection module mounted therein, The second wafer defect measurement device further includes a second gantry as a structure provided on the second body, the second surface detection module and the second defect depth detection module being mounted therein, The first and second bodies are arranged to be in contact with each other on the same plane, A high-speed wafer defect measurement system, characterized in that the first gantry and the second gantry are arranged to be in contact with each other.

5. In paragraph 4, A first linear servo and a first LM guide are mounted on both sides of the first main body, A first main table is mounted on the upper part of the first linear servo and the first LM guide so as to be able to move in the Y-axis. A second linear servo and a second LM guide are mounted on both sides of the second main body. A high-speed wafer defect measurement system characterized in that a second main table is mounted on the upper portion of the second linear servo and the second LM guide so as to be movable in the Y-axis.

6. In paragraph 5, A first line camera lighting unit and a first depth measurement lighting unit are provided between the first linear servo and the first LM guide. A high-speed wafer defect measurement system, characterized in that a second line camera lighting unit and a second depth measurement lighting unit are provided between the second linear servo and the second LM guide.

7. In paragraph 6, The first main body is equipped with a first line lighting unit, and the first line lighting unit includes an LED lamp or a halogen lamp, A high-speed wafer defect measurement system, characterized in that the second main body is equipped with a second line lighting unit, and the second line lighting unit includes an LED lamp or a halogen lamp.

8. In paragraph 1, A high-speed wafer defect measurement system, characterized in that the center line of the first wafer defect measurement device and the center line of the second wafer defect measurement device are located within the stroke area of ​​the robot arm.

9. In paragraph 4, A square-shaped first line camera bracket is coupled to the inside of the upper plate of the first gantry, a first Z-axis drive camera bracket is coupled to a side of the first line camera bracket, the first surface detection module is mounted inside the first line camera bracket, and the first defect depth detection module is mounted on the first Z-axis drive camera bracket. A high-speed wafer defect measurement system, characterized in that a square-shaped second line camera bracket is coupled to the inside of the upper plate of the second gantry, a second Z-axis drive camera bracket is coupled to a side of the second line camera bracket, the second surface detection module is mounted inside the second line camera bracket, and the second defect depth detection module is mounted on the second Z-axis drive camera bracket.

10. In paragraph 1, A high-speed wafer defect measurement system equipped with a twin stage, characterized in that the center line of the inspection load section of the load module and the center line of the storage load section of the load module are located within the stroke area of ​​the robot arm.

11. A method for measuring wafer defects at high speed using twin stages of the first and second stages, (a) A step of taking out a wafer from a FOUP (Front Opening Unified Pod) provided in the inspection load section; (b) a step of placing the wafer extracted in the above step (a) on a wafer edge area inspection module, inspecting the edge area of ​​the wafer for crack defects or damage defects, and aligning notches; (c) a step of placing the wafer with the notch position aligned in the above step (b) on the first wafer defect measurement device of the first stage, and detecting surface defects and measuring the defect depth; (d) a step of placing the wafer with the notch position aligned in the above step (b) on the second wafer defect measurement device of the second stage, and detecting surface defects and measuring the defect depth; (e) A high-speed method for measuring wafer defects, characterized in that it comprises a step of taking out the wafer whose defect has been measured in the step (c) or the step (d) and mounting it on a storage load unit.

12. In paragraph 11, A high-speed wafer defect measurement method, characterized in that the control module determines the progress from step (b) to step (c) or from step (b) to step (d) according to the inspection time in the first wafer defect measurement device and / or the second wafer defect measurement device.

13. In paragraph 12, A high-speed method for measuring wafer defects, characterized in that the removal and placement of the wafer in steps (a) to (e) above are sequentially and continuously performed by a single robot arm.

14. In paragraph 13, A high-speed wafer defect measurement method, characterized in that the wafer surface defect detection and defect depth measurement in the first wafer defect measurement device and the wafer surface defect detection and defect depth measurement in the second wafer defect measurement device are performed simultaneously.

15. In paragraph 13, A high-speed method for measuring wafer defects, characterized in that the single robot arm is provided on the main body of a wafer transfer module fixed within the system, and is provided to be able to move up and down on the main body and to move forward and backward left and right within a stroke area.

16. In paragraph 12, In the above steps (a) and (b), the withdrawal and placement of the wafer are sequentially and continuously performed by the first robot arm, A high-speed method for measuring wafer defects, characterized in that the withdrawal and placement of the wafer in the above steps (c) to (e) are sequentially and continuously performed by a second robot arm.

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