Array substrate, display panel and display apparatus

Abstract

The present disclosure provides an array substrate, a display panel and a display apparatus. The array substrate comprises: a base substrate; a plurality of pixel electrodes, arranged in an array on the base substrate; a plurality of transistors, located between the layer where the plurality of pixel electrodes are located and the base substrate; a first insulating layer, located between the layer where the plurality of transistors are located and the layer where the plurality of pixel electrodes are located, the first insulating layer comprising first via holes overlapping first electrodes of the transistors; and a second insulating layer, located between the first insulating layer and the layer where the first electrodes of the plurality of transistors are located, the second insulating layer comprising second via holes that overlap the first electrodes of the transistors and are communicated with the first via holes. The pixel electrodes are electrically connected to the first electrodes of the transistors by means of the first via holes and the second via holes, and the orthographic projections of the first via holes on the base substrate are away from the orthographic projections of the pixel electrodes on the base substrate with respect to the orthographic projections of the second via holes on the base substrate.

Description

Array substrate, display panel and display device Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to an array substrate, a display panel, and a display device. Background Technology

[0002] Thin-film transistor liquid crystal displays (TFT-LCDs) are characterized by their small size, low power consumption, high image quality, no radiation, and portability. They have experienced rapid development in recent years and have gradually replaced traditional cathode ray tube (CRT) displays, dominating the current flat panel display market. Currently, TFT-LCDs are widely used in products of various sizes, covering almost all major electronic products in today's information society, such as LCD TVs, high-definition digital TVs, computers (desktops and laptops), mobile phones, tablets, navigation systems, in-vehicle displays, projection displays, cameras, digital cameras, electronic watches, calculators, electronic instruments, meters, public displays, and virtual displays.

[0003] Summary of the Invention

[0004] The array substrate, display panel, and display device disclosed herein are specifically designed as follows:

[0005] On one hand, the array substrate provided in the embodiments of this disclosure includes:

[0006] Substrate;

[0007] Multiple pixel electrodes are arranged in an array on the substrate.

[0008] Multiple transistors are located between the layer containing the multiple pixel electrodes and the substrate.

[0009] A first insulating layer is located between the layer containing the first electrodes of the plurality of transistors and the layer containing the plurality of pixel electrodes. The first insulating layer includes a first via that overlaps with the first electrodes of the transistors.

[0010] A second insulating layer is located between the first insulating layer and the layer containing the first electrodes of the plurality of transistors. The second insulating layer includes a second via that overlaps with the first electrodes of the transistors and communicates with the first via. The pixel electrode is electrically connected to the first electrode of the transistor through the first via and the second via. The orthogonal projection of the first via on the substrate is positioned away from the orthogonal projection of the pixel electrode on the substrate relative to the orthogonal projection of the second via on the substrate.

[0011] In some embodiments, in the array substrate provided in the present disclosure, the first insulating layer covers the sidewall of the second via that is covered by the pixel electrode.

[0012] In some embodiments, in the array substrate provided in the present disclosure, the orthographic projection of the first via on the substrate overlaps with the orthographic projection of the sidewall of the second insulating layer on the side away from the pixel electrode on the substrate.

[0013] In some embodiments, in the array substrate provided in the present disclosure, the bottom of the first via includes a first boundary and a second boundary extending in the row direction, and the orthographic projection of the first boundary on the substrate is located on the side of the orthographic projection of the second boundary on the substrate that is close to the orthographic projection of the pixel electrode on the substrate.

[0014] The bottom of the second via includes a third boundary and a fourth boundary extending in the row direction, wherein the orthographic projection of the third boundary on the substrate is located on the side of the orthographic projection of the fourth boundary on the substrate that is close to the orthographic projection of the pixel electrode on the substrate.

[0015] Furthermore, the orthographic projection of the first boundary on the substrate is located between the orthographic projection of the third boundary on the substrate and the orthographic projection of the fourth boundary on the substrate, and the orthographic projection of the fourth boundary on the substrate is located between the orthographic projection of the first boundary on the substrate and the orthographic projection of the second boundary on the substrate.

[0016] In some embodiments, in the array substrate provided in the present disclosure, the first vias corresponding to the pixel electrodes in the same row are connected to form a first trench, and the second vias corresponding to the pixel electrodes in the same row are connected to form a second trench.

[0017] In some embodiments, the array substrate provided in this disclosure further includes a first common electrode located on the side of the layer containing the plurality of pixel electrodes away from the substrate.

[0018] The pixel electrode includes a first sub-pixel electrode and a second sub-pixel electrode located between the layer where the first sub-pixel electrode is located and the layer where the first common electrode is located, and the first sub-pixel electrode and the second sub-pixel electrode are electrically connected.

[0019] The partial orthographic projection of the first sub-pixel electrode on the substrate overlaps with the partial orthographic projection of the second sub-pixel electrode on the substrate;

[0020] The orthographic projection of the first sub-pixel electrode on the substrate and the orthographic projection of the first common electrode on the substrate have a first overlapping area, and the orthographic projection of the second sub-pixel electrode on the substrate and the orthographic projection of the first common electrode on the substrate have a second overlapping area, and the second overlapping area overlaps with the first overlapping area in at most a portion.

[0021] In some embodiments, the array substrate provided in this disclosure further includes a plurality of second common electrodes located between the first insulating layer and the second insulating layer, wherein the orthographic projection of the second common electrodes on the substrate intersects with the orthographic projection of the pixel electrodes on the substrate.

[0022] In some embodiments, in the array substrate provided in the present disclosure, the orthographic projection of the second common electrode on the substrate and the orthographic projection of the first sub-pixel electrode on the substrate have a third overlapping region, and the orthographic projection of the second common electrode on the substrate and the orthographic projection of the second sub-pixel electrode on the substrate have a fourth overlapping region, wherein the third overlapping region and the fourth overlapping region overlap in multiple parts.

[0023] In some embodiments, in the array substrate provided in the present disclosure, the third overlapping region is substantially located within the fourth overlapping region;

[0024] The first common electrode includes a slit; on one side of the slit's extension direction, the first overlapping region and the second overlapping region substantially coincide; on the other side of the slit's extension direction, the first overlapping region is substantially located within the second overlapping region.

[0025] In some embodiments, in the array substrate provided in the present disclosure, the third overlapping region and the fourth overlapping region partially overlap or are offset from each other;

[0026] The first common electrode includes a slit, and the first overlapping region and the second overlapping region are located on opposite sides of the slit's extension direction.

[0027] In some embodiments, in the array substrate provided in the present disclosure, the first common electrode is a single-layer structure, and the width of the slit is 2μm to 3μm.

[0028] In some embodiments, in the array substrate provided in the present disclosure, the first common electrode includes a first sub-common electrode and a second sub-common electrode that contacts and partially overlaps the first sub-common electrode on the side of the first sub-common electrode away from the layer where the pixel electrode is located, and the width of the slit is 0.8 μm to 2 μm.

[0029] In some embodiments, in the array substrate provided in the present disclosure, the first sub-pixel electrode and the second sub-pixel electrode extend to the region where the slit is located;

[0030] In the column direction, the length of the first sub-pixel electrode is greater than half the length of the slit, and the length of the second sub-pixel electrode is greater than the length of the slit.

[0031] In some embodiments, in the array substrate provided in the present disclosure, the orthogonal projection of the second common electrode on the substrate is located between the orthogonal projections of the first via and / or the second via on the substrate in the column direction.

[0032] In some embodiments, the array substrate provided in this disclosure further includes a conductive pattern disposed on the same layer as the second electrode of the transistor, wherein the first common electrode is electrically connected to the second common electrode through the conductive pattern.

[0033] In some embodiments, in the array substrate provided in the present disclosure, the first sub-pixel electrode includes an integrally disposed pixel portion and an overlapping portion, wherein the overlapping portion is located inside the second via, the pixel portion is located outside the second via, and the width of the overlapping portion is smaller than the width of the pixel portion.

[0034] In some embodiments, in the array substrate provided in the present disclosure, the first sub-pixel electrode further includes a transition portion connecting the pixel portion and the overlapping portion. In the direction from the pixel portion to the overlapping portion, the width of the transition portion is reduced at least once. The width of the transition portion is greater than the width of the overlapping portion and less than the width of the pixel portion.

[0035] In some embodiments, in the array substrate provided in the present disclosure, the transition portion is located on the plane of the first insulating layer, and / or the transition portion is located on the first insulating layer at the sidewall of the second via.

[0036] In some embodiments, the array substrate provided in this disclosure further includes a third insulating layer, which fills the first via and the second via;

[0037] The orthographic projection of the second sub-pixel electrode on the substrate overlaps with the orthographic projection of the first sub-pixel electrode in the previous row on the substrate, and the orthographic projection of the second sub-pixel electrode on the substrate overlaps with the orthographic projection of the second via in the previous row on the substrate.

[0038] In some embodiments, the array substrate provided in this disclosure further includes a fourth insulating layer located between the layer containing the first sub-pixel electrode and the layer containing the second sub-pixel electrode;

[0039] The first sub-pixel electrode is electrically connected to the second sub-pixel electrode through a third via penetrating the fourth insulating layer, and the orthographic projection of the third via on the substrate is located within the orthographic projection of the second via on the substrate.

[0040] In some embodiments, the array substrate provided in the present disclosure further includes a first common electrode located on the side of the layer where the plurality of pixel electrodes are located away from the substrate, and the first common electrode includes a slit;

[0041] Within the slit region: the length of the first sub-pixel electrode in the column direction is greater than half the length of the slit in the column direction and less than the length of the second sub-pixel electrode in the column direction, and the length of the second sub-pixel electrode in the column direction is less than the length of the slit in the column direction.

[0042] In some embodiments, the array substrate provided in this disclosure further includes data lines, a first light-shielding pattern, and a second light-shielding pattern; wherein,

[0043] The first light-shielding pattern is reused as the bottom gate of the transistor, and the orthographic projection of the first light-shielding pattern on the substrate covers the channel region of the active layer of the transistor.

[0044] The second electrode of the transistor is multiplexed with the data line. A fifth insulating layer is provided between the layer where the data line is located and the active layer of the transistor. The data line is electrically connected to the active layer of the transistor through a fourth via penetrating the fifth insulating layer.

[0045] The second light-shielding pattern is located on the side of the layer containing the first light-shielding pattern that is close to the substrate, and the orthographic projection of the second light-shielding pattern on the substrate covers the orthographic projection of the fourth via on the substrate.

[0046] In some embodiments, the array substrate provided in the present disclosure further includes a transition electrode and a color resist layer, wherein the transition electrode is located between the active layer of the transistor and the second insulating layer, and the transition electrode is multiplexed with the first electrode of the transistor, and the color resist layer is located between the layer containing the transition electrode and the second insulating layer.

[0047] On the other hand, this disclosure provides a display panel including the array substrate provided in this disclosure and a counter substrate disposed opposite to the array substrate.

[0048] On the other hand, this disclosure provides a display device, including the display panel provided in this disclosure and a backlight module located on the light-incident side of the display panel. Attached Figure Description

[0049] Figure 1A is a schematic diagram of a structure of three sub-pixels in an array substrate provided in an embodiment of this disclosure;

[0050] Figure 1B is a schematic diagram of the structure of the layer where the data line is located in Figure 1A;

[0051] Figure 1C is a schematic diagram of the structure of the layer where the transfer electrode is located in Figure 1A;

[0052] Figure 1D is a schematic diagram of the structure of the layer where the second via is located in Figure 1A;

[0053] Figure 1E is a schematic diagram of the structure of the layer where the second common electrode is located in Figure 1A;

[0054] Figure 1F is a schematic diagram of the structure of the layer where the first via is located in Figure 1A;

[0055] Figure 1G is a schematic diagram of the structure of the layer where the first sub-pixel electrode is located in Figure 1A;

[0056] Figure 1H is a schematic diagram of the structure of the layer where the second sub-pixel electrode is located in Figure 1A;

[0057] Figure 1I is a schematic diagram of the structure of the layer where the first common electrode is located in Figure 1A;

[0058] Figure 2 is a schematic diagram of the cross-sectional structure of the array substrate shown in Figure 1A;

[0059] Figure 3A is a schematic diagram of another structure of three sub-pixels in an array substrate provided in an embodiment of this disclosure;

[0060] Figure 3B is a schematic diagram of the structure of the layer where the data line is located in Figure 3A;

[0061] Figure 3C is a schematic diagram of the structure of the layer where the transfer electrode is located in Figure 3A;

[0062] Figure 3D is a schematic diagram of the structure of the layer where the second via is located in Figure 3A;

[0063] Figure 3E is a schematic diagram of the structure of the layer where the second common electrode is located in Figure 3A;

[0064] Figure 3F is a schematic diagram of the structure of the layer where the first and third vias in Figure 3A are located;

[0065] Figure 3G is a schematic diagram of the structure of the layer where the first sub-pixel electrode is located in Figure 3A;

[0066] Figure 3H is a schematic diagram of the structure of the layer where the second sub-pixel electrode is located in Figure 3A;

[0067] Figure 3I is a schematic diagram of the structure of the layer where the first common electrode is located in Figure 3A;

[0068] Figure 4 is a schematic diagram of the cross-sectional structure of the array substrate shown in Figure 3A;

[0069] Figure 5 is a schematic diagram of a structure of approximately three sub-pixels in an array substrate provided in an embodiment of this disclosure;

[0070] Figure 6 is a schematic diagram of another structure of three sub-pixels in the array substrate provided in the embodiment of this disclosure;

[0071] Figure 7 is a schematic diagram of another cross-sectional structure of the array substrate shown in Figure 1A;

[0072] Figure 8 is a schematic diagram of the first sub-pixel electrode breakage provided in an embodiment of this disclosure;

[0073] Figure 9 is a schematic diagram of another structure of approximately three sub-pixels in an array substrate provided in an embodiment of this disclosure;

[0074] Figure 10 is a schematic diagram of the cross-sectional structure of the array substrate shown in Figure 9;

[0075] Figure 11A is a schematic diagram of a structure of a first sub-pixel electrode provided in an embodiment of this disclosure;

[0076] Figure 11B is a schematic diagram of another structure of the first sub-pixel electrode provided in an embodiment of this disclosure;

[0077] Figure 11C is a schematic diagram of another structure of the first sub-pixel electrode provided in an embodiment of this disclosure;

[0078] Figure 12 is a schematic diagram of the connection between the first common electrode and the second common electrode provided in an embodiment of this disclosure;

[0079] Figure 13 is a schematic diagram of another structure of three sub-pixels in an array substrate provided in an embodiment of this disclosure;

[0080] Figure 14 is a schematic diagram of the cross-sectional structure of the array substrate shown in Figure 13;

[0081] Figure 15 is a flowchart of a method for fabricating an array substrate according to an embodiment of this disclosure;

[0082] Figure 16 is a schematic diagram of the structure of the display panel provided in an embodiment of this disclosure;

[0083] Figure 17 is a schematic diagram of the structure of the display device provided in the embodiment of this disclosure. Detailed Implementation

[0084] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. It should be noted that, for clarity, the thickness of layers, films, panels, regions, etc., is enlarged in the drawings. Exemplary embodiments are described in this disclosure with reference to cross-sectional views as schematic diagrams of idealized embodiments. Thus, deviations from the shape of the figures will be expected as a result of, for example, manufacturing techniques and / or tolerances. Therefore, the embodiments described in this disclosure should not be construed as limited to the specific shape of the regions shown in this disclosure, but rather include deviations in shape caused, for example, by manufacturing processes. For example, a region illustrated or described as flat may typically have rough and / or non-linear characteristics; a sharp corner illustrated may be rounded, etc. Therefore, the regions shown in the figures are schematic in nature, and their dimensions and shapes are not intended to illustrate the precise shape of the regions or reflect true proportions; their purpose is merely to illustrate the content of this disclosure. And throughout, the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions. To keep the following description of the embodiments of this disclosure clear and concise, detailed descriptions of known functions and known components are omitted.

[0085] Unless otherwise defined, the technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure and the claims do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that the element or object preceding the word covers the element or object listed following the word and its equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as “inner,” “outer,” “upper,” and “lower” are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described object changes.

[0086] In the following description, when an element or layer is referred to as "on" or "connected to" another element or layer, the element or layer may be directly on or directly connected to the other element or layer, or there may be intermediate elements or intermediate layers. When an element or layer is referred to as "located on one side of" another element or layer, the element or layer may be directly on or directly connected to the other element or layer, or there may be intermediate elements or intermediate layers. However, when an element or layer is referred to as "directly on" or "directly connected to" another element or layer, no intermediate elements or intermediate layers are present. The term "and / or" includes any and all combinations of one or more of the related listed items.

[0087] In some embodiments, the screen resolution (PPI) of TFT-LCD products such as VR and AR is constantly increasing. Future VR products will need to be upgraded to 1500 PPI, or even 2000 PPI or higher, to meet the visual experience requirements of the human eye. However, the increase in PPI corresponds to the continuous reduction in single pixel size. For example, the sub-pixel size of a 2.5-inch 1500 PPI product is approximately 5μm*15μm, while the sub-pixel size of a 2.5-inch 2000 PPI product is only 4μm*12μm. In VR products with LTPO and LTPS architectures, the pixel storage capacitors are designed with a reference common electrode. This means that the pixel electrode within the sub-pixel and the single-layer common electrode (VCOM signal) are vertically overlapped and laterally coupled in physical space to form a storage capacitor, maintaining the sub-pixel charge for one frame of display. As mentioned earlier, the realization of ultra-high PPI is based on the continuous reduction of sub-pixel size. This means that the area of ​​vertical overlap and lateral coupling between the pixel electrode and the common electrode in the physical space of the sub-pixel is also continuously reduced. The sub-pixel storage capacitance is continuously reduced, which causes the pixel charge to be unable to be maintained within a frame, resulting in problems such as screen flicker and crosstalk.

[0088] To address the aforementioned technical problems, this disclosure provides an array substrate. Figure 1A is a schematic diagram of one structure of three sub-pixels in the array substrate provided in this disclosure; Figures 1B to 1I are schematic diagrams of the structure of each single film layer in Figure 1; Figure 2 is a cross-sectional schematic diagram of the array substrate shown in Figure 1A; Figure 3A is another schematic diagram of one structure of three sub-pixels in the array substrate provided in this disclosure; Figures 3B to 3I are schematic diagrams of the structure of each single film layer in Figure 1; and Figure 4 is a cross-sectional schematic diagram of the array substrate shown in Figure 3A. For clarity, the transistor film layer below the transition electrode 105 is omitted in Figures 1A and 3A. As can be seen from Figures 1A to 1I, Figure 2, Figures 3A to 3I, and Figure 4, the array substrate provided in this disclosure may include:

[0089] Optionally, the substrate 101 includes a display area AA and a non-display area BB located on at least one side of the display area AA. In some embodiments, the display area AA includes an array of red sub-pixel areas, green sub-pixel areas, blue sub-pixel areas, etc. The substrate 101 is a substrate that allows visible light to pass through, such as glass, quartz, plastic, etc.

[0090] The first common electrode 102 is located in the display area AA of the substrate 101. In some embodiments, the first common electrode 102 can be a slit electrode, and the material of the first common electrode 102 can include at least one transparent conductive material such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc aluminum oxide (AZO), and zinc gallium oxide (GZO).

[0091] Multiple pixel electrodes 103 are located between the layer containing the first common electrode 102 and the substrate 101. The multiple pixel electrodes 103 are arranged in an array within the display area AA. Each pixel electrode 103 includes a first sub-pixel electrode 1031 and a second sub-pixel electrode 1032 located between the layer containing the first sub-pixel electrode 1031 and the layer containing the first common electrode 102, and the first sub-pixel electrode 1031 and the second sub-pixel electrode 1032 are electrically connected. In some embodiments, the materials of the first sub-pixel electrode 1031 and the second sub-pixel electrode 1032 may include at least one transparent conductive material such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc aluminum oxide (AZO), or zinc gallium oxide (GZO).

[0092] Optionally, in order to ensure that the overall area of ​​the pixel electrode 103 is large, thereby facilitating the formation of a large storage capacitance with the common electrode, this disclosure may configure the partial orthographic projection of the first sub-pixel electrode 1031 on the substrate 101 to overlap with the partial orthographic projection of the second sub-pixel electrode 1032 on the substrate 101. In some embodiments, the orthographic projection of the first sub-pixel electrode 1031 on the substrate 101 and the orthographic projection of the first common electrode 102 on the substrate 101 have a first overlapping region OL1, and the orthographic projection of the second sub-pixel electrode 1032 on the substrate 101 and the orthographic projection of the first common electrode 102 on the substrate 101 have a second overlapping region OL2, and the second overlapping region OL2 and the first overlapping region OL1 overlap in some extent; for example, in FIG1A, on one side (left side) of the slit S extension direction, the first overlapping region OL1 and the second overlapping region OL2 substantially coincide; on the other side (right side) of the slit S extension direction, the first overlapping region OL1 is substantially located within the second overlapping region OL2; as in FIG3A, the first overlapping region OL1 and the second overlapping region OL2 do not overlap each other, and optionally, the first overlapping region OL1 and the second overlapping region OL2 are located on the left and right sides of the slit S extension direction, respectively. Thus, the first common electrode 102 and the first sub-pixel electrode 1031 can form a first storage capacitor in the first overlapping region OL1 outside the second overlapping region OL2, and the first common electrode 102 and the second sub-pixel electrode 1032 can form a second storage capacitor in the second overlapping region OL2.

[0093] It should be noted that in the embodiments provided in this disclosure, due to limitations of process conditions or the influence of other factors such as measurement, "approximately coincident" may coincide exactly, or there may be some deviation (e.g., a deviation of ±1μm). Therefore, as long as the relationship of "approximately coincident" between related features satisfies the allowable error, it falls within the protection scope of this disclosure.

[0094] In some embodiments, the first sub-pixel electrode 1031 and the second sub-pixel electrode 1032 can be block electrodes extending to the region where the slit S is located. In the embodiment shown in FIG1A, when the first sub-pixel electrode 1031 is fabricated, the second via V2 is not filled, and the first sub-pixel electrode 1031 continues to extend in the direction of the arrow in the column direction Y, possibly reaching into the second via V2 of the previous row pixel, and short-circuiting with the first sub-pixel electrode 1031 of the previous row; however, when the second sub-pixel electrode 1032 is fabricated, the second via V2 is filled by the third insulating layer 108, so the second sub-pixel electrode 1032 can continue to extend in the direction of the arrow in the column direction Y until its orthographic projection overlaps with the orthographic projection of the first sub-pixel electrode 1031 of the previous row and the orthographic projection of the second via V2 of the previous row. In the embodiment shown in Figure 3A, when the first sub-pixel electrode 1031 is fabricated, the second vias V2 are not filled. The first sub-pixel electrode 1031 continues to extend in the direction of the arrow in the column direction Y, possibly reaching the second via V2 of the previous row of pixels, and short-circuiting with the first sub-pixel electrode 1031 of the previous row. When the second sub-pixel electrode 1032 is fabricated, the sidewall of the second via V2 is covered by the fourth insulating layer 109, but not filled. Therefore, if the second sub-pixel electrode 1032 continues to extend in the direction of the arrow in the column direction Y until its orthographic projection overlaps with the orthographic projection of the second via V2 of the previous row, the second via V2 will be too deep, which will lead to poor exposure and ultimately cause the second sub-pixel electrodes 1032 of the two adjacent rows to short-circuit. Based on this, in order to prevent short circuits between adjacent rows of pixel electrodes 103 and to take into account the large area of ​​pixel electrodes 103, this disclosure can be configured in the column direction Y, wherein the length of the first sub-pixel electrode 1301 is greater than half (e.g., 3 / 4) of the length of the slit S, and the length of the second sub-pixel electrode 1032 is greater than the length of the slit S. Specifically, within the slit S region of the embodiment shown in FIG1A: the length of the first sub-pixel electrode 1301 in the column direction Y is greater than half (e.g., 3 / 4) of the length of the slit S in the column direction Y, and less than the length of the second sub-pixel electrode 1032 in the column direction Y, and the length of the second sub-pixel electrode 1032 in the column direction Y is equal to the length of the slit S; within the slit S region of the embodiment shown in FIG3A: the length of the first sub-pixel electrode 1301 in the column direction Y is greater than half (e.g., 3 / 4) of the length of the slit S in the column direction Y, and less than the length of the second sub-pixel electrode 1032 in the column direction Y, and the length of the second sub-pixel electrode 1032 in the column direction Y is less than the length of the slit S in the column direction Y, for example, the length of the second sub-pixel electrode 1032 in the column direction Y is equal to 4 / 5 of the length of the slit S in the column direction Y.

[0095] Multiple second common electrodes 104 are located between the layer containing the first sub-pixel electrode 1031 and the substrate 101. The orthographic projection of the second common electrode 104 on the substrate 101 intersects with the orthographic projection of the adjacent pixel electrode 103 on the substrate 101. In other words, the orthographic projection of the second common electrode 104 on the substrate 101 overlaps with the orthographic projection of the adjacent pixel electrode 103 on the substrate 101, and the extension direction of the second common electrode 104 intersects with the extension direction of the pixel electrode 103. In some embodiments, the orthographic projection of the second common electrode 104 on the substrate 101 and the orthographic projection of the first sub-pixel electrode 1031 on the substrate 101 have a third overlapping region OL3, and the orthographic projection of the second common electrode 104 on the substrate 101 and the orthographic projection of the second sub-pixel electrode 1032 on the substrate 101 have a fourth overlapping region OL4. The third overlapping region OL3 and the fourth overlapping region OL4 may overlap at most partially. As shown in FIG1A, the third overlapping region OL3 may be substantially located within the fourth overlapping region OL4, or, as shown in FIG3A, the third overlapping region OL3 and the fourth overlapping region OL4 may partially overlap. Of course, in some embodiments, the third overlapping region OL3 and the fourth overlapping region OL4 may also be staggered. This causes the second common electrode 104 and the first sub-pixel electrode 1031 to form a third storage capacitor in the third overlapping region OL3, and the second common electrode 104 and the second sub-pixel electrode 1032 to form a fourth storage capacitor in the fourth overlapping region OL4 outside the third overlapping region OL3. In some embodiments, the material of the second common electrode 104 may include at least one transparent conductive material such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc aluminum oxide (AZO), or zinc gallium oxide (GZO).

[0096] In the array substrate provided in the embodiments of this disclosure, by setting a portion of the first sub-pixel electrode 1031 to overlap with a portion of the second sub-pixel electrode 1032, the first sub-pixel electrode 1031 and the first common electrode 102 form a first storage capacitor, and the second sub-pixel electrode 1032 and the first common electrode 102 form a second storage capacitor. Simultaneously, this disclosure also provides a second common electrode 104, which forms a third storage capacitor with the first sub-pixel electrode 1031 and a fourth storage capacitor with the second sub-pixel electrode 1032. Therefore, the storage capacitor between the pixel electrode 103 and the common electrode (including the first common electrode 102 and the second common electrode 104) in this disclosure includes the aforementioned first, second, third, and fourth storage capacitors. This ensures that the overall storage capacitor in a single sub-pixel is relatively large, thereby maintaining the pixel charge within a frame and effectively improving problems such as screen flicker and crosstalk.

[0097] In some embodiments, in the array substrate provided in the present disclosure, as shown in FIG1I and FIG3I, the first common electrode 102 can be a single-layer structure. Due to the limitation of the exposure process, the width of the slit S is at least 2μm to 3μm, such as 2μm, 2.1μm, 2.2μm, 2.3μm, 2.4μm, 2.5μm, 2.6μm, 2.7μm, 2.8μm, 2.9μm, 3μm, etc.

[0098] To further reduce the slit width and increase the area of ​​the first common electrode 102, thereby increasing the storage capacitance of the first common electrode 102 and the pixel electrode 103, this disclosure addresses the limitation of slit-limited exposure processes in miniaturizing the electrode by employing a first normal exposure followed by a second shift exposure. The process involves first coating a transparent conductive film layer, then coating photoresist, and then performing a first exposure, development, and etching using a photomask with a single-layer structure of the first common electrode 102 to form the first sub-common electrode 1021. Next, another transparent conductive film layer and photoresist are coated, and a second exposure, development, and etching are performed using a photomask with a single-layer structure of the first common electrode 102 offset relative to the first sub-common electrode 1021 by a specified distance (e.g., greater than or equal to 0.5 μm and less than 3 μm) to form the second sub-common electrode 1022. Ultimately, the slit S of the first common electrode 102, composed of the first sub-common electrode 1021 and the second sub-common electrode 1022, is smaller.

[0099] Based on this, Figure 5 shows a schematic diagram of approximately three sub-pixels in an array substrate provided by an embodiment of the present disclosure, and Figure 6 shows another schematic diagram of three sub-pixels in an array substrate provided by an embodiment of the present disclosure. As clear examples, Figures 5 and 6 only show the first sub-pixel electrode 1031, the second sub-pixel electrode 1032, the first sub-common electrode 1021, the second sub-common electrode 1022, and the second trench PLN1. The arrangement of the omitted transition electrode 105, the first trench SPVX, etc. can be found in the embodiments shown in Figures 1A and 3A, and will not be described in detail here. As shown in Figures 5 and 6, the first common electrode 102 of this disclosure may include a first sub-common electrode 1021 and a second sub-common electrode 1022 that contacts and partially overlaps the first sub-common electrode 1021 on the side of the first sub-common electrode 1021 away from the layer where the pixel electrode 103 is located. Optionally, the structure of the first sub-common electrode 1021 and the second sub-common electrode 1022 may be the same as the structure of the single-layer first common electrode 104. In other words, the slit width of the first sub-common electrode 1021 and the slit width of the second sub-common electrode 1022 may be 2μm to 3μm. However, because the first sub-common electrode 1021 and the second sub-common electrode 1022 partially overlap, the slit S width of the first common electrode 102 becomes smaller. In some embodiments, the slit S width of the first common electrode 1021 is 0.8μm to 2μm, for example, 0.8μm, 0.9μm, 1μm, 1.1μm, 1.2μm, 1.3μm, 1.4μm, 1.5μm, 1.6μm, 1.7μm, 1.8μm, 1.9μm, 2μm, etc.

[0100] In some embodiments, the array substrate provided in this disclosure, as shown in Figures 1A-1I, 2, 3A-3I, and 4, may further include a plurality of transistors (e.g., oxide transistors TO) located between the layer containing the plurality of second common electrodes 104 and the substrate 101, a first insulating layer 106 located between the layer containing the plurality of second common electrodes 104 and the layer containing the plurality of pixel electrodes 103, and a second insulating layer 107 located between the layer containing the plurality of second common electrodes 104 and the layer containing the plurality of transistors (e.g., oxide transistors TO). The first insulating layer 106 includes a first via V1 that overlaps with the transition electrode 105, and the second insulating layer 107 includes a second via V2 that overlaps with the transistor (e.g., oxide transistors TO) and communicates with the first via V1. The through-hole first via V1 and the second via V2 form a via structure, and the first sub-pixel electrode 1031 is electrically connected to the first electrode (e.g., the transition electrode 105) of the transistor (e.g., oxide transistors TO) through this via structure.

[0101] It should be noted that the first electrode of a transistor (e.g., an oxide transistor TO) can refer to the conductive portion of the active layer or to the transfer electrode 105 electrically connected to the active layer. This disclosure illustrates the use of the transfer electrode 105 as the first electrode of a transistor (e.g., an oxide transistor TO). Optionally, the first electrode of a transistor (e.g., an oxide transistor TO) can be either the source or the drain; this disclosure does not limit this.

[0102] In some embodiments, the material of the adapter electrode 105 may include at least one transparent conductive material such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc aluminum oxide (AZO), zinc gallium oxide (GZO), and / or at least one metallic material such as gold (Au), silver (Ag), copper (Cu), molybdenum (Mo), aluminum (Al), titanium (Ti), chromium (Cr), nickel (Ni); the material of the first insulating layer 106 may be an inorganic insulating material such as silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiON), aluminum oxide (AlOx), hafnium oxide (HfOx), tantalum oxide (TaOx), and may be a single layer or a multilayer; the material of the second insulating layer 107 may be an organic insulating material such as polyacrylic acid resin, polyepoxy acrylic resin, photosensitive polyimide resin, polyester acrylate, polyurethane acrylate resin, phenolic epoxy acrylic resin, and may be a single layer or a multilayer, and is not limited herein.

[0103] In some embodiments, in the array substrate provided in this disclosure, as shown in Figures 1A, 1E, and 1F, the first via V1 corresponding to the first sub-pixel electrode 1031 in the same row can be connected to form a first trench SPVX, and the second via V2 corresponding to the first sub-pixel electrode 1031 in the same row can be connected to form a second trench PLN1. The orthogonal projection of the first trench SPVX on the substrate 101 can be located within the orthogonal projection of the second trench PLN1 on the substrate 101. Higher resolution and smaller sub-pixel size increase the difficulty of the drilling process. By connecting the vias in the same row to form a trench, the process difficulty is reduced, while ensuring normal conduction between the first sub-pixel electrode 1031 and the transition electrode 105.

[0104] Figures 7 and 8 are schematic cross-sectional views of the array substrate in a single sub-pixel according to embodiments of this disclosure. As shown in Figure 7, when the profile angle of the second via V2 in the second insulating layer 107 is large, the second common electrode 104 may fall on the sidewall of the second via V2. However, the first via V1 and the second via V2 are a nested structure. When there is a deviation in the process alignment, the first via V1 and the second via V2 may be misaligned. For example, the first via V1 may be misaligned to the left side of the second via V2. When etching the first insulating layer 106, the sidewall of the second via V2 may be drilled, resulting in an undercut phenomenon on the left side of the second via V2. At this time, the first sub-pixel electrode 1031 may break on the left side of the second via V2, as shown in Figure 8.

[0105] Figure 9 is a schematic diagram of another structure of approximately three sub-pixels in the array substrate provided in this embodiment of the present disclosure, and Figure 10 is a schematic diagram of the cross-sectional structure of the array substrate shown in Figure 9. For clarity, Figure 9 only shows the first sub-pixel electrode 1031, the second common electrode 105, the first trench SPVX, and the second trench PLN1. The arrangement of the omitted second sub-pixel electrode 1032, the first common electrode 102, the transition electrode 105, etc. can be found in the embodiments shown in Figures 1A and 3A, and will not be described in detail here. As shown in Figures 9 and 10, this disclosure allows for the misalignment of the first via V1 and the second via V2, such that the orthographic projection of the first via V1 on the substrate 101 is offset by a certain distance relative to the orthographic projection of the second via V2 on the substrate 101, towards the side away from the first sub-pixel electrode 1031 (this distance can be equal to the alignment deviation between the first via V1 and the second via V2, for example, 0.5μm to 2μm). This ensures that the distance between the upper side of the first via V1 and the second via V2 in Figure 9 (i.e., the distance between the first boundary BL1 and the third boundary BL3) satisfies the process deviation of the alignment of the first via V1 with the second via V2. This allows the first insulating layer 106 to cover the sidewall of the second via V2 covered by the first sub-pixel electrode 1031 (as shown in Figure 10, the left sidewall of the second via V2), ensuring that no poor drilling of the sidewall of the second via V2 occurs when etching the first insulating layer 106, and avoiding the situation where the first sub-pixel electrode 1031 breaks at the sidewall drilling point.

[0106] Based on this, as shown in Figure 9, the bottom of the first via V1 (corresponding to the bottom of the first trench SPVX) in this disclosure includes a first boundary BL1 and a second boundary BL2 extending along the row direction X. The orthographic projection of the first boundary BL1 on the substrate 101 is located on the side of the orthographic projection of the second boundary BL2 on the substrate 101 that is close to the orthographic projection of the pixel electrode 103 on the substrate 101. The bottom of the second via V2 (corresponding to the bottom of the second trench PLN1) includes a third boundary BL3 extending along the row direction X. The orthographic projection of the fourth boundary BL4 and the third boundary BL3 on the substrate 101 is located on the side of the orthographic projection of the fourth boundary BL4 on the substrate 101 that is close to the orthographic projection of the pixel electrode 103 on the substrate 101. To prevent the first sub-pixel electrode 1031 from breaking due to drilling on the sidewall of the second via V2, the orthographic projection of the first boundary BL1 on the substrate 101 can be located between the orthographic projections of the third boundary BL3 and the fourth boundary BL4 on the substrate 101, and the orthographic projection of the fourth boundary BL4 on the substrate 101 can be located between the orthographic projections of the first boundary BL1 and the second boundary BL2 on the substrate 101. In some embodiments, the distance between the first boundary BL1 and the third boundary BL3 is equal to the alignment deviation between the first via V1 and the second via V2.

[0107] It should be noted that, as shown in Figures 1A, 2, 3A, and 4, when the profile angle of the second via PLN1 is small, the second common electrode 104 is located outside the second via V2. That is, the second common electrode 104 can be located only on the plane of the second insulating layer 107 and will not extend to the sidewall of the second via V2. Furthermore, when there is no alignment deviation or the alignment deviation is negligible, the etching process of the first insulating layer 106 will not drill into the sidewall of the second via V2, or the etching process of the first insulating layer 106 will drill into the sidewall near the bottom of the second via V2, but this will not affect the electrical connection between the first sub-pixel electrode 1031 and the adapter electrode 105. In this case, the bottom of the first via V1 can be located inside the bottom of the second via V2, without the need for misalignment design.

[0108] In some embodiments, in the array substrate provided in the present disclosure, as shown in FIG1A, FIG3A and FIG9, to avoid the second common electrode 104 being short-circuited with the transition electrode 105 in the second via V2, the present disclosure may configure the orthogonal projection of the second common electrode 104 on the substrate 101 to be located between the orthogonal projections of the bottom of the adjacent first via V1 and / or the bottom of the second via V2 on the substrate 101 in the column direction Y. In some embodiments, the second common electrode 104 may only cover the plane of the second insulating layer 107, or it may simultaneously cover the plane of the second insulating layer 107 and the sidewall of the second via V2.

[0109] In some embodiments, since the second via V2 is relatively deep, approximately 3μm to 4μm, the first sub-pixel electrode 1031 is subject to exposure limits within the deeper second via V2 and is prone to short-circuiting with adjacent first sub-pixel electrodes 1031. Therefore, to improve exposure yield and avoid short-circuiting of adjacent first sub-pixel electrodes 1031, the width of the first sub-pixel electrode 1031 within the second via V2 can be reduced. Specifically, as shown in Figures 11A, 11B, and 11C, the first sub-pixel electrode 1031 includes an integrally formed pixel portion P and an overlapping portion L, wherein the overlapping portion L is located within the second via V2, the pixel portion P is located outside the second via V2, and the width of the overlapping portion L is smaller than the width of the pixel portion P. Optionally, as shown in Figures 11A and 11B, the first sub-pixel electrode 1031 may further include a transition portion T connecting the pixel portion P and the overlapping portion L. In the direction from the pixel portion P to the overlapping portion L, the width of the transition portion T decreases at least once; for example, the width of the transition portion T may be linearly smaller or decrease in a gradient. In some embodiments, the transition portion T may be located on the plane of the first insulating layer 106, or the transition portion T may be located simultaneously on the plane of the first insulating layer 106 and on the first insulating layer 106 at the sidewall of the second via V2, or the transition portion T may be located on the first insulating layer 106 at the sidewall of the second via V2. It should be understood that in some embodiments, the transition portion T may not be provided; in this case, the pixel portion P and the overlapping portion L are in direct contact, as shown in Figure 11C.

[0110] In some embodiments, in the array substrate provided in this disclosure, as shown in Figures 2 and 10, the first sub-pixel electrode 1031 and the second sub-pixel electrode 1032 can be directly contacted and electrically connected, and the first via V1 and the second via V2 can be filled by the third insulating layer 108. It should be understood that when the first via V1 in the same row is connected to form a first trench SPVX, the third insulating layer 108 can fill the first trench SPVX and the second trench PLN1. Optionally, the material of the third insulating layer 108 can be organic insulating materials such as polyacrylic resin, polyepoxyacrylic resin, photosensitive polyimide resin, polyester acrylate, polyurethane acrylate resin, and phenolic epoxy acrylic resin, and is not limited thereto.

[0111] In some embodiments, the array substrate provided in this disclosure, as shown in Figures 3A to 3I and Figure 4, may further include a fourth insulating layer 109 located between the layer containing the first sub-pixel electrode 1031 and the layer containing the second sub-pixel electrode 1032. The first sub-pixel electrode 1031 is electrically connected to the second sub-pixel electrode 1032 through a third via V3 penetrating the fourth insulating layer 109. The orthographic projection of the third via V3 on the substrate 101 lies within the orthographic projection of the second via V2 on the substrate 101. In some embodiments, the fourth insulating layer 109 may share a mask with the first insulating layer 106. The fourth insulating layer 109 may also prevent short circuits between the first sub-pixel electrode 1031, the second sub-pixel electrode 1032, and the adjacent first sub-pixel electrodes 1031 and second sub-pixel electrodes 1032 on the left and right sides. Optionally, the material of the fourth insulating layer 109 can be an inorganic insulating material such as silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiON), aluminum oxide (AlOx), hafnium oxide (HfOx), tantalum oxide (TaOx), and can be a single layer or a multilayer.

[0112] Figure 13 shows another structural schematic diagram of three sub-pixels in the array substrate provided in the embodiment of this disclosure, and Figure 14 is a cross-sectional structural schematic diagram of the array substrate shown in Figure 13; and for clarity, Figure 13 only shows the first sub-pixel electrode 1031, the second sub-pixel electrode 1032, the second light-shielding pattern LS2 and the second trench PLN1. The arrangement of the omitted transition electrode 105, the first common electrode 102, the second common electrode 104, the first trench SPVX, etc. can be found in the embodiments shown in Figures 1A and 3A, and will not be described in detail here.

[0113] Referring to Figures 13 and 14, the orthographic projection of the second sub-pixel electrode 1032 on the substrate 101 overlaps with the orthographic projection of the first sub-pixel electrode 1031 in the previous row on the substrate 101, and the orthographic projection of the second sub-pixel electrode 1032 on the substrate 101 overlaps with the orthographic projection of the second via V2 in the previous row on the substrate 101. Since the second via V2 is filled by the third insulating layer 108, the second sub-pixel electrode 1032 and the first sub-pixel electrode 1031 in the previous row are insulated from each other by the third insulating layer 108 and will not be connected. By overlapping the second sub-pixel electrode 1032 with the first sub-pixel electrode 1031 in the previous row, the overall area of ​​the pixel electrode 103 can be increased, which is beneficial for forming a larger storage capacitance between the pixel electrode 103 and the common electrode (including the first common electrode 102 and / or the second common electrode 103).

[0114] Referring again to Figures 13 and 14, the array substrate provided in this embodiment may further include a data line DL, a first light-shielding pattern LS1, and a second light-shielding pattern LS2. The second electrode S of the transistor (e.g., an oxide transistor TO) is multiplexed with the data line DL. A fifth insulating layer is provided between the layer containing the data line DL and the active layer AC of the transistor (e.g., an oxide transistor TO). Optionally, the fifth insulating layer has a double-layer structure including a first sub-insulating layer 110 and a second sub-insulating layer 111. The data line DL is electrically connected to the active layer AC of the transistor (e.g., an oxide transistor TO) through a fourth via V4 penetrating the first sub-insulating layer 110 and the second sub-insulating layer 111. The second light-shielding pattern LS2 is located on the layer containing the first light-shielding pattern LS1 near the substrate 101. On one side, the orthographic projection of the second light-shielding pattern LS2 on the substrate 101 covers the orthographic projection of the fourth via V4 on the substrate 101; the first electrode D of the transistor (e.g., oxide transistor TO) (which can be reused with the transition electrode 105) is electrically connected to the active layer AC of the transistor (e.g., oxide transistor TO) through the fifth via V5 passing through the first sub-insulating layer 110, the second sub-insulating layer 111, and the seventh insulating layer 112; the first light-shielding pattern LS1 can be reused as the bottom gate LG of the transistor (e.g., oxide transistor TO), and the transistor (e.g., oxide transistor TO) may also include a top gate UG. Optionally, the orthographic projection of the first light-shielding pattern LS1 on the substrate 101 covers the channel region of the active layer AC of the transistor (e.g., oxide transistor TO) and the fifth via V5. As can be seen from FIG13, the fourth via V4 is located on the data line DL between the pixel electrodes 103 and cannot be blocked by the black matrix (BM). By blocking the fourth via V4 with the second light-shielding pattern LS2, light leakage at the fourth via V4 can be avoided. Meanwhile, by setting the first light-shielding pattern LS1 and the second light-shielding pattern LS2 to be on different layers, the vertical space of the array substrate can be made reasonable, which is beneficial to improving the aperture ratio. It should be noted that in some embodiments, only the first light-shielding pattern LS1 can be set, and the first light-shielding pattern LS1 can be used to block the channel region of the active layer AC, the fourth via V4 and the fifth via V5.

[0115] In some embodiments, the array substrate provided in the present disclosure, as shown in Figures 2, 4, 7, 10, and 14, may further include a color resist layer 113 located between the layer containing the plurality of transition electrodes 105 and the second insulating layer 107. Optionally, the color resist layer 113 may include red, green, and blue color resists, making the present disclosure applicable to products with a COA structure. Of course, in some embodiments, the color resist layer 110 may also be disposed on the opposing substrate (also known as the color filter substrate CF), and the present disclosure does not limit this.

[0116] In some embodiments, the array substrate provided in this disclosure, as shown in Figures 2, 4, 7, 10, 12, and 14, may further include: a low-temperature polysilicon transistor TL located in the non-display area BB and belonging to a multiplexer MUX, a shift register GOA, etc., and a conductive pattern 114 disposed on the same layer as the data line DL and located in the non-display area BB. The first common electrode 102 is electrically connected to the second common electrode 104 through the conductive pattern 114. The first electrode D and the second electrode S of the low-temperature polysilicon transistor TL are disposed on the same layer as the data line DL, and the gate G of the low-temperature polysilicon transistor TL is disposed on the same layer as the first light-shielding pattern LS1. The gate G of the low-temperature polysilicon transistor TL may be located above the active layer AC of the low-temperature polysilicon transistor TL (i.e., the low-temperature polysilicon transistor TL may be a top-gate transistor). In some embodiments, as shown in Figures 1A, 1B, 3A, 3B and 13, the data line DL can be a straight line or a broken line. When the data line DL is a broken line, the tilt direction of the data line DL can be the same as the tilt direction of the pixel electrode 103 and the tilt direction of the slit S in the first common electrode 102.

[0117] In some embodiments, as shown in FIG2, 4, 7, 10, and 13, the array substrate provided in this disclosure may further include an eighth insulating layer 115 located between the layer containing the first common electrode 102 and the layer containing the second sub-pixel electrode 1032. The thickness of the eighth insulating layer 115 may be [missing information]. Correspondingly, the thickness of the first insulating layer 106 can be For example, the thickness of the eighth insulating layer 115 is The thickness of the first insulating layer 106 is Alternatively, the thickness of the eighth insulating layer 115 is The thickness of the first insulating layer 106 is Thus, by matching the thickness of the insulating layer between the common electrode and the pixel electrode, the storage capacitance between the common electrode and the pixel electrode can also be increased. In some embodiments, the material of the eighth insulating layer 115 can be an inorganic insulating material such as silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiON), aluminum oxide (AlOx), hafnium oxide (HfOx), tantalum oxide (TaOx), and can be a single layer or a stacked layer.

[0118] In some embodiments, the array substrate provided in the present disclosure, as shown in FIG2, 4, 7 and 10, may further include a buffer layer 116, a ninth insulating layer 117, a tenth insulating layer 118, and an auxiliary electrode 119, etc. Optionally, the materials of the first sub-insulating layer 110, the second sub-insulating layer 111, the seventh insulating layer 112, the eighth insulating layer 115, the buffer layer 116, the ninth insulating layer 117 and the tenth insulating layer 118 may be inorganic insulating materials such as silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiON), aluminum oxide (AlOx), hafnium oxide (HfOx), tantalum oxide (TaOx), etc., and may be single-layer or stacked. The auxiliary electrode 119 is in direct contact with the first common electrode 102 to prevent pixel color mixing or enhance the transmission capability of the common voltage signal. Furthermore, the auxiliary electrode 119 can shield the data line 102. The reflectivity of the auxiliary electrode 119 is lower than that of the data line 102 to reduce reflection of ambient light and improve display performance. The material of the auxiliary electrode 119 may include at least one metal such as gold (Au), silver (Ag), copper (Cu), molybdenum (Mo), aluminum (Al), titanium (Ti), chromium (Cr), and nickel (Ni). For example, the material of the auxiliary electrode 119 may be molybdenum. Other essential components of the array substrate are understood by those skilled in the art and are not described in detail here, nor should they be construed as limiting this disclosure.

[0119] Based on the same inventive concept, this disclosure provides a method for manufacturing the above-mentioned array substrate. Since the principle of this manufacturing method in solving the problem is similar to that of the above-mentioned array substrate in solving the problem, the implementation of the manufacturing method provided in this disclosure can refer to the implementation of the above-mentioned array substrate provided in this disclosure, and repeated details will not be described again.

[0120] In some embodiments, FIG15 shows a flowchart of the fabrication method provided in this disclosure. As shown in FIG15, the fabrication method of the array substrate provided in this disclosure may include the following steps:

[0121] S1501, Provide a substrate;

[0122] S1502, Patterning and forming multiple transistors on a substrate;

[0123] S1503, A second insulating layer including a second via is patterned on the layer containing multiple transistors, wherein the second via overlaps with the first electrode of the transistor;

[0124] S1504. A first insulating layer including a first via is patterned on the second insulating layer. The first via overlaps with the first electrode of the transistor and communicates with the second via. The partial orthographic projection of the first via on the substrate overlaps with the partial orthographic projection of the second via on the substrate.

[0125] S1505. A plurality of pixel electrodes are patterned on the first insulating layer. The pixel electrodes are electrically connected to the first electrode of the transistor through a first via and a second via. The orthogonal projection of the first via on the substrate is far away from the orthogonal projection of the pixel electrode on the substrate relative to the orthogonal projection of the second via on the substrate.

[0126] In some embodiments, in the manufacturing method provided in this disclosure, step S1505, which involves patterning and forming multiple pixel electrodes, can be implemented in the following ways:

[0127] The pattern is designed to form multiple first sub-pixel electrodes;

[0128] Multiple second sub-pixel electrodes electrically connected to the first sub-pixel electrode are formed on the layer where the first sub-pixel electrode is located. The partial orthographic projection of the second sub-pixel electrode on the substrate overlaps with the partial orthographic projection of the first sub-pixel electrode on the substrate.

[0129] In some embodiments, in the above-described fabrication method provided in this disclosure, after performing step S1505 and forming a plurality of pixel electrodes, a first common electrode can also be formed on the layer where the plurality of second sub-pixel electrodes are located. The orthographic projection of the first common electrode on the substrate and the orthographic projection of the first sub-pixel electrode on the substrate have a first overlapping area, and the orthographic projection of the first common electrode on the substrate and the orthographic projection of the second sub-pixel electrode on the substrate have a second overlapping area. The second overlapping area overlaps with the first overlapping area in at most a portion.

[0130] In some embodiments, in the fabrication method provided in this disclosure, the formation of the first common electrode on the layer containing the plurality of second sub-pixel electrodes can be specifically implemented in the following ways:

[0131] A first sub-common electrode is formed by mapping on the layer containing multiple second sub-pixel electrodes;

[0132] Using a mask of the first sub-common electrode, a second sub-common electrode is patterned to be offset from and overlapped with the first sub-common electrode. The second sub-common electrode and the first sub-common electrode together constitute the first common electrode.

[0133] In some embodiments, in the above-described fabrication method provided in this disclosure, after the formation of a plurality of first sub-pixel electrodes and before the formation of a plurality of second sub-pixel electrodes, a mask of a first insulating layer may be used to form a fourth insulating layer having a third via, so as to connect the first sub-pixel electrodes and the second sub-pixel electrodes through the third via.

[0134] It should be noted that in the fabrication method provided in the embodiments of the present invention, the patterning processes involved in forming each layer structure may include not only some or all of the processes such as deposition, photoresist coating, masking, exposure, development, etching, and photoresist stripping, but may also include other processes, depending on the desired pattern formed in the actual fabrication process, and are not limited here. For example, a post-baking process may be included after development and before etching. The deposition process may be chemical vapor deposition, plasma-enhanced chemical vapor deposition, or physical vapor deposition, and is not limited here; the etching may be dry etching or wet etching, and is not limited here.

[0135] Based on the same inventive concept, this disclosure provides a display panel, and Figure 16 is a schematic diagram of a structure of the display panel provided in this disclosure. As shown in Figure 16, the display panel of this disclosure includes the array substrate 001 provided in the embodiment of this disclosure, and a counter substrate 002 disposed opposite to the array substrate 001. Since the principle by which this display panel solves the problem is similar to the principle by which the array substrate solves the problem, the implementation of this display panel can refer to the embodiment of the array substrate described above, and repeated details will not be described again.

[0136] In some embodiments of the present disclosure, the array substrate 001 may further include a gate line extending at the row gap of the pixel electrode 103, and the opposing substrate 002 may further include a black matrix (BM) covering the gate line. Since the data line DL is shielded by the auxiliary electrode 119, the present disclosure does not require the setting of a vertical black matrix to shield the data line DL, thereby effectively increasing the transmittance.

[0137] In some embodiments, as shown in FIG16, in the display panel provided in the present disclosure, a liquid crystal layer 003 may be disposed between the array substrate 001 and the opposing substrate 002. A first polarizer 004 may be disposed on the side of the array substrate 001 away from the opposing substrate 002, and a second polarizer 005 may be disposed on the side of the opposing substrate 002 away from the array substrate 001. The polarization direction of the first polarizer 004 and the polarization direction of the second polarizer 005 are perpendicular to each other. Other essential components of the display panel are understood by those skilled in the art and will not be described in detail here, nor should they be construed as limiting the present disclosure.

[0138] Based on the same inventive concept, this disclosure provides a display device, and Figure 17 is a schematic diagram of the structure of the display device provided in this disclosure. As shown in Figure 17, the display device provided in this disclosure may include the display panel PNL provided in this disclosure, and a backlight module BLU located on the light-incident side of the display panel PNL. The backlight module BLU may be a direct-lit backlight module or an edge-lit backlight module. Optionally, the edge-lit backlight module may include LED strips, stacked reflective sheets, light guide plates, diffusers, prism groups, etc., with the LED strips located on one side of the thickness direction of the light guide plate. The direct-lit backlight module may include a matrix light source, a reflective sheet, a diffuser plate, and a brightness enhancement film stacked on the light-emitting side of the matrix light source, with the reflective sheet including openings directly opposite the positions of the LEDs in the matrix light source. The LEDs in the LED strips and the LEDs in the matrix light source may be light-emitting devices (LEDs), such as quantum dot light-emitting devices.

[0139] In some embodiments, the LEDs can also be micro-light-emitting devices (such as Mini LEDs and Micro LEDs). Sub-millimeter or even micrometer-scale micro-light-emitting devices, like organic light-emitting devices (OLEDs), are self-emissive devices. Like OLEDs, they offer advantages such as high brightness, ultra-low latency, and ultra-wide viewing angles. Furthermore, because inorganic light-emitting devices emit light based on more stable and lower-resistance metal semiconductors, they offer advantages over organic light-emitting devices (based on organic materials) in terms of lower power consumption, greater resistance to high and low temperatures, and longer lifespan. Moreover, when micro-light-emitting devices are used as backlights, they can achieve more precise dynamic backlighting effects, effectively improving screen brightness and contrast while also solving the glare problem caused by traditional dynamic backlighting between bright and dark areas of the screen, thus optimizing the visual experience.

[0140] In some embodiments, the display device provided in this disclosure can be any product or component with display function, such as a television, monitor, projector, 3D printer, virtual reality device, mobile phone, tablet computer, laptop computer, digital photo frame, navigator, smartwatch, fitness wristband, or personal digital assistant. Optionally, the display device provided in this disclosure includes, but is not limited to, components such as a radio frequency unit, network module, audio output & input unit, sensor, display unit, user input unit, interface unit, and control chip. Optionally, the control chip is a central processing unit, digital signal processor, system-on-a-chip (SoC), etc. For example, the control chip may also include a memory, a power module, etc., and achieve power supply and signal input / output functions through additionally provided wires, signal lines, etc. For example, the control chip may also include hardware circuits and computer-executable code, etc. The hardware circuit may include conventional very large-scale integrated circuits (VLSI) or gate arrays, as well as existing semiconductors or other discrete components such as logic chips and transistors; the hardware circuit may also include field-programmable gate arrays, programmable array logic, programmable logic devices, etc. In addition, the display device provided in this disclosure may include more or fewer of the above-mentioned components, or combine certain components, or arrange different components.

[0141] Although preferred embodiments of this disclosure have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this disclosure.

[0142] Obviously, those skilled in the art can make various modifications and variations to the embodiments of this disclosure without departing from the spirit and scope of the embodiments of this disclosure. Therefore, if these modifications and variations to the embodiments of this disclosure fall within the scope of the claims of this disclosure and their equivalents, this disclosure is also intended to include these modifications and variations.

Claims

1. An array substrate, wherein, The display panel comprises: a substrate; a plurality of pixel electrodes arranged in an array on the substrate; a plurality of transistors between the layer where the plurality of pixel electrodes are located and the substrate; a first insulating layer between the layer where the plurality of transistors are located and the layer where the plurality of pixel electrodes are located, the first insulating layer comprising a first via hole overlapping the first electrode of the transistor; a second insulating layer between the first insulating layer and the layer where the first electrode of the transistor is located, the second insulating layer comprising a second via hole overlapping the first electrode of the transistor and communicating with the first via hole; the pixel electrode is electrically connected to the first electrode of the transistor through the first via hole and the second via hole; and the orthogonal projection of the first via hole on the substrate is arranged away from the orthogonal projection of the second via hole on the substrate relative to the orthogonal projection of the pixel electrode on the substrate.

2. The array substrate of claim 1, wherein, The first insulating layer covers the sidewall of the second via hole covered by the pixel electrode.

3. The array substrate of claim 1 or 2, wherein, The orthogonal projection of the first via hole on the substrate overlaps the sidewall of the second insulating layer away from the pixel electrode.

4. The array substrate according to any one of claims 1 to 3, wherein, The bottom of the first via hole comprises a first boundary and a second boundary extending in the row direction, the orthogonal projection of the first boundary on the substrate is located on the side of the orthogonal projection of the second boundary on the substrate close to the orthogonal projection of the pixel electrode on the substrate; The bottom of the second via hole comprises a third boundary and a fourth boundary extending in the row direction, the orthogonal projection of the third boundary on the substrate is located on the side of the orthogonal projection of the fourth boundary on the substrate close to the orthogonal projection of the pixel electrode on the substrate; And the orthogonal projection of the first boundary on the substrate is located between the orthogonal projection of the third boundary on the substrate and the orthogonal projection of the fourth boundary on the substrate, the orthogonal projection of the fourth boundary on the substrate is located between the orthogonal projection of the first boundary on the substrate and the orthogonal projection of the second boundary on the substrate. The first via holes corresponding to the pixel electrodes in the same row communicate to form a first groove, and the second via holes corresponding to the pixel electrodes in the same row communicate to form a second groove.

5. The array substrate of claim 4, wherein, Further comprising a first common electrode on the side of the layer where the plurality of pixel electrodes are located away from the substrate; 6. The array substrate according to any one of claims 1 to 5, wherein, The pixel electrode comprises a first sub-pixel electrode and a second sub-pixel electrode between the layer where the first sub-pixel electrode is located and the layer where the first common electrode is located, and the first sub-pixel electrode is electrically connected to the second sub-pixel electrode; The partial orthogonal projection of the first sub-pixel electrode on the substrate overlaps the partial orthogonal projection of the second sub-pixel electrode on the substrate. ​ The first sub-pixel electrode has a first overlapping area with the first common electrode on the substrate, and the second sub-pixel electrode has a second overlapping area with the first common electrode on the substrate, and the second overlapping area at most partially overlaps with the first overlapping area.

7. The array substrate of claim 6, wherein, A plurality of second common electrodes are further included between the first insulating layer and the second insulating layer, and the second common electrodes have projections on the substrate which cross the projections of the pixel electrodes on the substrate.

8. The array substrate of claim 7, wherein, The second common electrode has a third overlapping area with the first sub-pixel electrode on the substrate, and a fourth overlapping area with the second sub-pixel electrode on the substrate, and the third overlapping area at most partially overlaps with the fourth overlapping area.

9. The array substrate of claim 8, wherein, The third overlapping area is substantially located in the fourth overlapping area. The first common electrode includes a slit, and on one side of the extending direction of the slit, the first overlapping area substantially coincides with the second overlapping area, and on the other side of the extending direction of the slit, the first overlapping area is substantially located in the second overlapping area.

10. The array substrate of claim 8, wherein, The third overlapping area partially overlaps with the fourth overlapping area or is staggered with the fourth overlapping area. The first common electrode includes a slit, and the first overlapping area and the second overlapping area are located on both sides of the extending direction of the slit.

11. The array substrate of claim 9, wherein, The first common electrode is a single-layer structure, and the width of the slit is 2-3 μm.

12. The array substrate of claim 10, wherein, The first common electrode includes a first sub-common electrode and a second sub-common electrode which is in contact with and partially overlaps with the first sub-common electrode on the side away from the layer where the pixel electrode is located, and the width of the slit is 0.8-2 μm.

13. The array substrate according to any one of claims 9 to 12, wherein, The first sub-pixel electrode and the second sub-pixel electrode extend to the area where the slit is located. In the column direction, the length of the first sub-pixel electrode is greater than half the length of the slit, and the length of the second sub-pixel electrode is greater than the length of the slit.

14. The array substrate of any one of claims 7 to 13, wherein, The projection of the second common electrode on the substrate is located between the projections of the first via and / or the second via on the substrate in the column direction.

15. The array substrate according to any one of claims 7 to 14, wherein, Further comprising: A conductive pattern arranged in the same layer as the second electrode of the transistor, and the first common electrode is electrically connected with the second common electrode through the conductive pattern.

16. The array substrate according to any one of claims 6 to 15, wherein, The first sub-pixel electrode includes a pixel part and a lap part arranged integrally, wherein the lap part is located in the second via, the pixel part is located outside the second via, and the width of the lap part is smaller than the width of the pixel part.

17. The array substrate of claim 16, wherein, The first sub-pixel electrode further includes a transition part connecting the pixel part and the lap part, and in the direction from the pixel part to the lap part, the width of the transition part is reduced at least once, and the width of the transition part is greater than the width of the lap part and smaller than the width of the pixel part.

18. The array substrate of claim 17, wherein, The transition portion is located on a plane of the first insulating layer, and / or the transition portion is located on the first insulating layer at a sidewall of the second via.

19. The array substrate of any one of claims 6 to 18, wherein, A third insulating layer is further included, and the third insulating layer fills the first via and the second via. A projection of the second sub-pixel electrode on the substrate substrate partially overlaps with a projection of the first sub-pixel electrode on the substrate substrate of the previous row, and a projection of the second sub-pixel electrode on the substrate substrate partially overlaps with a projection of the second via on the substrate substrate of the previous row.

20. The array substrate of any one of claims 6 to 18, wherein, A fourth insulating layer is further included between the layer where the first sub-pixel electrode is located and the layer where the second sub-pixel electrode is located. The first sub-pixel electrode is electrically connected with the second sub-pixel electrode through a third via penetrating through the fourth insulating layer, and a projection of the third via on the substrate substrate is located within a projection of the second via on the substrate substrate.

21. The array substrate of claim 20, wherein, A first common electrode is further included on a side of the layer where the plurality of pixel electrodes are located away from the substrate substrate, and the first common electrode includes a slit. In the slit area: a length of the first sub-pixel electrode in the column direction is greater than half of a length of the slit in the column direction, and less than a length of the second sub-pixel electrode in the column direction, and the length of the second sub-pixel electrode in the column direction is less than the length of the slit in the column direction.

22. The array substrate of any one of claims 1 to 21, wherein, A data line, a first light shielding pattern and a second light shielding pattern are further included, wherein The first light shielding pattern is multiplexed as a bottom gate of the transistor, and a projection of the first light shielding pattern on the substrate substrate covers a channel region of the active layer of the transistor. A second electrode of the first transistor is multiplexed as the data line, and a fifth insulating layer is arranged between the layer where the data line is located and the active layer of the transistor, and the data line is electrically connected with the active layer of the transistor through a fourth via penetrating through the fifth insulating layer. The second light shielding pattern is located on a side of the layer where the first light shielding pattern is located close to the substrate substrate, and a projection of the second light shielding pattern on the substrate substrate covers a projection of the fourth via on the substrate substrate. An adapter electrode and a color resist layer are further included, wherein the adapter electrode is located between the active layer of the transistor and the second insulating layer, and the adapter electrode is multiplexed as the first electrode of the transistor, and the color resist layer is located between the layer where the adapter electrode is located and the second insulating layer.

23. The array substrate of any one of claims 1-22, wherein, The array substrate as claimed in any one of claims 1-23 is included, and an opposite substrate is arranged opposite to the array substrate.

24. A display panel, wherein, The display panel as claimed in claim 24 is included, and a backlight module is arranged on a light-incident side of the display panel.

25. A display device comprising: The display panel as claimed in claim 24 is included, and a backlight module is arranged on a light-incident side of the display panel.

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