Power backup system, method and apparatus, device, medium, and computer program product

Abstract

The present application provides a power backup system, method and apparatus, a device, a medium, and a computer program product. The power backup system comprises a memory resource all-in-one machine, and the memory resource all-in-one machine comprises an interconnect switch board, computing node boards, a memory resource board, a power module and a power backup module; the interconnect switch board comprises a first baseboard management controller and an interconnect switch chip; and the interconnect switch chip is used for connecting computing nodes in the computing node boards and memory modules in the memory resource board. In some embodiments of the present application, the power backup module is used for power backup of memory resources and computing resources, and different power backup control logics are adopted for a memory resource node and a computing resource node of the all-in-one machine.

Description

Backup power systems, methods, apparatus, equipment, media, and computer program products

[0001] Cross-references to related applications

[0002] This application claims priority to Chinese Patent Application No. 202411034707.4, filed on July 30, 2024, entitled “Backup Power System, Method, Apparatus, Equipment, Medium and Computer Program Product”, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This application relates to the field of memory technology, and in particular to a power backup system, method, apparatus, device, medium, and computer program product. Background Technology

[0004] With the development of technologies such as cloud computing, artificial intelligence, and high-performance computing, processor computing power is constantly increasing and the number of cores is constantly growing, driving memory systems to evolve towards larger capacity and higher bandwidth. In order to meet the ever-increasing demand for memory resources, it is necessary to re-examine the server resource management architecture based on the traditional server hardware architecture. Server architects have optimized and restructured the traditional server architecture, and proposed an integrated reorganization architecture solution for server memory resource pooling with the aim of improving resource utilization and reducing maintenance costs.

[0005] In a pooled memory environment, memory resources in the memory resource pool will be provided to multiple different host computing nodes. Once the all-in-one machine experiences a loss of mains power or a power supply failure that causes abnormal power supply, it will affect the normal operation of all memory resources in the all-in-one machine and the business of the host computing nodes.

[0006] In related technologies, in order to solve the above problems, a solution is to use BBU or supercapacitor modules to manage backup power for server systems. However, this solution is limited by the power supply time of the BBU module and can only perform dumping of some important memory data. In memory resource pool scenarios, there is a large amount of memory data, and the power supply time provided by the BBU is insufficient to dump all the memory data to non-volatile storage devices. Summary of the Invention

[0007] The purpose of some embodiments of this application is to provide a power backup system, method, apparatus, device, medium, and computer program product, the specific technical solutions of which are as follows:

[0008] In some embodiments, a backup power system is first provided, which includes an interconnect switching board, a compute node board, a memory resource board, a power supply module, and a backup power module; the interconnect switching board includes a first baseboard management controller and an interconnect switching chip; the interconnect switching chip is used to connect the compute nodes in the compute node board and the memory modules in the memory resource board;

[0009] The first baseboard management controller is used to obtain the power supply fault status corresponding to the memory resource integrated machine; if the power supply fault status is the first power supply fault status, it controls the backup power module to supply power to the memory resource integrated machine based on the external power supply failure signal sent by the complex programmable logic device in the interconnect switching board, and executes the memory resource dumping strategy; if the power supply fault status is the second power supply fault status, it executes the memory pre-dumping strategy, and when it detects that the power module is in a power loss state, it controls the backup power module to supply power to the memory resource integrated machine, and executes the memory resource dumping strategy.

[0010] In some embodiments, the backup power system also includes a network switching chip board;

[0011] The compute node board, memory resource board, and interconnect switch board are connected via a network switch chip board.

[0012] In some embodiments, the compute node board, interconnect switch board, and memory resource board are connected according to a preset topology.

[0013] In some embodiments, the preset topology connection method includes the upstream port of the interconnect switching chip connected to the computing node board and the downstream port connected to the memory resource board; by managing the computing node to configure the upstream and downstream interconnection relationship of the interconnect switching chip and the memory resource slicing management, the first baseboard management controller of the interconnect switching board interacts with the management computing node through the network preset interface to obtain the downstream port corresponding to the memory resource of the upstream computing node of the interconnect switching chip of the interconnect switching board, and forms the connection topology of computing resources and memory resources.

[0014] In some embodiments, the interconnect switching board includes a management computing node and a first baseboard management controller;

[0015] The management computing node is used to control the interconnect switching chip to manage and configure memory resource information;

[0016] The first baseboard management controller is connected to the management computing node through a preset network. The first baseboard management controller is used to interact with the management computing node to obtain memory resource information.

[0017] In some embodiments, the memory resource board includes a memory controller, a second baseboard management controller, and a memory module;

[0018] The memory controller is used to connect to the interconnect switching board through a preset interface, monitor and manage memory resource information, and transfer the interconnect switching bus of the memory module to the interconnect switching chip in the interconnect switching board so that the compute node board can use the memory resource information corresponding to the memory module.

[0019] The second baseboard management controller is connected to the memory controller via a preset bus. The second baseboard management controller is used to monitor and manage the interconnected switching memory and to control the power-on and power-off of the memory modules in each memory controller.

[0020] In some embodiments, a power backup method is also provided, applied to a first baseboard management controller in an interconnect switching board of a power backup system. The power backup system includes an interconnect switching board, a compute node board, a memory resource board, a power supply module, and a power backup module. The interconnect switching board includes a first baseboard management controller and an interconnect switching chip. The interconnect switching chip is used to connect compute nodes in the compute node board and memory modules in the memory resource board. The method includes:

[0021] Obtain the power supply fault status corresponding to the memory resource all-in-one machine;

[0022] If the power supply failure state is the first power supply failure state, the backup power module is controlled to supply power to the memory resource all-in-one machine based on the external power supply failure signal sent by the complex programmable logic device in the interconnection switching board, and the memory resource dumping strategy is executed.

[0023] If the power supply failure status is the second power supply failure status, the memory pre-dump strategy is executed, and if the power module is detected to be in a power loss state, the backup power module is controlled to supply power to the memory resource all-in-one machine, and the memory resource dump strategy is executed.

[0024] In some embodiments, obtaining the power supply fault status corresponding to the memory resource all-in-one machine includes:

[0025] Upon receiving an external power failure signal from a complex programmable logic device in the interconnect switching board, the power supply fault state is determined to be the first power supply fault state.

[0026] If a power module is detected to be in a faulty state, the power supply fault state is determined to be the second power supply fault state.

[0027] In some embodiments, the external power supply failure signal is generated when the complex programmable logic device in the interconnect switching board identifies that the voltage corresponding to the external power supply board is lower than a preset voltage.

[0028] In some embodiments, determining the power supply failure state as a second power supply failure state when a power module failure state is detected includes:

[0029] Monitor the power status of the power module via power management bus commands.

[0030] Confirm whether the power module is in a faulty state based on the power status;

[0031] If a power module is detected to be in a fault state, the power supply fault state is determined to be the second power supply fault state.

[0032] The fault states include at least one of the following: the power module is in a state of power redundancy loss, the output voltage of the power module is in an abnormal state, the output current of the power module is in an abnormal state, and the power module is in an AC power interruption state.

[0033] In some embodiments, performing a memory pre-dump strategy includes:

[0034] Send power module fault warning information to the computing nodes in the computing node board, and transfer the memory data corresponding to the computing nodes to a preset non-volatile storage device.

[0035] In some embodiments, when a power supply loss is detected in the power module, controlling the backup power module to supply power to the memory resource all-in-one machine includes:

[0036] If the system detects that a memory pre-dumping strategy is being executed and that the power module is in a power loss state, it controls the backup power module to supply power to the memory resource all-in-one machine.

[0037] In some embodiments, executing a memory resource dump strategy includes:

[0038] Obtain the first target memory data, where the target memory data is in a dump completed state; perform hot removal processing on the first target memory data.

[0039] In some embodiments, hot removal of the first target memory data includes:

[0040] Determine the first target computing node corresponding to the first target memory data based on the first target memory data;

[0041] Power off the first target computing node.

[0042] In some embodiments, executing a memory resource dump strategy includes:

[0043] Acquire the second target memory data, wherein the second target memory data is in an uncompleted dump state;

[0044] The second target memory data is transferred to the corresponding preset non-volatile storage device.

[0045] In some embodiments, after the step of sending a power supply signal to the backup power module according to an external power outage signal, so that the backup power module supplies power to the memory resource all-in-one machine, the method includes:

[0046] A power consumption limit signal is sent to the third baseboard management controller corresponding to the computing node in each computing node board.

[0047] In some embodiments, a power backup device is also provided, applied to a first baseboard management controller in an interconnect switching board of a power backup system. The power backup system includes an interconnect switching board, a compute node board, a memory resource board, a power supply module, and a power backup module. The interconnect switching board includes a first baseboard management controller and an interconnect switching chip. The interconnect switching chip is used to connect compute nodes in the compute node board and memory modules in the memory resource board. The device includes:

[0048] The acquisition module is used to acquire the power supply fault status corresponding to the memory resource all-in-one machine;

[0049] The first execution module is used to control the backup power module to supply power to the memory resource all-in-one machine based on the external power failure signal sent by the complex programmable logic device in the interconnection switching board if the power failure state is the first power failure state, and to execute the memory resource dumping strategy.

[0050] The second execution module is used to execute a memory pre-dump strategy if the power supply failure state is the second power supply failure state, and to control the backup power module to supply power to the memory resource all-in-one machine when the power supply module is detected to be in a power loss state, and to execute a memory resource dump strategy.

[0051] In some embodiments, an electronic device is also provided, including: a processor;

[0052] Memory used to store processor-executable instructions;

[0053] The processor is configured to execute instructions to implement the power backup method described above.

[0054] In some embodiments, a non-volatile readable storage medium is also provided, which stores instructions that, when executed on a computer, cause the computer to implement the power backup method described above.

[0055] In some embodiments, a computer program product is also provided, including a computer program / instruction that, when executed by a processor, implements the power backup method described above.

[0056] Some embodiments of this application provide a backup power system, which includes an interconnect switching board, a compute node board, a memory resource board, a power supply module, and a backup power module. The interconnect switching board includes a first baseboard management controller and an interconnect switching chip. The interconnect switching chip is used to connect compute nodes in the compute node board and memory modules in the memory resource board. The first baseboard management controller is used to obtain the power supply fault status corresponding to the memory resource integrated machine. If the power supply fault status is a first power supply fault status, the backup power module is controlled to supply power to the memory resource integrated machine based on the external power failure signal sent by the complex programmable logic device in the interconnect switching board, and a memory resource dumping strategy is executed. If the power supply fault status is a second power supply fault status, a memory pre-dumping strategy is executed, and when the power supply module is detected to be in a power loss state, the backup power module is controlled to supply power to the memory resource integrated machine, and a memory resource dumping strategy is executed. In some embodiments of this application, the backup power system provided by some embodiments of this application intelligently monitors the power supply fault status through the first baseboard management controller in the interconnect switching board, and flexibly adjusts the backup power strategy according to different fault statuses (first or second power supply fault status). In the event of a mains power outage or loss of power supply from the power module, the backup power module can quickly intervene to ensure continuous power supply to the memory resource integrated machine. At the same time, it executes memory resource dumping or pre-dumping strategies to effectively prevent data loss, ensure stable system operation, and significantly improve system reliability and data security. Attached Figure Description

[0057] To more clearly illustrate the technical solutions in some embodiments of this application, the drawings used in the prior art and embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0058] Figure 1 is a schematic diagram of the architecture of a backup power system provided in some embodiments of this application;

[0059] Figure 2 is a schematic diagram of the network connection topology of a backup power system provided in some embodiments of this application;

[0060] Figure 3 is a flowchart of a power backup method provided in some embodiments of this application;

[0061] Figure 4 is an overall schematic diagram of an exemplary power backup method provided by some embodiments of this application;

[0062] Figure 5 is an overall schematic diagram of another exemplary power backup method provided by some embodiments of this application;

[0063] Figure 6 is a schematic diagram of a memory hot-plug control topology provided by some embodiments of this application;

[0064] Figure 7 is a device block diagram of a backup power device provided in some embodiments of this application;

[0065] Figure 8 is a schematic diagram of an electronic device provided by some embodiments of this application;

[0066] Figure 9 is a schematic diagram of a non-volatile readable storage medium provided in some embodiments of this application;

[0067] Figure 10 is a schematic diagram of a computer program product provided by some embodiments of this application. Detailed Implementation

[0068] To make the objectives, technical solutions, and advantages of some embodiments of this application clearer, the various embodiments of this application will be described in detail below with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details are presented in the various embodiments of this application to facilitate a better understanding of the application. However, the technical solutions claimed in this application can be implemented even without these technical details and with various changes and modifications based on the following embodiments. The division of the various embodiments below is for ease of description and should not constitute any limitation on the specific implementation of this application. The various embodiments can be combined with and referenced by each other without contradiction.

[0069] In some embodiments, for ease of understanding of the technical solutions of this application, some contents are explained as follows: CPU (Central Processing Unit) Board is a computing node board; CXL (Compute Express Link) SW (Switch) Board is an interconnect switching board; DIMM (Dual In-Line Memory Module) Board is a memory resource board; LAN SW Board is a network switching chip board; CXL SW chip is an interconnect interaction chip; MXC is a memory controller, short for Memory Expander Controller; BMC is a Baseboard Management Controller; CXL (Compute Express Link) is a new type of high-speed interconnect technology; mCPU (Management CPU) is a management computing node, which is a memory resource management CPU; BBU (Battery Backup Unit) is a battery backup unit, which in some embodiments is a backup power module; PSU (Power Supply Unit) is a power supply module.

[0070] Referring to Figure 1, a schematic diagram of the architecture of a backup power system provided by some embodiments of this application is shown. The backup power system includes a memory resource integrated machine, which includes an interconnect switching board, a compute node board, a memory resource board, a power supply module, and a backup power module. The interconnect switching board includes a first baseboard management controller and an interconnect switching chip. The interconnect switching chip is used to connect the compute nodes in the compute node board and the memory modules in the memory resource board.

[0071] The first baseboard management controller is used to obtain the power supply fault status corresponding to the memory resource integrated machine; if the power supply fault status is the first power supply fault status, it controls the backup power module to supply power to the memory resource integrated machine based on the external power supply failure signal sent by the complex programmable logic device in the interconnect switching board, and executes the memory resource dumping strategy; if the power supply fault status is the second power supply fault status, it executes the memory pre-dumping strategy, and when it detects that the power module is in a power loss state, it controls the backup power module to supply power to the memory resource integrated machine, and executes the memory resource dumping strategy.

[0072] In some embodiments, the backup power system also includes a network switching chip board;

[0073] The compute node board, memory resource board, and interconnect switch board are connected via a network switch chip board.

[0074] In some embodiments, referring to Figure 1, which is a schematic diagram of a memory resource integrated machine system architecture provided by some embodiments of this application, various resources are allocated to different hardware boards in the integrated architecture. These boards may include a CPU board for processing computing tasks, an interconnect switching board for interconnect switching, a DIMM board for managing memory resources, and a LAN SW board for network switching. These boards are connected via the LAN SW board to form a unified BMC management network. The physical connection cables between the CPU board, interconnect switching board, and DIMM board are pre-defined. Referring to Figure 2, which is a schematic diagram of a network connection topology for a memory resource integrated machine provided by some embodiments of this application, the network connection topology describes how the various components are connected and communicate via the network in the integrated architecture.

[0075] In some embodiments, the compute node board, interconnect switching board, and memory resource board are connected according to a preset topology. The preset topology includes the interconnect switching chip being connected upstream to the port of the compute node board and downstream to the memory resource board. The interconnect switching chip's upstream and downstream interconnect relationships and memory resource slicing are configured by the management compute node. The first baseboard management controller of the interconnect switching board interacts with the management compute node through a preset network interface to obtain the downstream port corresponding to the memory resource of the upstream compute node of the interconnect switching chip on the interconnect switching board, and forms a connection topology between the compute resources and memory resources.

[0076] In some embodiments, the CXL SW chip has fixed connections to upstream and downstream hardware topologies. Upstream, it connects to the ports of the CPU Board of the compute node, and downstream, it connects to the memory resources of the DIMM Board. The mCPU configures the upstream and downstream Fabric interconnections and memory resource slicing management of the CXL SW chip. The CXL SW Board BMC interacts with the mCPU via a network Redfish interface to obtain which downstream ports correspond to the memory resources currently used by the upstream compute node CPU of the CXL SW chip, and forms the connection topology between the compute resources and memory resources.

[0077] In some embodiments, the interconnect switching board includes a management computing node and a first baseboard management controller;

[0078] The management computing node is used to control the interconnect switching chip to manage and configure memory resource information;

[0079] The first baseboard management controller is connected to the management computing node through a preset network. The first baseboard management controller is used to interact with the management computing node to obtain memory resource information.

[0080] In some embodiments, within the interconnect switching board, the main CPU (mCPU) is responsible for directing the interconnect switching chips to manage and configure interconnect switching memory resources. The BMC is connected to the mCPU via an SGMII network, through which the BMC can communicate with the mCPU to obtain and adjust the allocation of memory resources.

[0081] In some embodiments, the interconnect switching chip is the CXL SW chip. The CXL SW chip (which may refer to the CXL switching chip) mainly functions in the following ways:

[0082] Connectivity: The CXL SW chip acts as a bridge, connecting the upstream compute node CPU Board with the downstream DIMM Board memory resources. This connection ensures that the compute node can effectively access and manage memory resources.

[0083] Configuration Management: The upstream and downstream fabric interconnects and memory resource slicing management of the CXL SW chip are configured by the mCPU (which may be the main control CPU). This means that the CXL SW chip needs to support complex configuration logic in order to adjust its connections and resource allocation according to the instructions of the mCPU.

[0084] Communication Interface: The CXL SW chip interacts with the mCPU via its Board BMC (Board Management Controller) through a network Redfish interface. This interaction allows the CXL SW chip to obtain detailed information about the memory resources used by the compute node's CPU, thereby dynamically adjusting the connection topology between compute and memory resources.

[0085] Resource optimization: Through the connectivity and configuration management described above, the CXL SW chip helps optimize the use of computing and memory resources, improving the overall performance and efficiency of the system.

[0086] In some embodiments, the memory resource board includes a memory controller, a second baseboard management controller, and a memory module;

[0087] The memory controller is used to connect to the interconnect switching board through a preset interface, monitor and manage memory resource information, and transfer the interconnect switching bus of the memory module to the interconnect switching chip in the interconnect switching board so that the compute node board can use the memory resource information corresponding to the memory module.

[0088] The second baseboard management controller is connected to the memory controller via a preset bus. The second baseboard management controller is used to monitor and manage the interconnected switching memory and to control the power-on and power-off of the memory modules in each memory controller.

[0089] In some embodiments, within the DIMM board, the MXC acts as a memory controller. It connects to the interconnect switching memory via DDR and SMBus, monitoring and managing this memory, and connecting the interconnect switching bus to the interconnect switching chip so that compute nodes can access and use these memory resources. The DIMM board's BMC connects to the MXC via SMBus, thereby monitoring and managing the interconnect switching memory. Furthermore, the BMC is connected to the eFuse via an I2C hardware link to control the power state of each MXC memory module.

[0090] The PSU power module provides power to the entire system, while the BBU acts as a backup power module. It charges the PSU power supply when it is working normally, and provides power when the PSU power supply fails, ensuring the continuous operation of the system.

[0091] In the memory resource integrated system architecture, in addition to the aforementioned boards for resource allocation and interaction, there are also PSU power modules and BBU backup power modules. For the sake of convenience in the subsequent explanation of the technical solutions, the PSU power modules will be referred to as power modules and the BBU backup power modules as backup power modules.

[0092] Some embodiments of this application provide a backup power system, which includes an interconnect switching board, a compute node board, a memory resource board, a power supply module, and a backup power module. The interconnect switching board includes a first baseboard management controller and an interconnect switching chip. The interconnect switching chip is used to connect compute nodes in the compute node board and memory modules in the memory resource board. The first baseboard management controller is used to obtain the power supply fault status corresponding to the memory resource integrated machine. If the power supply fault status is a first power supply fault status, the backup power module is controlled to supply power to the memory resource integrated machine based on the external power failure signal sent by the complex programmable logic device in the interconnect switching board, and a memory resource dumping strategy is executed. If the power supply fault status is a second power supply fault status, a memory pre-dumping strategy is executed, and when the power supply module is detected to be in a power loss state, the backup power module is controlled to supply power to the memory resource integrated machine, and a memory resource dumping strategy is executed. In some embodiments of this application, the backup power system provided by some embodiments of this application intelligently monitors the power supply fault status through the first baseboard management controller in the interconnect switching board, and flexibly adjusts the backup power strategy according to different fault statuses (first or second power supply fault status). In the event of a mains power outage or loss of power supply from the power module, the backup power module can quickly intervene to ensure continuous power supply to the memory resource integrated machine. At the same time, it executes memory resource dumping or pre-dumping strategies to effectively prevent data loss, ensure stable system operation, and significantly improve system reliability and data security.

[0093] In the memory resource appliance described in this application, memory resources are provided to multiple different host computing nodes. If the memory resource appliance experiences a mains power loss or power failure leading to abnormal power supply, it will affect the normal operation of all memory resources within the memory resource appliance and the services of the host computing nodes. Therefore, this application also provides a method to ensure normal power supply in the event of a failure, i.e., a backup power method. In some embodiments, referring to FIG3, a flowchart of the steps of a backup power method provided by some embodiments of this application is shown. The backup power method is applied to a first baseboard management controller in an interconnect switching board of a backup power system. The backup power system includes a memory resource appliance, which includes an interconnect switching board, a computing node board, a memory resource board, a power supply module, and a backup power module. The interconnect switching board includes a first baseboard management controller and an interconnect switching chip. The interconnect switching chip is used to connect the computing nodes in the computing node board and the memory modules in the memory resource board. The method includes:

[0094] Step 101: Obtain the power supply fault status corresponding to the memory resource all-in-one machine;

[0095] In some embodiments, backup power triggering involves two scenarios: the first is mains power failure triggering, and the second is PSU power supply unrecoverable fault triggering.

[0096] Therefore, the first step is to determine the current scenario, that is, to confirm whether the power module is in a faulty state.

[0097] Whether the power module is in a faulty state is the second scenario, the PSU power supply unrecoverable fault trigger.

[0098] In some embodiments, step 101, namely obtaining the power supply fault status corresponding to the memory resource all-in-one machine, includes:

[0099] S1011, upon receiving an external power failure signal from a complex programmable logic device in the interconnect switching board, determine the power supply fault state as the first power supply fault state;

[0100] S1012, if the power module is detected to be in a fault state, the power supply fault state is determined to be the second power supply fault state.

[0101] The external power supply failure signal is generated when the complex programmable logic device in the interconnect switching board identifies that the voltage corresponding to the external power supply board is lower than the preset voltage.

[0102] In some embodiments, determining the power supply failure state as a second power supply failure state when a power module failure state is detected includes:

[0103] Monitor the power status of the power module via power management bus commands.

[0104] Confirm whether the power module is in a faulty state based on the power status;

[0105] If a power module is detected to be in a fault state, the power supply fault state is determined to be the second power supply fault state.

[0106] The fault states include at least one of the following: the power module is in a state of power redundancy loss, the output voltage of the power module is in an abnormal state, the output current of the power module is in an abnormal state, and the power module is in an AC power interruption state.

[0107] Step 102: If the power supply failure state is the first power supply failure state, then control the backup power module to supply power to the memory resource all-in-one machine based on the external power supply failure signal sent by the complex programmable logic device in the interconnection switching board, and execute the memory resource dumping strategy.

[0108] If an unrecoverable fault is detected in the PSU, the memory pre-dump strategy is triggered first. When the CPLD detects the loss of power supply to the PSU, the memory backup power data protection scheme is then triggered.

[0109] In some embodiments, performing a memory pre-dump strategy includes:

[0110] Send power module fault warning information to the computing nodes in the computing node board, and transfer the memory data corresponding to the computing nodes to a preset non-volatile storage device.

[0111] In some embodiments, when a power supply loss is detected in the power module, controlling the backup power module to supply power to the memory resource all-in-one machine includes:

[0112] If the system detects that a memory pre-dumping strategy is being executed and that the power module is in a power loss state, it controls the backup power module to supply power to the memory resource all-in-one machine.

[0113] In some embodiments, referring to Figure 4, which illustrates a backup power memory data saving scheme triggered by mains power loss, the external power supply failure signal is the signal of mains power loss.

[0114] If the BBU backup power is triggered by a loss of mains power, the memory backup power data saving scheme will be directly triggered.

[0115] In some embodiments, a mains power failure triggers the operation. When the CPLD detects that the standby voltage of the mains power supply board is lower than the threshold voltage, it determines that the mains power is out and the PSU power supply capacity is insufficient. It then triggers the BBU backup power module to supply power to the entire system, thereby triggering a memory dump operation to transfer the memory data to a non-volatile storage unit.

[0116] 1) When the CXL SW Board CPLD detects that the Standby voltage of the mains power supply board is lower than the threshold voltage, it determines that the mains power has been lost. It immediately notifies the BBU backup power module MCU, so that the BBU module supplies power to the entire system, and informs the CXL SW Board BMC of the power loss through hardware links such as GPIO or SMBus, triggering the BBU backup power control logic;

[0117] 2) The CXL SW Board BMC communicates with each compute node BMC via network hardware links and software protocols such as IPMI or Redfish, controlling the CPU power consumption cap of the compute nodes, reducing the power consumption of the compute nodes, and extending the power supply time of the BBU.

[0118] 3) The CXL SW Board BMC notifies the Host compute node CPU via the network Redfish interface to trigger the memory resource pool memory data dump logic;

[0119] 4) The upper-level system management software running on the CPU of each Host compute node transfers the memory data to non-volatile storage devices such as hard disks, and stores the CXL memory mark after the memory data is transferred, and notifies the CXL SW Board BMC through the network Redfish interface;

[0120] 5) The CXL SW Board BMC processes the received CXL memory information after the memory data has been dumped, and matches it with the CXL memory resource allocation topology established and saved in the CXL SW Board BMC, matching it to the uplink compute node that uses this memory resource. When all CXL memory resources matched in this compute node's topology have completed memory data dumping, hot-plugging of this part of the memory resource is triggered, hot-removing this part of the CXL memory (see the memory hot-plugging scheme for specific solutions), reducing memory resource power consumption, and further extending the power supply time of the BBU.

[0121] For host compute nodes that have completed memory data transfer, the CXL SW Board BMC sends Redfish commands over the network to the corresponding host compute node BMC, controlling the CPU of that compute node to shut down and power off. This enables unit power-off in memory pooled resource appliance scenarios, further reducing the overall power consumption of the machine in BBU backup power module scenarios, further extending the power supply time of the BBU, and thus preserving more memory data without loss.

[0122] Step 103: If the power supply failure state is the second power supply failure state, then execute the memory pre-dump strategy, and when the power module is detected to be in a power loss state, control the backup power module to supply power to the memory resource all-in-one machine, and execute the memory resource dump strategy.

[0123] If the BBU backup power is triggered by a loss of mains power, the memory backup power data saving scheme will be directly triggered.

[0124] In one embodiment, executing a memory resource dump strategy includes:

[0125] Obtain the first target memory data, where the target memory data is in a dump completed state; perform hot removal processing on the first target memory data.

[0126] In some embodiments, hot removal of target memory data includes: determining a first target computing node corresponding to the first target memory data based on the first target memory data; and controlling the first target computing node to power down.

[0127] In another embodiment, executing the memory resource dump strategy includes:

[0128] Acquire the second target memory data, wherein the second target memory data is in an uncompleted dump state;

[0129] The second target memory data is transferred to the corresponding preset non-volatile storage device.

[0130] In some embodiments, step 103, controlling the backup power module to supply power to the memory resource all-in-one machine based on the external power supply failure signal sent by the complex programmable logic device in the interconnect switching board, includes:

[0131] S1031, receives an external power supply failure signal sent by a complex programmable logic device in the interconnect switching board, wherein the external power supply failure signal is generated based on the mains power supply board voltage being lower than a threshold voltage;

[0132] S1032 sends a power supply signal to the backup power module based on the external power supply failure signal, so that the backup power module can supply power to the memory resource all-in-one machine.

[0133] Following S1032 above, the following may be included: sending a power consumption limit signal to the third baseboard management controller corresponding to the computing node in each computing node board.

[0134] In some embodiments, referring to Figure 5, Figure 5 shows a power failure-triggered backup power memory data saving scheme. If an unrecoverable fault is detected in the PSU, the memory pre-dumping strategy is triggered first. When the CPLD detects the loss of PSU power supply, the memory backup power data protection scheme is triggered again.

[0135] In some embodiments, an unrecoverable PSU power supply failure is triggered. The CXL SW Board BMC monitors the health status of the PSU power supply module via PMBus. If an unrecoverable severe failure is triggered, a memory pre-dump operation is initiated, dumping memory resources to non-volatile memory units. Once power supply loss occurs, the CPLD detects that the board's standby voltage is below a threshold, determines a power supply anomaly, and triggers the BBU backup power module to supply power to the entire system. Based on the pre-dump, the memory resource dump operation continues, dumping more memory data to non-volatile memory units.

[0136] 1) The CXL SW Board BMC monitors the health status of the PSU power supply module through PMBus commands. If it detects that the PSU power supply module has lost power redundancy and the power supply has abnormal output voltage, abnormal output current, AC Lost and other abnormal alarm states, it will trigger the memory data pre-dumping strategy.

[0137] 2) The CXL SW Board BMC informs the host compute node CPU upper-layer management software via the network to pre-dump memory data to non-volatile storage devices such as hard disks, and stores the CXL memory after the memory data has been dumped, and notifies the CXL SW Board BMC through the network Redfish interface;

[0138] 3) If, during the memory data pre-dumping process, the CPLD detects that the standby voltage of the power supply board is lower than the threshold voltage, it determines that the power supply has been lost. The following solution will be adopted:

[0139] a. Immediately notify the BBU backup power module MCU, so that the BBU module can supply power to the entire system, and inform the CXL SW Board BMC of the power supply loss through hardware links such as GPIO or SMBus, triggering the BBU backup power control logic;

[0140] b. The CXL SW Board BMC identifies the CXL memory that has completed the memory dump and performs a hot removal process;

[0141] c.CXL SW Board BMC sends Redfish commands over the network to the corresponding Host compute node BMC, controlling the CPU of that compute node to shut down and power off.

[0142] d. For memory that has not been dumped, continue to perform the pre-dump operation, and then perform memory hot-plugging and host power-down.

[0143] Referring to Figure 6, which shows a memory hot-swappable topology, after the CXL SW Board BMC identifies that all memory resources corresponding to a certain computing node in the topology have completed memory data dumping, it informs the DIMM Board BMC through the network, and then sends a command to the eFuse device corresponding to this part of memory through I2C to power off this part of memory resources.

[0144] The CXL SW Board BMC sends Redfish commands over the network to the corresponding Host compute node BMC, controlling the CPU of that compute node to shut down and power off. This enables unit power-off in memory pooled resource appliance scenarios, further reducing the overall power consumption of the machine in BBU backup power module scenarios, further extending the power supply time of the BBU, and thus preserving more memory data without loss.

[0145] Therefore, some embodiments of this application provide a backup power method that intelligently monitors the power supply failure status through a first baseboard management controller in the interconnect switching board, and flexibly adjusts the backup power strategy according to different failure states (first or second power supply failure state). In the event of a mains power outage or power module power loss, the backup power module can quickly intervene to ensure continuous power supply to the memory resource integrated machine, while executing a memory resource dumping strategy or a pre-dumping strategy to effectively prevent data loss, ensure stable system operation, and significantly improve system reliability and data security. In essence, this application reorganizes computing resources and memory resources into an integrated resource architecture scheme, dynamically allocating the integrated machine's memory resources to different computing resource service nodes, greatly improving the utilization rate of server hardware resources, and reducing the operation and maintenance costs of separately maintaining multiple server racks with different resources. Under the integrated architecture, the topological connection relationship between memory resources and different host computing nodes is monitored. Once the integrated machine experiences a mains power loss or power failure leading to power supply abnormality, in order to avoid affecting the normal operation of all memory resources and host computing nodes within the integrated machine, backup power is provided. Based on the data dumping of memory resources, an automatic and controlled hot-swap strategy is adopted for the CXL memory resources after the dumping is completed. The memory resources that have completed the data dumping are hot-swapped and powered down, and the host computing nodes using the corresponding Device memory resources are powered down. This further reduces the power consumption of the whole machine, thereby extending the power supply time of the BBU backup power module and ensuring that more memory resources can complete the data dumping and migration.

[0146] Additionally, in some embodiments of the backup power method, when the CXL SW Board CPLD detects that the standby voltage of the mains power supply board is lower than the threshold voltage, it is determined that the mains power has been lost. The BBU backup power module MCU is immediately notified, and the BBU module supplies power to the entire system. The CXL SW Board BMC is also notified of the power loss via hardware links such as GPIO or SMBus, triggering the BBU backup power control logic.

[0147] In some embodiments of the backup power method provided, the CXL SW Board BMC communicates with each compute node BMC via a network hardware link and software protocols such as IPMI or Redfish, thereby controlling the CPU power consumption cap of the compute nodes, reducing the power consumption of the compute nodes, and extending the BBU power supply time.

[0148] In some embodiments of the power backup method provided, the CXL SW Board BMC notifies the Host compute node CPU via the network Redfish interface to trigger the memory resource pool memory data dump logic.

[0149] In some embodiments of the power backup method, the upper-level system management software running on the CPU of each Host computing node transfers memory data to non-volatile storage devices such as hard disks, and stores the CXL memory tag after the memory data has been transferred, and notifies the CXL SW Board BMC through the network Redfish interface.

[0150] In some embodiments of the backup power method, the CXL memory information with the received dumped memory data is processed by the CXL SW Board BMC and matched with the CXL memory resource allocation topology established and saved in the CXL SW Board BMC, matching the compute node that uses this memory resource. When all CXL memory resources matched in this compute node topology have completed memory data dumping, hot-plugging of this part of the memory resource is triggered, hot-removing this part of the CXL memory, reducing memory resource power consumption, and further extending the power supply time of the BBU.

[0151] In some embodiments of the backup power method, after the CXL SW Board BMC identifies that all memory resources corresponding to a certain computing node in the topology have completed memory data dumping, it sends this part of the memory information to the DIMM Board BMC through the network, and then informs the eFuse device corresponding to this part of the memory through I2C to cut off the power to this part of the memory resources.

[0152] In some embodiments of the power backup method, the CXL SW Board BMC sends a Redfish command over the network to the corresponding Host compute node BMC, controlling the CPU of that compute node to shut down. This enables unit power-off in memory pooled resource appliance scenarios, further reducing the overall power consumption of the machine in BBU backup power module scenarios, further extending the power supply time of the BBU, and thus preserving more memory data without loss.

[0153] Referring to Figure 7, a schematic diagram of a power backup device provided in some embodiments of this application is shown. This device is applied to a baseboard management controller in an interconnect switching board of a memory resource integrated machine. The memory resource integrated machine includes an interconnect switching board, a power module, and a power backup module. The device includes:

[0154] The confirmation module 301 is used to obtain the power supply fault status corresponding to the memory resource all-in-one machine;

[0155] The first execution module 302 is used to control the backup power module to supply power to the memory resource all-in-one machine based on the external power failure signal sent by the complex programmable logic device in the interconnection switching board if the power failure state is the first power failure state, and to execute the memory resource dumping strategy.

[0156] The second execution module 303 is used to execute a memory pre-dump strategy if the power supply failure state is the second power supply failure state, and to control the backup power module to supply power to the memory resource all-in-one machine when the power supply module is detected to be in a power loss state, and to execute a memory resource dump strategy.

[0157] Some embodiments of this application provide a backup power device that intelligently monitors power supply failure status through a first baseboard management controller in the interconnect switching board, and flexibly adjusts the backup power strategy according to different failure statuses (first or second power supply failure status). In the event of a mains power outage or loss of power supply from the power module, the backup power module can quickly intervene to ensure continuous power supply to the memory resource integrated machine, while executing a memory resource dumping strategy or a pre-dumping strategy, effectively preventing data loss, ensuring stable system operation, and significantly improving system reliability and data security.

[0158] Some embodiments of this application also provide a communication device, as shown in FIG8, including a processor 401, a communication interface 402, a memory 403, and a communication bus 404, wherein the processor 401, the communication interface 402, and the memory 403 communicate with each other through the communication bus 404.

[0159] Memory 403 is used to store computer programs;

[0160] When the processor 401 executes the program stored in the memory 403, it can implement the above-mentioned backup power method.

[0161] The memory and processor are connected via a bus, which can include any number of interconnecting buses and bridges, connecting various circuits of one or more processors and the memory. The bus can also connect various other circuits, such as peripheral devices, voltage regulators, and power management circuits, which are well known in the art and therefore will not be described further herein. The bus interface provides an interface between the bus and the transceiver. The transceiver can be a single element or multiple elements, such as multiple receivers and transmitters, providing a unit for communicating with various other devices over a transmission medium. Data processed by the processor can be transmitted over a wired medium or wirelessly via an antenna, which further receives and transmits data to the processor. The processor manages the bus and general processing, and can also provide various functions, including timing, peripheral interface, voltage regulation, power management, and other control functions. The memory can be used to store data used by the processor during operation.

[0162] The communication bus mentioned above can be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. This communication bus can be divided into address bus, data bus, control bus, etc. For ease of illustration, only one thick line is used to represent it in the diagram, but this does not mean that there is only one bus or one type of bus.

[0163] The communication interface is used for communication between the aforementioned terminal and other devices.

[0164] The memory may include random access memory (RAM) or non-volatile memory, such as at least one disk storage device. Optionally, the memory may also be at least one storage device located remotely from the aforementioned processor.

[0165] The processors mentioned above can be general-purpose processors, including central processing units (CPUs), network processors (NPs), etc.; they can also be digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components.

[0166] In some embodiments provided in this application, as shown in FIG9, a non-volatile readable storage medium 90 is also provided, which stores instructions 910 that, when run on a computer, cause the computer to execute any of the power backup methods in the above embodiments.

[0167] In some embodiments provided in this application, as shown in FIG10, a computer program product 100 including instructions 1010 is also provided, which, when run on a computer, causes the computer to perform any of the backup power methods described above.

[0168] In the above embodiments, implementation can be achieved, in whole or in part, through software, hardware, firmware, or any combination thereof. When implemented in software, it can be implemented, in whole or in part, as a computer program product. A computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions according to some embodiments of this application are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a non-volatile readable storage medium or transmitted from one non-volatile readable storage medium to another. For example, computer instructions can be transmitted from one website, computer, server, or data center to another via wired (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that integrates one or more available media. The available media can be magnetic media (e.g., floppy disks, hard disks, magnetic tapes), optical media (e.g., DVDs), or semiconductor media (e.g., solid state disks (SSDs)).

[0169] In this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, without necessarily requiring or implying any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes the element.

[0170] The various embodiments in this specification are described in a related manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, the system embodiments are basically similar to the method embodiments, so the description is relatively simple; relevant parts can be referred to the descriptions of the method embodiments.

[0171] The above are merely preferred embodiments of this application and are not intended to limit the scope of protection of this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application are included within the scope of protection of this application.

Claims

1. A backup power system, characterized in that, The backup power system includes a memory resource integrated machine, which includes an interconnect switching board, a compute node board, a memory resource board, a power supply module, and a backup power module; the interconnect switching board includes a first baseboard management controller and an interconnect switching chip; the interconnect switching chip is used to connect the compute nodes in the compute node board and the memory modules in the memory resource board; The first baseboard management controller is used to obtain the power supply fault status corresponding to the memory resource integrated machine; if the power supply fault status is the first power supply fault status, it controls the backup power module to supply power to the memory resource integrated machine based on the external power supply failure signal sent by the complex programmable logic device in the interconnect switching board, and executes the memory resource dumping strategy. If the power supply failure state is the second power supply failure state, then the memory pre-dump strategy is executed, and if the power module is detected to be in a power loss state, the backup power module is controlled to supply power to the memory resource all-in-one machine, and the memory resource dump strategy is executed.

2. The system according to claim 1, characterized in that, The backup power system also includes a network switching chip board; The compute node board, the memory resource board, and the interconnect switching board are connected via the network switching chip board.

3. The system according to claim 2, characterized in that, The computing node board, the interconnect switching board, and the memory resource board are connected according to a preset topology.

4. The system according to claim 3, characterized in that, The preset topology connection method includes the upstream port of the interconnect switching chip connected to the computing node board and the downstream port connected to the memory resource board. The upstream and downstream interconnection relationship of the interconnect switching chip and the memory resource slicing management are configured by the management computing node. The first baseboard management controller of the interconnect switching board interacts with the management computing node through the network preset interface to obtain the downstream port corresponding to the memory resource of the upstream computing node of the interconnect switching chip of the interconnect switching board and form the connection topology of computing resources and memory resources.

5. The system according to claim 1, characterized in that, The interconnect switching board includes a management computing node and a first baseboard management controller; The management computing node is used to control the interconnect switching chip to manage and configure memory resource information; The first baseboard management controller is connected to the management computing node through a preset network, and the first baseboard management controller is used to interact with the management computing node to obtain the memory resource information.

6. The system according to claim 1, characterized in that, The memory resource board includes a memory controller, a second baseboard management controller, and a memory module; The memory controller is used to connect to the interconnect switching board through a preset interface, monitor and manage memory resource information, and transfer the interconnect switching bus of the memory module to the interconnect switching chip in the interconnect switching board, so that the computing node board can use the memory resource information corresponding to the memory module; The second baseboard management controller is connected to the memory controller via a preset bus. The second baseboard management controller is used to monitor and manage interconnected switching memory and to control the power-on and power-off of the memory modules in each of the memory controllers.

7. A power backup method, characterized in that, A first baseboard management controller is applied in an interconnect switching board in a backup power system. The backup power system includes a memory resource integrated machine, which includes the interconnect switching board, a compute node board, a memory resource board, a power supply module, and a backup power module. The interconnect switching board includes a first baseboard management controller and an interconnect switching chip. The interconnect switching chip is used to connect the compute nodes in the compute node board and the memory modules in the memory resource board, and the method includes: Obtain the power supply fault status corresponding to the memory resource all-in-one machine; If the power supply failure state is the first power supply failure state, then the backup power module is controlled to supply power to the memory resource all-in-one machine based on the external power supply failure signal sent by the complex programmable logic device in the interconnect switching board, and the memory resource dumping strategy is executed. If the power supply failure state is the second power supply failure state, then the memory pre-dump strategy is executed, and if the power module is detected to be in a power loss state, the backup power module is controlled to supply power to the memory resource all-in-one machine, and the memory resource dump strategy is executed.

8. The method according to claim 7, characterized in that, The power supply fault status corresponding to the memory resource all-in-one machine includes: Upon receiving an external power failure signal from a complex programmable logic device in the interconnect switching board, the power supply failure state is determined to be the first power supply failure state. If the power module is detected to be in a fault state, the power supply fault state is determined to be a second power supply fault state.

9. The method according to claim 8, characterized in that, The external power supply failure signal is generated when the complex programmable logic device in the interconnect switching board identifies that the voltage corresponding to the external power supply board is lower than a preset voltage.

10. The method according to claim 8, characterized in that, The step of determining the power supply failure state as a second power supply failure state when the power module is detected to be in a fault state includes: The power status of the power module is monitored via power management bus commands. Based on the power status, determine whether the power module is in a fault state; If the power module is detected to be in a fault state, the power supply fault state is determined to be a second power supply fault state. The fault state includes at least one of the following: the power module is in a state of power redundancy loss, the output voltage of the power module is in an abnormal state, the output current of the power module is in an abnormal state, and the power module is in an AC power interruption state.

11. The method according to claim 7, characterized in that, The execution memory pre-dump strategy includes: Send power module fault warning information to the computing nodes in the computing node board, and transfer the memory data corresponding to the computing nodes to a preset non-volatile storage device.

12. The method according to claim 11, characterized in that, The step of controlling the backup power module to supply power to the memory resource all-in-one machine when the power module is detected to be in a power loss state includes: If the execution of the memory pre-dumping strategy is detected and the power module is in a power loss state, the backup power module is controlled to supply power to the memory resource all-in-one machine.

13. The method according to claim 7, characterized in that, The execution memory resource dumping strategy includes: Obtain first target memory data, wherein the target memory data is in a dump completed state; perform hot removal processing on the first target memory data.

14. The method according to claim 13, characterized in that, The hot removal process for the first target memory data includes: Determine the first target computing node corresponding to the first target memory data based on the first target memory data; Power off the first target computing node.

15. The method according to claim 7, characterized in that, The execution memory resource dumping strategy includes: Acquire second target memory data, wherein the second target memory data is in an uncompleted dump state; The second target memory data is transferred to the corresponding preset non-volatile storage device.

16. The method according to claim 15, characterized in that, The method of controlling the backup power module to supply power to the memory resource all-in-one machine based on the external power failure signal sent by the complex programmable logic device in the interconnect switching board includes: Receive an external power supply failure signal sent by a complex programmable logic device in an interconnect switching board, wherein the external power supply failure signal is generated based on the mains power supply board voltage being lower than a threshold voltage; The power supply signal is sent to the backup power module according to the external power supply failure signal, so that the backup power module can supply power to the memory resource all-in-one machine.

17. The method according to claim 16, characterized in that, After the step of sending a power supply signal to the backup power module according to the external power supply failure signal, so that the backup power module supplies power to the memory resource all-in-one machine, the method includes: A power consumption limit signal is sent to the third baseboard management controller corresponding to the computing node in each computing node board.

18. A backup power device, characterized in that, A first baseboard management controller is applied in an interconnect switching board in a backup power system. The backup power system includes a memory resource integrated machine, which includes the interconnect switching board, a compute node board, a memory resource board, a power supply module, and a backup power module. The interconnect switching board includes a first baseboard management controller and an interconnect switching chip. The interconnect switching chip is used to connect the compute nodes in the compute node board and the memory modules in the memory resource board. The device includes: The acquisition module is used to acquire the power supply fault status corresponding to the memory resource all-in-one machine; The first execution module is configured to, if the power supply failure state is the first power supply failure state, control the backup power module to supply power to the memory resource all-in-one machine based on the external power supply failure signal sent by the complex programmable logic device in the interconnect switching board, and execute the memory resource dumping strategy. The second execution module is configured to execute a memory pre-dumping strategy if the power supply failure state is a second power supply failure state, and control the backup power module to supply power to the memory resource all-in-one machine when the power module is detected to be in a power loss state, and execute a memory resource dumping strategy.

19. An electronic device, characterized in that, include: processor; Memory used to store the processor's executable instructions; The processor is configured to execute the instructions to implement the power backup method as described in any one of claims 7-17.

20. A non-volatile readable storage medium for storing a program, characterized in that, When the program is executed by the processor, it implements the backup power method as described in any one of claims 7-17.

21. A computer program product, comprising a computer program / instructions, characterized in that, When the computer program / instructions are executed by the processor, they implement the power backup method as described in any one of claims 7-17.

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