Display substrate and display apparatus

Abstract

A display substrate and a manufacturing method therefor, and a display apparatus are disclosed. The display substrate comprises: a base substrate; a plurality of light-emitting devices disposed on the substrate; a first light-shielding layer, which is located on a side of the plurality of light-emitting devices away from the substrate, the first light-shielding layer having a plurality of first light-transmitting openings; an organic spacer layer, which is located on a side of the first light-shielding layer away from the substrate and is provided with a first via, the organic spacer layer comprising a plurality of organic spacer sub-layers sequentially arranged in a direction away from the substrate, an organic spacer sub-layer having a first side surface facing the first via, and, between two adjacent organic spacer sub-layers, the one farther away from the substrate covering a first side surface of the one closer to the substrate; a touch connection line, which is located on a side of the plurality of light-emitting devices close to the substrate; and a touch signal line, which is located on a side of the organic spacer layer away from the substrate, the touch signal line being electrically connected to the touch connection line by means of the first via.

Description

Display substrate and display device TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of display, in particular to a display substrate and a display device. BACKGROUND

[0002] With the increasing application of display technology, people will like to share information with others, but in special cases, they also hope to have privacy. For example, when dealing with company confidential information, the information does not want to be seen by others nearby; for example, when entering personal information on a mobile phone, personal information does not want to be seen by others, therefore, the sharing and privacy switching of display will gradually form a functional trend. SUMMARY

[0003] The present disclosure provides a display substrate and a display device.

[0004] In a first aspect, the present disclosure provides a display substrate having a plurality of pixel regions, the pixel regions comprising shared sub-pixel regions and anti-peeping sub-pixel regions; the display substrate comprising:

[0005] a substrate;

[0006] a plurality of light emitting devices disposed on the substrate, wherein the shared sub-pixel regions and the anti-peeping sub-pixel regions are each provided with the light emitting devices;

[0007] a first light shielding layer located on a side of the plurality of light emitting devices away from the substrate, the first light shielding layer having a plurality of first light transmission openings; the orthographic projection of each of the light emitting devices on the substrate overlaps the orthographic projection of the first light transmission opening on the substrate;

[0008] an organic spacer layer located on a side of the first light shielding layer away from the substrate, and provided with a first via hole; the organic spacer layer comprises a plurality of organic spacer sub-layers disposed in sequence in a direction away from the substrate, the organic spacer sub-layers having a first side surface facing the first via hole; in adjacent two layers of the organic spacer sub-layers, the one away from the substrate covers the first side surface of the one close to the substrate;

[0009] a touch connection line located on a side of the plurality of light emitting devices close to the substrate;

[0010] a touch signal line located on a side of the organic spacer layer away from the substrate, the touch signal line being electrically connected to the touch connection line through the first via hole.

[0011] In some embodiments, on the first side surface of the organic spacer sub-layer farthest from the substrate, the angle between the tangent plane at each position and the plane in which the substrate lies is less than or equal to 30°.

[0012] In some embodiments, in two adjacent organic spacer sublayers, the slope angle of the first side of the one farther from the substrate is less than or equal to the slope angle of the first side of the one closer to the substrate;

[0013] Wherein, the slope angle of the first side is the maximum value of the angle between the cross-section at each position on the first side and the plane where the substrate is located.

[0014] In some embodiments, the pixel regions are arranged in an array, and in the same pixel region, the privacy sub-pixels and the shared sub-pixel regions are arranged along the column direction. The privacy sub-pixels include a plurality of privacy pixel portions arranged along the row direction, and each privacy pixel portion is provided with the light-emitting device.

[0015] In the same row, the spacing between two adjacent shared sub-pixels does not overlap with the orthographic projection of the first light-shielding layer on the substrate; each privacy pixel corresponds to one first light-transmitting port, different privacy pixel corresponds to different first light-transmitting ports, and the orthographic projection of each privacy pixel on the substrate overlaps with the orthographic projection of the corresponding first light-transmitting port on the substrate.

[0016] In some embodiments, the display substrate further includes: a second light-shielding layer, wherein the second light-shielding layer is located on the side of the layer containing the touch signal line away from the substrate;

[0017] The second light-shielding layer has multiple second light-transmitting openings, and the orthographic projection of each second light-transmitting opening on the substrate overlaps with the orthographic projection of at least one first light-transmitting opening on the substrate.

[0018] In some embodiments, the display substrate further includes:

[0019] A touch-sensitive insulating layer is located on the side of the organic spacer layer away from the substrate;

[0020] A touch electrode layer is located on the side of the organic spacer layer away from the substrate, and includes a plurality of touch driving electrodes and a plurality of touch sensing electrodes. The touch driving electrodes and touch sensing electrodes are arranged intersectingly, and the intersection of the touch driving electrodes and the touch sensing electrodes is insulated and separated by the touch insulating layer. Each touch driving electrode and each touch sensing electrode is connected to a touch signal line.

[0021] The touch signal line is disposed on the same layer as at least a portion of the touch driving electrode.

[0022] In some embodiments, the thickness of the organic spacer layer is greater than or equal to 6 micrometers.

[0023] In some embodiments, the organic spacer layer includes 2 to 5 organic spacer sublayers.

[0024] In some embodiments, the display substrate further includes a buffer layer located between the organic spacer layer and the layer containing the touch signal line. The buffer layer includes a first buffer portion covering the side of the first via. The first buffer portion includes a first buffer surface and a second buffer surface facing each other. The first buffer surface is in contact with the side of the first via, and the second buffer surface is conformal to the first buffer surface.

[0025] Wherein, at least a portion of the orthogonal projection of the first via on the substrate lies outside the orthogonal projection of the buffer layer on the substrate.

[0026] In a second aspect, this disclosure provides a display substrate having multiple pixel regions, the pixel regions including shared sub-pixel regions and privacy-protecting sub-pixel regions; the display substrate includes:

[0027] Substrate;

[0028] Multiple light-emitting devices are disposed on the substrate, wherein both the shared sub-pixel area and the privacy-protecting sub-pixel area are provided with the light-emitting devices;

[0029] A first light-shielding layer is located on the side of the plurality of light-emitting devices away from the substrate. The first light-shielding layer has a plurality of first light-transmitting openings. The orthographic projection of each of the light-emitting devices on the substrate overlaps with the orthographic projection of the first light-transmitting opening on the substrate.

[0030] An organic spacer layer is located on the side of the first light-shielding layer away from the substrate and has a first via. The organic spacer layer includes a first surface facing the substrate, a second surface away from the substrate, and a second side surface connected between the first surface and the second surface and facing the first via. The second side surface is a stepped surface.

[0031] The touch connection line is located on the side of the plurality of light-emitting devices closer to the substrate;

[0032] The touch signal line is located on the side of the organic spacer layer away from the substrate, and the touch signal line is electrically connected to the touch connection line through the first via.

[0033] In some embodiments, the second side surface includes a plurality of sub-surfaces sequentially disposed along a direction away from the substrate, the sub-surfaces being arc-shaped surfaces protruding toward the first via, and the plurality of sub-surfaces being connected sequentially to form the stepped surface.

[0034] In some embodiments, the angle between the cut surface at each position on the sub-surface and the plane where the substrate is located is less than or equal to 30°.

[0035] In some embodiments, in two adjacent sub-faces, the slope angle of the sub-face closer to the substrate is greater than or equal to the slope angle of the sub-face farther from the substrate; the slope angle of the sub-face is the maximum value of the angle between the tangent at each position on the sub-face and the plane containing the substrate.

[0036] In some embodiments, in two adjacent sub-faces, the dimension of the one closer to the substrate in the substrate thickness direction is greater than or equal to the dimension of the one farther from the substrate in the substrate thickness direction.

[0037] In some embodiments, the pixel regions are arranged in an array, and in the same pixel region, the privacy sub-pixels and the shared sub-pixel regions are arranged along the column direction. The privacy sub-pixels include a plurality of privacy pixel portions arranged along the row direction, and each privacy pixel portion is provided with the light-emitting device.

[0038] In the same row, the spacing between two adjacent shared sub-pixels does not overlap with the orthographic projection of the first light-shielding layer on the substrate; each privacy pixel corresponds to one first light-transmitting port, different privacy pixel corresponds to different first light-transmitting ports, and the orthographic projection of each privacy pixel on the substrate overlaps with the orthographic projection of the corresponding first light-transmitting port on the substrate.

[0039] In some embodiments, the display substrate further includes: a second light-shielding layer, wherein the second light-shielding layer is located on the side of the layer containing the touch signal line away from the substrate;

[0040] The second light-shielding layer has multiple second light-transmitting openings, and the orthographic projection of each second light-transmitting opening on the substrate overlaps with the orthographic projection of at least one first light-transmitting opening on the substrate.

[0041] In some embodiments, the display substrate further includes:

[0042] A touch-sensitive insulating layer is located on the side of the organic spacer layer away from the substrate;

[0043] A touch electrode layer is located on the side of the organic spacer layer away from the substrate, and includes a plurality of touch driving electrodes and a plurality of touch sensing electrodes. The touch driving electrodes and touch sensing electrodes are arranged intersectingly, and the intersection of the touch driving electrodes and the touch sensing electrodes is insulated and separated by the touch insulating layer. Each touch driving electrode and each touch sensing electrode is connected to a touch signal line.

[0044] The touch signal line is disposed on the same layer as at least a portion of the touch driving electrode.

[0045] In some embodiments, the thickness of the organic spacer layer is greater than or equal to 6 micrometers.

[0046] In some embodiments, the display substrate further includes a buffer layer located between the organic spacer layer and the layer containing the touch signal line. The buffer layer includes a first buffer portion covering the side of the first via. The first buffer portion includes a first buffer surface and a second buffer surface facing each other. The first buffer surface is in contact with the side of the first via, and the second buffer surface is conformal to the first buffer surface.

[0047] Wherein, at least a portion of the orthogonal projection of the first via on the substrate lies outside the orthogonal projection of the buffer layer on the substrate.

[0048] Thirdly, this disclosure provides a display device including the display substrate described above. Attached Figure Description

[0049] The accompanying drawings are provided to further illustrate the present disclosure and form part of the specification. They are used together with the following detailed description to explain the present disclosure, but do not constitute a limitation thereof. In the drawings:

[0050] Figure 1A is a plan view of a display substrate provided in some embodiments.

[0051] Figure 1B is a schematic diagram of the film layers of the display substrate provided in some embodiments.

[0052] Figure 1C is a schematic diagram showing the correspondence between the first light-shielding layer and the shared sub-pixels and privacy sub-pixels provided in some embodiments.

[0053] Figure 2 is a schematic diagram of the connection between the touch signal line and the touch connection line provided in some embodiments.

[0054] Figure 3 is a plan view of a display substrate provided in some embodiments of this disclosure.

[0055] Figure 4A is a schematic diagram of the film layer structure of a display substrate provided in some embodiments of this disclosure.

[0056] Figure 4B is a schematic diagram of the film layer structure of a display substrate provided in some other embodiments of this disclosure.

[0057] Figure 4C is a schematic diagram of the film structure of a display substrate provided in some embodiments of the present disclosure.

[0058] Figure 5 is a plan view of the first light-shielding layer provided in some embodiments of this disclosure.

[0059] Figure 6 is a plan view of the second light-shielding layer provided in some embodiments of this disclosure.

[0060] Figure 7 is an enlarged view of region Q in Figure 3 provided in some embodiments of this disclosure.

[0061] Figure 8A is a cross-sectional view along line A-A' in Figure 7.

[0062] Figure 8B is a schematic diagram showing the positional relationship of the organic spacer layer, the barrier, and the organic encapsulation layer provided in some embodiments of this disclosure.

[0063] Figure 9A is a schematic diagram of the organic spacer layer and touch connection line in Figure 8A.

[0064] Figure 9B is a schematic diagram of multiple cross-sections on the first side of the organic spacer sublayer furthest from the substrate SUB in Figure 9A.

[0065] Figure 9C is a schematic cross-sectional view of each organic spacer sublayer in Figure 9A.

[0066] Figure 10 is a cross-sectional view along line C-C' in Figure 3.

[0067] Figure 11 is a schematic diagram of the execution process of step S141 provided in some embodiments of this disclosure.

[0068] Figure 12A shows the morphology of the organic material layer at the boundary of the first mask region of the mask plate and the energy curve at the boundary of the first mask region.

[0069] Figure 12B shows the light energy distribution in the first mask area.

[0070] Figure 13 is a schematic diagram of the film layers of a display substrate provided in some other embodiments of this disclosure.

[0071] Figure 14 is a cross-sectional view of a display substrate provided in some other embodiments of this disclosure along line A-A' in Figure 7.

[0072] Figure 15A is a schematic diagram of the morphology of a part of the structure in Figure 14.

[0073] Figure 15B is a schematic diagram of another morphology of some of the structures in Figure 14.

[0074] Figure 15C is another schematic diagram of the morphology of some of the structures in Figure 14.

[0075] Figure 15D is a schematic diagram of the slope angle of each sub-face in Figure 14.

[0076] Figure 16 is another cross-sectional view of the display substrate provided in some other embodiments of this disclosure along line A-A' in Figure 7.

[0077] Figure 17 is a partial structural diagram of Figure 16.

[0078] Figure 18 is a schematic diagram showing the position of the mask plate during the preparation of the organic spacer layer provided in some other embodiments of this disclosure.

[0079] Figure 19 shows the light energy curve transmitted through a semi-transparent membrane with slits. Detailed Implementation

[0080] The specific embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are for illustration and explanation only and are not intended to limit this disclosure.

[0081] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0082] Unless otherwise defined, the technical or scientific terms used in the embodiments of this disclosure should have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms "first," "second," and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, terms such as "comprising" or "including" mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as "connected" or "linked" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as "upper," "lower," "left," and "right" are used only to indicate relative positional relationships; when the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0083] As used herein, “parallel” and “perpendicular” include the described situation and situations that are similar to the described situation, within an acceptable range of deviation, which is determined by those skilled in the art taking into account the measurement under discussion and the error associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, “parallel” includes absolute parallelism and approximate parallelism, where an acceptable range of deviation for approximate parallelism may be, for example, within 5°; “perpendicular” includes absolute perpendicularity and approximate perpendicularity, where an acceptable range of deviation for approximate perpendicularity may also be, for example, within 5°.

[0084] It should be understood that when a layer or element is referred to as being on another layer or substrate, it can mean that the layer or element is directly on the other layer or substrate, or that there is an intermediate layer between the layer or element and the other layer or substrate.

[0085] This document describes exemplary embodiments with reference to sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and regions is enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Therefore, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. Thus, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0086] Figure 1A is a plan view of a display substrate provided in some embodiments, Figure 1B is a schematic diagram of the film layers of a display substrate provided in some embodiments, and Figure 2 is a schematic diagram of the connection between a touch signal line TL and a touch connection line 20 provided in some embodiments. As shown in Figures 1A and 2, the display substrate has a display area DA, a peripheral area PA surrounding the display area DA, and a pad area WA located on the side of the peripheral area PA away from the display area DA. The pad area WA is provided with multiple bonding pads PAD. The display area DA includes multiple pixel areas, and the pixel areas include a shared sub-pixel area SD and a privacy sub-pixel area PD. The display substrate includes a driving backplane 100, which may include a substrate SUB and a driving circuit layer 110 disposed on the substrate SUB. The driving circuit layer 110 includes a pixel driving circuit, and the pixel driving circuit includes multiple transistors. The display substrate also includes multiple light-emitting devices 50 disposed on the side of the driving circuit layer 110 away from the substrate SUB and a pixel defining layer PDL, wherein the shared sub-pixel area SD and the privacy sub-pixel area PD are both provided with light-emitting devices 50. The pixel defining layer (PDL) has multiple pixel openings, each corresponding to a light-emitting device (LED) 50. An encapsulation layer (EPL) is also provided on the side of the LEDs 50 away from the substrate (SUB), which encapsulates the LEDs 50. A first light-shielding layer (BM1) is provided on the side of the encapsulation layer (EPL) away from the substrate (SUB). The first light-shielding layer (BM1) has multiple first light-transmitting openings (OP1), and the orthographic projection of each LED 50 onto the substrate (SUB) overlaps with the orthographic projection of each first light-transmitting opening (OP1) onto the substrate (SUB).

[0087] Figure 1C is a schematic diagram showing the correspondence between the first light-shielding layer and the shared sub-pixels and privacy sub-pixels provided in some embodiments, wherein Figure 1B is a cross-sectional view of the display substrate corresponding to the position of the F-F' section line in Figure 1C. As shown in Figure 1C, the pixel areas P are arranged in an array. In the same pixel area P, the shared sub-pixel area SD is located on one side of the privacy sub-pixel PD, and the shared sub-pixel area SD and the privacy sub-pixel PD are arranged along the column direction. The privacy sub-pixel PD may include a plurality of privacy pixel portions P-D1 arranged along the row direction, or the privacy sub-pixel PD may include a plurality of privacy pixel portions P-D1 arranged along the column direction; or the privacy sub-pixel PD may include a plurality of privacy pixel portions P-D1 arranged in an array. The orthographic projection shape of the privacy pixel portion P-D1 on the substrate SUB can be a rectangle, square, rhombus, circle, ellipse or other shapes. Each privacy pixel portion P-D1 is provided with a light-emitting device 50. Figure 1C illustrates an example where the privacy sub-pixel PD includes two privacy pixel portions P-D1. In a privacy-protected sub-pixel PD comprising multiple privacy-protected pixel units P-D1, the multiple light-emitting devices 50 within the same privacy-protected sub-pixel PD can be controlled by the same pixel driving circuit. Therefore, in the same privacy-protected sub-pixel PD, the first electrodes of the multiple light-emitting devices 50 of the multiple privacy-protected pixel units P-D1 can be connected into a single structure. Furthermore, in the same privacy-protected sub-pixel PD, the light-emitting layers of the multiple light-emitting devices 50 of the multiple privacy-protected pixel units P-D1 are also connected into a single structure, thereby reducing the precision requirements during the fabrication of the first electrode and the light-emitting layer. The first electrodes of the light-emitting devices 50 in the privacy-protected sub-pixel PD are spaced apart from the first electrodes of the light-emitting devices 50 in the shared sub-pixel SD.

[0088] It should be noted that, in other embodiments, in the same privacy pixel PD, the first electrodes of the multiple light-emitting devices 50 of the multiple privacy pixel P-D1 can also be separated from each other, and the light-emitting layers of the multiple light-emitting devices 50 of the multiple privacy pixel P-D1 can also be separated.

[0089] As shown in Figure 1C, the gap between two adjacent shared sub-pixels SD in the same row does not overlap with the orthographic projection of the first light-shielding layer BM1 onto the substrate SUB. Each privacy pixel P-D1 corresponds to a first light-transmitting opening OP1, and different privacy pixel P-D1s correspond to different first light-transmitting openings OP1. The orthographic projection of the privacy pixel P-D1 onto the substrate SUB overlaps with the orthographic projection of the corresponding first light-transmitting opening OP1 onto the substrate SUB. In short, the shared sub-pixel SD has a first light-shielding layer BM1 on both sides, while the privacy pixel P-D1 has a first light-shielding layer BM1 around its perimeter. For a single pixel area, this is equivalent to dividing the layer containing the first electrode, thus obtaining the shared sub-pixel SD and the privacy sub-pixel PD. In this case, when the display substrate is in the shared display mode, the light-emitting device 50 in the shared sub-pixel area SD emits light, and the large-angle light emitted by the light-emitting device 50 to the left and right sides will not be blocked by the first light-shielding layer BM1; when the display substrate is in the privacy display mode, the light-emitting device 50 in the privacy sub-pixel area PD emits light, and the first light-shielding layer BM1 blocks the large-angle light of the light-emitting device 50.

[0090] As shown in Figure 1B, an organic spacer layer OC and a buffer layer BFL1 are disposed on the side of the first light-shielding layer BM1 away from the substrate SUB. A touch electrode layer is disposed on the side of the buffer layer BFL1 away from the substrate SUB, and the touch electrode layer is used to detect touch events. The touch electrode layer includes a first touch pattern layer TMA and a second touch pattern layer TMB. A touch insulating layer TLD is disposed between the first touch pattern layer TMA and the second touch pattern layer TMB. A touch protective layer TOC is disposed on the side of the touch electrode layer away from the substrate SUB. The touch electrode layer is electrically connected to the bonding pad PAD via a touch signal line TL, as shown in Figure 1A. At least a portion of the touch signal line TL is located in the peripheral region PA, and it is disposed on the same layer as the second touch pattern layer TMB. As shown in Figure 2, a first via V1 is formed in the organic spacer layer OC, and the first via V1 is located in the peripheral region PA, for example, in region M in Figure 1A. The touch signal line TL is electrically connected to the touch connection line 20 through the first via V1. The touch connection line 20 is electrically connected to the bonding pad PAD, thereby enabling the touch signal to be transmitted between the touch electrode layer and the bonding pad PAD. The touch connection line 20 is located on the side of the layer containing the multiple light-emitting devices 50 closest to the substrate SUB. For example, the touch connection line 20 can be disposed on the same layer as the source and drain of the transistors in the driving circuit layer 110. In this embodiment, "disposed on the same layer" means that multiple structures are formed from the same material layer through the same patterning process, and therefore these structures are in the same layer in terms of stack-up; however, this does not necessarily mean that the distance between these structures and the substrate SUB is the same.

[0091] When the thickness of the organic spacer layer OC is large, it will result in a steeper slope on the side of the first via V1, which will cause the touch connection line 20 to have a larger climbing angle and is prone to breakage at the location of the first via V1.

[0092] Figure 3 is a planar schematic diagram of a display substrate provided in some embodiments of this disclosure. As shown in Figure 3, the display substrate has a display area DA, a peripheral area PA, and a pad area WA located on the side of the peripheral area PA away from the display area DA. The display area DA can be provided with components for displaying images, such as pixel circuits, scan lines, data lines, light-emitting devices 50, etc. Additionally, a touch electrode layer can be provided in the display area DA to realize touch functionality. The pad area WA includes multiple bonding pads PAD, each configured to electrically connect to a signal line extending from the display area DA or the peripheral area PA. For example, a data line can be connected to a bonding pad PAD via a data connection line. The bonding pads PAD can be exposed on the surface of the pad area WA, i.e., not covered by any layer, which facilitates electrical connection to a flexible printed circuit board (FPCB). The flexible printed circuit board (FPCB) is electrically connected to an external controller and configured to transmit signals from the external controller. The bonding pads PAD are electrically connected to each signal line, thereby enabling communication between the signal lines and the flexible printed circuit board. It should be understood that the number and arrangement of the bonding pads in Figure 3 are for illustrative purposes only and do not constitute a limitation on the bonding pads.

[0093] Figure 4A is a schematic diagram of the film structure of a display substrate provided in some embodiments of this disclosure. Figure 5 is a plan view of a first light-shielding layer provided in some embodiments of this disclosure. Figure 6 is a plan view of a second light-shielding layer provided in some embodiments of this disclosure. Referring to Figures 2 to 5, the display substrate has a display area DA and a peripheral area PA located around the display area DA. The peripheral area PA includes a bonding area located on one side of the display area DA. The display area DA includes multiple pixel areas, each pixel area including multiple sub-pixel areas. These sub-pixel areas may include, for example, a shared sub-pixel area SD and a privacy sub-pixel area PD. The display substrate includes a substrate SUB, and disposed on the substrate SUB: multiple light-emitting devices 50, a first light-shielding layer BM1, an organic spacer layer OC, a touch connection line 20, and a touch signal line TL.

[0094] Both the shared sub-pixel area SD and the privacy sub-pixel area PD are equipped with light-emitting devices 50. The first light-shielding layer BM1 is located on the side of the multiple light-emitting devices 50 away from the substrate SUB, and the first light-shielding layer BM1 has multiple first light-transmitting openings OP1; the orthographic projection of each light-emitting device 50 on the substrate SUB overlaps with the orthographic projection of the first light-transmitting opening OP1 on the substrate SUB.

[0095] Figure 7 is an enlarged view of region Q in Figure 3 provided in some embodiments of this disclosure. Region Q is located in the peripheral region PA, and a first via V1 is provided in region Q, as described below. Figure 8A is a cross-sectional view along line A-A' in Figure 7. Figure 9A is a schematic diagram of the organic spacer layer OC and the touch connection line 20 in Figure 8A. Figure 9B is a schematic diagram of multiple cross-sections on the first side of the organic spacer sublayer furthest from the substrate SUB in Figure 9A. Figure 9C is a schematic diagram of cross-sections of each organic spacer sublayer in Figure 9A. As shown in Figures 3, 4A, 7 to 9C, the organic spacer layer OC is located on the side of the first light-shielding layer BM1 furthest from the substrate SUB, and a first via V1 is provided therein. The organic spacer layer OC includes multiple organic spacer sublayers OC1 arranged sequentially in a direction furthest from the substrate SUB. Each organic spacer sublayer OC1 has a first side SL1 facing the first via V1.

[0096] Touch connection line 20 is located on the side of multiple light-emitting devices 50 closest to the substrate SUB. Touch signal line TL is located on the side of organic spacer layer OC furthest from the substrate SUB, and touch signal line TL is electrically connected to touch connection line 20 through first via V1. A touch electrode layer is provided on the side of multiple light-emitting devices 50 furthest from the substrate SUB, and touch signal line TL is electrically connected to the touch electrode layer.

[0097] In some embodiments, the display substrate further includes a second light-shielding layer BM2, located on the side of the organic spacer layer OC away from the substrate SUB, and having multiple second light-transmitting openings OP2. The orthographic projection of each second light-transmitting opening OP2 onto the substrate SUB overlaps with the orthographic projection of at least one first light-transmitting opening OP1 onto the substrate SUB. By providing the second light-shielding layer BM2, more wide-angle light can be blocked and the viewing angle reduced when the display substrate is in privacy mode. Furthermore, when the thickness of the organic spacer layer OC is greater, the distance between the first light-shielding layer BM1 and the second light-shielding layer BM2 increases accordingly, resulting in better restriction of wide-angle light.

[0098] In this embodiment of the disclosure, the organic spacer layer OC is divided into multiple organic spacer sublayers OC1. In two adjacent organic spacer sublayers OC1, the upper organic spacer sublayer OC1 covers the first side surface SL1 of the lower organic spacer sublayer OC1. Therefore, when preparing the organic spacer layer OC with the first via V1, multiple organic material layers with smaller thicknesses can be formed sequentially. Each organic material layer is patterned to pattern each organic material layer into an organic spacer sublayer OC1 with a via. The via of the topmost organic spacer sublayer OC1 is the first via V1. Except for the topmost organic spacer sublayer OC1, the vias on the other organic spacer sublayers OC1 surround the first via V1. Since the organic spacer layer OC includes multiple organic spacer sublayers OC1 with smaller thicknesses, under the same process capability, the slope of the first side SL1 of each organic spacer sublayer OC1 is relatively gentle. In other words, when the overall thickness of the organic spacer layer OC is large, the embodiments of this disclosure can reduce the ramp angle of the touch signal line TL and reduce the probability of the touch signal line TL breaking, thereby improving the privacy protection effect of the display substrate while preventing the touch effect of the display substrate from being affected.

[0099] In some embodiments, on the first side surface SL1 of the organic spacer sublayer OC1 furthest from the substrate SUB, the angles between the cross-sections at each location (e.g., cross-sections Cp0 and Cp0' in FIG. 9B) and the plane containing the substrate SUB (e.g., angles θ and θ' in FIG. 9B) are all less than or equal to 30°, thereby further reducing the probability of the touch signal line TL breaking. FIG. 9B only schematically shows two cross-sections Cp0 and Cp0' on the first side surface SL1 of the top organic spacer sublayer OC1; the angles between the cross-sections at other locations and the plane containing the substrate SUB also do not exceed 30°, thus reducing the probability of the touch signal line TL breaking at each location on the first side surface SL1 of the top organic spacer sublayer OC1.

[0100] In some embodiments, as shown in FIG9C, the first side surface of each organic spacer sublayer OC1 has a certain slope angle θ, wherein the slope angle of the first side surface SL1 refers to the maximum value of the angle between the cross-section at each position on the first side surface SL1 and the plane where the substrate SUB is located. FIG9C shows the steepest cross-section Cp0 on the first side surface SL1 of each organic spacer sublayer OC1, and the angle between the cross-section Cp0 corresponding to the organic spacer sublayer OC1 and the plane where the substrate SUB is located is taken as the slope angle θ of the organic spacer sublayer OC1. The slope angle θ of each organic spacer sublayer OC1 can be equal, or, in two adjacent organic spacer sublayers OC1, the slope angle θ of the first side surface SL1 of the one farther from the substrate SUB is smaller than the slope angle θ of the first side surface SL1 of the one closer to the substrate SUB, thereby facilitating a smaller slope on the side surface of the finally formed first via V1.

[0101] Figure 10 is a cross-sectional view along line C-C' in Figure 3, and Figure 10 shows the specific structure of a single sub-pixel region in Figure 4A. The display substrate in the embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0102] In some embodiments, the substrate SUB is a flexible substrate, which may be made of a flexible organic material. For example, the organic material is a resin-based material such as polyimide, polycarbonate, polyacrylate, polyetherimide, polyethersulfone, polyethylene terephthalate, and polyethylene naphthalate. The display substrate may also include a curved region BA located between the peripheral region PA and the pad region WA, the curved region BA being configured to bend along a bending axis BX. By bending the curved region BA, the pad region WA can be positioned on the back side of the display substrate (where the display side of the display substrate is the front side, and the side opposite to the display side is the rear side or back side), thereby improving space utilization and reducing the bezel width of the display product.

[0103] In some embodiments, the light-emitting device 50 can be an organic light-emitting diode (OLED), which can emit, for example, red, green, blue, or white light. Pixel circuitry is electrically connected to the light-emitting device 50 and provides driving signals to it. Pixel electrodes may include multiple transistors and at least one capacitor. Only one transistor and one capacitor are illustrated in Figure 10.

[0104] In some embodiments, a semiconductor layer is disposed on a substrate SUB. The material of the semiconductor layer may include, for example, inorganic semiconductor materials (e.g., polycrystalline silicon, amorphous silicon, etc.), organic semiconductor materials, and oxide semiconductor materials. The semiconductor layer includes an active layer 31 for each transistor 30. The active layer 31 includes a channel portion and source and drain connection portions located on opposite sides of the channel portion. The source connection portion is connected to the source 33 of the transistor 30, and the drain connection portion is connected to the drain 34 of the transistor 30. Both the source and drain connection portions may be doped with impurities (e.g., N-type or P-type impurities) with a higher impurity concentration than the channel portion. The channel portion is directly opposite the gate 32 of the transistor 30. When the voltage signal applied to the gate 32 reaches a certain value, a carrier path is formed in the channel portion, turning on the source 33 and drain 34 of the transistor 30.

[0105] In one example, to prevent or reduce the diffusion of metal atoms and / or impurities from the substrate SUB into the active layer of the transistor, a second buffer layer BFL2 can be provided between the semiconductor layer and the substrate SUB.

[0106] In some embodiments, a first gate insulating layer GI1 is disposed on the semiconductor layer, wherein the first gate insulating layer GI1 may expose the upper surface of the substrate SUB located in a portion of the bending region BA to facilitate bending of the substrate SUB. The material of the first gate insulating layer GI1 may include silicon compounds. For example, the material of the first gate insulating layer GI1 includes silicon oxynitride (SiON), silicon oxide (SiOx), silicon nitride (SiNx), silicon carbide (SiOxCy), silicon carbide nitride (SiCxNy), etc. In addition, the first gate insulating layer GI1 may be a single layer or multiple layers.

[0107] In some embodiments, a first gate electrode layer is disposed on a first gate insulating layer GI1. The first gate electrode layer includes the gate 32 of each transistor 30 and the first electrode plate 41 of the capacitor 40. The material of the first gate electrode layer may include, for example, metal, metal alloy, metal nitride, conductive metal oxide, transparent conductive material, etc. For example, the first gate electrode layer may include gold (Au), gold alloys, silver (Ag), silver alloys, aluminum (Al), aluminum alloys, aluminum nitride (AlNx), tungsten (W), tungsten nitride (WNx), copper (Cu), copper alloys, nickel (Ni), chromium (Cr), chromium nitride (CrNx), molybdenum (Mo), molybdenum alloys, titanium (Ti), titanium nitride (TiNx), platinum (Pt), tantalum (Ta), tantalum nitride (TaNx), neodymium (Nd), scandium (Sc), strontium ruthenium oxide (SRO), zinc oxide (ZnOx), tin oxide (SnOx), indium oxide (InOx), gallium oxide (GaOx), indium tin oxide (ITO), indium zinc oxide (IZO), etc. The first gate electrode layer may have a single layer or multiple layers.

[0108] In some embodiments, as shown in FIG10, a second gate insulating layer GI2 is disposed on the first gate electrode layer G1, and the material of the second gate insulating layer GI2 may be selected from the materials of the first gate insulating layer GI1 listed above. The second gate insulating layer GI2 may be formed as a single layer or multiple layers.

[0109] In some embodiments, as shown in FIG10, a second gate electrode layer is disposed on a second gate insulating layer GI2. The second gate electrode layer may include a second electrode plate 42 of the capacitor 40. The material of the second gate electrode layer is selected from the materials of the first gate electrode layer listed above. The second gate electrode layer may have a single layer or multiple layers.

[0110] In some embodiments, as shown in FIG10, an interlayer insulating layer (ILD) is disposed on the second gate electrode layer. The material of the interlayer insulating layer (ILD) may include, for example, silicon compounds, metal oxides, etc. Specifically, silicon compounds and metal oxides listed above can be selected, which will not be elaborated here.

[0111] In some embodiments, as shown in FIG10, a source-drain conductive layer is disposed on the interlayer insulating layer (ILD). The source-drain conductive layer may include the source 33 and drain 34 of each transistor in the display area DA. The source 33 is electrically connected to the source connection portion, and the drain 34 is electrically connected to the drain connection portion. The source-drain conductive layer may include metal, alloy, metal nitride, conductive metal oxide, transparent conductive material, etc. For example, the source-drain conductive layer may be a single layer or multiple layers made of metal, such as Mo / Al / Mo or Ti / Al / Ti. The transistor 30 shown in FIG10 includes a gate 32, a source 33, a drain 34, and an active layer 31.

[0112] In some embodiments, the touch connection line 20 may be located in the source-drain conductive layer, that is, the touch connection line 20 is disposed in the same layer as the source 33 and drain 34 of the transistor.

[0113] In some embodiments, as shown in FIG10, a passivation layer PVX is disposed on a first source / drain conductive layer. The material of the passivation layer PVX may include silicon compounds, such as silicon oxide, silicon nitride, or silicon oxynitride.

[0114] In some embodiments, as shown in FIG10, the planarization layer PLN is located on the side of the passivation layer PVX away from the substrate SUB, and the surface of the planarization layer PLN away from the substrate SUB is substantially flat. The planarization layer PLN is made of an organic insulating material, such as polyimide, epoxy resin, acrylic, polyester, photoresist, polyacrylate, polyamide, siloxane, and other resin-based materials. Another example is that the organic insulating material includes an elastic material, such as urethane, thermoplastic polyurethane (TPU), etc.

[0115] In some embodiments, as shown in FIG10, the first electrode of the light-emitting device 50 is disposed on the side of the planarization layer PLN away from the substrate SUB. The first electrode 51 can be the anode of the light-emitting device 50. As shown in FIG10, the light-emitting element includes a first electrode 51, a light-emitting layer 53, and a second electrode 52, with the first electrode 51 disposed on the planarization layer PLN. The first electrode 51 is electrically connected to the drain 34 of the transistor 30 through a via penetrating the planarization layer PLN. The first electrode 51 can be made of materials such as metal, metal alloy, metal nitride, conductive metal oxide, or transparent conductive material. The first electrode 51 can be a single-layer or multi-layer structure.

[0116] In some embodiments, as shown in FIG10, a pixel defining layer (PDL) is disposed on a planarization layer (PLN). The PDL includes pixel openings corresponding one-to-one with the light-emitting devices 50, each exposing a portion of the corresponding first electrode 51. Light-emitting layers 53 are disposed one-to-one in the pixel openings. The light-emitting layers 53 may include small-molecule organic materials or polymeric organic materials, and may be fluorescent or phosphorescent materials, emitting red, green, blue, or white light. The material of the PDL may include organic insulating materials such as polyimide, polyphthalamide, polyamide, acrylic resin, benzocyclobutene, or phenolic resin.

[0117] In some embodiments, as shown in FIG10, the second electrode 52 is located on the side of the light-emitting layer 53 away from the substrate SUB. The second electrode 52 can be made of metal, metal alloy, metal nitride, conductive metal oxide, transparent conductive material, etc. In this embodiment, the light-emitting device 50 can adopt a top-emitting structure or a bottom-emitting structure. When a top-emitting structure is adopted, the first electrode 51 includes a conductive material with light-reflective properties or includes a light-reflective film, and the second electrode 52 includes a transparent or semi-transparent conductive material. When a bottom-emitting structure is adopted, the second electrode 52 is made of a conductive material with light-reflective properties or includes a light-reflective film, and the first electrode 51 includes a transparent or semi-transparent conductive material. The second electrodes 52 of each light-emitting device 50 can be connected as a whole to form a second electrode layer.

[0118] It should be noted that the light-emitting device 50 may also include other film layers, such as: a hole injection layer and a hole transport layer located between the first electrode 51 and the light-emitting layer 53, and an electron transport layer and an electron injection layer located between the light-emitting layer 53 and the second electrode 52.

[0119] In some embodiments, as shown in FIG10, the display substrate further includes an encapsulation layer EPL. The encapsulation layer EPL is disposed on the side of the plurality of light-emitting devices 50 away from the substrate SUB. The encapsulation layer EPL covers the pixel defining layer PDL and the light-emitting devices 50, and is used to encapsulate the light-emitting devices 50 to prevent moisture and / or oxygen in the external environment from corroding the light-emitting devices 50. In some embodiments, the encapsulation layer EPL includes a first inorganic encapsulation layer CVD1, a second inorganic encapsulation layer CVD2, and an organic encapsulation layer IJP. The second inorganic encapsulation layer CVD2 is located on the side of the first inorganic encapsulation layer CVD1 away from the substrate SUB, and the organic encapsulation layer IJP is located between the first inorganic encapsulation layer CVD1 and the second inorganic encapsulation layer CVD2.

[0120] Optionally, as shown in FIG3, the display substrate may further include barriers located in the peripheral area PA. These barriers may include a first barrier DAM1 and a second barrier DAM2. The first barrier DAM1 surrounds the display area DA, and the second barrier DAM2 surrounds the first barrier DAM1. The arrangement of the first barrier DAM1 and the second barrier DAM2 prevents external moisture or oxygen from entering the display area DA, providing dual protection for the display area DA. In some embodiments, the vertical distance from the end of the first barrier DAM1 away from the substrate SUB to the substrate SUB is less than the vertical distance from the end of the second barrier DAM2 away from the substrate SUB to the substrate SUB, thereby extending the path for external moisture and oxygen to enter the display area DA and improving the barrier's blocking capability. Both the first barrier DAM1 and the second barrier DAM2 may include a barrier layer disposed on the same layer as the planarization layer PLN and a barrier layer disposed on the same layer as the pixel defining layer PDL, to simplify the fabrication process. The first inorganic encapsulation layer CVD1 and the second inorganic encapsulation layer CVD2 extend into the peripheral region PA and cover the barrier; the organic encapsulation layer IJP extends into the peripheral region PA and is located within the area surrounded by the barrier. Both the first inorganic encapsulation layer CVD1 and the second inorganic encapsulation layer CVD2 can be made of highly dense inorganic materials such as silicon oxynitride (SiON), silicon oxide (SiOx), and silicon nitride (SiNx). The organic encapsulation layer IJP can be made of a polymer material containing a desiccant or a polymer material that can block moisture. For example, a polymer resin can be used to relieve stress in the first inorganic encapsulation layer CVD1 and the second inorganic encapsulation layer CVD2, and it can also include a desiccant or other water-absorbing material to absorb water, oxygen, and other substances that penetrate the interior.

[0121] Figure 8B is a schematic diagram of the positional relationship between the organic spacer layer, the barrier, and the organic encapsulation layer provided in some embodiments of this disclosure. Figure 8B corresponds to the E-E' section line in Figure 7. As shown in Figure 8B, in some embodiments, the organic encapsulation layer IJP is located in the area surrounded by the first barrier DAM1, the organic spacer layer OC covers the first barrier DAM1 and the second barrier DAM2, and at least part of the first via V1 is located on the side of the second barrier DAM2 away from the first barrier DAM1 to prevent the first via V1 from affecting the encapsulation effect of the encapsulation layer EPL.

[0122] In some embodiments, as shown in Figures 4A and 10, the first light-shielding layer BM1 is located on the side of the encapsulation layer EPL away from the substrate SUB, and the first light-shielding layer BM1 has a plurality of first light-transmitting holes OP1; the orthographic projection of each light-emitting device 50 on the substrate SUB overlaps with the orthographic projection of the first light-transmitting hole OP1 on the substrate SUB.

[0123] Figure 4A is a cross-sectional view of the display substrate corresponding to the position of the cut line J-J' in Figure 5. As shown in Figures 4A and 5, multiple pixel regions P are arranged in an array. In the same pixel region P, the shared sub-pixel region SD is located on one side of the privacy sub-pixel PD, and the shared sub-pixel region SD and the privacy sub-pixel PD are arranged along the column direction. Each privacy sub-pixel PD may include multiple privacy pixel parts P-D1, and each privacy pixel part P-D1 is provided with a light-emitting device 50. The multiple light-emitting devices 50 in the same privacy sub-pixel PD can be controlled by the same pixel driving circuit. Therefore, the first electrodes 51 of the multiple light-emitting devices 50 in the same privacy sub-pixel PD can be connected into a single structure, and the light-emitting layers 52 of the multiple light-emitting devices 50 in the same privacy sub-pixel PD are also connected into a single structure. The first electrodes 51 of the light-emitting devices 50 in the privacy sub-pixel PD and the first electrodes 51 of the light-emitting devices 50 in the shared sub-pixel SD are spaced apart from each other.

[0124] As shown in Figure 5, the first light-shielding layer BM1 includes multiple first light-shielding strips BM11 extending along the row direction and multiple second light-shielding strips BM12 extending along the column direction. The multiple first light-shielding strips BM11 are arranged along the column direction. First light-shielding strips BM11 are provided on both opposite sides of the shared sub-pixel SD along the column direction (i.e., the top and bottom sides of the shared sub-pixel SD in Figure 5). The first light-shielding strips BM11 on opposite sides of the shared sub-pixel SD are independent of each other, i.e., they are not connected. The gap between two adjacent shared sub-pixels SD in the same row does not overlap with the orthographic projection of the first light-shielding layer BM1 onto the substrate SUB. Furthermore, each privacy pixel P-D1 has second light-shielding strips BM12 on both opposite sides along the row direction (i.e., the left and right sides of the privacy pixel P-D1 in Figure 5), and first light-shielding strips BM11 on both opposite sides along the column direction. A row of shared sub-pixels SD and an adjacent row of privacy sub-pixels PD are separated by first light-shielding strips BM11. Each privacy pixel P-D1 corresponds to a first light-transmitting opening OP1. Different privacy pixel P-D1s correspond to different first light-transmitting openings OP1. The orthographic projection of the privacy pixel P-D1 on the substrate SUB overlaps with the orthographic projection of the corresponding first light-transmitting opening OP1 on the substrate SUB. In short, there are first light-shielding layers BM1 on opposite sides of the shared sub-pixel SD, and first light-shielding layers BM1 are present around the privacy pixel P-D1. In this configuration, when the display substrate is in shared display mode, the light-emitting device 50 in the shared sub-pixel area SD emits light, and the large-angle light emitted by the light-emitting device 50 to the left and right sides is not blocked by the first light-shielding layer BM1; when the display substrate is in privacy display mode, the light-emitting device 50 in the privacy sub-pixel area PD emits light, and the first light-shielding layer BM1 blocks the large-angle light of the light-emitting device 50.

[0125] When the first light-shielding layer BM1 adopts the structure shown in Figure 5, in the shared mode, the light-emitting devices 50 in each shared sub-pixel area SD can be controlled to emit light, and the first light-shielding layer BM1 will not affect the viewing angle in the left and right directions of the display substrate; or, the light-emitting devices 50 in each shared sub-pixel area SD and the privacy sub-pixel PD can be controlled to emit light; in the privacy mode, the light-emitting devices 50 in each privacy sub-pixel area PD can be controlled to emit light, and the large viewing angle light of the privacy sub-pixel in the upper, lower, left and right directions will be blocked by the first light-shielding layer BM1, thereby realizing privacy display.

[0126] In this case, the width of the second light-shielding strip BM12 between two adjacent privacy pixel sections P-D1 in the same privacy sub-pixel PD is smaller than the width of the second light-shielding strip BM12 between two adjacent privacy sub-pixel PDs. Since the privacy sub-pixel PD is divided into multiple privacy pixel sections P-D1, and the spacing between adjacent privacy pixel sections P-D1 in the same privacy sub-pixel PD is small, the width of the second light-shielding strip BM12 between adjacent privacy pixel sections P-D1 in the same privacy sub-pixel PD is correspondingly reduced to prevent interference with the normal light emission of the light-emitting device 50 in the privacy pixel section P-D1.

[0127] In some embodiments, as shown in Figures 4A and 7 to 10, the organic spacer layer OC is located on the side of the first light-shielding layer BM1 away from the substrate SUB, and has a first via V1 located in the peripheral region PA. The material of the organic spacer layer OC may include resin-based materials such as organic polyimide, epoxy resin, acrylic, polyester, photoresist, polyacrylate, polyamide, and siloxane. The organic spacer layer OC includes multiple organic spacer sublayers OC1 arranged sequentially along the direction away from the substrate SUB, each organic spacer sublayer OC1 extending from the display area DA to the peripheral region PA. The organic spacer sublayer OC1 has a first side surface SL1 facing the first via V1, and the first side surface SL1 of the organic spacer sublayer OC1 furthest from the substrate SUB is the side surface of the first via V1. Along the direction close to the substrate SUB, the cross-section of the first via V1 (i.e., the cross-section perpendicular to the thickness direction of the substrate SUB) gradually decreases or decreases in a stepped manner, so that the touch signal line TL forms a ramp at the side position corresponding to the first via V1. In the two adjacent organic spacer sublayers OC1, the one farther from the substrate SUB covers the first side SL1 of the one closer to the substrate SUB, thereby helping to reduce the slope angle of the side of the first via V1, so as to reduce the ramp angle of the touch signal line TL.

[0128] In some embodiments, as shown in Figures 3, 4A, and 8A, a buffer layer BFL1 is disposed on the side of the organic spacer layer OC away from the substrate SUB, extending from the display area DA to the peripheral area PA. The buffer layer BFL1 can cover the side surface of the first via V1. Specifically, the buffer layer BFL1 includes a first buffer portion BFL11 covering the side surface of the first via V1. The thickness of the first buffer portion BFL11 at various locations can be the same or substantially the same; that is, the first buffer portion BFL11 includes opposing first and second buffer surfaces. The first buffer surface is fitted to the side surface of the first via V1, and the first and second buffer surfaces are conformal, thereby ensuring that after the buffer layer BFL1 is applied, the touch signal line TL still has a small ramp angle, preventing the touch signal line TL from breaking. It should be noted that "the first and second buffer surfaces are conformal" here means that the thickness of the first buffer portion BFL11 is uniformly distributed at various locations, making the morphology of the first and second buffer surfaces substantially the same.

[0129] In some embodiments, the buffer layer BFL1 is made of an inorganic material, which may include silicon oxide (SiOx), silicon nitride (SiNx), and / or silicon oxynitride (SiON). The buffer layer BFL1 can be prepared using a chemical vapor deposition process to achieve a uniform thickness distribution at each location.

[0130] It should be noted that the buffer layer BFL1 exposes at least a portion of the bottom of the first via V1 to ensure a stable connection between the touch signal line TL and the touch connection line 20.

[0131] In some embodiments, the touch electrode layer is located on the side of the buffer layer BFL1 away from the substrate SUB. The touch electrode layer can adopt a mutual capacitance structure or a self-capacitance structure. This disclosure describes an embodiment using a mutual capacitance structure as an example. As shown in Figures 3 and 10, the touch electrode layer includes multiple touch driving electrodes and multiple touch sensing electrodes, including multiple touch driving electrodes TX and multiple touch sensing electrodes RX. The touch driving electrodes TX and touch sensing electrodes RX are intersected, and the intersection of the touch driving electrodes TX and touch sensing electrodes RX is insulated and separated by a touch insulating layer TLD. The touch driving electrode TX includes multiple driving electrode units TX1 arranged along a first direction and a connecting portion TX2 connected between the driving electrode units TX1. The touch sensing electrode RX includes multiple sensing electrode units RX1 and a bridging portion RX2 connected between the sensing electrode units. The first direction intersects with the second direction. For example, the first direction is the up-down direction in Figure 3, and the second direction is the left-right direction in Figure 3. The driving electrode unit TX1, the connecting portion TX2, and the sensing electrode unit RX1 are all located on the side of the touch insulating layer TLD away from the substrate SUB, and the driving electrode unit TX1, the connecting portion TX2, and the sensing electrode unit RX1 can be disposed on the same layer. The bridging portion RX2 is located on the side of the touch insulating layer TLD closer to the substrate SUB. The bridging portion RX2 and the connecting portion TX2 are intersected and separated by the touch insulating layer TLD. The sensing electrode unit RX1 is connected to the bridging portion RX2 through a via on the touch insulating layer TLD. It should be noted that the touch driving electrode TX and the touch sensing electrode RX shown in Figures 3 and 10 are merely illustrative examples and do not constitute a limitation of this disclosure. For example, the bridging portion RX2 can also be located on the side of the touch insulating layer TLD away from the substrate SUB, and the connecting portion can be located on the side of the touch insulating layer TLD closer to the substrate SUB. As another example, adjacent driving electrode units TX1 can be connected through bridging portions disposed on different layers, and adjacent sensing electrode units RX1 can be connected using connecting portions on the same layer.

[0132] Each touch driving electrode TX and touch sensing electrode RX can be connected to a corresponding touch driving line TL. In some embodiments, the touch signal line TL is disposed on the same layer as at least part of the touch driving electrode. For example, the touch signal line TL can be disposed on the same layer as the driving electrode unit TX1, the connecting part TX2, and the sensing electrode unit RX1, and all are located in the second touch pattern layer TMB; the bridging part RX2 is located in the first touch pattern layer TMA, so that the touch signal line TL can be fabricated simultaneously with the driving electrode unit TX1, the connecting part TX2, and the sensing electrode unit RX1, simplifying the manufacturing process.

[0133] In some embodiments, the touch protection layer TOC is located on the side of the touch electrode layer away from the substrate SUB and extends from the display area DA to the peripheral area PA, thereby covering the touch electrode layer and the touch signal line TL to protect the touch electrode layer and the touch signal line TL in the peripheral area PA. The material of the touch protection layer TOC may include inorganic insulating materials or organic insulating materials.

[0134] In some embodiments, as shown in Figures 4A and 10, the second light-shielding layer BM2 is located on the side of the touch protection layer away from the substrate SUB. As shown in Figure 6, the second light-shielding layer BM2 has a plurality of second light-transmitting openings OP2, and the orthographic projection of each second light-transmitting opening OP2 on the substrate SUB overlaps with the orthographic projection of at least one first light-transmitting opening OP1 on the substrate SUB. The orthographic projection of the second light-shielding layer BM2 on the substrate SUB is within the range of the orthographic projection of the first light-shielding layer BM1 on the substrate SUB. By setting the second light-shielding layer BM2, light from a wide viewing angle can be further restricted during privacy display, improving the privacy protection effect.

[0135] As shown in Figure 6, the second light-shielding layer BM2 includes multiple third light-shielding strips BM21 extending along the row direction and multiple fourth light-shielding strips BM22 extending along the column direction. The multiple third light-shielding strips BM21 are arranged along the column direction. The third light-shielding strips BM21 are arranged on opposite sides of the shared sub-pixels SD along the column direction. The orthographic projection of the gap area between two adjacent shared sub-pixels SD in the same row onto the substrate SUB does not overlap with the orthographic projection of the second light-shielding layer BM2 onto the substrate SUB. The privacy-protecting sub-pixels PD have fourth light-shielding strips BM22 arranged on opposite sides of the row direction, and the privacy-protecting sub-pixels PD have third light-shielding strips BM21 arranged on opposite sides of the column direction. The orthographic projection of each third light-shielding strip BM21 on the substrate SUB lies within the orthographic projection range of a first light-shielding strip BM11 on the substrate SUB, and the width of the third light-shielding strip BM21 is smaller than the width of the first light-shielding strip BM11; the orthographic projection of the fourth light-shielding strip BM22 on the substrate SUB lies within the orthographic projection range of a second light-shielding strip BM12 on the substrate, and the width of the fourth light-shielding strip BM22 is smaller than the width of the second light-shielding strip BM12, thereby ensuring that large-angle light is blocked, while light of the required angle can be emitted normally.

[0136] Furthermore, in the space between two adjacent privacy pixel portions P-D1 within the same privacy sub-pixel PD, a fourth light-shielding strip BM22 can be omitted, and instead, an auxiliary light-shielding strip TMA1 can be provided (as shown in Figure 4A). The auxiliary light-shielding strip TMA1 can be located within the first touch graphics layer TMA. Since the spacing between two adjacent privacy pixel portions P-D1 within the same privacy sub-pixel PD is small, and it is currently difficult to form a narrow fourth light-shielding strip BM22 during the patterning process of the second light-shielding layer BM2, a fourth light-shielding strip BM22 is no longer provided between two adjacent privacy pixel portions P-D1 within the same privacy sub-pixel PD. Moreover, the first touch graphics layer TMA uses a metal material, which has higher patterning precision and is easier to fabricate with a narrower structure. Therefore, providing an auxiliary light-shielding strip TMA1 within the first touch graphics layer TMA for light shielding can reduce the manufacturing difficulty while maintaining the privacy effect. In addition, once an auxiliary light-shielding strip TMA1 is set in the first touch graphics layer TMA, there is no need to set an auxiliary light-shielding strip in the second touch graphics layer TMB, so as to simplify the structure.

[0137] In some embodiments, the thickness of the organic spacer layer OC is greater than or equal to 6 micrometers, thereby creating a larger gap between the first light-shielding layer BM1 and the second light-shielding layer BM2 to further improve the privacy protection effect. For example, the thickness of the organic spacer layer OC is between 6 and 9 micrometers, or between 9 and 12 micrometers, or between 12 and 15 micrometers, or between 15 and 18 micrometers.

[0138] In one example, the thickness of each organic spacer sublayer OC1 is less than or equal to 2 micrometers, which facilitates the formation of a smooth first side SL1. For example, the thickness of each organic spacer sublayer OC1 is 1.8 to 2 micrometers, or 1.5 to 1.8 micrometers, or 1.2 to 1.5 micrometers, or 1 to 1.2 micrometers.

[0139] In some embodiments, the organic spacer layer OC may include 2 to 5 organic spacer sublayers OC1, for example, 3 or 4 organic spacer sublayers OC1, thereby ensuring that the first via V1 has a smooth side surface while reducing the number of process steps in the fabrication process of the organic spacer layer OC.

[0140] In some embodiments, in order to further reduce the viewing angle in the privacy display mode and improve the brightness of the display substrate from the forward viewing angle, a lens can be provided on the light-emitting side of the light-emitting device 50 in the privacy sub-pixel area PD. For example, the touch protection layer TOC is patterned to form a convex lens that corresponds one-to-one with the privacy sub-pixel area PD.

[0141] In some embodiments, as shown in Figures 4A and 10, the display substrate further includes a cover layer OC3, which is located on the side of the second light-shielding layer BM2 away from the substrate SUB.

[0142] Figure 4B is a schematic diagram of the film structure of a display substrate provided in some other embodiments of this disclosure. The display substrate shown in Figure 4B is similar to that in Figure 4A, except that in Figure 4B, the display substrate may further include a color filter layer. The color filter layer is located on the side of the touch protection layer TOC away from the substrate SUB. The color filter layer may include multiple color filters CF, which are located in the second light-transmitting aperture. The orthographic projections of the light-emitting device 50 on the substrate SUB and the color filters CF on the substrate SUB overlap. Each light-emitting device 50 may correspond to one color filter CF, and different color filters CF are independent of each other. Alternatively, the color filters CF corresponding to multiple light-emitting devices 50 in the same privacy pixel PD may be connected into one unit, thereby reducing the requirements for the fabrication precision of the color filters CF.

[0143] The display substrate can emit various colors from its multiple light-emitting devices 50, such as red, green, and blue. The color filter CF has the same color as the corresponding light-emitting device 50. By providing the color filter CF, the color gamut of the display substrate can be improved.

[0144] As shown in Figure 4B, the cover layer OC3 is located on the side of the color filter section CF away from the substrate SUB. The display substrate may also include an optical adhesive layer OCA and a cover plate CG. The optical adhesive layer OCA is located on the side of the cover layer OC3 away from the substrate SUB, and the cover plate CG is located on the side of the optical adhesive layer OCA away from the substrate SUB.

[0145] Figure 4C is a schematic diagram of the film structure of a display substrate provided in some embodiments of the present disclosure. The display substrate shown in Figure 4C is similar to that in Figure 4A, except that in Figure 4C, the display substrate may also include a polarizer POL located on the side of the cover layer OC3 away from the substrate SUB. The polarizer POL is a circular polarizer, which can reduce the reflection of ambient light by the display substrate.

[0146] As shown in Figure 4C, an optical adhesive layer OCA and a cover plate CG are also provided on the side of the polarizer POL away from the substrate SUB. The optical adhesive layer OCA is located on the side of the cover layer OC3 away from the substrate SUB, and the cover plate CG is located on the side of the optical adhesive layer OCA away from the substrate SUB.

[0147] This disclosure also provides a method for manufacturing the above-mentioned display substrate, including:

[0148] S11. A touch connection line 20 is formed on the substrate SUB.

[0149] In some embodiments, as described above, the touch connection line 20 can be disposed on the same layer as the source and drain of the transistor. In this case, the source, drain of the transistor and the touch connection line 20 are formed simultaneously using the same patterning process.

[0150] S12. Multiple light-emitting devices 50 are formed on the side of the layer where the touch connection line 20 is located away from the substrate SUB; wherein, the shared sub-pixel area SD and the privacy sub-pixel area PD are both provided with light-emitting devices 50.

[0151] S13. A first light-shielding layer BM1 is formed on the side of the plurality of light-emitting devices 50 away from the substrate SUB. The first light-shielding layer BM1 has a plurality of first light-transmitting holes OP1. The orthographic projection of each light-emitting device 50 on the substrate SUB overlaps with the orthographic projection of the first light-transmitting hole OP1 on the substrate SUB.

[0152] S14. An organic spacer layer OC with a first via V1 is formed on the side of the first light-shielding layer BM1 away from the substrate SUB.

[0153] S15. A touch signal line TL is formed on the side of the organic spacer layer OC away from the substrate SUB. The touch signal line TL is electrically connected to the touch connection line 20 through the first via V1.

[0154] S16. A second light-shielding layer BM2 is formed on the side of the layer where the touch signal line TL is located away from the substrate SUB. The second light-shielding layer BM2 has a plurality of second light-transmitting holes OP2. The orthographic projection of each second light-transmitting hole OP2 on the substrate SUB overlaps with the orthographic projection of at least one first light-transmitting hole OP1 on the substrate SUB.

[0155] Step S14 includes:

[0156] S141. Multiple organic material layers are formed sequentially. For each organic material layer formed, a corresponding mask is used to pattern the organic material layer to form an organic spacer sublayer OC1. The organic spacer sublayer OC1 has a first side surface SL1 facing the first via V1. In two adjacent organic spacer sublayers OC1, the one farther from the substrate SUB covers the first side surface SL1 of the one closer to the substrate SUB.

[0157] Figure 11 is a schematic diagram of the execution process of step S141 provided in some embodiments of this disclosure. Figure 11 is illustrated using an organic spacer layer OC comprising three organic spacer sublayers OC1 as an example. As shown in Figure 11, each organic material layer PR corresponds to a mask M1. Each patterning process includes: exposing the organic material layer PR using the mask M1 corresponding to the organic material layer PR; and then developing the exposed organic material layer PR.

[0158] The mask M1 includes a first mask region M11 and a second mask region M12. In each patterning process of the organic material layer PR, the orthographic projection of the first mask region M11 on the substrate SUB covers the orthographic projection of the bottom of the first via V1 on the substrate SUB. For the mask M1 corresponding to two adjacent organic material layers PR, the first mask region M11 corresponding to the organic material layer PR away from the substrate SUB has a first orthographic projection on the substrate SUB, and the first mask region M11 corresponding to the organic material layer PR close to the substrate SUB has a second orthographic projection on the substrate SUB. The first orthographic projection covers and exceeds the second orthographic projection, so that in the two adjacent organic spacer sublayers OC1, the one away from the substrate SUB covers the first side surface SL1 of the one close to the substrate SUB.

[0159] For example, there is a ring-shaped region between the edge of the first orthographic projection and the edge of the second orthographic projection.

[0160] The bottom of the first via V1 refers to the area in the organic material layer PR that corresponds to the area where the first via V1 is located and is completely removed. When the organic material layer PR uses a positive photoresist material, the first mask area M11 is the light-transmitting area of ​​the mask plate M1, and the second mask area M12 is the opaque area; when the organic material layer PR uses a negative photoresist material, the first mask area M11 is the opaque area of ​​the mask plate M1, and the second mask area M12 is the light-transmitting area.

[0161] Figure 12A shows the morphology of the organic material layer PR at the boundary of the first mask region M11 of the mask plate M1 and the energy curve at the boundary of the first mask region M11. Taking the organic material layer PR using negative photoresist as an example, the first mask region M11 is an opaque region. Figure 12B shows the light energy distribution in the first mask region M11. In each patterning process of the organic material layer PR, as shown in Figure 12, the central position of the opaque region of the mask plate M1 will not transmit light, so that the corresponding position of the organic material layer PR will not be exposed to light at all, and can be completely removed after development; however, due to the diffraction of light, there will still be a certain amount of light energy at the edge of the opaque region, so that the corresponding position of the organic material layer PR will be partially removed after development, forming the aforementioned first side surface SL1.

[0162] Figure 13 is a schematic diagram of the film layers of a display substrate provided in some other embodiments of this disclosure. Figure 14 is a cross-sectional view of a display substrate provided in some other embodiments of this disclosure along line A-A' in Figure 7. Figure 15A is a schematic diagram of the morphology of a portion of the structure in Figure 14. Figure 15B is a schematic diagram of another morphology of a portion of the structure in Figure 14. Figure 15C is a schematic diagram of yet another morphology of a portion of the structure in Figure 14. Figure 16 is another cross-sectional view of a display substrate provided in some other embodiments of this disclosure along line A-A' in Figure 7. Figure 17 is a schematic diagram of a portion of the structure in Figure 16. As shown in Figures 13 to 17, the display substrates provided in some other embodiments of this disclosure are similar to the display substrates shown in Figures 4A and 8A, the only difference being the morphology of the organic spacer layer OC. The differences between the two organic spacer layers OC will be described below. As shown in Figures 13 to 17, the organic spacer layer OC has a first via V1 and includes a first surface facing the substrate SUB, a second surface facing away from the substrate SUB, and a second side surface SL2 connecting the first and second surfaces and facing the first via V1. The second side surface SL2 is the side surface of the first via V1. The second side surface SL2 is a stepped surface. Along the direction close to the central axis of the first via V1, the thickness of the organic spacer layer OC decreases in a stepped manner. It should be noted that "the second side surface SL2 is a stepped surface" means that the intersection line between the second side surface SL2 and the plane perpendicular to the substrate SUB is stepped; the stepped shape can be a broken line (as shown in Figure 15B) or a shape formed by multiple arcs connected in sequence (as shown in Figure 15A). The stepped surface can include multiple protruding portions facing the first via V1, with recessed portions formed between adjacent protruding portions. The stepped surface can be a surface formed by multiple bent surfaces connected in sequence or a surface formed by multiple smooth curved surfaces connected in sequence.

[0163] For the organic spacer layer OC shown in Figures 13 to 17, during its preparation process, an organic material layer is first formed, and then the organic material layer is exposed using a mask. Taking the organic material layer as a positive photoresist as an example, during the exposure process, the light-transmitting area of ​​the mask corresponds to the area where the first via V1 is to be formed. Since the light energy at the edge of the light-transmitting area is less, the organic material layer corresponding to the edge of the light-transmitting area is not fully exposed. As a result, after development, the thickness of the organic material layer corresponding to the edge of the light-transmitting area gradually changes, forming the first via V1 with a certain slope.

[0164] Figure 18 is a schematic diagram of the mask position during the fabrication of the organic spacer layer OC in some other embodiments of this disclosure. Figure 18 illustrates the organic spacer layer OC as a forward photoresist. In the embodiments shown in Figures 13 to 17, as shown in Figure 18, when fabricating the organic spacer layer OC with the first via V1, an organic material layer can be formed first. Then, the organic material layer is exposed using a half-tone mask with multiple transmittances. The transmittance of the area corresponding to each sub-surface SL21 in the half-tone mask gradually changes, so that the thickness of the incompletely exposed organic material layer changes more slowly after development, thereby making the side surface of the formed first via V1 smoother and reducing the probability of breakage of the touch signal line TL.

[0165] In some embodiments, as shown in Figures 15A, 15C, and 17, the second side surface SL2 includes a plurality of sub-surfaces SL21 sequentially arranged and connected along a direction away from the substrate SUB. Each sub-surface SL21 is an arc-shaped surface protruding towards the first via V1. The plurality of sub-surfaces SL21 are connected sequentially to form the aforementioned stepped surface. Adjacent sub-surfaces SL21 can be directly connected or connected via a connecting plane SL22. When each sub-surface SL21 is a smooth arc-shaped surface, bending of the touch signal line TL on the sub-surface SL21 can be prevented, further reducing the probability of breakage of the touch signal line TL.

[0166] In some embodiments, the angles between the cross-sections at various positions on sub-surface SL21 (as shown by cross-sections Cp1 and Cp2 in Figure 15D) and the plane containing the substrate SUB (as shown by γ1 and γ2 in Figure 15D) are less than or equal to 30°, so that each sub-surface SL21 is as smooth as possible, reducing the probability of the touch signal line TL breaking. Figure 15D only schematically shows the cross-section Cp1 of sub-surface SL21 near the substrate SUB and the cross-section Cp2 at the middle position of sub-surface SL22. The angles between the cross-sections at other positions and the plane containing the substrate SUB are referenced to cross-sections Cp1 and Cp2, and are no more than 30°, further reducing the probability of the touch signal line TL breaking.

[0167] In one example, as shown in Figure 15D, the slope angle γ1 of two adjacent sub-surfaces SL21 is the same. Here, "slope angle γ1 of sub-surface SL21" in this disclosure refers to the maximum value of the angle between the tangent plane at each position on sub-surface SL21 and the plane containing the substrate SUB. As shown in Figure 15D, among the tangent planes at each position on sub-surface SL21, the steepest tangent plane is Cp1, and the angle γ1 between this tangent plane Cp1 and the plane containing the substrate SUB is the slope angle of sub-surface SL21.

[0168] In one example, as shown in Figure 15A, each sub-surface SL21 has the same dimension, H, in the thickness direction of the substrate SUB, which is beneficial for the uniform thickness distribution of the subsequently formed touch signal line CL on the side of the first via V1.

[0169] In another example, as shown in Figure 17, in two adjacent sub-surfaces SL21, the slope angle of the sub-surface SL21 closer to the substrate SUB is greater than the slope angle of the sub-surface SL21 farther from the substrate SUB. This arrangement helps to further reduce the probability of touch signal line TL breakage. For example, as shown in Figure 17, along the direction away from the substrate SUB, the slope angles of multiple sub-surfaces SL21 are α1, α2, α3, α4, and α5, respectively, where α1 > α2 > α3 > α4 > α5.

[0170] Furthermore, in two adjacent sub-surfaces SL21, the one closer to the substrate SUB has a larger dimension in the substrate SUB thickness direction than the one farther away from the substrate SUB. For example, in Figure 17, H1 > H2 > H3 > H4 > H5. This allows the sub-surface SL21 that is relatively farther away from the substrate SUB to have a smaller slope angle, further reducing the probability of the touch signal line TL breaking.

[0171] For example, the sub-face SL21 closest to the substrate SUB has a size between 1.5 and 2 micrometers in the thickness direction of the substrate SUB, while the sub-face SL21 furthest from the substrate SUB has a size between 0.5 and 1 micrometer in the thickness direction of the substrate SUB. This makes the touch signal line TL climb more gently in the first via V1, reducing the probability of breakage.

[0172] In Figures 13 to 17, the thickness of the organic spacer layer OC can also be set to 6 micrometers or more to further reduce the viewing angle in privacy display mode.

[0173] The remaining structures in Figures 13 to 17 are set up according to the method shown in Figure 4A, and will not be described again here.

[0174] This disclosure also provides a method for manufacturing the display substrate shown in Figures 13 to 17, including:

[0175] S21. A touch connection line 20 is formed on the substrate SUB.

[0176] S22. Multiple light-emitting devices 50 are formed on the side of the layer where the touch connection line 20 is located away from the substrate SUB; both the shared sub-pixel area SD and the privacy sub-pixel area PD are provided with light-emitting devices 50.

[0177] S23. A first light-shielding layer BM1 is formed on the side of the plurality of light-emitting devices 50 away from the substrate SUB. The first light-shielding layer BM1 has a plurality of first light-transmitting openings OP1. The orthographic projection of each light-emitting device 50 on the substrate SUB overlaps with the orthographic projection of the first light-transmitting opening OP1 on the substrate SUB.

[0178] S24. An organic spacer layer OC with a first via V1 is formed on the side of the first light-shielding layer BM1 away from the substrate SUB. The organic spacer layer OC includes a first surface facing the substrate SUB, a second surface away from the substrate SUB, and a second side surface SL2 connected between the first surface and the second surface and facing the first via V1. The second side surface SL2 is a stepped surface.

[0179] S25. A touch signal line TL is formed on the side of the organic spacer layer OC away from the substrate SUB. The touch signal line TL is electrically connected to the touch connection line 20 through the first via V1.

[0180] S26. A second light-shielding layer BM2 is formed on the side of the layer where the touch signal line TL is located away from the substrate SUB. The second light-shielding layer BM2 has multiple second light-transmitting holes OP2. Each second light-transmitting hole OP2 overlaps with the orthogonal projection of at least one first light-transmitting hole OP1 on the substrate SUB.

[0181] In some embodiments, the organic spacer layer OC is formed by patterning an organic material layer using a halftone mask. This patterning process includes exposing the organic material layer using a halftone mask, followed by developing the exposed organic material layer.

[0182] The second side surface SL2 includes N sub-surfaces SL21 sequentially arranged and connected along the direction away from the substrate SUB. Each sub-surface SL21 is an arc-shaped surface protruding towards the second via, and N is an integer greater than 1. As shown in Figure 18, taking the organic material layer as an example using a positive photoresist material, during the exposure process of the patterning process, the transmittance of the area corresponding to the i-th sub-surface SL21 of the halftone mask M2 is greater than the transmittance of the area corresponding to the (i+1)-th sub-surface SL21 of the halftone mask, where i is an integer greater than 0 and less than N.

[0183] In this design, each of the second to last sub-faces SL21 corresponds to a semi-transparent area M2-H of the halftone mask M2, and the portion of the organic material layer that does not need to be removed corresponds to the opaque area M2-S of the halftone mask M2. The area corresponding to the first sub-face SL21 (i.e., the sub-face SL21 closest to the substrate SUB) and the area corresponding to the bottom of the first via V1 are the transparent areas M2-T, with a transmittance of 100%. As described above, at the edge of the transparent area M2-T, the light energy is less than that at the center. Therefore, at the edge of the transparent area M2-T, there will still be some organic material layer residue after development, thus forming the first sub-face SL21. For the second to Nth sub-faces SL21, the transmittance of the corresponding areas of the halftone mask M2 gradually decreases, and the transmittance difference between adjacent areas can be set according to actual needs and process capabilities. For example, when N is 3, the transmittance of the halftone mask M2 in the area corresponding to the first sub-surface SL21 (transparent area M2-T) is 100%, the transmittance of the area corresponding to the second sub-surface SL21 (semi-transparent area M2-H) is 50% to 70%, for example, 60%; and the transmittance of the area corresponding to the third sub-surface SL21 (semi-transparent area M2-H) is 30% to 40%, for example, 33%.

[0184] Similarly, when the organic material layer uses a negative photoresist material, during exposure, the transmittance of the halftone mask corresponding to the i-th sub-surface SL21 is less than the transmittance of the halftone mask corresponding to the (i+1)-th sub-surface SL21. For example, when N is 3, the transmittance of the halftone mask corresponding to the 3rd sub-surface SL21 is 50%–70%, for example, 60%; the transmittance of the region corresponding to the 2nd sub-surface SL21 is 30%–40%, for example, 33%; the transmittance of the region corresponding to the 1st sub-surface SL21 (the sub-surface closest to the substrate SUB) and the region corresponding to the bottom of the first via V1 is 0%; the transmittance of the region where the organic material layer does not need to be removed is 100%.

[0185] In this embodiment, the transmittance of each region of the halftone mask can be controlled through different implementation methods. Specifically, the second to last sub-surfaces SL21 all correspond to the semi-transparent areas of the halftone mask M2, which includes a semi-transparent film located within the semi-transparent areas M2. It should be noted that the terms "semi-transparent area" and "semi-transparent film" do not necessarily refer to a transmittance of 50% for the area or film layer; they can also be other transmittance values ​​greater than 0 and less than 100%. In one example, the semi-transparent film is made of a metallic material, such as chromium.

[0186] The thickness of the semi-transparent film corresponding to the two adjacent sub-surfaces SL21 is different, thereby achieving different light transmittance of the semi-transparent film corresponding to the two adjacent sub-surfaces SL21; or, the semi-transparent film has slits, and the slit distribution density of the semi-transparent film corresponding to the two adjacent sub-surfaces SL21 is different, which can also achieve different light transmittance of the semi-transparent film corresponding to the two adjacent sub-surfaces SL21.

[0187] For example, when the organic material layer uses positive photoresist, the thickness of the semi-permeable film corresponding to the j-th sub-surface SL21 is the same as the thickness of the semi-permeable film corresponding to the (j+1)-th sub-surface SL21; or, slits are formed on the semi-permeable film, and the slit distribution density on the semi-permeable film corresponding to the j-th sub-surface SL21 is greater than the slit distribution density on the semi-permeable film corresponding to the (j+1)-th sub-surface SL21; where j is an integer greater than 1 and less than N, and N is greater than 2.

[0188] Figure 19 shows the light energy curve transmitted through a semi-transparent film with slits. The vertical axis represents the ratio of the transmitted light intensity to the light intensity at the location of maximum light transmission in the halftone mask. In one example, the halftone mask M2 includes a semi-transparent area M2-H, a transparent area M2-T, and a shading area M2-S. A semi-transparent film with slits is placed in the semi-transparent area M2-H. Simulation results show that when slits are placed on the semi-transparent film in the semi-transparent area M2-H, the light energy in this area is less than the light energy in the transparent area but greater than the light energy in the opaque area, thus achieving a partial light transmission effect.

[0189] This disclosure also provides a display device, including the display substrate of any of the above embodiments.

[0190] The display device can include any device or product with display functionality. For example, the display device can be a smartphone, mobile phone, e-book reader, desktop computer (PC), laptop PC, netbook PC, personal digital assistant (PDA), portable multimedia player (PMP), digital audio player, mobile medical device, camera, wearable device (such as head-mounted devices, electronic clothing, electronic bracelets, electronic necklaces, electronic accessories, electronic tattoos, or smartwatches), television set, etc.

[0191] It is understood that the above embodiments are merely exemplary embodiments used to illustrate the principles of this disclosure, and this disclosure is not limited thereto. For those skilled in the art, various modifications and improvements can be made without departing from the spirit and substance of this disclosure, and these modifications and improvements are also considered to be within the scope of protection of this disclosure.

Claims

1. A display substrate having a plurality of pixel regions, the pixel regions comprising a shared sub-pixel region and a privacy sub-pixel region; the display substrate comprising: a substrate; a plurality of light emitting devices disposed on the substrate, wherein the shared sub-pixel region and the privacy sub-pixel region are both provided with the light emitting devices; a first light shielding layer located on a side of the plurality of light emitting devices away from the substrate, the first light shielding layer having a plurality of first light transmission openings; a normal projection of each of the light emitting devices on the substrate overlaps a normal projection of the first light transmission opening on the substrate; an organic spacer layer located on a side of the first light shielding layer away from the substrate, and provided with a first via hole; the organic spacer layer comprises a plurality of organic spacer sub-layers disposed in sequence in a direction away from the substrate, the organic spacer sub-layers have a first side surface facing the first via hole; in adjacent two layers of the organic spacer sub-layers, one away from the substrate covers the first side surface of the other close to the substrate; a touch connection line located on a side of the plurality of light emitting devices close to the substrate; a touch signal line located on a side of the organic spacer layer away from the substrate, the touch signal line is electrically connected with the touch connection line through the first via hole. On the first side surface of a layer of the organic spacer sub-layers farthest away from the substrate, the angle between the tangent plane at each position and the plane in which the substrate lies is less than or equal to 30°. In adjacent two layers of the organic spacer sub-layers, the slope angle of the first side surface of one away from the substrate is less than or equal to the slope angle of the first side surface of the other close to the substrate; wherein the slope angle of the first side surface is the maximum value of the angle between the tangent plane at each position on the first side surface and the plane in which the substrate lies. The pixel regions are arranged in an array, in a same pixel region, the privacy sub-pixel and the shared sub-pixel region are arranged in a column direction, the privacy sub-pixel comprises a plurality of privacy pixel portions arranged in a row direction, and the light emitting device is disposed in each privacy pixel portion; in the same row, the interval region between adjacent two shared sub-pixels does not overlap the normal projection of the first light shielding layer on the substrate; each privacy pixel portion corresponds to a first light transmission opening, different privacy pixel portions correspond to different first light transmission openings, and the normal projection of each privacy pixel portion on the substrate overlaps the normal projection of the corresponding first light transmission opening on the substrate. The display substrate further comprises: a second light shielding layer located on a side of the layer where the touch signal line is located away from the substrate; the second light shielding layer is provided with a plurality of second light transmission openings, and a normal projection of each second light transmission opening on the substrate overlaps a normal projection of at least one first light transmission opening on the substrate. The display substrate further comprises: a touch insulating layer located on a side of the organic spacer layer away from the substrate; ​ ​ ​ ​ ​ ​ 2.The display substrate of claim 1, wherein, ​ 3.The display substrate of claim 1, wherein, ​ ​ 4.The display substrate of claim 1, wherein, ​ ​ 5.The display substrate according to any one of claims 1-4, wherein, ​ ​ 6.The display substrate according to any one of claims 1-4, wherein, ​ ​ A touch electrode layer is located on a side of the organic spacer layer away from the substrate and includes a plurality of touch driving electrodes and a plurality of touch sensing electrodes, the touch driving electrodes and the touch sensing electrodes are arranged in a cross manner, the touch driving electrodes and the touch sensing electrodes are insulated and spaced apart by the touch insulating layer at the cross positions, each of the touch driving electrodes and each of the touch sensing electrodes is correspondingly connected to one of the touch signal lines; The touch signal lines are arranged in the same layer as at least part of the touch driving electrodes. 7.The display substrate according to any one of claims 1-4, wherein, The thickness of the organic spacer layer is greater than or equal to 6 microns. 8.The display substrate according to any one of claims 1 to 4, wherein The organic spacer layer includes 2-5 organic spacer sub-layers. 9.The display substrate according to any one of claims 1 to 4, wherein The display substrate further includes a buffer layer between the organic spacer layer and the layer in which the touch signal lines are located, the buffer layer includes a first buffer portion covering the side surface of the first via, the first buffer portion includes opposite first and second buffer surfaces, the first buffer surface is attached to the side surface of the first via, and the second buffer surface is conformal to the first buffer surface. At least part of the normal projection of the first via on the substrate is located outside the normal projection of the buffer layer on the substrate.

10. A display substrate having a plurality of pixel regions, the pixel regions including shared sub-pixel regions and anti-peep sub-pixel regions; the display substrate comprising: a substrate; a plurality of light emitting devices disposed on the substrate, wherein the shared sub-pixel regions and the anti-peep sub-pixel regions are each provided with the light emitting devices; a first light shielding layer located on a side of the plurality of light emitting devices away from the substrate, the first light shielding layer having a plurality of first light transmission openings; the normal projection of each of the light emitting devices on the substrate overlaps the normal projection of the first light transmission opening on the substrate; an organic spacer layer located on a side of the first light shielding layer away from the substrate and having a first via; the organic spacer layer includes a first surface facing the substrate, a second surface facing away from the substrate, and a second side surface connected between the first surface and the second surface and facing the first via, the second side surface being a stepped surface; a touch connection line located on a side of the plurality of light emitting devices close to the substrate; a touch signal line located on a side of the organic spacer layer away from the substrate, the touch signal line being electrically connected to the touch connection line through the first via. 11.The display substrate of claim 10, wherein, The second side surface includes a plurality of sub-surfaces arranged in sequence in a direction away from the substrate, the sub-surfaces being arc-shaped surfaces protruding towards the first via, and the plurality of sub-surfaces are sequentially connected to form the stepped surface. 12.The display substrate of claim 11, wherein, The angle between the tangent plane at each position on the sub-surface and the plane in which the substrate is located is less than or equal to 30°. 13.The display substrate of claim 11, wherein, In adjacent two of the sub-surfaces, the slope angle of the sub-surface close to the substrate is greater than or equal to the slope angle of the sub-surface away from the substrate; the slope angle of the sub-surface is the maximum value of the angle between the tangent plane at each position on the sub-surface and the plane in which the substrate is located. 14.The display substrate of claim 11, wherein, In adjacent two of the sub-surfaces, the dimension of the sub-surface close to the substrate in the thickness direction of the substrate is greater than or equal to the dimension of the sub-surface away from the substrate in the thickness direction of the substrate. 15.The display substrate of claim 10, wherein, The pixel regions are arranged in an array, in a same pixel region, the anti-peep sub-pixel and the shared sub-pixel region are arranged in a column direction, the anti-peep sub-pixel includes a plurality of anti-peep pixel parts arranged in a row direction, and the light emitting device is arranged in each anti-peep pixel part; In the same row, the interval region between the adjacent two shared sub-pixels and the orthographic projection of the first light shielding layer on the substrate are non-overlapping; each anti-peep pixel part corresponds to a first light transmission opening, different anti-peep pixel parts correspond to different first light transmission openings, and the orthographic projection of each anti-peep pixel part on the substrate and the orthographic projection of the corresponding first light transmission opening on the substrate are overlapping. 16.The display substrate according to any one of claims 10-15, wherein, The display substrate further includes a second light shielding layer located on a side of the layer where the touch signal line is away from the substrate; The second light shielding layer is provided with a plurality of second light transmission openings, and the orthographic projection of each second light transmission opening on the substrate and the orthographic projection of at least one first light transmission opening on the substrate are overlapping.

17. The display substrate according to any one of claims 10 to 15, wherein, The display substrate further includes: A touch insulating layer located on a side of the organic spacing layer away from the substrate; A touch electrode layer located on a side of the organic spacing layer away from the substrate and including a plurality of touch driving electrodes and a plurality of touch sensing electrodes, the touch driving electrodes and the touch sensing electrodes are cross arranged, the touch driving electrodes and the touch sensing electrodes are insulated and spaced apart by the touch insulating layer at the intersection, each touch driving electrode and each touch sensing electrode correspond to a touch signal line; Wherein, the touch signal line and at least part of the touch driving electrode are arranged in the same layer. 18.The display substrate according to any one of claims 10-15, wherein, The thickness of the organic spacing layer is greater than or equal to 6 microns.

19. The display substrate according to any one of claims 10 to 15, wherein, The display substrate further includes a buffer layer between the organic spacing layer and the layer where the touch signal line is located, the buffer layer includes a first buffer part covering the side surface of the first via, the first buffer part includes opposite first and second buffer surfaces, the first buffer surface is fitted with the side surface of the first via, and the second buffer surface is conformal with the first buffer surface; Wherein, at least part of the orthographic projection of the first via on the substrate is located outside the orthographic projection of the buffer layer on the substrate.

20. A display device comprising the display substrate of any one of claims 1 to 19.

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