Signal transmission circuit and signal transmission system

Abstract

A signal transmission circuit (10), comprising: an isolation module (20), a clamping module (30) and a receiving module (40), wherein the isolation module (20) is used for receiving a first differential signal, electrically isolating the first differential signal and then outputting a second differential signal, which comprises a second positive signal and a second negative signal; the clamping module (30) is connected to an output end of the isolation module (20), and is used for clamping common-mode levels of the second positive signal and the second negative signal on the basis of the second positive signal and the second negative signal; and an input end of the receiving module (40) is connected to an output end of the isolation module (30), and the receiving module (40) is used for demodulating the second differential signal and then outputting the demodulated second differential signal. The anti-interference capability of an application architecture can be improved, thereby ensuring that signals transmitted from a primary side to a secondary side are normal, and reducing the risk of damage to devices on the primary side and the secondary side. Further disclosed are a signal transmission system and an electronic control system.

Description

Signal transmission circuit and signal transmission system

[0001] The present application claims priority to the Chinese patent application No. 202411044509.6, filed on July 30, 2024, and entitled "Signal transmission circuit and signal transmission system", the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0002] The present application relates to the technical field of capacitive isolation, in particular to a signal transmission circuit and a signal transmission system, and an electric control system. BACKGROUND

[0003] The capacitive isolation chip is mainly used for isolating high-voltage domains and low-voltage domains to realize the "ground" isolation between different power supply domains, and is commonly used in signal transmission between chips or systems in different power supply domains. The current use architecture of the high-voltage capacitive isolator is that when the primary side input of the high-voltage capacitive isolator is high, the high-frequency carrier is transmitted to the secondary side of the capacitive isolator through the high-voltage capacitive isolator. After the received signal is amplified by the secondary side, the output signal is output to the subsequent driving circuit to drive the power device to operate.

[0004] In this use architecture, when the power device is switched, the existence of common-mode interference between the primary side and the secondary side is mainly caused by the large parasitic capacitance of the lower plate of the high-voltage capacitive isolator to the ground. The existence of common-mode interference not only causes the signal transmitted from the primary side to the secondary side to be abnormal, but also may damage the devices in the primary side and the secondary side.

[0005] Therefore, how to improve the anti-interference of the use architecture, ensure the normal signal transmitted from the primary side to the secondary side, and reduce the risk of damage to the devices in the primary side and the secondary side still needs to be solved. SUMMARY

[0006] The purpose of the present application is to provide a signal transmission circuit and a signal transmission system, and an electric control system, for improving the anti-interference of the use architecture, ensuring the normal signal transmitted from the primary side to the secondary side, and reducing the risk of damage to the devices in the primary side and the secondary side.

[0007] In a first aspect, the present application discloses a signal transmission circuit, comprising: an isolation module, a clamping module, and a receiving module.

[0008] The isolation module is configured to receive a first differential signal, and output a second differential signal after electrically isolating the first differential signal, wherein the second differential signal comprises a second positive signal and a second negative signal.

[0009] The clamping module is connected with the output end of the isolation module, and is configured to clamp the common-mode level of the second positive signal and the second negative signal according to the second positive signal and the second negative signal.

[0010] The receiving module is connected with the output end of the isolation module, and is configured to demodulate and output the second differential signal.

[0011] In a second aspect, the present application discloses a signal transmission system, comprising the signal transmission circuit according to the first aspect, and further comprising a controller, a driving module and a power device.

[0012] The output end of the controller is connected with the input end of the signal transmission circuit.

[0013] The input end of the driving module is connected with the output end of the signal transmission circuit.

[0014] The input end of the power device is connected with the output end of the driving module.

[0015] In a third aspect, the present application discloses an electric control system of a vehicle, comprising the signal transmission system according to the second aspect.

[0016] In a fourth aspect, the present application discloses a vehicle, comprising the electric control system of the vehicle according to the third aspect.

[0017] According to the above technical solution, the signal transmission circuit disclosed by the present application comprises an isolation module, a clamping module and a receiving module. The isolation module is configured to receive a first differential signal and output a second differential signal. The second differential signal comprises a second positive signal and a second negative signal. The clamping module is connected with the output end of the isolation module, and is configured to clamp the common mode level of the second positive signal and the second negative signal according to the second positive signal and the second negative signal. The signal receiving module is connected with the output end of the isolation module, and is configured to demodulate and output the second differential signal.

[0018] That is, the clamping module connected with the output end of the isolation module clamps the high-frequency signal transmitted by the isolation module, that is, the second positive signal and the second negative signal are clamped. When clamping, the common mode level is adjusted based on the second positive signal and the second negative signal, and the common mode level carried by the second positive signal and the common mode level carried by the second negative signal are clamped at the same time and in the same amount, so as to improve the clamping effect. More importantly, it prevents the common mode level from being too large due to the difference between the primary side and the secondary side of the signal transmitted from the primary side, thereby causing damage to the devices of the secondary side. In addition, by clamping the common mode level, the risk of abnormality of the signal transmitted from the primary side to the secondary side is reduced. BRIEF DESCRIPTION OF DRAWINGS

[0019] FIG. 1 is a structural schematic diagram of a signal transmission circuit according to some embodiments of the present application;

[0020] Figure 2 is a structure diagram of a clamping module in a signal transmission circuit according to some embodiments of the present application;

[0021] Figure 3 is a structure diagram of a clamping module in a signal transmission circuit according to some embodiments of the present application;

[0022] Figure 4 is a structure diagram of a signal transmission circuit according to some embodiments of the present application;

[0023] Figure 5 is a structure diagram of a signal transmission circuit according to some embodiments of the present application;

[0024] Figure 6 is a structure diagram of an integrator in a signal transmission circuit according to some embodiments of the present application;

[0025] Figure 7 is a structure diagram of a receiving module in a signal transmission circuit according to some embodiments of the present application;

[0026] Figure 8 is a structure diagram of a first amplification circuit in a signal transmission circuit according to some embodiments of the present application;

[0027] Figure 9 is a structure diagram of a second amplification circuit in a signal transmission circuit according to some embodiments of the present application;

[0028] Figure 10 is a structure diagram of a first amplification circuit in a signal transmission circuit according to some embodiments of the present application;

[0029] Figure 11 is a structure diagram of a first amplification circuit in a signal transmission circuit according to some embodiments of the present application;

[0030] Figure 12 is a structure diagram of a first amplification circuit in a signal transmission circuit according to some embodiments of the present application;

[0031] Figure 13 is a structure diagram of a second amplification circuit in a signal transmission circuit according to some embodiments of the present application;

[0032] Figure 14 is a structure diagram of a second amplification circuit in a signal transmission circuit according to some embodiments of the present application;

[0033] Figure 15 is a structure diagram of a second amplification circuit in a signal transmission circuit according to some embodiments of the present application;

[0034] Figure 16 is a structure diagram of a second differential amplification circuit in a signal transmission circuit according to some embodiments of the present application;

[0035] Figure 17 is a structure diagram of an input module in a signal transmission circuit according to some embodiments of the present application;

[0036] Figure 18 is a diagram of an input signal in a signal transmission circuit according to some embodiments of the present application;

[0037] Fig. 19 is a schematic diagram of an oscillator signal in a signal transmission circuit according to some embodiments of the present application;

[0038] Fig. 20 is a schematic diagram of a first differential signal in a signal transmission circuit according to some embodiments of the present application;

[0039] Fig. 21 is a schematic diagram of a structure in a signal transmission circuit according to some embodiments of the present application;

[0040] Fig. 22 is a schematic diagram of a structure of a filter circuit in a signal transmission circuit according to some embodiments of the present application;

[0041] Fig. 23 is a schematic diagram of a structure of a signal transmission system according to some embodiments of the present application;

[0042] Fig. 24 is a schematic diagram of a structure of an electric control system according to some embodiments of the present application;

[0043] Fig. 25 is a schematic diagram of a structure of a vehicle according to some embodiments of the present application.

[0044] Reference Signs: 10 - signal transmission circuit; 20 - isolation module; 30 - clamping module; 31 - trigger circuit; 32 - bleeder circuit; 40 - receiving module; 41 - multi-stage differential amplification circuit; 42 - fusion circuit; 43 - logical AND gate circuit; 44 - integrator; 45 - filter circuit; 50 - input module; 51 - oscillator; 52 - logic circuit; 53 - driving circuit; 60 - signal transmission system; 61 - controller; 62 - driving module; 63 - power device; 70 - electric control system; 71 - load; 310 - first voltage dividing circuit; 320 - second voltage dividing circuit; 410 - first-stage differential amplification circuit; 420 - second-stage differential amplification circuit; 411 - first amplification circuit; 412 - second amplification circuit; 413 - first-stage sub-circuit; 414 - second-stage sub-circuit; 415 - third-stage sub-circuit; 416 - fourth-stage sub-circuit; 419 - preset voltage circuit; 421 - second pull-up circuit; 422 - second pull-down circuit; 423 - third pull-up circuit; 424 - third pull-down circuit; 425 - fourth pull-up circuit; 426 - fourth pull-down circuit; 427 - fifth pull-up circuit; 428 - fifth pull-down circuit; 430 - another preset voltage circuit; 450 - cross-coupled circuit; 451 - back-end amplification circuit. DETAILED DESCRIPTION

[0045] In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the following will clearly and completely describe the technical solutions in the embodiments of the present application with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some but not all of the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the protection scope of the present application.

[0046] In the description of the present application, it should be noted that unless specifically defined and limited, the terms "mounting", "connection", "connecting" should be understood in a broad sense, for example, it can be fixedly connected, or indirectly connected through an intermediate medium, or the internal communication of two elements or the interaction relationship between two elements. For those of ordinary skill in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0047] In the description of the present application, it should be understood that the terms "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present application.

[0048] The terms "first", "second", "third" (if any) in the specification and claims of the present application and the above drawings are used to distinguish similar objects, and do not necessarily describe a specific order or sequence. It should be understood that the data thus used can be interchanged under appropriate circumstances, so that the embodiments of the present application described herein can be implemented in an order other than that illustrated or described herein.

[0049] In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion, for example, a process, method, system, product or maintenance tool including a series of steps or units does not have to be limited to those steps or units clearly listed, but can include other steps or units not clearly listed or inherent to these processes, methods, products or maintenance tools.

[0050] The capacitor isolation chip is mainly used for isolating high-voltage and low-voltage domains to realize "ground" isolation between different power domains, and is commonly used in signal transmission between chips or systems in different power domains. The current use structure of high-voltage capacitor isolator is: when the main side input of the high-voltage capacitor isolator is high, the high-frequency carrier is transmitted to the secondary side of the capacitor isolator through the high-voltage capacitor isolator. After the secondary side amplifies the received signal, the output signal is output to the subsequent driving circuit to drive the power device to operate.

[0051] In this use architecture, when the power device switches, the common mode interference exists between the main side and the secondary side mainly due to the large parasitic capacitance of the lower plate of the high-voltage capacitor isolator to the ground. The main form of the common mode interference is the common mode level, and the excessive common mode level can damage the circuits and devices in the secondary side and affect the normal transmission of signals.

[0052] Based on this, the application provides a signal transmission circuit and a signal transmission system and an electric control system.

[0053] The signal transmission circuit includes an isolation module, a clamping module and a receiving module. The isolation module is configured to receive a first differential signal and output a second differential signal. The second differential signal includes a second positive signal and a second negative signal. The clamping module is connected to the output end of the isolation module and is configured to clamp the common mode level of the second positive signal and the second negative signal according to the second positive signal and the second negative signal. The signal receiving module is connected to the output end of the isolation module and is configured to output after demodulation of the second differential signal.

[0054] That is, the clamping module connected to the output end of the isolation module is used to clamp the high-frequency signal transmitted by the isolation module, so as to prevent the excessive common mode level caused by the difference between the main side and the secondary side from damaging the devices in the secondary side. In addition, clamping the common mode level also reduces the risk of abnormal signal transmission from the main side to the secondary side.

[0055] Please refer to FIG. 1, one embodiment of the application provides a signal transmission circuit 10, which includes an isolation module 20, a clamping module 30 and a receiving module 40.

[0056] The isolation module 20 is described as follows:

[0057] The isolation module 20 is configured to receive a first differential signal and output a second differential signal. Specifically, the isolation module is configured to electrically isolate the first differential signal and output the second differential signal.

[0058] The first differential signal is output by an input module. When the input module is connected to a chip, the pulse signal output from the chip to the input module is processed as the first differential signal. The first differential signal can also be output by other modules, which is not limited here.

[0059] As shown in FIG. 1, the first differential signal includes a first positive signal (OUT+) and a first negative signal (OUT-). The isolation module 20 outputs a second positive signal (INPUT+) after receiving the first positive signal and outputs a second negative signal (INPUT-) after receiving the first negative signal.

[0060] In some optional embodiments, the isolation module 20 is a capacitive isolation module 20, which includes an isolation capacitor, which can be a high-voltage isolation capacitor.

[0061] For example, at least one high-voltage isolation capacitor can be provided for the first positive signal (OUT+), and two high-voltage isolation capacitors connected in series with each other can be provided. Correspondingly, at least one high-voltage isolation capacitor can be provided for the second positive signal (OUT-), and two high-voltage isolation capacitors connected in series with each other can be provided.

[0062] It should be noted that the number of high-voltage isolation capacitors provided for the first positive signal and the second positive signal needs to be consistent. For example, if two high-voltage isolation capacitors connected in series with each other are provided for the first positive signal, two high-voltage isolation capacitors connected in series with each other also need to be provided for the second positive signal.

[0063] The clamping module 30 is described as follows:

[0064] The clamping module 30 is connected to the output end of the isolation module 20, and is used to clamp the common-mode level of the second positive signal and the second negative signal according to the second positive signal and the second negative signal.

[0065] The reason for clamping the common-mode level is that the transient interference caused by the switching of the devices on the secondary side of the signal transmission circuit 10 during the secondary side can cause the ground of the primary side to be different from the ground of the secondary side. Different grounds can cause the absolute value of the common-mode level (positive common-mode level or negative common-mode level) of the second differential signal output by the isolation module 20 to increase. The devices on the secondary side can be understood as power devices. The size of the common-mode level is affected by the working voltage and the switching time of the power devices. The larger the working voltage and the shorter the switching time, the larger the common-mode level. The devices inside the receiving module 40 have a limited withstand voltage. In order to prevent the common-mode level from being too large to damage the devices inside the receiving module 40, the clamping module 30 clamps the common-mode level below the withstand voltage of the devices inside the receiving module 40 when the common-mode level is too large.

[0066] A circuit for discharging the common-mode level can be provided in the clamping module 30. The circuit can discharge the positive common-mode level and discharge the negative common-mode level. One end of the circuit receives the second differential signal, and the other end can be connected to a power supply end with a lower voltage. When discharging the positive common-mode level, the positive common-mode level is discharged to the power supply end with a lower voltage. When discharging the negative common-mode level, the output end of the isolation module is charged from the power supply end.

[0067] It should be noted that the clamping circuit needs to be arranged between the output end of the isolation module 20 and the input end of the receiving module 40, so as to clamp the common-mode voltage of the second differential signal before the second differential signal enters the receiving module 40. Preventing the common-mode voltage from damaging the devices in the receiving module 40.

[0068] The description of the receiving module 40 is as follows:

[0069] The input end of the receiving module 40 is connected with the output end of the isolation module 20, for outputting after demodulating the second differential signal. The demodulation processing can be amplifying the second differential signal and then fusing. That is, the second positive signal and the second negative signal are amplified respectively, and then the second positive signal and the second negative signal are fused into one signal.

[0070] It should be noted that due to the influence of the isolation module 20 and the related parasitic parameters (such as isolation capacitor parasitic parameters, power device parasitic parameters, etc.), the amplitude of the second differential signal output by the first differential signal at the input end of the isolation module 20 is greatly attenuated after being transmitted to the output end, so that the next step cannot be normally processed. Therefore, the attenuated second differential signal needs to be amplified so that the subsequent devices can be recognized.

[0071] In order to improve the effect of signal amplification, the receiving module 40 can include multiple stages of amplification circuits to amplify the second positive signal and the second negative signal in multiple stages.

[0072] In summary, the signal transmission circuit 10 provided by the embodiment includes an isolation module 20, a clamping module 30, and a receiving module 40. The isolation module 20 is used to receive a first differential signal and output a second differential signal. The second differential signal includes a second positive signal and a second negative signal. The clamping module 30 is connected with the output end of the isolation module 20, and is used to clamp the common-mode voltage of the second positive signal and the second negative signal according to the second positive signal and the second negative signal. The signal receiving module 40, the input end is connected with the output end of the isolation module 20, for outputting after demodulating the second differential signal.

[0073] That is, the clamping module 30 connected to the output end of the isolation module 20 is used to clamp the high-frequency signal (i.e., the second positive signal and the second negative signal) transmitted from the isolation module 20. When clamping, the common-mode level is adjusted based on the second positive signal and the second negative signal. The common-mode level carried by the second positive signal and the common-mode level carried by the second negative signal are clamped at the same time and in the same amount, which improves the clamping effect. More importantly, it prevents the common-mode level from being too large due to the difference between the primary side and the secondary side, thereby causing damage to the devices on the secondary side. In addition, by clamping the common-mode level, the risk of abnormal signal transmission from the primary side to the secondary side is reduced.

[0074] In some embodiments, the clamping module 30 is configured to adjust the common-mode level of the second positive signal and the second negative signal when the absolute value of the common-mode level of the second positive signal and the second negative signal is greater than a preset level threshold.

[0075] The preset level threshold can be less than or equal to the voltage withstand value of the device in the receiving module 40. When there are multiple devices in the receiving module 40, the preset level threshold is less than or equal to the voltage withstand value of the self-checking device with the worst voltage withstand performance.

[0076] Regardless of whether the common-mode level is a positive common-mode level or a negative common-mode level, when the absolute value of the common-mode level is greater than the preset level threshold, the common-mode level of the second positive signal and the second negative signal is adjusted to be less than or equal to the preset level threshold. In this way, it can be ensured that the devices in the receiving module 40 will not be damaged due to the common-mode level, and it can also be ensured that the signals received by the receiving module 40 and the signals output by the receiving module 40 are both normal.

[0077] In some embodiments, the clamping module 30 is configured to adjust the clamping amount of the common-mode level based on the second positive signal and the second negative signal, and adjust the common-mode level of the second positive signal and the second negative signal based on the clamping amount of the common-mode level.

[0078] That is, the clamping amount is determined based on the second positive signal and the second negative signal. When the absolute value of the common-mode level carried by the second positive signal and the second negative signal is greater, the clamping amount can be greater. When the absolute value of the common-mode level carried by the second positive signal and the second negative signal is smaller, the clamping amount can be smaller.

[0079] Adjusting the common-mode level of the second positive signal and the second negative signal based on the clamping amount means reducing the absolute value of the common-mode level based on the clamping amount. The clamping amount can be understood as a voltage value. For a positive common-mode level, the voltage value is negative. For a negative common-mode level, the voltage value is positive.

[0080] Please refer to Fig. 2, in one embodiment of the present application, the clamping module 30 comprises a trigger circuit 31 and a discharge circuit 32.

[0081] The first input terminal of the trigger circuit 31 receives the second positive signal, the second input terminal of the trigger circuit 31 receives the second negative signal, and the trigger circuit 31 is configured to output a trigger signal.

[0082] The control terminal of the discharge circuit 32 is connected to the output terminal of the trigger circuit 31, the first terminal of the discharge circuit 32 receives the second positive signal, the second terminal of the discharge circuit 32 receives the second negative signal, and the third terminal of the discharge circuit 32 is connected to the first power terminal. The first power terminal can be a ground terminal (VSS shown in Fig. 2), or a low-voltage power terminal, where low voltage means less than the common-mode voltage when the common-mode voltage is positive.

[0083] The second positive signal can be discharged from the discharge path formed between the first terminal and the third terminal of the discharge circuit 32, or from the discharge path formed between the third terminal and the first terminal of the discharge circuit 32. The discharge circuit 32 controls the amount of charge discharged between the first terminal and the third terminal of the discharge circuit 32 according to the trigger signal.

[0084] The second negative signal can be discharged from the discharge path formed between the second terminal and the third terminal of the discharge circuit 32, or from the discharge path formed between the third terminal and the second terminal of the discharge circuit 32. The discharge circuit 32 controls the amount of charge discharged between the second terminal and the third terminal of the discharge circuit 32 according to the trigger signal.

[0085] Specifically, when the second positive signal and the second negative signal both carry positive common-mode voltage, the second positive signal is discharged from the discharge path formed between the first terminal and the third terminal of the discharge circuit 32, and the second negative signal is discharged from the discharge path formed between the second terminal and the third terminal of the discharge circuit 32.

[0086] Specifically, when the second positive signal and the second negative signal both carry negative common-mode voltage, the second positive signal is discharged from the discharge path formed between the third terminal and the first terminal of the discharge circuit 32, and the second negative signal is discharged from the discharge path formed between the third terminal and the second terminal of the discharge circuit 32.

[0087] The trigger signal is generated when the second positive signal and the second negative signal are input, and is positively related to the absolute value of the common-mode level carried by the second positive signal and the second negative signal. The trigger signal is used to trigger the bleed circuit 32 to bleed the common-mode level. The higher the absolute value of the common-mode level, the higher the level of the trigger signal, the greater the amount of charge between the first end and the third end of the bleed circuit 32, and the greater the amount of charge between the second end and the third end of the bleed circuit 32. The smaller the absolute value of the common-mode level, the lower the level of the trigger signal, the smaller the amount of charge between the first end and the third end of the bleed circuit 32, and the smaller the amount of charge between the second end and the third end of the bleed circuit 32.

[0088] In some embodiments, the device between the first end and the third end and the device between the second end and the third end can be configured to have the same structure.

[0089] In this way, for a positive common-mode level, since the device between the first end and the third end and the device between the second end and the third end have the same structure, the amount of charge corresponding to the discharge path between the first end and the third end is the same as the amount of charge corresponding to the discharge path between the second end and the third end. And because they are controlled by the trigger signal at the same time, the discharge path between the first end and the third end and the discharge path between the second end and the third end are formed at the same time. In this way, the positive common-mode level carried by the second positive signal and the positive common-mode level carried by the second negative signal can be clamped at the same time and in the same amount.

[0090] For a negative common-mode level, since the device between the first end and the third end and the device between the second end and the third end have the same structure, the amount of charge corresponding to the discharge path between the third end and the first end is the same as the amount of charge corresponding to the discharge path between the third end and the second end. And because they are controlled by the trigger signal at the same time, the discharge path between the third end and the first end and the discharge path between the third end and the second end are formed at the same time. In this way, the negative common-mode level carried by the second positive signal and the negative common-mode level carried by the second negative signal can be clamped at the same time and in the same amount.

[0091] The clamp module 30 provided by the embodiment receives the second positive signal and the second negative signal through the trigger circuit 31, and outputs a trigger signal to the bleed circuit 32. The bleed circuit 32 controls the amount of charge according to the trigger signal, and bleeds the common-mode level of the second positive signal and the second negative signal based on the amount of charge. By bleeding the common-mode level through the bleed circuit 32, the problem of the absolute value of the common-mode level being too large is effectively suppressed, preventing damage to the devices in the receiving circuit. And since the same trigger signal is used to control the bleeding of the common-mode level of the second positive signal and the second negative signal, the common-mode level carried by the second positive signal and the common-mode level carried by the second negative signal are clamped at the same time and in the same amount.

[0092] In some embodiments, when a positive common mode level is formed, i.e., the common mode level of the second positive signal and the second negative signal is greater than the voltage of the first power terminal, the bleed circuit 32 forms a bleed path from the first terminal to the third terminal. Correspondingly, the common mode level flows from the first terminal to the third terminal. Since the third terminal is connected to the first power terminal, which is a low voltage terminal (e.g., ground terminal), the common mode level can flow to the low voltage terminal (e.g., ground terminal), thereby bleeding the common mode level and achieving the effect of clamping the common mode level.

[0093] When a positive common mode level is formed, the bleed circuit 32 also forms a bleed path from the second terminal to the third terminal. Correspondingly, the common mode level flows from the second terminal to the third terminal. Since the third terminal is connected to the first power terminal, which is a low voltage terminal (e.g., ground terminal), the common mode level can flow to the low voltage terminal (e.g., ground terminal), thereby bleeding the common mode level and achieving the effect of clamping the common mode level.

[0094] In some embodiments, when a negative common mode level is formed, i.e., the common mode level of the second positive signal and the second negative signal is less than the voltage of the first power terminal, the bleed circuit 32 forms a bleed path from the third terminal to the first terminal. Correspondingly, the common mode level flows from the third terminal connected to the first power terminal to the first terminal, i.e., from the low voltage terminal (e.g., ground terminal) to the output terminal of the isolation module, thereby suppressing the negative common mode level. The common mode level is then bled into the second positive signal, achieving the effect of clamping the common mode level.

[0095] When a negative common mode level is formed, the bleed circuit 32 also forms a bleed path from the third terminal to the second terminal, and correspondingly, the common mode level flows from the third terminal connected to the first power terminal to the second terminal, i.e., from the low voltage terminal (e.g., ground terminal) to the output terminal of the isolation module, thereby suppressing the negative common mode level. The common mode level is then bled into the second negative signal, achieving the effect of clamping the common mode level.

[0096] Referring to FIG. 3, in one embodiment of the present application, the bleed circuit 32 includes a first transistor MA1 and a second transistor MA2. The first transistor MA1 and the second transistor MA2 can be metal-oxide-semiconductor (MOS) transistors as shown in FIG. 3.

[0097] The control terminal of the first transistor MA1 is connected to the control terminal of the second transistor MA2. As shown in FIG. 3, the gate of the first transistor MA1 is connected to the gate of the second transistor MA2, and the gate is the control terminal. The first transistor MA1 and the second transistor MA2 shown in FIG. 3 are both NMOS tubes, and in actual use, they can also be replaced by PMOS tubes as long as the common-mode level can be discharged. However, it is emphasized that the first transistor MA1 and the second transistor MA2 are of the same size, so as to ensure that the charge discharge amount of the first transistor MA1 and the second transistor MA2 needs to be the same.

[0098] The control terminal of the first transistor MA1 and the control terminal of the second transistor MA2 both receive the trigger signal. As shown in FIG. 3, the gate of the first transistor MA1 and the gate of the second transistor MA2 simultaneously receive the trigger signal, and the first transistor MA1 and the second transistor MA2 are simultaneously triggered to be turned on, and the common-mode level carried by the second positive signal and the second negative signal is simultaneously discharged.

[0099] The first end of the first transistor MA1 is the first end of the discharge circuit 32, that is, the first end of the first transistor MA1 receives the second positive signal (INPUT+). The second end of the first transistor MA1 is connected to the first power supply end, and the first power supply end is VSS as shown in FIG. 3. When forming a positive common-mode level, as shown in FIG. 3, the first end of the first transistor MA1 is the drain, and the second end of the first transistor MA1 is the source. When the positive common-mode level is formed, the first transistor MA1 is turned on, and the positive common-mode level flows into the first power supply end, achieving the effect of clamping the common-mode level. When forming a negative common-mode level, the first end of the first transistor MA1 is the source, and the second end of the first transistor MA1 is the drain. When the negative common-mode level is formed, the first transistor MA1 is turned on, and the negative common-mode level flows from the first power supply end to the output end of the isolation module, achieving the effect of clamping the common-mode level.

[0100] The first end of the second transistor MA2 is the second end of the leakage circuit 32, i.e. the second end of the second transistor MA2 receives the second negative signal (INPUT-). The second end of the second transistor MA2 is connected to the first power supply end, which is VSS as shown in FIG. 3. When forming a positive common mode level, the first end of the second transistor MA2 is the drain, and the second end of the second transistor MA2 is the source, as shown in FIG. 3. When the positive common mode level is formed, the second transistor MA2 is turned on, and the positive common mode level flows into the first power supply end, achieving the effect of clamping the common mode level. When forming a negative common mode level, the first end of the first transistor MA1 is the source, and the second end of the first transistor MA1 is the drain. When the negative common mode level is formed, the second transistor MA2 is turned on, and the negative common mode level flows from the first power supply end into the second negative signal, achieving the effect of clamping the common mode level.

[0101] It should be emphasized that the first transistor MA1 and the second transistor MA2 have the same conduction condition, the same conduction time, and the same charge leakage amount.

[0102] The leakage circuit 32 provided in the embodiment can leak the common mode level by setting the transistor that can switch the source and the drain. Specifically, the trigger signal controls the first transistor MA1 and the second transistor MA2 to be turned on at the same time, and the common mode levels carried by the second positive signal and the second negative signal are simultaneously leaked. For both positive common mode levels and negative common mode levels, the effect of clamping the common mode level can be achieved.

[0103] Please also refer to FIG. 3. In some embodiments, the first transistor MA1 and the second transistor MA2 are formed based on the same substrate. The purpose of this is to support the first transistor MA1 or the second transistor MA2 to switch the source and the drain. The first transistor MA1 can switch the current source to the drain and switch the current drain to the source. Similarly, the second transistor MA2 can switch the current source to the drain and switch the current drain to the source.

[0104] In some embodiments, please refer to the example in FIG. 3, the trigger circuit 31 includes a first voltage dividing circuit 310 and a second voltage dividing circuit 320.

[0105] The first end of the first voltage dividing circuit 310 receives the second positive signal, and the second end of the first voltage dividing circuit 310 is connected to the second end of the second voltage dividing circuit 320. The second end of the first voltage dividing circuit 310 is used to output the trigger signal. The third end of the first voltage dividing circuit 310 is connected to the first power supply end.

[0106] The first end of the second voltage dividing circuit 320 receives the second negative signal, and the third end of the second voltage dividing circuit 320 is connected to the first power supply end.

[0107] The first voltage dividing circuit 310 is used to divide the second positive signal, and the second voltage dividing circuit 320 is used to divide the second negative signal. The trigger signal is formed when the first voltage dividing circuit 310 divides the second positive signal and the second voltage dividing circuit 320 divides the second negative signal. The second positive signal and the second negative signal are input at the same time, and the trigger signal is formed when the second positive signal and the second negative signal are divided after being input.

[0108] The first voltage dividing circuit 310 and the second voltage dividing circuit 320 have the same voltage dividing capability. The first voltage dividing circuit 310 and the second voltage dividing circuit 320 can be provided with voltage dividing resistors or other voltage dividing devices, and the voltage dividing resistors or other voltage dividing devices provided should meet the requirement that the first voltage dividing circuit 310 and the second voltage dividing circuit 320 have the same voltage dividing capability.

[0109] In some embodiments, referring also to FIG. 3, the first voltage dividing circuit 310 includes a first resistor RA1 and a second resistor RA2. The second voltage dividing circuit 320 includes a third resistor RA3 and a fourth resistor RA4.

[0110] The first end of the first resistor RA1 is the first end of the first voltage dividing circuit 310, and the second end of the first resistor RA1 is connected to the first end of the second resistor RA2. The second end of the first resistor RA1 is the second end of the first voltage dividing circuit 310. The second end of the second resistor RA2 is the third end of the first voltage dividing circuit 310. As shown in FIG. 3, the first end of the first resistor RA1 receives the second positive signal, and the second end of the second resistor RA2 is connected to the first power supply end.

[0111] The first end of the third resistor RA3 is the first end of the second voltage dividing circuit 320, the second end of the third resistor RA3 is connected to the first end of the fourth resistor RA4, the second end of the third resistor RA3 is the second end of the second voltage dividing circuit 320, and the second end of the fourth resistor RA4 is the third end of the second voltage dividing circuit 320. As shown in FIG. 3, the first end of the third resistor RA3 receives the second negative signal, and the second end of the fourth resistor RA4 is connected to the first power supply end.

[0112] The resistance values of the first resistor RA1 and the second resistor RA2 can be different. The resistance values of the third resistor RA3 and the fourth resistor RA4 can be different.

[0113] When the first transistor MA1 and the second transistor MA2 are the same, the first resistance RA1 and the third resistance RA3 should be the same, and the second resistance RA2 and the fourth resistance RA4 should be the same.

[0114] When a positive common-mode level is generated, the first resistance RA1 and the second resistance RA2 divide the voltage, and the third resistance RA3 and the fourth resistance RA4 divide the voltage, so that the gate voltage of the first transistor MA1 and the gate voltage of the second transistor MA2 are both raised, at this time, the common-mode current corresponding to the common-mode level flows to the first power supply end (for example, the ground end), and the common-mode level is clamped.

[0115] When a negative common-mode level is generated, the original source of the first transistor MA1 is switched to the drain, and the original drain is switched to the source, at this time, the common-mode current corresponding to the common-mode level flows from the first power supply end (for example, the ground end) to the second positive signal. Similarly, the original source of the second transistor MA2 is switched to the drain, and the original drain is switched to the source, at this time, the common-mode current corresponding to the common-mode level flows from the first power supply end (for example, the ground end) to the second negative signal.

[0116] In some optional embodiments, the first voltage dividing circuit 310 can further be provided with a resistance, and the second voltage dividing circuit 320 can also be provided with a resistance. If the first voltage dividing circuit 310 is provided with a resistance, the second voltage dividing circuit 320 also needs to be provided with a resistance, and the resistance values of the resistances provided in the first voltage dividing circuit 310 and the second voltage dividing circuit 320 should be the same, and in addition, the connection positions of the resistances should be corresponding.

[0117] The connection positions of the resistances are corresponding, for example, a resistance is provided in the first voltage dividing circuit 310, the first end of the resistance is connected to the first end of the first resistance RA1, and the second end of the resistance receives the second positive signal. Then, a resistance with the same resistance value is provided in the second voltage dividing circuit 320, the first end of the resistance is connected to the first end of the third resistance RA3, and the second end of the resistance receives the second negative signal.

[0118] The voltage dividing circuit provided by the embodiment includes the first voltage dividing circuit 310 and the second voltage dividing circuit 320. The first voltage dividing circuit 310 includes the first resistance RA1 and the second resistance RA2, and the second voltage dividing circuit 320 includes the third resistance RA3 and the fourth resistance RA4. When a positive common-mode level is generated, the common-mode current corresponding to the common-mode level flows to the first power supply end through the first transistor MA1 and the second transistor MA2, so that the effect of clamping the common-mode level is achieved. When a negative common-mode level is generated, the common-mode current flows to the output end of the isolation module through the first transistor MA1 and the second transistor MA2, so that the effect of clamping the common-mode level is achieved.

[0119] In some embodiments, referring to FIG. 4, the receiving module 40 includes a multi-stage differential amplification circuit 41 and a fusion circuit 42.

[0120] The multi-stage differential amplification circuit 41 is configured to perform multi-stage differential amplification on the second differential signal, i.e., to amplify the differential signal transmitted by the isolation module 20.

[0121] As described above, due to the influence of the isolation module 20 and related parasitic parameters, the differential high-frequency signal at the input end of the isolation module 20 is greatly attenuated after being transmitted to the output end, and thus cannot be processed in the next step. Therefore, the attenuated differential signal (i.e., the second differential signal) needs to be amplified so that it can be recognized by the subsequent circuit. The multi-stage differential amplification can be replaced by single-stage differential amplification. The purpose of setting the multi-stage differential amplification is to improve the amplification effect of the second differential signal. The multi-stage differential amplification includes at least two stages of differential amplification.

[0122] The multi-stage differential amplification circuit 41 includes at least two stages of differential amplification circuits. The input end of each stage of differential amplification circuit receives the differential signal output by the previous stage of differential amplification circuit.

[0123] The differential signal output by the previous stage of differential amplification circuit includes a positive signal and a negative signal. The first input end of each stage of differential amplification circuit receives the positive signal, and the second input end of the first stage of differential amplification circuit receives the negative signal. Each stage of differential amplification circuit is configured to amplify the positive signal and the negative signal and output a current stage of differential signal.

[0124] The multi-stage differential amplification circuit 41 can include multiple differential amplifiers or other devices capable of differential amplification.

[0125] In an example, the multi-stage differential amplification circuit 41 compares the voltage difference of the differential signal, thereby reducing the interference of the common-mode level on the signal.

[0126] The fusion circuit 42 is connected to the multi-stage differential amplification circuit and is configured to fuse the amplified differential signal into a single-channel signal. More specifically, the fusion circuit 42 is configured to demodulate the amplified differential signal and output a single-channel signal.

[0127] Please refer to the example of FIG. 5, the fusion circuit 42 can include a logical AND gate circuit 43, through which the amplified differential signals are fused into one signal. The fusion circuit 42 can also include an integrator 44, which receives the one signal output by the logical AND gate circuit 43 and outputs the one signal after restoration. Restoration refers to restoring the signal received from the logical AND gate circuit 43 into a signal of the same type as the first differential signal or the second differential signal, which are signals of the same type. It should be noted that after multi-stage differential amplification of the second differential signal, the output differential signal is of a different type from the second differential signal, for example, the second differential signal is a square wave pulse signal, and after multi-stage differential amplification, the output differential signal is a signal with irregular signal waveform, and the one signal output by the logical AND gate circuit after the differential signal is still a signal with irregular signal waveform, and is not a square wave pulse signal. Therefore, the integrator 44 is needed to restore the one signal output by the logical AND gate circuit 43 and output a single signal.

[0128] In some optional embodiments, the structure of the integrator 44 can be as shown in FIG. 6, including transistors MD1, MD2, MD3, MD4, a capacitor CD1, and a resistor RD1.

[0129] The control end of the transistor MD1 receives the one signal output by the logical AND gate circuit. The first end of the transistor MD1 is connected to a current source AD1. The current source AD1 is powered by a power supply end VCC. The second end of the transistor MD1 is connected to the first end of the transistor MD3 and the control end of the transistor MD3. The second end of the transistor MD3 is grounded.

[0130] The first end of the transistor MD2 is connected to the current source AD1 and the second end of the transistor MD1. The second end of the transistor MD2 is connected to the first end of the transistor MD4. The second end of the transistor MD4 is connected to a power supply end VSS. The control end of the transistor MD4 is connected to the control end of the transistor MD3 and the second end of the transistor MD1.

[0131] The control end of the transistor MD2 is connected to the first end of the capacitor CD1 and the first end of the resistor RD1. The second end of the capacitor CD1 is connected to the second end of the transistor MD2 and the first end of the transistor MD4, and the connection point is used to output a signal. The second end of the resistor RD1 is connected to the first power supply end VSS.

[0132] As shown in FIG. 6, the integrator 44 finally outputs a single signal OUT.

[0133] The receiving module 40 provided by the embodiment includes a multi-stage differential amplification circuit 41 and a fusion circuit 42. The multi-stage differential amplification circuit 41 is configured to perform multi-stage differential amplification on the second differential signal, i.e., amplify the differential signal transmitted by the isolation module 20, so that the differential signal can be recognized by a subsequent circuit. The purpose of setting multi-stage differential amplification is to improve the amplification effect of the differential signal.

[0134] In some embodiments, referring to FIG. 7, the multi-stage differential amplification circuit 41 includes a first-stage differential amplification circuit 410 and a second-stage differential amplification circuit 420. The first-stage differential amplification circuit 410 is configured to perform pre-stage amplification, for example, amplify the second differential signal in the range of 0V-2.5V. The second-stage differential amplification circuit 420 is configured to perform larger-amplitude amplification, for example, amplify the differential signal output by the first-stage differential amplification circuit 410 in the range of 0V-5V.

[0135] After receiving the second differential signal, the first-stage differential amplification circuit 410 outputs a third differential signal, which includes a third positive signal (OUTA+ shown in FIG. 7) and a third negative signal (OUTA- shown in FIG. 7). The differential signal output by the second-stage differential amplification circuit 420 after receiving the third differential signal includes a positive signal OUTB+ and a negative signal OUTB- shown in FIG. 7. The positive signal OUTB+ and the negative signal OUTB- output a single-channel signal after passing through the fusion circuit 42.

[0136] The multi-stage differential amplification circuit 41 provided by the embodiment includes a first-stage differential amplification circuit 410 and a second-stage differential amplification circuit 420. The signals output by the two-stage differential amplification are output to the fusion circuit 42. The first-stage differential amplification circuit 410 performs pre-stage amplification on the second differential signal, and the second-stage differential amplification circuit 420 performs differential amplification on the differential signal after pre-stage amplification. The second differential signal is amplified by two-stage differential amplification, so that the differential signal can be recognized by a subsequent circuit, and the amplification effect of the differential signal is further improved.

[0137] In some embodiments, referring to FIG. 8 and FIG. 9, the first-stage differential amplification circuit 410 includes a first amplification circuit 411 shown in FIG. 8 and a second amplification circuit 412 shown in FIG. 9. The first amplification circuit 411 outputs a third positive signal, and the second amplification circuit 412 outputs a third negative signal. It should be noted that IN+ shown in FIG. 8 represents the second positive signal after common-mode level clamping, and IN- represents the second negative signal after common-mode level clamping.

[0138] Specifically, the first input end of the first amplification circuit 411 receives the second negative signal (IN- shown in FIG. 8), and the second input end of the first amplification circuit 411 receives the second positive signal (IN+ shown in FIG. 8). The first amplification circuit 411 is configured to generate a third positive signal (OUTA+ shown in FIG. 8) according to the difference between the second negative signal and the second positive signal.

[0139] Specifically, the first input end of the second amplification circuit 412 receives the second positive signal (IN+ shown in FIG. 8), and the second input end of the second amplification circuit 412 receives the second negative signal (IN- shown in FIG. 8). The second amplification circuit 412 is configured to generate a third negative signal (OUTA- shown in FIG. 8) according to the difference between the second positive signal and the second negative signal.

[0140] In an example, the first amplification circuit 411 and the second amplification circuit 412 have the same structure.

[0141] The first amplification circuit 411 is described in detail as follows.

[0142] The first amplification circuit 411 can be configured with one-stage or multiple-stage amplification sub-circuits, and the second amplification circuit 412 can also be configured with one-stage or multiple-stage amplification sub-circuits. However, the amplification degrees of the first amplification circuit 411 and the second amplification circuit 412 need to be the same.

[0143] In some embodiments, the first amplification circuit 411 includes a first-stage sub-circuit 413. The first input end of the first-stage sub-circuit 413 receives the second positive signal, and the second input end of the first-stage sub-circuit 413 receives the second negative signal. The first-stage sub-circuit 413 generates a third positive signal according to the second positive signal and the second negative signal, specifically, according to the difference between the second positive signal and the second negative signal.

[0144] In some embodiments, the first amplification circuit 411 can further include more-stage sub-circuits, which can be configured according to actual signal amplification requirements.

[0145] The second amplification circuit 412 is described in detail as follows.

[0146] The second amplification circuit 412 can be configured with one-stage or multiple-stage amplification sub-circuits. However, the amplification degrees of the first amplification circuit 411 and the second amplification circuit 412 need to be the same.

[0147] In some embodiments, the second amplification circuit 412 includes a first-stage sub-circuit 413. A first input terminal of the first-stage sub-circuit 413 receives the second positive signal, and a second input terminal of the first-stage sub-circuit 413 receives the second negative signal. The first-stage sub-circuit 413 generates a third negative signal according to the second positive signal and the second negative signal, specifically, according to the voltage difference between the second positive signal and the second negative signal.

[0148] In some embodiments, the first amplification circuit 411 can further include more stages of sub-circuits, which can be set according to actual signal amplification requirements.

[0149] In the above, the first-stage differential amplification circuit 410 provided by the embodiment includes the first amplification circuit 411 and the second amplification circuit 412. The first amplification circuit 411 is configured to generate a third positive signal according to the voltage difference between the second negative signal and the second positive signal. The second amplification circuit 412 is configured to generate a third negative signal according to the voltage difference between the second positive signal and the second negative signal. The third differential signal output by the first-stage differential amplification circuit 410 includes the third positive signal and the third negative signal. By amplifying the second differential signal through the first-stage differential amplification circuit 410, the signal strength can be effectively improved, so that the differential signal can be recognized by subsequent circuits.

[0150] The following will be described in detail for the case that the first amplification circuit 411 includes different numbers of sub-circuits.

[0151] The first case: the first amplification circuit 411 only includes the first-stage sub-circuit 413.

[0152] Please refer to FIG. 8. At this time, the first-stage sub-circuit 413 can include a third pull-up circuit 423 and a third pull-down circuit 424.

[0153] A first terminal of the third pull-up circuit 423 is connected to a power supply terminal (such as VCC shown in FIG. 8), and a second terminal of the third pull-up circuit 423 is connected to a first terminal of the third pull-down circuit 424.

[0154] A control terminal of the third pull-down circuit 424 receives the second negative signal, and a second terminal of the third pull-down circuit 424 receives the second positive signal. A first terminal of the third pull-down circuit 424 outputs the third positive signal.

[0155] The third pull-down circuit 424 adjusts the downward driving capability of the second positive signal to the first terminal of the third pull-down circuit 424 under the control of the second negative signal.

[0156] The third pull-up circuit 423 is configured to amplify the voltage difference signal output by the third pull-down circuit 424, which is the amplified signal of the voltage difference between the second negative signal and the second positive signal.

[0157] As shown in FIG. 8, the third pull-down circuit 424 includes a first capacitor CB1 and a third transistor MB1.

[0158] The first end of the first capacitor CB1 receives the second negative signal, and the second end is connected to the control end of the third transistor MB1. The first end of the first capacitor CB1 is the first end of the third pull-down circuit 424.

[0159] The first end of the third transistor MB1 is connected to the second end of the third pull-up circuit 423. The second end of the third transistor MB1 receives the second positive signal. The control end of the third transistor MB1 is connected to the second end of the first capacitor CB1. The third transistor MB1 can be an NMOS transistor as shown in FIG. 8, the gate (control end) of which is connected to the second end of the first capacitor CB1, the source receives the second positive signal, and the drain is connected to the second end of the third pull-up circuit 423.

[0160] The third transistor MB1 outputs the difference between the second negative signal and the second positive signal when it is turned on.

[0161] As shown in FIG. 8, the third pull-up circuit 423 includes a transistor (MB2 as shown in FIG. 8) and a capacitor (CB2 as shown in FIG. 8). The first end of the capacitor is connected to the power supply end, and the second end is connected to the control end of the transistor. The first end of the transistor is connected to the power supply end and the first end of the capacitor, and the second end of the transistor is connected to the first end of the third transistor MB1.

[0162] The transistor can be a PMOS transistor as shown in FIG. 8, the first end of which is the source, and the second end of which is the drain.

[0163] When the transistor is turned on, the third pull-up circuit 423 outputs a stable voltage signal, which is used to amplify the voltage difference signal output by the third transistor MB1.

[0164] The third pull-up circuit 423 can also be provided with a resistor RB1 as shown in FIG. 8, which acts as a load to further enhance the amplification effect of the voltage difference signal.

[0165] As shown in FIG. 10, in some embodiments, the third pull-down circuit 424 further includes a second capacitor CB3 and a fourth transistor MB3.

[0166] The first end of the second capacitor CB3 receives the second negative signal, and the second end is connected to the control end of the fourth transistor MB3. The first end of the fourth transistor MB3 is connected to the first end of the third transistor MB1, and the second end receives the second positive signal.

[0167] After the fourth transistor MB3 is turned on, the voltage difference signal between the second negative signal and the second positive signal is input to the first end of the third transistor MB1 after being amplified by the fourth transistor MB3. After the third transistor MB1 is turned on, the voltage difference signal between the second negative signal and the voltage difference signal output by the fourth transistor MB3 is output, and the voltage difference signal is further amplified by the third transistor MB1. That is, the second capacitor CB3 and the fourth transistor MB3 provided in the embodiment can further improve the amplification effect of the voltage difference signal.

[0168] The third transistor MB1 and the fourth transistor MB3 can both be NMOS tubes. The control end of the fourth transistor MB3 is the gate, the first end is the drain, and the second end is the source.

[0169] Please refer to FIG. 11. In some embodiments, the first-stage sub-circuit 413 further includes a preset voltage circuit 419.

[0170] The first end of the preset voltage circuit 419 receives the second negative signal, and the second end of the preset voltage circuit 419 is connected to the control end of the third pull-down circuit 424. The control end of the third pull-down circuit 424 is the control end of the fourth transistor MB3.

[0171] The preset voltage circuit 419 is used to generate a preset voltage at the control end of the third pull-down circuit 424 according to the second negative signal. The preset voltage output by the preset voltage circuit 419 is input to the gate of the fourth transistor MB3, so as to further improve the amplification effect of the voltage difference signal.

[0172] The preset voltage circuit 419 can include a fifth transistor MB4 and a sixth transistor MB5 (such as the transistor MB5 shown in FIG. 11). The control end of the fifth transistor MB4 is connected to the other end of the second capacitor CB3, the first end receives the second negative signal, and the second end is connected to the first end of the sixth transistor MB5. The control end of the sixth transistor MB5 is connected to the other end of the first capacitor CB1, and the second end is connected to the control end of the fourth transistor MB3.

[0173] The fifth transistor MB4 and the sixth transistor MB5 can both be NMOS tubes. The gate of the fifth transistor MB4 is connected to the second end of the second capacitor CB3, the source receives the second negative signal, and the drain is connected to the source of the sixth transistor MB5. The gate of the sixth transistor MB5 is connected to the second end of the first capacitor CB1, and the drain is connected to the gate of the fourth transistor MB3.

[0174] In some optional embodiments, the preset voltage circuit 419 can further include a resistor RB2 and a current source Al as shown in FIG. 11, and the current source Al in FIG. 11 provides the required power for the resistor RB2. The current source Al takes power from the power supply end VCC. The first end of the resistor RB2 is connected to the current source Al, and the second end is connected to the control end of the fourth transistor MB3. At this time, the input signal of the fourth transistor MB3 includes the signal output by the second end of the first capacitor CB1 and the signal output by the second end of the resistor RB2.

[0175] The design of the preset voltage circuit 419 provided by the present embodiment can further improve the amplification effect of the voltage difference signal.

[0176] The second case: please refer to FIG. 12, the first amplification circuit 411 includes a first-stage sub-circuit 413 and a second-stage sub-circuit 414. The specific structure of the first amplification circuit 411 can be any of the structures shown above or any variation of the structures, which is not limited by the present embodiment. At this time, the first amplification circuit 411 is used to output an intermediate signal, and the second-stage sub-circuit 414 is used to amplify the intermediate signal and output a third positive signal.

[0177] Please refer to FIG. 12, the input end of the second-stage sub-circuit 414 is connected to the output end of the first-stage sub-circuit 413, and the second-stage sub-circuit 414 is used to amplify the signal output by the first-stage sub-circuit 413 and output the third positive signal.

[0178] The second-stage sub-circuit 414 includes a second pull-up circuit 421 and a second pull-down circuit 422. The first end of the second pull-up circuit 421 is connected to a power supply end (such as VSS shown in FIG. 12), and the second end of the second pull-up circuit 421 is connected to the first end of the third pull-down circuit 424. The second end of the second pull-down circuit 422 is connected to a second power supply end (such as A3 shown in FIG. 12).

[0179] The control end of the second pull-down circuit 422 receives the signal output by the first-stage sub-circuit 413. The first end of the second pull-down circuit 422 outputs the third positive signal.

[0180] The second pull-down circuit 422 adjusts the downward driving capability of the second power supply end to the second end of the second pull-down circuit 422 under the control of the second negative signal, and the first end of the second pull-down circuit 422 outputs the third positive signal.

[0181] In some embodiments, the second pull-down circuit 422 includes a seventh transistor MB6. The second pull-up circuit 421 includes an eighth transistor MB7 and a third capacitor CB4. The control terminal of the seventh transistor MB6 is the control terminal of the second pull-down circuit 422, and receives the signal output by the first-stage sub-circuit 413. The first terminal of the seventh transistor MB6 is connected to the second power supply terminal, and the second terminal is connected to the first terminal of the eighth transistor MB7. The control terminal of the eighth transistor MB7 is connected to the first terminal of the third capacitor CB4, and the second terminal is connected to the power supply terminal. The second terminal of the third capacitor CB4 is connected to the power supply terminal.

[0182] The seventh transistor MB6 can be an NMOS transistor as shown in FIG. 12, the gate being the control terminal, the source being the second terminal, and the drain being the second terminal. The eighth transistor MB7 can be a PMOS transistor as shown in FIG. 12, the gate being the control terminal, the drain being the first terminal, and the source being the second terminal.

[0183] A resistor RB3 as shown in FIG. 12 can also be provided to further improve the amplification effect of the voltage difference signal.

[0184] When the first amplification circuit 411 provided in the embodiment includes the first-stage sub-circuit 413 and the second-stage sub-circuit 414, the voltage difference signal between the second positive signal and the second negative signal is amplified once by the first-stage sub-circuit 413, and the voltage difference signal amplified by the first-stage sub-circuit 413 is amplified again by the second-stage sub-circuit 414, thereby further improving the amplification effect of the voltage difference signal.

[0185] The following will be described in detail with respect to the case where the second amplification circuit 412 includes different numbers of sub-circuits.

[0186] First case: please refer to FIG. 9. The second amplification circuit 412 only includes a third-stage sub-circuit 415.

[0187] The first input terminal of the third-stage sub-circuit 415 receives the second negative signal, the second input terminal of the third-stage sub-circuit 415 receives the second positive signal, and the third-stage sub-circuit 415 generates a third negative signal according to the second negative signal and the second positive signal.

[0188] Please refer to FIG. 9. The third-stage sub-circuit 415 can include a fourth pull-up circuit 425 and a fourth pull-down circuit 426.

[0189] The first terminal of the fourth pull-up circuit 425 is connected to the power supply terminal (VCC as shown in FIG. 9), and the second terminal of the fourth pull-up circuit 425 is connected to the first terminal of the fourth pull-down circuit 426.

[0190] The control end of the fourth pull-down circuit 426 receives the second forward signal, and the second end of the fourth pull-down circuit 426 receives the second reverse signal. The first end of the fourth pull-down circuit 426 outputs the third reverse signal.

[0191] The fourth pull-down circuit 426 adjusts the downward driving capability of the second forward signal to the first end of the fourth pull-down circuit 426 under the control of the second reverse signal.

[0192] The fourth pull-up circuit 425 is used to amplify the voltage difference signal output by the fourth pull-down circuit 426, which is the voltage difference signal of the second forward signal minus the second reverse signal.

[0193] As shown in FIG. 9, the fourth pull-down circuit 426 includes a fourth capacitor CB5 and a ninth transistor MB8.

[0194] The first end of the fourth capacitor CB5 receives the second forward signal, and the second end is connected to the control end of the ninth transistor MB8. The first end of the fourth capacitor CB5 is the first end of the fourth pull-down circuit 426.

[0195] The first end of the ninth transistor MB8 is connected to the second end of the fourth pull-up circuit 425. The second end of the ninth transistor MB8 receives the second forward signal. The control end of the ninth transistor MB8 is connected to the second end of the fourth capacitor CB5. The ninth transistor MB8 can be an NMOS tube as shown in FIG. 9, the gate (control end) of which is connected to the second end of the fourth capacitor CB5, the source receives the second forward signal, and the drain is connected to the second end of the fourth pull-up circuit 425.

[0196] The ninth transistor MB8 outputs the voltage difference between the second reverse signal and the second forward signal when it is turned on.

[0197] Also see FIG. 13, the fourth pull-up circuit 425 includes a transistor MB9 and a capacitor CB6. The first end of the capacitor CB6 is connected to the power supply end, and the second end is connected to the control end of the transistor MB9. The first end of the transistor MB9 is connected to the power supply end and the first end of the capacitor CB6, and the second end of the transistor MB9 is connected to the first end of the third transistor MB1.

[0198] The transistor MB9 can be a PMOS tube as shown in FIG. 13, the first end of which is the source, and the second end of which is the drain.

[0199] When the transistor MB9 is turned on, the fourth pull-up circuit 425 outputs a stable voltage signal, which is used to amplify the voltage difference signal output by the ninth transistor MB8.

[0200] The fourth pull-up circuit 425 can also be provided with a resistor RB4 as shown in FIG. 13, where the RB4 functions as a load, and the effect is to further enhance the amplification of the voltage difference signal.

[0201] Referring to FIG. 13, in some embodiments, the fourth pull-down circuit 426 further includes a fifth capacitor CB7 and a tenth transistor MB10.

[0202] The first end of the fifth capacitor CB7 receives the second negative signal, and the second end is connected to the control end of the tenth transistor MB10. The first end of the tenth transistor MB10 is connected to the first end of the ninth transistor MB8, and the second end receives the second positive signal.

[0203] After the tenth transistor MB10 is turned on, the voltage difference signal between the second negative signal and the second positive signal is amplified by the tenth transistor MB10 and input to the first end of the ninth transistor MB8. After the ninth transistor MB8 is turned on, the voltage difference signal between the second negative signal and the voltage difference signal output by the tenth transistor MB10 is output, and the ninth transistor MB8 further amplifies the voltage difference signal. That is, the fifth capacitor CB7 and the tenth transistor MB10 provided in this embodiment can further enhance the amplification of the voltage difference signal.

[0204] The ninth transistor MB8 and the tenth transistor MB10 can both be NMOS transistors. The control end of the tenth transistor MB10 is the gate, the first end is the drain, and the second end is the source.

[0205] Referring to FIG. 14, in some embodiments, the third-stage sub-circuit 415 further includes another preset voltage circuit 430.

[0206] The first end of the another preset voltage circuit 430 receives the second positive signal, and the second end of the another preset voltage circuit 430 is connected to the control end of the third pull-down circuit 424. The control end of the third pull-down circuit 424 is the control end of the tenth transistor MB10.

[0207] The another preset voltage circuit 430 is configured to generate a preset voltage at the control end of the third pull-down circuit 424 according to the second positive signal. The preset voltage output by the another preset voltage circuit 430 is input to the gate of the tenth transistor MB10, so as to further enhance the amplification of the voltage difference signal.

[0208] The another preset voltage circuit 430 can include an eleventh transistor MB11 and a twelfth transistor MB12. The control end of the eleventh transistor MB11 is connected to the other end of the fifth capacitor CB7, the first end receives the second positive signal, and the second end is connected to the first end of the twelfth transistor MB12. The control end of the twelfth transistor MB12 is connected to the other end of the fourth capacitor CB5, and the second end is connected to the control end of the tenth transistor MB10.

[0209] The eleventh transistor MB11 and the twelfth transistor MB12 can both be NMOS tubes. The gate of the eleventh transistor MB11 is connected to the second end of the fifth capacitor CB7, the source receives the second negative signal, and the drain is connected to the source of the eleventh transistor MB12. The gate of the twelfth transistor MB12 is connected to the second end of the fourth capacitor CB5, and the drain is connected to the gate of the tenth transistor MB10.

[0210] In some optional embodiments, a resistor RB5 and a current source A2 as shown in FIG. 14 can also be provided. The current source A2 in FIG. 14 provides the required electrical energy for the branch where the resistor RB5 is located. The current source A2 takes electricity from the power supply end VCC. The first end of the resistor RB5 is connected to the current source A2, and the second end is connected to the control end of the tenth transistor MB10. At this time, the signal input by the tenth transistor MB10 includes the signal output by the second end of the first capacitor CB1 and the signal output by the second end of the resistor RB5. The resistor RB5 is provided to amplify the amplification multiple of the voltage difference signal.

[0211] The design of the another preset voltage circuit 430 provided in the embodiment can further improve the amplification effect of the voltage difference signal.

[0212] The second case: the second amplification circuit 412 includes a third-level sub-circuit 415 and a fourth-level sub-circuit 416. The specific structure of the second amplification circuit 412 can be any of the structures shown above or a variation of any of the structures, which is not limited in the embodiment. At this time, the signal output by the second amplification circuit 412 is not the third negative signal, and the fourth-level sub-circuit 416 outputs the third negative signal.

[0213] Please refer to FIG. 15. The input end of the fourth-level sub-circuit 416 is connected to the output end of the third-level sub-circuit 415. The fourth-level sub-circuit 416 is used to amplify the signal output by the third-level sub-circuit 415 and output the third positive signal.

[0214] The fourth-stage sub-circuit 416 includes a fifth pull-up circuit 427 and a fifth pull-down circuit 428. The first terminal of the fifth pull-up circuit 427 is connected to a power supply terminal (VSS as shown in Figure 15), and the second terminal of the fifth pull-up circuit 427 is connected to the first terminal of the fifth pull-down circuit 428. The second terminal of the fifth pull-down circuit 428 is connected to a second power supply terminal (A3 as shown in Figure 15). This second power supply terminal is used to make the voltage difference signal more differential.

[0215] The control terminal of the fifth pull-down circuit 428 receives the signal output from the third-stage sub-circuit 415. The first terminal of the fifth pull-down circuit 428 outputs a third positive signal.

[0216] The fifth pull-down circuit 428 adjusts the downward driving capability of the second power supply terminal to the second terminal of the fifth pull-down circuit 428 under the control of the second positive signal, and the first terminal of the fifth pull-down circuit 428 outputs the third negative signal.

[0217] In some embodiments, the fifth pull-down circuit 428 includes a thirteenth transistor MB13. The fifth pull-up circuit 427 includes a fourteenth transistor MB14 and a sixth capacitor CB8. The control terminal of the thirteenth transistor MB13 is the control terminal of the fifth pull-down circuit 428, receiving the signal output from the third-stage sub-circuit 415. The first terminal of the thirteenth transistor MB13 is connected to the second power supply terminal, and the second terminal is connected to the first terminal of the fourteenth transistor MB14. The control terminal of the fourteenth transistor MB14 is connected to the first terminal of the sixth capacitor CB8, and the second terminal is connected to the power supply terminal. The second terminal of the sixth capacitor CB8 is connected to the power supply terminal.

[0218] The thirteenth transistor MB13 can be an NMOS transistor as shown in Figure 15, with the gate as the control terminal, the source as the second terminal, and the drain as the second terminal. The fourteenth transistor MB14 can be a PMOS transistor as shown in Figure 15, with the gate as the control terminal, the drain as the first terminal, and the source as the second terminal.

[0219] You can also set resistor RB6 as shown in Figure 15 to further enhance the amplification effect of the differential pressure signal.

[0220] When the second amplifier circuit 412 provided in this embodiment includes a third-stage sub-circuit 415 and a fourth-stage sub-circuit 416, the voltage difference signal between the second positive signal and the second negative signal is amplified once by the third-stage sub-circuit 415, and then the voltage difference signal amplified by the third-stage sub-circuit 415 is amplified again by the fourth-stage sub-circuit 416, thereby further improving the amplification effect of the voltage difference signal.

[0221] Please refer to FIG. 16, in some embodiments of the present application, the second stage differential amplification circuit 420 in the multi-stage differential amplification circuit 41 comprises a cross-coupled circuit 450 and a back-end amplification circuit 451.

[0222] The first input end of the cross-coupled circuit 450 receives the third positive signal, and the second input end of the cross-coupled circuit 450 receives the third negative signal. The first output end of the cross-coupled circuit 450 is connected to the first input end of the back-end amplification circuit 451, and the second output end of the cross-coupled circuit 450 is connected to the second input end of the back-end amplification circuit 451.

[0223] The cross-coupled circuit 450 is configured to output a voltage difference signal of the third positive signal and the third negative signal to the back-end amplification circuit 451, and output a voltage difference signal of the third negative signal and the third positive signal to the back-end amplification circuit 451. Correspondingly, the back-end amplification circuit 451 simultaneously and with the same amplitude amplifies the two voltage difference signals, respectively.

[0224] The back-end amplification circuit 451 outputs the fourth positive signal according to the signal of the first input end, specifically, outputs the fourth positive signal based on the voltage difference signal of the third positive signal and the third negative signal. The back-end amplification circuit 451 outputs the fourth negative signal according to the signal of the second input end. Specifically, outputs the fourth negative signal based on the voltage difference signal of the third negative signal and the third positive signal.

[0225] The cross-coupled circuit 450 and the back-end amplification circuit 451 can be the structure as shown in FIG. 16, or a variation of the structure as shown in FIG. 16.

[0226] As shown in FIG. 16, the cross-coupled circuit 450 comprises a fourteenth transistor MC1, a fifteenth transistor MC2, a resistor RC1 as shown in FIG. 16, and a resistor RC2 as shown in FIG. 16. The back-end amplification circuit 451 comprises a sixteenth transistor MC3 and a seventeenth transistor MC4.

[0227] The control end (gate) of the fourteenth transistor MC1 receives the third negative signal, the first end (source) receives the third positive signal, and the second end (drain) is connected to the first end of the resistor RC1. The second end of the resistor RC1 is connected to the power supply end (VCC as shown in FIG. 16).

[0228] The control end (gate) of the fifteenth transistor MC2 receives the third positive signal, the first end (source) receives the third negative signal, and the second end (drain) is connected to the first end of the resistor RC2. The second end of the resistor RC2 is connected to the power supply end (VCC as shown in FIG. 16).

[0229] The control end of the sixteenth transistor MC3 is connected with the first end of the resistor RC1 and the second end of the fourteenth transistor, so as to receive the voltage difference signal output by the fourteenth transistor. The first end of the sixteenth transistor MC3 is connected with the power supply end AC1, and the second end is connected with the power supply end VCC.

[0230] The control end of the seventeenth transistor MC4 is connected with the first end of the resistor RC2 and the second end of the fifteenth transistor MC2, so as to receive the voltage difference signal output by the fifteenth transistor MC2. The first end of the seventeenth transistor MC4 is connected with the power supply end AC2, and the second end is connected with the power supply end VCC.

[0231] The second differential amplification circuit 420 provided by the embodiment includes a cross-coupled circuit 450 and a rear-end amplification circuit 451. The cross-coupled circuit 450 is configured to output a voltage difference signal of the third positive signal and the third negative signal, and output a voltage difference signal of the third negative signal and the third positive signal. The rear-end amplification circuit 451 is configured to amplify the two voltage difference signals respectively, output a fourth positive signal based on the voltage difference signal of the third positive signal and the third negative signal, and output a fourth negative signal based on the voltage difference signal of the third positive signal and the third negative signal. Compared with the first differential amplification circuit 410, the second differential amplification circuit 420 has a larger amplification range, can further amplify the differential signal, so that the differential signal can be recognized by the subsequent circuit. In addition, through the cross structure of the cross-coupled circuit 450, the interference of the common mode level can be further reduced.

[0232] Please refer to FIG. 17, the signal transmission circuit 10 provided by one embodiment of the present application further includes an input module 50.

[0233] The input end of the input module 50 receives an input signal, and the output end of the input module 50 is connected with the isolation module and outputs the first differential signal after modulating the input signal.

[0234] The input signal can be a square wave pulse signal as shown in FIG. 18. The input module 50 can include an oscillator 51 and a logic circuit 52 as shown in FIG. 17.

[0235] If the input signal is a square wave pulse signal as shown in FIG. 18, the oscillator 51 is configured to output a continuous and high-frequency oscillation signal as shown in FIG. 19. The oscillator 51 can be a ring oscillator 51 or the like. The signal frequency of the oscillator 51 can be adjusted according to the internal resistance and capacitance and the like. The signal frequency of the input signal is lower than the signal frequency of the oscillator 51, and the pulse width is at least 2 periods of the oscillator 51, so as to ensure the transmission of the signal.

[0236] The logic circuit 52 includes a logic AND gate circuit and a logic NOT gate circuit. After the input signal and the oscillation signal enter the logic circuit 52, a signal is output through the logic AND gate circuit, and a signal is output through the logic NOT gate circuit. The two signals are differential signals, and the pulse widths of the two signals are close to each other. The logic circuit 52 outputs the differential signal shown in FIG. 20. The differential signal shown in FIG. 20 is the first differential signal. The first differential signal is input to the isolation module 20.

[0237] In some optional embodiments, the input module 50 can further include the drive circuit 53 shown in FIG. 17. In this case, the drive circuit 53 outputs the first differential signal. The waveform of the first differential signal output by the drive circuit 53 is approximately consistent with the waveform of the signal output by the logic circuit 52, and the main difference is that the drive capability is enhanced. The drive circuit 53 is used to further improve the strength of the differential signal output by the logic circuit 52.

[0238] It should be noted that when the high-voltage isolation capacitor is designed in the isolation module 20, the high-voltage isolation capacitor can achieve very high voltage resistance, so that the transient disturbance on the secondary side can be prevented from being transmitted to the primary side, and the circuit in the input module 50 can be protected from damage. In addition, the input module 50 processes the input signal into a differential signal, and transmits the differential signal to the isolation module 20, so that the common-mode level interference can be reduced.

[0239] Please refer to FIG. 21 and FIG. 22. In some embodiments of the present application, the signal transmission circuit further includes the filter circuit 45 shown in FIG. 21.

[0240] The filter circuit 45 is used to filter the second differential signal output by the isolation module 20.

[0241] The filter circuit 45 can be a high-pass filter. As shown in FIG. 22, the filter circuit 45 includes a resistor R1 and a resistor R2. The first end of the resistor R1 receives the second positive signal, and the second end is grounded. The first end of the resistor R2 receives the second negative signal, and the second end is grounded. The resistor R1, the resistor R2 and the isolation capacitor in the isolation module 20 form a high-pass filter, which can greatly attenuate the interference of low-frequency signals.

[0242] It should be noted that the filter circuit 45 connected to the input end of the receiving module 40 must match the two signal channels to prevent signal failure.

[0243] The filter circuit 45 is preferably arranged between the isolation module 20 and the clamping module 30, and can also be arranged at other positions according to actual needs, which is not limited in the present embodiment.

[0244] The filter circuit 45 provided in the present embodiment can also be other filters as long as it can attenuate the interference of low-frequency signals.

[0245] Please refer to Figure 23, some embodiments of the present application further provide a signal transmission system 60.

[0246] The signal transmission system 60 comprises the signal transmission circuit 10 provided by any one of the above embodiments, further comprises a controller 61, a driving module 62 and a power device 63.

[0247] The output end of the controller 61 is connected with the input end of the signal transmission circuit 10. The controller 61 can be a microcontroller unit (MCU). The output signal of the controller 61 is a square wave pulse signal.

[0248] The input end of the driving module 62 is connected with the output end of the signal transmission circuit 10, and receives the single-channel signal output by the signal transmission circuit 10. Please refer to the above description of the single-channel signal output by the receiving module 40, and the single-channel signal output by the signal transmission circuit 10 is a square wave pulse signal. The driving module 62 is used to output the signal output by the signal transmission circuit 10 to the power device 63 after voltage boosting, so as to drive the power device 63 to run. That is, the driving module 62 is used to further drive the square wave pulse signal to meet the use requirements of the power device 63.

[0249] The power device 63 is, for example, a silicon carbide power device, an insulate-gate bipolar transistor (IGBT).

[0250] The signal transmission system 60 provided by the present embodiment, the transient interference generated by the switching moment of the power device 63 is clamped by the signal transmission circuit 10, so as not to damage the signal transmission circuit 10. Compared with the existing signal transmission system 60, the safety is higher, and the practicability is stronger.

[0251] Please refer to Figure 24, some embodiments of the present application further provide an electric control system 70 of a vehicle, the electric control system 70 comprises the signal transmission system 60 provided by any one of the above embodiments, and can further comprise a load 71. The load 71 is, for example, a motor.

[0252] As shown in Figure 24, the power device 63 can be an IGBT as shown in Figure 24, and the IGBT is connected with the motor on the vehicle.

[0253] Some embodiments of the present application further provide a vehicle, as shown in Figure 25, the vehicle 100 comprises the electric control system 70 of the vehicle as described above. The vehicle can also be provided with other functions, such as head-up display function, adaptive cruise control function, active brake function, etc., which are not limited by the present embodiment.

[0254] According to some embodiments of the present application, referring to FIG. 25, the vehicle 100 further comprises a battery 102 and a charger 101, the electric control system 70 is connected to the charger 101 and the battery 102, and the charger 101 is connected to the battery 102. The electric control system 70 can monitor the state of the battery 102 and control the charging parameters of the charger 101 according to the state of the battery 102, and the charger 101 charges the battery 102 according to the charging parameters.

[0255] For example, the electric control system 70 can comprise a battery management system (BMS) for monitoring the state of the battery 101, such as voltage, current, temperature, state of charge, etc., and the battery management system can also communicate with the charger 101 to enable the charger 101 to adjust the charging parameters.

[0256] The electric control system can also comprise a vehicle control unit (VCU) responsible for the management and coordination of the overall vehicle, including the control of the powertrain, energy management, regenerative braking, thermal management, etc. It can also comprise a motor controller that controls the operation of the drive motor, including adjusting the current and voltage to control the speed and torque of the motor.

[0257] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, and not to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand: it can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement to part or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A signal transmission circuit, wherein, The application relates to an isolation module (20), a clamping module (30) and a receiving module (40). The isolation module (20) is used for receiving a first differential signal and outputting a second differential signal after electrically isolating the first differential signal, wherein the second differential signal comprises a second positive signal and a second negative signal. The clamping module (30) is connected with the output end of the isolation module (20) and is used for clamping the common-mode level of the second positive signal and the second negative signal according to the second positive signal and the second negative signal. The receiving module (40) is connected with the output end of the isolation module (20) and is used for outputting after demodulating the second differential signal. The clamping module (30) is used for adjusting the common-mode level of the second positive signal and the second negative signal when the absolute value of the common-mode level of the second positive signal and the second negative signal is greater than a preset level threshold.

2. The signal transmission circuit according to claim 1, wherein The clamping module (30) is used for adjusting the common-mode level clamping amount according to the second positive signal and the second negative signal and adjusting the common-mode level of the second positive signal and the second negative signal according to the common-mode level clamping amount.

3. The signal transmission circuit according to claim 1 or 2, wherein The clamping module (30) comprises a trigger circuit (31) and a discharge circuit (32).

4. The signal transmission circuit according to any one of claims 1 to 3, wherein, The first input end of the trigger circuit (31) receives the second positive signal, the second input end of the trigger circuit (31) receives the second negative signal, and the trigger circuit (31) is used for outputting a trigger signal. The control end of the discharge circuit (32) is connected with the output end of the trigger circuit (31), the first end of the discharge circuit (32) receives the second positive signal, the second end of the discharge circuit (32) receives the second negative signal, the third end of the discharge circuit (32) is connected with a first power supply end, the discharge circuit (32) controls the charge discharge amount between the first end and the third end of the discharge circuit (32) according to the trigger signal, and the discharge circuit (32) controls the charge discharge amount between the second end and the third end of the discharge circuit (32) according to the trigger signal. When the common-mode level of the second positive signal and the second negative signal is greater than the voltage of the first power supply end, the discharge circuit (32) forms a discharge path from the first end to the third end, and the discharge circuit (32) forms a discharge path from the second end to the third end.

5. The signal transmission circuit of claim 4, wherein, When the common-mode level of the second positive signal and the second negative signal is less than the voltage of the first power supply end, the discharge circuit (32) forms a discharge path from the third end to the first end, and the discharge circuit (32) forms a discharge path from the third end to the first end.

6. The signal transmission circuit according to claim 4 or 5, wherein The discharge circuit (32) comprises a first transistor and a second transistor.

7. The signal transmission circuit according to any one of claims 4-6, wherein, ​ The control end of the first transistor is connected to the control end of the second transistor, the control end of the first transistor and the control end of the second transistor both receive the trigger signal, the first end of the first transistor is the first end of the bleed circuit (32), the first end of the second transistor is the second end of the bleed circuit, and the second end of the first transistor and the second end of the second transistor are both connected to the first power supply end.

8. The signal transmission circuit of claim 7, wherein, The first transistor and the second transistor are formed based on the same substrate.

9. The signal transmission circuit according to any one of claims 4-8, wherein, The trigger circuit (31) comprises a first voltage dividing circuit (310) and a second voltage dividing circuit (320); The first end of the first voltage dividing circuit (310) receives the second positive signal, the second end of the first voltage dividing circuit (310) is connected to the second end of the second voltage dividing circuit (320), and the second end of the first voltage dividing circuit (310) is used for outputting the trigger signal; the third end of the first voltage dividing circuit (310) is connected to the first power supply end; The first end of the second voltage dividing circuit (320) receives the second negative signal, and the third end of the second voltage dividing circuit (320) is connected to the first power supply end.

10. The signal transmission circuit of claim 9, wherein, The first voltage dividing circuit (310) comprises a first resistor and a second resistor; The first end of the first resistor is the first end of the first voltage dividing circuit (310), the second end of the first resistor is connected to the first end of the second resistor, the second end of the first resistor is the second end of the first voltage dividing circuit (310), and the second end of the second resistor is the third end of the first voltage dividing circuit (310).

11. The signal transmission circuit according to claim 9 or 10, wherein The second voltage dividing circuit (320) comprises a third resistor and a fourth resistor; The first end of the third resistor is the first end of the second voltage dividing circuit (320), the second end of the third resistor is connected to the first end of the fourth resistor, the second end of the third resistor is the third end of the second voltage dividing circuit (320), and the second end of the fourth resistor is the third end of the second voltage dividing circuit (320).

12. The signal transmission circuit according to any one of claims 1-11, wherein, The receiving module (40) comprises a multi-stage differential amplification circuit (41) and a fusion circuit (42); The multi-stage differential amplification circuit (41) is used for multi-stage differential amplification of the second differential signal; The fusion circuit (42) is connected with the multi-stage differential amplification circuit (41) and is used for fusing the amplified differential signal into a single-channel signal output.

13. The signal transmission circuit of claim 12, wherein, The first-stage differential amplification circuit (410) in the multi-stage differential amplification circuit (41) outputs a third differential signal, and the third differential signal comprises a third positive signal and a third negative signal.

14. The signal transmission circuit of claim 13, wherein, The first-stage differential amplification circuit comprises a first amplification circuit (411) and a second amplification circuit (412); The first input end of the first amplification circuit (411) receives the second negative signal, the second input end of the first amplification circuit (411) receives the second positive signal, and the first amplification circuit (411) is used for generating a third positive signal according to the difference between the second negative signal and the second positive signal; A first input end of the second amplification circuit (412) receives the second positive signal, a second input end of the second amplification circuit (412) receives the second negative signal, and the second amplification circuit (412) is configured to generate a third negative signal according to a difference between the second positive signal and the second negative signal.

15. The signal transmission circuit of claim 14, wherein, The first amplification circuit (411) and the second amplification circuit (412) are of the same structure.

16. The signal transmission circuit according to claim 14 or 15, wherein, The first amplification circuit (411) comprises a first-stage sub-circuit (413). A first input end of the first-stage sub-circuit (413) receives the second positive signal, a second input end of the first-stage sub-circuit (413) receives the second negative signal, and the first-stage sub-circuit (413) is configured to generate a third positive signal according to the second positive signal and the second negative signal.

17. The signal transmission circuit of claim 16, wherein, The first-stage sub-circuit (413) comprises a third pull-up circuit (423) and a third pull-down circuit (424), a first end of the third pull-up circuit (423) is connected to a power supply end, a second end of the third pull-up circuit (423) is connected to a first end of the third pull-down circuit (424), a control end of the third pull-down circuit (424) receives the second negative signal, and a second end of the third pull-down circuit (424) receives the second positive signal; the third pull-down circuit (424) adjusts a downward driving capability of the second positive signal to the first end of the third pull-down circuit (424) under the control of the second negative signal, and the first end of the third pull-down circuit (424) outputs the third positive signal.

18. The signal transmission circuit of claim 17, wherein, The third pull-down circuit (424) comprises a first capacitor and a third transistor. A first end of the first capacitor receives the second negative signal, and a second end of the first capacitor is connected to a control end of the third transistor. A first end of the third transistor is connected to the second end of the third pull-up circuit, and a second end of the third transistor receives the second positive signal.

19. The signal transmission circuit of claim 18, wherein, The third pull-down circuit (424) further comprises a second capacitor and a fourth transistor. A first end of the second capacitor receives the second negative signal, and a second end of the second capacitor is connected to a control end of the fourth transistor. A first end of the fourth transistor is connected to the first end of the third transistor, and a second end of the fourth transistor receives the second positive signal.

20. The signal transmission circuit of any one of claims 17-19, wherein, The first-stage sub-circuit (413) further comprises a preset voltage circuit (419), a first end of the preset voltage circuit (419) receives the second negative signal, a second end of the preset voltage circuit (419) is connected to the control end of the third pull-down circuit (424), and the preset voltage circuit (419) is configured to generate a preset voltage at the control end of the third pull-down circuit (424) according to the second negative signal.

21. The signal transmission circuit of claim 20, wherein, The preset voltage circuit (419) comprises a fifth transistor and a sixth transistor. A control end of the fifth transistor is connected to the other end of the second capacitor, a first end of the fifth transistor receives the second negative signal, and a second end of the fifth transistor is connected to a first end of the sixth transistor. A control end of the sixth transistor is connected to the other end of the first capacitor, and a second end of the sixth transistor is connected to the control end of the fourth transistor.

22. The signal transmission circuit of any one of claims 16-21, wherein, The first amplification circuit (411) further comprises a second-stage sub-circuit (414). An input end of the second-stage sub-circuit (414) is connected to an output end of the first-stage sub-circuit (411), and the second-stage sub-circuit (414) is configured to amplify the signal output by the first-stage sub-circuit (411) and output the third positive signal.

23. The signal transmission circuit of claim 22, wherein, The second-stage sub-circuit (414) comprises a second pull-up circuit (421) and a second pull-down circuit (422). A first end of the second pull-up circuit (421) is connected to a power supply end. A second end of the second pull-down circuit (422) is connected to a first end of the second pull-down circuit (422). A second end of the second pull-down circuit (422) is connected to a second power supply end. A control end of the second pull-down circuit (422) receives a signal output by the first-stage sub-circuit (413). The second pull-down circuit (422) adjusts a downward driving capability of the second power supply end to the second end of the second pull-down circuit (422) under control of the second negative signal. A first end of the second pull-down circuit (422) outputs the third positive signal.

24. The signal transmission circuit of claim 23, wherein, The second pull-down circuit (422) comprises a seventh transistor. The second pull-up circuit (422) comprises an eighth transistor and a third capacitor. The control end of the seventh transistor is the control end of the second pull-down circuit, and receives the signal output by the first-stage sub-circuit (413). The first end of the seventh transistor is connected to the second power supply end, and the second end of the seventh transistor is connected to the first end of the eighth transistor. The control end of the eighth transistor is connected to the first end of the third capacitor, and the second end of the eighth transistor is connected to the power supply end. The second end of the third capacitor is connected to the power supply end.

25. The signal transmission circuit of any one of claims 12-24, wherein, The second-stage differential amplification circuit (420) in the multi-stage differential amplification circuit (41) comprises a cross-coupled circuit (450) and a back-end amplification circuit (451). The first input end of the cross-coupled circuit (450) receives the third positive signal, and the second input end of the cross-coupled circuit (450) receives the third negative signal. The first output end of the cross-coupled circuit (450) is connected to the first input end of the back-end amplification circuit (451), and the second output end of the cross-coupled circuit (450) is connected to the second input end of the back-end amplification circuit (451). The back-end amplification circuit (451) outputs a fourth positive signal according to the signal of the first input end, and outputs a fourth negative signal according to the signal of the second input end.

26. The signal transmission circuit of any one of claims 1-25, wherein, The signal transmission circuit further comprises an input module (50). An input end of the input module (50) receives an input signal, and an output end of the input module (50) is connected to the isolation module (20) and outputs the first differential signal after modulating the input signal.

27. The signal transmission circuit of any one of claims 1-26, wherein, The isolation module (20) is a capacitive isolation module.

28. A signal transmission system (60), wherein, The signal transmission circuit comprises a controller (61), a driving module (62), and a power device (63). An output end of the controller (61) is connected to an input end of the signal transmission circuit. An input end of the driving module (62) is connected to an output end of the signal transmission circuit. An input end of the power device (63) is connected with an output end of the driving module (62). The driving module (62) is used for performing voltage boosting processing on the signal output by the signal transmission circuit and then outputting the signal to the power device (63), so as to drive the power device (62) to operate.

29. The signal transmission system (60) according to claim 28, wherein, The output signal of the controller (61) is a square wave pulse signal.

30. An electric control system (70) of a vehicle, wherein The signal transmission system (60) comprises the signal transmission system (60) according to claim 28 or 29.

31. A vehicle (100), wherein The electric control system (70) of the vehicle comprises the electric control system (70) according to claim 30.

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