Differential signal output circuit, driving system and vehicle

Abstract

A vehicle comprises a driving system, wherein the driving system comprises a differential signal output circuit. The differential signal output circuit comprises a boost circuit and a driving output circuit. A first input terminal of the boost circuit is used for receiving a clock signal, and a power supply terminal of the boost circuit receives a supply voltage, and is used for controlling, when the clock signal is a low-level signal, a plurality of first output terminals to output a plurality of driving voltage signals where at least one voltage value is greater than the supply voltage, and for controlling, when the clock signal is a high-level signal, the plurality of first output terminals to output a plurality of driving voltage signals where voltage values are less than or equal to the supply voltage. A second input terminal of the driving output circuit is used for receiving the clock signal, a plurality of voltage input terminals of the driving output circuit are connected to the plurality of first output terminals in the manner of corresponding to each other on a one-to-one basis, the plurality of voltage input terminals are used for receiving the plurality of driving voltage signals, and the driving output circuit is used for controlling a second output terminal to output a differential signal.

Description

Differential signal output circuit, drive system and vehicle

[0001] Cross-references to related applications

[0002] This application claims priority to Chinese patent application filed on August 2, 2024, with application number 202411060123.4 and entitled "Differential signal output circuit, drive system and vehicle", the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to the field of vehicle technology, and in particular to a differential signal output circuit, a drive system, and a vehicle. Background Technology

[0004] In related technologies, existing charge pump circuits continuously generate voltage to power the drive module, and then the drive module outputs a differential signal of a corresponding voltage magnitude based on the voltage generated by the charge pump. When the charge pump and drive module use low-voltage MOSFETs, the voltage output by the charge pump is 5.5V when the supply voltage is equal to 3.3V. At this time, the voltage has reached the maximum operating voltage of the low-voltage MOSFET, and it cannot achieve the purpose of the drive module to output a higher voltage differential signal.

[0005] Public content

[0006] This disclosure aims to at least address one of the technical problems existing in the prior art. To this end, one object of this disclosure is to provide a differential signal output circuit that can output a higher voltage differential signal by incorporating a boost circuit.

[0007] The second objective of this disclosure is to propose a driving system.

[0008] The third objective of this disclosure is to propose a vehicle.

[0009] To address the aforementioned problems, a first aspect of this disclosure provides a differential signal output circuit, comprising: a boost circuit, wherein a first input terminal of the boost circuit is used to receive a clock signal, a power supply terminal of the boost circuit is used to receive a power supply voltage, the boost circuit is used to control a plurality of first output terminals to output at least one plurality of drive voltage signals with a voltage value greater than the power supply voltage when the clock signal is a low-level signal, and to control the plurality of first output terminals to output a plurality of drive voltage signals with a voltage value less than or equal to the power supply voltage when the clock signal is a high-level signal; and a drive output circuit, wherein a second input terminal of the drive output circuit is used to receive the clock signal, a plurality of voltage input terminals of the drive output circuit are connected one-to-one with the plurality of first output terminals, the plurality of voltage input terminals are used to receive a plurality of the drive voltage signals, and the drive output circuit is used to control the second output terminal to output a differential signal.

[0010] According to the differential signal output circuit of this disclosure, a boost circuit is provided in the circuit. Under the control of a clock signal, the boost circuit selectively boosts the supply voltage to output a drive voltage signal, so that the drive output circuit outputs a higher voltage differential signal through the boosted drive voltage signal. Therefore, compared with the prior art that uses a charge pump circuit and a low-voltage MOSFET to output a differential signal, this application uses a boost circuit to boost the supply voltage to output a drive voltage signal. Thus, the drive output circuit can output a higher voltage differential signal according to the boosted drive voltage signal. At the same time, the boost circuit selectively boosts the voltage according to the clock signal during the boost process, instead of continuously outputting a high voltage signal, thereby improving the stability and reliability of the circuit.

[0011] In some embodiments, both the boost circuit and the drive output circuit include two, with each boost circuit and the drive output circuit connected in a one-to-one correspondence. The first input terminal of each boost circuit is used to receive the clock signal, and the power supply terminal of each boost circuit is used to receive the supply voltage. Each boost circuit is used to control the plurality of first output terminals to output at least one of the plurality of drive voltage signals with a voltage value greater than the supply voltage when the clock signal is a low-level signal, and to control the plurality of first output terminals to output the plurality of drive voltage signals with a voltage value less than or equal to the supply voltage when the clock signal is a high-level signal. The second input terminal of each drive output circuit is used to receive the clock signal, and the plurality of voltage input terminals of each drive output circuit are connected to the plurality of first output terminals of the corresponding boost circuit. The plurality of voltage input terminals of each drive output circuit are used to receive the plurality of drive voltage signals output by the corresponding plurality of first output terminals, and each drive output circuit is used to control the second output terminal to output a differential signal.

[0012] In some embodiments, the boost circuit includes a multi-stage charge pump circuit. Each stage of the charge pump circuit includes a charge pump input terminal, a high-side output terminal, and a low-side output terminal. The clock signal is input to the charge pump input terminal of each stage of the charge pump circuit. The power supply terminal of the first-stage charge pump circuit in the multi-stage charge pump circuit is used to receive the supply voltage. The ground terminal of the first-stage charge pump circuit is grounded. The power supply terminals of the other stages of the multi-stage charge pump circuit, excluding the first-stage charge pump circuit, are connected to the high-side output terminal of the previous stage charge pump circuit. The ground terminal of the other stages of the charge pump circuit is connected to the low-side output terminal of the previous stage charge pump circuit. The high-side output terminal and the low-side output terminal of the last stage charge pump circuit in the multi-stage charge pump circuit jointly output multiple driving voltage signals.

[0013] In some embodiments, the first-stage charge pump circuit includes a first dead-time control circuit and a first voltage adjustment circuit, and the other-stage charge pump circuits include a first level shift circuit, a first dead-time control circuit, and a first voltage adjustment circuit; the first terminal of the first dead-time control circuit of the first-stage charge pump circuit is the input terminal of the charge pump, the input terminal of the first level shift circuit of the other-stage charge pump circuit is the input terminal of the charge pump, the first terminal of the first dead-time control circuit of the other-stage charge pump circuit is connected to the output terminal of the first level shift circuit, and the first dead-time control circuit is used to output a clock signal with a dead time according to the clock signal; the first connection terminal of the first voltage adjustment circuit is connected to the second terminal of the first dead-time control circuit, the second connection terminal of the first voltage adjustment circuit is connected to the third terminal of the first dead-time control circuit, the third connection terminal of the first voltage adjustment circuit is connected to the fourth terminal of the first dead-time control circuit, and the first connection terminal of the first voltage adjustment circuit is connected to the fourth terminal of the first dead-time control circuit. The fourth connection terminal is connected to the fifth terminal of the first dead-time control circuit. The power supply terminal of the first voltage adjustment circuit in the first-stage charge pump circuit is used to receive the supply voltage. The ground terminal of the first voltage adjustment circuit in the first-stage charge pump circuit is grounded. The power supply terminal of the first voltage adjustment circuit in the other-stage charge pump circuits is connected to the high-side output terminal of the previous-stage charge pump circuit. The ground terminal of the first voltage adjustment circuit in the other-stage charge pump circuits is connected to the low-side output terminal of the previous-stage charge pump circuit. The high-side output terminal and the low-side output terminal of the first voltage adjustment circuit in the final-stage charge pump circuit jointly output multiple driving voltage signals. The first dead-time control circuit is used to sequentially control the level state at the first connection terminal and the level state at the fourth connection terminal of the first voltage adjustment circuit through the clock signal with dead time. The first voltage adjustment circuit is used to control the voltage difference between the low-side output terminal and the high-side output terminal to be a preset difference value.

[0014] In some embodiments, the first-stage charge pump circuit includes a second dead-time control circuit and a second voltage adjustment circuit, and the other-stage charge pump circuit includes a first level shift circuit, a first dead-time control circuit, and a first voltage adjustment circuit; the first terminal of the second dead-time control circuit is the input terminal of the charge pump, the input terminal of the first level shift circuit of the other-stage charge pump circuit is the input terminal of the charge pump, the first terminal of the first dead-time control circuit of the other-stage charge pump circuit is connected to the output terminal of the first level shift circuit, and the second dead-time control circuit or the first dead-time control circuit is used to output a clock signal with a dead time according to the clock signal; the first connection terminal of the second voltage adjustment circuit is connected to the second terminal of the second dead-time control circuit, the second connection terminal of the second voltage adjustment circuit is connected to the third terminal of the second dead-time control circuit, the third connection terminal of the second voltage adjustment circuit is connected to the fourth terminal of the second dead-time control circuit, the fourth connection terminal of the second voltage adjustment circuit is connected to the fifth terminal of the second dead-time control circuit, the power supply terminal of the second voltage adjustment circuit is used to receive the supply voltage, and the ground terminal of the second voltage adjustment circuit is grounded; the first connection terminal of the first voltage adjustment circuit is connected to the first dead-time control circuit's first dead-time control circuit's first dead-time control circuit's second dead-time control circuit's third dead-time control circuit's fourth dead-time control circuit's fifth ... The first voltage adjustment circuit has two terminals connected: the second terminal is connected to the third terminal of the first dead-time control circuit; the third terminal is connected to the fourth terminal of the first dead-time control circuit; the fourth terminal is connected to the fifth terminal of the first dead-time control circuit; the power supply terminal of the first voltage adjustment circuit is connected to the high-side output terminal of the previous stage charge pump circuit; and the ground terminal of the first voltage adjustment circuit is connected to the low-side output terminal of the previous stage charge pump circuit. In the final stage charge pump circuit, the high-side and low-side output terminals of the first voltage adjustment circuit jointly output multiple driving voltage signals. The second dead-time control circuit is used to sequentially control the voltage level at the first terminal and the fourth terminal of the second voltage adjustment circuit using a clock signal with a dead-time. The first dead-time control circuit is used to sequentially control the voltage level at the first terminal and the fourth terminal of the first voltage adjustment circuit using a clock signal with a dead-time. The first voltage adjustment circuit or the second voltage adjustment circuit controls the voltage difference between the low-side output terminal and the high-side output terminal to a preset value.

[0015] In some embodiments, the first voltage adjustment circuit includes: a first voltage adjustment subunit, a first terminal of which is a power supply terminal of the first voltage adjustment circuit, a second terminal of which is connected to a second terminal of the first dead-time control circuit, a third terminal of which is connected to a fifth terminal of the first dead-time control circuit, and a fourth terminal of which is grounded; a first switching subunit, the power supply terminal of which is connected to the first terminal of the first voltage adjustment subunit, a first connection terminal of which is connected to a third terminal of the first dead-time control circuit, and a second connection terminal of which is connected to a fourth terminal of the first dead-time control circuit; and a first energy storage subunit, the first terminal of which is connected to the third connection terminal of the first switching subunit and has a high-side output terminal, and the second terminal of which is connected to the fifth terminal of the first voltage adjustment subunit and has a low-side output terminal.

[0016] In some embodiments, the first voltage regulation subunit includes: a first PMOS transistor, the source of which is the power supply terminal of the first voltage regulation circuit, and the gate of which is connected to the second terminal of the first dead-time control circuit; a first NMOS transistor, the gate of which is connected to the fifth terminal of the first dead-time control circuit, the drain of which is connected to the drain of the first PMOS transistor and the second terminal of the first energy storage subunit, and the source of which is grounded.

[0017] In some embodiments, the first switching subunit includes: a first capacitor, the first terminal of which is connected to the third terminal of the first dead-time control circuit; a second capacitor, the first terminal of which is connected to the fourth terminal of the first dead-time control circuit; a second NMOS transistor, the gate of which is connected to the second terminal of the second capacitor, and the drain of which is connected to the second terminal of the first capacitor; a third NMOS transistor, the gate of which is connected to the second terminal of the first capacitor, and the drain of which is connected to the second terminal of the second capacitor; and a fourth NMOS transistor, the gate of which is connected to the second terminal of the second capacitor, and the drain of which is connected to the first terminal of the first energy storage subunit; wherein the sources of the second NMOS transistor, the third NMOS transistor, and the fourth NMOS transistor are connected together to the source of the first PMOS transistor.

[0018] In some embodiments, the first energy storage sub-unit includes: a third capacitor, the first end of which is connected to the drain of the fourth NMOS transistor, and the second end of which is connected to the drain of the first NMOS transistor and the drain of the first PMOS transistor.

[0019] In some embodiments, the first dead-time control circuit includes: a first logic subunit, wherein a first terminal of the first logic subunit is the charge pump input terminal, a second terminal of the first logic subunit is connected to the gate of the first PMOS transistor, a third terminal of the first logic subunit is connected to the first terminal of the first capacitor, and a fourth terminal of the first logic subunit is connected to the first terminal of the second capacitor, the first logic subunit being used to control the conduction state of the first PMOS transistor according to the clock signal; and a second logic subunit, wherein a first terminal of the second logic subunit is connected to the first terminal of the first logic subunit, a second terminal of the second logic subunit is connected to the second terminal of the first logic subunit, and a third terminal of the second logic subunit is connected to the gate of the first NMOS transistor and the first terminal of the second capacitor, the second logic subunit being used to control the conduction state of the first NMOS transistor according to the clock signal.

[0020] In some embodiments, the first logic subunit includes: a first NOR gate, wherein the first input terminal of the first NOR gate is the charge pump input terminal, the second input terminal of the first NOR gate is connected to the first terminal of the second capacitor and the third terminal of the second logic subunit, and the output terminal of the first NOR gate is connected to the first terminal of the first capacitor; and a first NOT gate, wherein the input terminal of the first NOT gate is connected to the output terminal of the first NOR gate, and the output terminal of the first NOT gate is connected to the gate of the first PMOS transistor and the second terminal of the second logic subunit.

[0021] In some embodiments, the second logic subunit includes: a first NAND gate, wherein the first input terminal of the first NAND gate is connected to the output terminal of the first NOT gate, and the second input terminal of the first NAND gate is connected to the first input terminal of the first NOR gate; and a second NOT gate, wherein the input terminal of the second NOT gate is connected to the output terminal of the first NAND gate, and the output terminal of the second NOT gate is connected to the second input terminal of the first NOR gate, the first terminal of the second capacitor, and the gate of the first NMOS transistor.

[0022] In some embodiments, the second voltage adjustment circuit includes: a second voltage adjustment subunit, a first terminal of which is used to receive the supply voltage, a second terminal of which is connected to a second terminal of the second dead-time control circuit, a third terminal of which is connected to a fifth terminal of the second dead-time control circuit, and a fourth terminal of which is grounded; a second switching subunit, a first connection terminal of which is connected to a third terminal of the second dead-time control circuit, and a second connection terminal of which is connected to a fourth terminal of the second dead-time control circuit; and a second energy storage subunit, a first terminal of which is connected to a fifth terminal of the second voltage adjustment subunit and has a high-side output terminal, and a second terminal of which is connected to a third connection terminal of the second switching subunit and has a low-side output terminal.

[0023] In some embodiments, the second voltage adjustment subunit includes: a second PMOS transistor, the source of which receives the supply voltage, the gate of which is connected to the second terminal of the second dead-time control circuit, and the drain of which is connected to the first terminal of the second energy storage subunit; and a fifth NMOS transistor, the gate of which is connected to the fifth terminal of the second dead-time control circuit, the drain of which is connected to the drain of the second PMOS transistor and the first terminal of the second energy storage subunit, and the source of which is grounded.

[0024] In some embodiments, the second switching subunit includes: a fourth capacitor, the first terminal of which is connected to the third terminal of the second dead-time control circuit; a fifth capacitor, the first terminal of which is connected to the fourth terminal of the second dead-time control circuit; a third PMOS transistor, the gate of which is connected to the second terminal of the fourth capacitor, and the drain of which is connected to the second terminal of the fifth capacitor; a fourth PMOS transistor, the gate of which is connected to the second terminal of the fifth capacitor, and the drain of which is connected to the second terminal of the fourth capacitor; and a fifth PMOS transistor, the gate of which is connected to the second terminal of the fourth capacitor, and the drain of which is connected to the second terminal of the second energy storage subunit; wherein the sources of the third PMOS transistor, the fourth PMOS transistor, and the fifth PMOS transistor are all grounded.

[0025] In some embodiments, the second energy storage sub-unit includes: a sixth capacitor, the first end of which is connected to the drain of the second PMOS transistor and the drain of the fifth NMOS transistor, and the second end of which is connected to the drain of the fifth PMOS transistor.

[0026] In some embodiments, the second dead-time control circuit includes: a third logic subunit, the first terminal of which is the charge pump input terminal, the second terminal of which is connected to the gate of the second PMOS transistor and the first terminal of the fourth capacitor, the third logic subunit being used to control the conduction state of the second PMOS transistor according to the clock signal; and a fourth logic subunit, the first terminal of which is connected to the first terminal of the third logic subunit, the second terminal of which is connected to the second terminal of the third logic subunit, the third terminal of which is connected to the first terminal of the fifth capacitor, the fourth terminal of which is connected to the third terminal of the third logic subunit and the gate of the fifth NMOS transistor, the fourth logic subunit being used to control the conduction state of the fifth NMOS transistor according to the clock signal.

[0027] In some embodiments, the third logic subunit includes: a second NOR gate, the first input terminal of which is the charge pump input terminal, and the second input terminal of which is connected to the fourth terminal of the fourth logic subunit; and a third NOT gate, the input terminal of which is connected to the output terminal of the second NOR gate, and the output terminal of which is connected to the gate of the second PMOS transistor, the first terminal of the fourth capacitor, and the second terminal of the fourth logic subunit.

[0028] In some embodiments, the fourth logic subunit includes: a second NAND gate, wherein the first input terminal of the second NAND gate is connected to the output terminal of the third NOT gate, the second input terminal of the second NAND gate is connected to the first input terminal of the second NOR gate, and the output terminal of the second NAND gate is connected to the first terminal of the fifth capacitor; and a fourth NOT gate, wherein the input terminal of the fourth NOT gate is connected to the output terminal of the second NAND gate, and the output terminal of the fourth NOT gate is connected to the second input terminal of the second NOR gate and the gate of the fifth NMOS transistor.

[0029] In some embodiments, the drive output circuit includes: a second level shift circuit, the input terminal of which is used to receive the clock signal and shift the drive voltage signal to the input voltage of the drive output circuit; a third dead-time control circuit, the input terminal of which is connected to the output terminal of the second level shift circuit and is used to output a clock signal with a dead time according to the clock signal; and a signal processing circuit, the power supply terminal of which is connected to the high-side output terminal of the final stage charge pump circuit in the corresponding boost circuit, the ground terminal of which is connected to the low-side output terminal of the final stage charge pump circuit in the corresponding boost circuit, the control terminal of which is connected to the third dead-time control circuit and is used to output a differential signal according to the clock signal with dead time and the plurality of drive voltage signals.

[0030] In some embodiments, the signal processing circuit includes: a sixth PMOS transistor, the gate of which is connected to the first output terminal of the third dead-time control circuit, and the source of which is connected to the high-side output terminal of the final stage charge pump circuit in the corresponding boost circuit; and a sixth NMOS transistor, the gate of which is connected to the second output terminal of the third dead-time control circuit, the source of which is connected to the low-side output terminal of the final stage charge pump circuit in the corresponding boost circuit, and the drain of which is connected to the drain of the sixth PMOS transistor and used to output the differential signal.

[0031] In some embodiments, the third dead-time control circuit includes: a fifth logic subunit, the first terminal of which is connected to the output terminal of the second level shift circuit, and the second terminal of which is connected to the gate of the sixth PMOS transistor, the fifth logic subunit being used to control the conduction state of the sixth PMOS transistor according to the clock signal; and a sixth logic subunit, the first terminal of which is connected to the second terminal of the fifth logic subunit, the second terminal of which is connected to the output terminal of the second level shift circuit, and the third terminal of which is connected to the third terminal of the fifth logic subunit and the gate of the sixth NMOS transistor, the sixth logic subunit being used to control the conduction state of the sixth NMOS transistor according to the clock signal.

[0032] In some embodiments, the fifth logic subunit includes: a third NOR gate, the first input of which is connected to the output of the second level shift circuit, and the second input of which is connected to the third terminal of the sixth logic subunit; and a fifth NOT gate, the input of which is connected to the output of the third NOR gate, and the output of which is connected to the gate of the sixth PMOS transistor and the first terminal of the sixth logic subunit.

[0033] In some embodiments, the sixth logic subunit includes: a third NAND gate, the first input of which is connected to the output of the fifth NOT gate, and the second input of which is connected to the output of the second level shift circuit; and a sixth NOT gate, the input of which is connected to the output of the third NAND gate, and the output of which is connected to the second input of the third NOR gate and the gate of the sixth NMOS transistor.

[0034] A second aspect of this disclosure provides a driving system including the differential signal output circuit described in the above embodiments.

[0035] According to the driving system of the present disclosure, the charge pump circuit of the above embodiment can output a higher voltage differential signal by setting a boost circuit.

[0036] A third aspect of this disclosure provides a vehicle including the drive system described in the above embodiments.

[0037] According to the vehicle of the present disclosure, the drive system of the above embodiment can output a higher voltage differential signal by setting a boost circuit.

[0038] Additional aspects and advantages of this disclosure will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this disclosure. Attached Figure Description

[0039] The above and / or additional aspects and advantages of this disclosure will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which:

[0040] Figure 1 is a schematic diagram of a differential signal output circuit according to an embodiment of the present disclosure;

[0041] Figure 2 is a schematic diagram of a boost circuit according to an embodiment of the present disclosure;

[0042] Figure 3 is a schematic diagram of a boost circuit according to another embodiment of the present disclosure;

[0043] Figure 4 is a schematic diagram of a drive output circuit according to an embodiment of the present disclosure;

[0044] Figure 5 is a structural block diagram of a drive system according to an embodiment of the present disclosure;

[0045] Figure 6 is a structural block diagram of a vehicle according to an embodiment of the present disclosure.

[0046] Reference numerals: Vehicle 1000; Drive system 900; Differential signal output circuit 800; Charge pump circuit 1; Boost circuit 2; Drive output circuit 4; First dead-time control circuit 11; First voltage adjustment circuit 12; First level shift circuit 13; Second dead-time control circuit 15; Second voltage adjustment circuit 14; First output terminal 21; Voltage input terminal 44; First logic subunit 111; Second logic subunit 112; First voltage adjustment subunit 121; First switching subunit 122; First energy storage subunit 123; Third logic subunit 151; Fourth logic subunit 152; Second voltage adjustment subunit 141; Second switching subunit 142; Second energy storage subunit 143; Second level shift circuit 41; Third dead-time control circuit 42; Signal processing circuit 43; Fifth logic subunit 421; Sixth logic subunit 422; First capacitor C1; The... Two capacitors: C2; C3; C4; C5; C6; N1; N2; N3; N4; N5; N6; P1; P2; P3; P4; P5; P6; N1; N2; P3; P4; P5; P6; NOR gate I1; NOR gate I2; NAND gate I3; NOR gate I4; NOR gate I5; NOR gate I6; NAND gate I7; NOR gate I8; NOR gate I9; NOR gate I10; NAND gate I11; NOR gate I12. Detailed Implementation

[0047] The embodiments of this disclosure are described in detail below, and the embodiments described with reference to the accompanying drawings are exemplary disclosures.

[0048] To address the aforementioned issues, the first aspect of this disclosure provides a differential signal output circuit that can output a higher voltage differential signal by using a boost circuit 2.

[0049] The differential signal output circuit 800 according to an embodiment of the present disclosure is described below with reference to FIG1. ​​As shown in FIG1, it includes a boost circuit 2 and a drive output circuit 4.

[0050] In this circuit, the first input terminal of the boost circuit 2 receives the clock signal, and the power supply terminal receives the supply voltage. When the clock signal is low, the boost circuit 2 controls multiple first output terminals 21 to output at least one drive voltage signal with a voltage value greater than the supply voltage; and when the clock signal is high, it controls multiple first output terminals 21 to output multiple drive voltage signals with a voltage value less than or equal to the supply voltage. The second input terminal of the drive output circuit 4 receives the clock signal. Multiple voltage input terminals 44 of the drive output circuit 4 are connected one-to-one with the multiple first output terminals 21, and the multiple voltage input terminals 44 receive multiple drive voltage signals. The drive output circuit 4 controls the second output terminal to output differential signals. The clock signal is generated by the OSC (Oscillated Crystal Oscillator) in Figure 2.

[0051] Specifically, in order to solve the above problems, the differential signal output circuit 800 in this application selectively boosts the supply voltage according to the periodic changes in the level of the clock signal after the boost circuit 2 receives the clock signal. That is, the boost circuit 2 no longer continuously outputs a high voltage signal, but periodically boosts the supply voltage with the clock signal to obtain multiple drive voltage signals, and outputs multiple drive voltage signals to the drive output circuit 4. After receiving multiple drive voltage signals, the drive output circuit 4 outputs a differential signal through the second output terminal. For example, when the clock signal is a high-level signal, the boost circuit 2 does not boost the supply voltage. Instead, it directly outputs multiple drive voltage signals with voltage values ​​less than or equal to the supply voltage. That is, the boost circuit 2 outputs multiple drive voltage signals with voltage values ​​less than or equal to the supply voltage through its multiple first output terminals 21 to the multiple voltage input terminals 44 of the drive output circuit 4. After obtaining the multiple drive voltage signals with voltage values ​​less than or equal to the supply voltage, the drive output circuit 4 outputs differential signals with voltage values ​​less than or equal to the supply voltage through its second output terminal. That is, it does not output high-voltage differential signals. When the clock signal is a low-level signal, the boost circuit 2 boosts the supply voltage to obtain at least one multiple drive voltage signal with a voltage value greater than the supply voltage. That is, it obtains at least one boosted multiple drive voltage signal, and then outputs it through the multiple first output terminals 21 of the boost circuit 2. At least one drive voltage signal with a voltage value greater than the supply voltage is output to multiple voltage input terminals 44 of the drive output circuit 4. A differential signal with a voltage value greater than the supply voltage is output through the second output terminal. That is, after the drive output circuit 4 obtains the multiple drive voltage signals after boosting, it outputs a differential signal with a higher voltage through the second output terminal. Therefore, compared with the charge pump circuit and drive module in the prior art that use low voltage MOSFETs to output differential signals, this application sets up a boost circuit 2 to boost the supply voltage to output drive voltage signals. Thus, the drive output circuit 4 can output a differential signal with a higher voltage according to the boosted drive voltage signal. At the same time, the boost circuit 2 selectively performs boost processing according to the clock signal during boost processing, and no longer continuously outputs high voltage signals, thereby improving the stability and reliability of the circuit.

[0052] According to the differential signal output circuit 800 of this disclosure embodiment, a boost circuit 2 is provided in the circuit. Under the control of a clock signal, the boost circuit 2 selectively boosts the supply voltage to output a drive voltage signal, so that the drive output circuit 4 outputs a higher voltage differential signal through the boosted drive voltage signal. Therefore, compared with the prior art that uses a charge pump circuit and a low-voltage MOSFET to output a differential signal, this application uses a boost circuit 2 to boost the supply voltage to output a drive voltage signal, so that the drive output circuit 4 can output a higher voltage differential signal according to the boosted drive voltage signal. At the same time, the boost circuit 2 selectively boosts the voltage according to the clock signal during the boost process, instead of continuously outputting a high voltage signal, thereby improving the stability and reliability of the circuit.

[0053] In some embodiments, both the boost circuit 2 and the drive output circuit 4 include two, with each boost circuit 2 and drive output circuit 4 connected in a one-to-one correspondence. The first input terminal of each boost circuit 2 is used to receive a clock signal, and the power supply terminal of each boost circuit 2 is used to receive a supply voltage. Each boost circuit 2 is used to control multiple first output terminals 21 to output at least one drive voltage signal with a voltage value greater than the supply voltage when the clock signal is low, and to control multiple first output terminals 21 to output multiple drive voltage signals with a voltage value less than or equal to the supply voltage when the clock signal is high. The second input terminal of each drive output circuit 4 is used to receive the clock signal, and multiple voltage input terminals 44 of each drive output circuit 4 are connected to the corresponding multiple first output terminals 21 of the boost circuit 2. The multiple voltage input terminals 44 of each drive output circuit 4 are used to receive the multiple drive voltage signals output by the corresponding multiple first output terminals 21, and each drive output circuit 4 is used to control the second output terminal to output a differential signal.

[0054] Specifically, the two drive output circuits 4 in this application employ independent boost circuits 2. Therefore, the two drive output circuits 4 can output different differential signals. That is, when one boost circuit 2 is a low-level clock signal, it outputs at least one drive voltage signal with a voltage value greater than the supply voltage. In other words, this boost circuit 2 boosts the supply voltage. When the drive output circuit 4 obtains at least one drive voltage signal with a voltage value greater than the supply voltage, it can output a differential signal with a voltage value greater than the supply voltage, i.e., obtain a higher voltage differential signal. The other boost circuit 2, when the clock signal is a high-level clock signal... The boost circuit 2 outputs multiple drive voltage signals with voltage values ​​less than or equal to the supply voltage. That is, the boost circuit 2 does not boost the supply voltage. After the drive output circuit 4 obtains multiple drive voltage signals with voltage values ​​less than or equal to the supply voltage, it can output differential signals with voltage values ​​less than or equal to the supply voltage. Thus, the two drive output circuits 4 obtain two differential signals with different voltage values ​​under the control of the clock signal, so that the driving components controlled by the two differential signals have different operating states. For example, the first driving component controlled by one differential signal stops working, and the second driving component controlled by the other differential signal starts working.

[0055] In some embodiments, the boost circuit 2 includes a multi-stage charge pump circuit 1. The boost circuit 2 may include a two-stage charge pump circuit 1 or a three-stage charge pump circuit 1, without limitation. Each stage charge pump circuit 1 includes a charge pump input terminal, a high-side output terminal, and a low-side output terminal, and the charge pump input terminal of each stage charge pump circuit 1 receives a clock signal. The power supply terminal of the first stage charge pump circuit 1 in the multi-stage charge pump circuit 1 is used to receive the supply voltage. The first stage charge pump circuit is the first charge pump circuit 1 in Figure 2. The ground terminal of the first stage charge pump circuit 1 is grounded. The power supply terminals of the other stage charge pump circuits 1 in the multi-stage charge pump circuit 1, excluding the first stage charge pump circuit 1, are connected to the high-side output terminal of the previous stage charge pump circuit 1. The ground terminal of the other stage charge pump circuit 1 is connected to the low-side output terminal of the previous stage charge pump circuit 1. The high-side output terminal and the low-side output terminal of the last stage charge pump circuit 1 in the multi-stage charge pump circuit 1 jointly output multiple drive voltage signals. The last stage charge pump circuit is the second charge pump circuit 1 in Figure 2.

[0056] Specifically, when the clock signal received by the boost circuit 2 is a low-level signal, the supply voltage is boosted. That is, each stage charge pump circuit 1 of the boost circuit 2 boosts the voltage when the clock signal is low. In other words, the first-stage charge pump of the boost circuit 2 obtains the clock signal through the charge pump input terminal. When the clock signal is low, the first-stage charge pump circuit 1 boosts the supply voltage received through its power supply terminal to obtain the high-side voltage signal after the initial boost. This high-side voltage signal is then output through the high-side output terminal of the first-stage charge pump circuit 1 to the power supply terminal of other stage charge pump circuits 1 connected to the first-stage charge pump circuit 1. The voltage at the ground terminal is boosted to obtain a low-side voltage signal after initial boosting. This signal is then output to the ground terminal of another stage charge pump circuit 1 connected to the first-stage charge pump circuit 1 via the low-side output terminal of the first-stage charge pump circuit 1. When the other stage charge pump circuit 1 receives a low-level clock signal, it boosts the high-side voltage signal boosted by the first-stage charge pump circuit 1 to obtain a high-side voltage signal after further boosting. This high-side voltage signal is then output to the power supply terminal of the other stage charge pump circuit 1 connected to it via the high-side output terminal of the other stage charge pump circuit 1. Simultaneously, the other stage charge pump circuit 1 boosts the low-side voltage signal boosted by the first-stage charge pump circuit 1. This process is repeated to obtain a low-side voltage signal after further boosting. This signal is then output through the low-side output of the other stage charge pump circuit 1 to the ground terminal of the other stage charge pump circuit 1 connected to it. This continues until the final stage charge pump circuit 1 boosts the voltage at the power supply terminal, except for the first stage charge pump circuit 1. This continues until the final stage charge pump circuit 1 performs a final boost on the high-side voltage signal output from the high-side output of the previous stage charge pump circuit 1, thus obtaining the final boosted high-side voltage signal. Finally, the final stage charge pump circuit 1 also performs a final boost on the low-side voltage signal output from the low-side output of the previous stage charge pump circuit 1, thus obtaining the final... The low-side voltage signal from the first boost is output as the low-side voltage signal and high-side voltage signal from the last boost through the high-side output and low-side output of the final stage charge pump circuit 1. The low-side voltage signal and high-side voltage signal from the last boost are the driving voltage signals. It should be noted that at least one of the high-side voltage signal and low-side voltage signal is a driving voltage signal that is greater than the supply voltage. Thus, when the clock signal is a low level signal, the boost circuit 2 upgrades the supply voltage multiple times through the multi-stage charge pump circuit 1 to output at least one driving voltage signal with a voltage value greater than the supply voltage, so that the drive output circuit 4 outputs a differential signal with a higher voltage.

[0057] For example, when the clock signal received by the boost circuit 2 is a high-level signal, the supply voltage is not boosted. That is, when the clock signal is a high-level signal, each stage of the charge pump circuit 1 of the boost circuit 2 outputs a supply voltage through its high-side output terminal to the power supply terminal of other stage charge pump circuits 1 connected to the first stage charge pump circuit 1, and outputs a ground terminal voltage through its low-side output terminal to the ground terminal of other stage charge pump circuits 1 connected to the first stage charge pump circuit 1. Other stage charge pump circuits 1 also output a supply voltage through their high-side output terminals to the power supply terminal of other stage charge pump circuits 1 connected to the first stage charge pump circuit 1. The other stage charge pump circuit 1 is connected to the power supply terminal of the other stage charge pump circuit 1. The other stage charge pump circuit 1 also outputs the ground terminal voltage through the low-side output terminal to the ground terminal of the other stage charge pump circuit 1 connected to it. This continues until it outputs to the power supply terminal and ground terminal of the final stage charge pump circuit 1. The final stage charge pump circuit 1 outputs the supply voltage and ground terminal voltage through the high-side output terminal and the low-side output terminal. The supply voltage and ground terminal voltage are the driving voltage signals. Thus, when the clock signal is a high-level signal, the boost circuit 2 outputs multiple driving voltage signals with voltage values ​​less than or equal to the supply voltage through the multi-stage charge pump circuit 1.

[0058] In some embodiments, as shown in FIG2, the first-stage charge pump circuit 1 includes a first dead-time control circuit 11 and a first voltage adjustment circuit 12, and the other-stage charge pump circuits 1 include a first level shift circuit 13, a first dead-time control circuit 11, and a first voltage adjustment circuit 12. The first terminal of the first dead-time control circuit 11 of the first-stage charge pump circuit 1 is the charge pump input terminal; the input terminal of the first level shift circuit 13 of the other-stage charge pump circuits 1 is the charge pump input terminal, and the first terminal of the first dead-time control circuit 11 of the other-stage charge pump circuits 1 is connected to the output terminal of the first level shift circuit 13. The first dead-time control circuit 11 is used to output a clock signal with a dead time according to a clock signal; the first connection terminal of the first voltage adjustment circuit 12 is connected to the second terminal of the first dead-time control circuit 11, the second connection terminal of the first voltage adjustment circuit 12 is connected to the third terminal of the first dead-time control circuit 11, and the third connection terminal of the first voltage adjustment circuit 12 is connected to the fourth terminal of the first dead-time control circuit 11. The fourth connection terminal of the voltage adjustment circuit 12 is connected to the fifth terminal of the first dead-time control circuit 11; the power supply terminal of the first voltage adjustment circuit 12 in the first-stage charge pump circuit 1 is used to receive the power supply voltage, the ground terminal of the first voltage adjustment circuit 12 in the first-stage charge pump circuit 1 is grounded, the power supply terminal of the first voltage adjustment circuit 12 in other-stage charge pump circuits 1 is connected to the high-side output terminal of the previous-stage charge pump circuit 1, and the ground terminal of the first voltage adjustment circuit 12 in other-stage charge pump circuits 1 is connected to the low-side output terminal of the previous-stage charge pump circuit 1; the high-side output terminal and the low-side output terminal of the first voltage adjustment circuit 12 in the final-stage charge pump circuit 1 jointly output multiple driving voltage signals; the first dead-time control circuit 11 is used to sequentially control the level state at the first connection terminal and the level state at the fourth connection terminal of the first voltage adjustment circuit 12 through a clock signal with dead time; the first voltage adjustment circuit 12 is used to control the voltage difference between the low-side output terminal and the high-side output terminal to a preset difference value. The first level shifting circuit 13 is used to shift the voltage level of the clock signal from the voltage at the ground terminal to the power supply terminal of the previous stage charge pump circuit 1 to the voltage at the ground terminal to the power supply terminal of the other stage charge pump circuit 1.

[0059] The clock signal for the dead time can be understood as having a time delay between the level state at the first connection terminal and the level state at the fourth connection terminal of the first voltage adjustment circuit 12.

[0060] Specifically, after receiving the clock signal, the first dead-time control circuit 11 of the first-stage charge pump circuit 1 outputs a clock signal with a dead time. The clock signal with the dead time sequentially controls the level state at the first connection terminal and the level state at the fourth connection terminal of the first voltage adjustment circuit 12. For example, the level state at the first connection terminal of the first voltage adjustment circuit 12 is controlled first, and then the level state at the fourth connection terminal of the first voltage adjustment circuit 12 is controlled. The first voltage adjustment circuit 12 controls the voltage difference between the low-side output terminal and the high-side output terminal of the first-stage charge pump circuit 1 to be a preset difference value. The preset difference value is less than or equal to the maximum operating voltage of the first-stage charge pump circuit 1, so that the voltage difference value is less than or equal to the maximum operating voltage of the first-stage charge pump circuit 1, that is, the voltage difference between the ground terminal and the power supply terminal of the first-stage charge pump circuit 1 does not exceed the maximum operating voltage of the first-stage charge pump circuit 1.

[0061] After receiving the clock signal, the first dead-time control circuit 11 of the other stage charge pump circuit 1 outputs a clock signal with a dead time. The clock signal with the dead time sequentially controls the level state at the first connection terminal and the level state at the fourth connection terminal of the first voltage adjustment circuit 12. For example, the level state at the first connection terminal of the first voltage adjustment circuit 12 is controlled first, and then the level state at the fourth connection terminal of the first voltage adjustment circuit 12 is controlled. The first voltage adjustment circuit 12 controls the voltage difference between the low-side output terminal and the high-side output terminal of the other stage charge pump circuit 1 to be a preset difference value. The preset difference value is less than or equal to the maximum operating voltage of the other stage charge pump circuit 1, so that the voltage difference value is less than or equal to the maximum operating voltage of the other stage charge pump circuit 1, that is, the voltage difference between the ground terminal and the power supply terminal of the other stage charge pump circuit 1 does not exceed the maximum operating voltage of the other stage charge pump circuit 1.

[0062] Therefore, the MOS transistor used in the charge pump circuit 1 of this application is a low-voltage MOS transistor. The voltage of the charge pump circuit 1 will not exceed the maximum operating voltage of the MOS transistor. Compared with the existing charge pump circuit 1 which uses a high-voltage MOS transistor, there is no need to add a voltage limiting circuit to ensure that the gate of the MOS transistor is not broken down, which can reduce the layout area and cost.

[0063] In some embodiments, as shown in FIG3, the first-stage charge pump circuit 1 includes a second dead-time control circuit 15 and a second voltage adjustment circuit 14, and the other-stage charge pump circuits 1 include a first level shift circuit 13, a first dead-time control circuit 11, and a first voltage adjustment circuit 12; the first terminal of the second dead-time control circuit 15 is the charge pump input terminal, the input terminal of the first level shift circuit 13 of the other-stage charge pump circuit 1 is the charge pump input terminal, the first terminal of the first dead-time control circuit 11 of the other-stage charge pump circuit 1 is connected to the output terminal of the first level shift circuit 13, and the second dead-time control circuit 15 or the first dead-time control circuit 11 is used to adjust the voltage according to the time. The clock signal output has a clock signal with dead time; the first connection terminal of the second voltage adjustment circuit 14 is connected to the second terminal of the second dead time control circuit 15, the second connection terminal of the second voltage adjustment circuit 14 is connected to the third terminal of the second dead time control circuit 15, the third connection terminal of the second voltage adjustment circuit 14 is connected to the fourth terminal of the second dead time control circuit 15, the fourth connection terminal of the second voltage adjustment circuit 14 is connected to the fifth terminal of the second dead time control circuit 15, the power supply terminal of the second voltage adjustment circuit 14 is used to receive the supply voltage, and the ground terminal of the second voltage adjustment circuit 14 is grounded; the first connection terminal of the first voltage adjustment circuit 12 is connected to the first dead time control circuit 15. The second terminal of the zone control circuit 11 is connected to the third terminal of the first dead-zone control circuit 11, the third terminal of the first voltage adjustment circuit 12 is connected to the fourth terminal of the first dead-zone control circuit 11, the fourth terminal of the first voltage adjustment circuit 12 is connected to the fifth terminal of the first dead-zone control circuit 11, the power supply terminal of the first voltage adjustment circuit 12 is connected to the high-side output terminal of the previous stage charge pump circuit 1, and the ground terminal of the first voltage adjustment circuit 12 is connected to the low-side output terminal of the previous stage charge pump circuit 1. The high-side output terminal and low-side output terminal of the first voltage adjustment circuit 12 in the final stage charge pump circuit 1... The terminals jointly output multiple drive voltage signals; the second dead-time control circuit 15 is used to sequentially control the level state at the first connection terminal and the fourth connection terminal of the second voltage adjustment circuit 14 through a clock signal with dead time; the first dead-time control circuit 11 is used to sequentially control the level state at the first connection terminal and the fourth connection terminal of the first voltage adjustment circuit 12 through a clock signal with dead time; the first voltage adjustment circuit 12 or the second voltage adjustment circuit 14 is used to control the voltage difference between the low-side output terminal and the high-side output terminal to a preset difference value.

[0064] Specifically, after receiving the clock signal, the second dead-time control circuit 15 of the primary charge pump circuit 1 outputs a clock signal with a dead time. The clock signal with the dead time sequentially controls the level state at the first connection terminal and the level state at the fourth connection terminal of the second voltage adjustment circuit 14. For example, the level state at the first connection terminal of the second voltage adjustment circuit 14 is controlled first, and then the level state at the fourth connection terminal of the second voltage adjustment circuit 14 is controlled. The second voltage adjustment circuit 14 controls the voltage difference between the low-side output terminal and the high-side output terminal of the primary charge pump circuit 1 to be a preset difference value. The preset difference value is less than or equal to the maximum operating voltage of the primary charge pump circuit 1, so that the voltage difference value is less than or equal to the maximum operating voltage of the primary charge pump circuit 1, that is, the voltage difference between the ground terminal and the power supply terminal of the primary charge pump circuit 1 does not exceed the maximum operating voltage of the primary charge pump circuit 1.

[0065] After receiving the clock signal, the second dead-time control circuit 15 of the other stage charge pump circuit 1 outputs a clock signal with a dead time. The clock signal with the dead time sequentially controls the level state at the first connection terminal and the level state at the fourth connection terminal of the second voltage adjustment circuit 14. For example, the level state at the first connection terminal of the second voltage adjustment circuit 14 is controlled first, and then the level state at the fourth connection terminal of the second voltage adjustment circuit 14 is controlled. The second voltage adjustment circuit 14 controls the voltage difference between the low-side output terminal and the high-side output terminal of the other stage charge pump circuit 1 to a preset difference value. The preset difference value is less than or equal to the maximum operating voltage of the other stage charge pump circuit 1, so that the voltage difference value is less than or equal to the maximum operating voltage of the other stage charge pump circuit 1, that is, the voltage difference between the ground terminal and the power supply terminal of the other stage charge pump circuit 1 does not exceed the maximum operating voltage of the other stage charge pump circuit 1.

[0066] Therefore, the MOS transistor used in the charge pump circuit 1 of this application is a low-voltage MOS transistor. The voltage of the charge pump circuit 1 will not exceed the maximum operating voltage of the MOS transistor. Compared with the existing charge pump circuit 1 which uses a high-voltage MOS transistor, there is no need to add a voltage limiting circuit to ensure that the gate of the MOS transistor is not broken down, which can reduce the layout area and cost.

[0067] In some embodiments, as shown in FIG2, the first voltage adjustment circuit 12 includes: a first voltage adjustment subunit 121, a first switching subunit 122, and a first energy storage subunit 123.

[0068] The first voltage adjustment subunit 121 has a first terminal that is the power supply terminal of the first voltage adjustment circuit 12, a second terminal that is connected to the second terminal of the first dead-zone control circuit 11, a third terminal that is connected to the fifth terminal of the first dead-zone control circuit 11, and a fourth terminal that is grounded. The power supply terminal of the first switching subunit 122 is connected to the first terminal of the first voltage adjustment subunit 121, a first connection terminal that is connected to the third terminal of the first dead-zone control circuit 11, and a second connection terminal that is connected to the fourth terminal of the first dead-zone control circuit 11. The first terminal of the first energy storage subunit 123 is connected to the third connection terminal of the first switching subunit 122 and leads out a high-side output terminal, and the second terminal of the first energy storage subunit 123 is connected to the fifth terminal of the first voltage adjustment subunit 121 and leads out a low-side output terminal.

[0069] Specifically, the first-stage charge pump circuit 1 of the boost circuit 2 includes a first dead-time control circuit 11. The clock signal received by the first dead-time control circuit 11 controls the state of the first voltage adjustment subunit 121 and the first switching subunit 122, so that the power supply can charge the two ends of the first energy storage subunit 123 through the first voltage adjustment subunit 121 and output the boosted voltage signal through the two ends of the first energy storage subunit 123, thereby boosting the power supply voltage. Alternatively, the power supply can charge one end of the second energy storage subunit 143 through the first voltage adjustment subunit 121 and the first switching subunit 122, so that the power supply voltage can be directly output through the two ends of the first energy storage subunit 123.

[0070] In some embodiments, as shown in FIG2, the first voltage adjustment subunit 121 includes: a first PMOS transistor P1 and a first NMOS transistor N1.

[0071] In this circuit, the source of the first PMOS transistor P1 is connected to the power supply terminal VDD of the first voltage adjustment circuit 12, and the gate of the first PMOS transistor P1 is connected to the second terminal of the first dead-time control circuit 11. The gate of the first NMOS transistor N1 is connected to the fifth terminal of the first dead-time control circuit 11, the drain of the first NMOS transistor N1 is connected to the drain of the first PMOS transistor P1 and the second terminal of the first energy storage sub-unit 123, and the source of the first NMOS transistor N1 is grounded.

[0072] Specifically, the gate of the first PMOS transistor P1 controls the conduction state of the first PMOS transistor P1 according to the clock signal output by the first dead-time control circuit 11, and the gate of the first NMOS transistor N1 controls the conduction state of the first NMOS transistor N1 according to the clock signal output by the first dead-time control circuit 11.

[0073] In some embodiments, as shown in FIG2, the first switching subunit 122 includes: a first capacitor C1, a second capacitor C2, a second NMOS transistor N2, a third NMOS transistor N3, and a fourth NMOS transistor N4.

[0074] In this circuit, the first terminal of the first capacitor C1 is connected to the third terminal of the first dead-time control circuit 11; the first terminal of the second capacitor C2 is connected to the fourth terminal of the first dead-time control circuit 11; the gate of the second NMOS transistor N2 is connected to the second terminal of the second capacitor C2, and the drain of the second NMOS transistor N2 is connected to the second terminal of the first capacitor C1; the gate of the third NMOS transistor N3 is connected to the second terminal of the first capacitor C1, and the drain of the third NMOS transistor N3 is connected to the second terminal of the second capacitor C2; the gate of the fourth NMOS transistor N4 is connected to the second terminal of the second capacitor C2, and the drain of the fourth NMOS transistor N4 is connected to the first terminal of the first energy storage sub-unit 123; and the sources of the second NMOS transistor N2, the third NMOS transistor N3, and the fourth NMOS transistor N4 are connected together to the source of the first PMOS transistor P1. Therefore, the gate voltage of the third NMOS transistor N3 is changed by the first capacitor C1 to control the conduction state of the third NMOS transistor N3, and the gate voltages of the second NMOS transistor N2 and the fourth NMOS transistor N4 are changed by the second capacitor C2 to control the conduction state of the second NMOS transistor N2 and the fourth NMOS transistor N4.

[0075] In some embodiments, as shown in FIG2, the first energy storage sub-unit 123 includes a third capacitor C3.

[0076] In this circuit, the first terminal of the third capacitor C3 is connected to the drain of the fourth NMOS transistor N4, and the second terminal of the third capacitor C3 is connected to the drain of the first NMOS transistor N1 and the drain of the first PMOS transistor P1. For example, the first terminal (upper plate) of the third capacitor C3 in the primary charge pump circuit 1 serves as the power supply for the secondary charge pump circuit, while the other plate serves as the ground for the secondary charge pump circuit, ensuring that the voltage difference between the power supply and ground of the secondary charge pump circuit does not exceed 5V.

[0077] In some embodiments, as shown in FIG2, the first dead-time control circuit 11 includes: a first logic subunit 111 and a second logic subunit 112.

[0078] The first logic subunit 111 has a first terminal that is a charge pump input terminal, a second terminal that is connected to the gate of the first PMOS transistor P1, a third terminal that is connected to the first terminal of the first capacitor C1, and a fourth terminal that is connected to the first terminal of the second capacitor C2. The first logic subunit 111 is used to control the conduction state of the first PMOS transistor P1 according to a clock signal. The second logic subunit 112 has a first terminal that is connected to the first terminal of the first logic subunit 111, a second terminal that is connected to the second terminal of the first logic subunit 111, and a third terminal that is connected to the gate of the first NMOS transistor N1 and the first terminal of the second capacitor C2. The second logic subunit 112 is used to control the conduction state of the first NMOS transistor N1 according to a clock signal.

[0079] Specifically, the first dead-time control circuit 11 receives a clock signal, the first logic subunit 111 and the second logic subunit 112 perform logical operations on the received clock signal and output the logical operation results, and then control the conduction state of the first NMOS transistor N1 and the first PMOS transistor P1 through the logical operation results.

[0080] In some embodiments, as shown in FIG2, the first logic subunit 111 includes a first NOR gate I1 and a first NOT gate I2.

[0081] In this configuration, the first input terminal of the first NOR gate I1 is the charge pump input terminal, the second input terminal of the first NOR gate I1 is connected to the first terminal of the second capacitor C2 and the third terminal of the second logic subunit 112, and the output terminal of the first NOR gate I1 is connected to the first terminal of the first capacitor C1; the input terminal of the first NOT gate I2 is connected to the output terminal of the first NOR gate I1, and the output terminal of the first NOT gate I2 is connected to the gate of the first PMOS transistor P1 and the second terminal of the second logic subunit 112. In other words, when the clock signal CLK received at the input terminal A of the first NOR gate I1 flips from a low level to a high level, the first NOR gate I1 outputs a low level signal, and the first NOT gate I2 then flips the low level signal output by the first NOR gate I1 back to a high level, at which point the first logic subunit 111 outputs a high level signal.

[0082] In some embodiments, as shown in FIG2, the second logic subunit 112 includes: a first NAND gate I3 and a second NOT gate I4.

[0083] In this configuration, the first input terminal of the first NAND gate I3 is connected to the output terminal of the first NOT gate I2, and the second input terminal of the first NAND gate I3 is connected to the first input terminal of the first NOR gate I1. The input terminal of the second NOT gate I4 is connected to the output terminal of the first NAND gate I3, and the output terminal of the second NOT gate I4 is connected to the second input terminal of the first NOR gate I1, the first terminal of the second capacitor C2, and the gate of the first NMOS transistor N1. That is, when the clock signal CLK / CLK- received at the input terminal B of the first NAND gate I3 is a low-level signal, the first NAND gate I3 outputs a high-level signal, and the second NOT gate I4 then flips the high-level signal to a low-level signal. At this time, the second logic subunit 112 outputs a low-level signal.

[0084] Furthermore, the level signal output by the first NOT gate I2 is first sent to the first PMOS transistor P1 to control the first PMOS transistor P1 to be turned on or off. At the same time, the level signal output by the first NOT gate I2 is sent to the first NAND gate I3. The first NAND gate I3 performs a logical operation on the clock signal and the level signal output by the first NOT gate I2. The second NOT gate I4 performs a logical operation on the level signal output by the first NAND gate I3 to output the logical operation result. Only then can the first NMOS transistor N1 be turned on or off according to the logical operation result. Similarly, the level signal output by the second NOT gate I4 is first sent to the first NMOS transistor N1, so the conduction state of the first NMOS transistor N1 is controlled first and then the conduction state of the first PMOS transistor P1 is controlled. Therefore, there is a time delay in controlling the conduction state of the first PMOS transistor P1 and the first NMOS transistor N1.

[0085] Specifically, when the clock signal is low, the boost circuit 2 boosts the supply voltage multiple times through the multi-stage charge pump circuit 1 to obtain at least one driving voltage signal with a voltage value greater than the supply voltage. That is, the first-stage charge pump circuit 1 includes a first dead-time control circuit 11 and a first voltage adjustment circuit 12. The first dead-time control circuit 11 includes a first logic subunit 111 and a second logic subunit 112. The first voltage adjustment circuit 12 includes a first PMOS transistor P1, a first NMOS transistor N1, a first capacitor C1, a second capacitor C2, a second NMOS transistor N2, a third NMOS transistor N3, and a fourth NMOS transistor N4. The clock signal received by the second logic subunit 112 and the first logic subunit 111 of the first-stage charge pump circuit 1 is a low-level signal. The second logic subunit 112 includes a first NAND gate I3 and a second NOT gate I4. When the clock signal CLK / CLK- received at input B of the first NAND gate I3 is low, the first NAND gate I3 outputs a high-level signal. The second NOT gate I4 then flips the high-level signal to a low-level signal. The gate of the first NMOS transistor N1 receives the low-level signal output by the second NOT gate I4 and is turned off. The gate voltages of the second NMOS transistor N2 and the fourth NMOS transistor N4 are pulled down to approximately equal to VDD through the second capacitor C2. VDD can be 5V. The second NMOS transistor N2 and the fourth NMOS transistor N4 are turned off.The first logic subunit 111 includes a first NOR gate I1 and a first NOT gate I2. Simultaneously, the clock signal received at input terminal A of the first NOR gate I1 is a low-level signal, and the input terminal B of the first NOR gate I1 receives a low-level signal output from the second NOT gate I4. At this time, the first NOR gate I1 outputs a high-level signal. The first NOT gate I2 then flips the high-level signal output by the first NOR gate I1 to a low-level signal. The gate of the first PMOS transistor P1 receives the low-level signal output by the first NOT gate I2 and is turned on. The supply voltage VDD is output from the second terminal (lower plate) of the third capacitor C3 through the first PMOS transistor P1. VDD can be 5V, meaning the second terminal of the third capacitor C3 serves as the low-side output terminal of the first-stage charge pump circuit 1, outputting a voltage value VSS1, where VSS1 = VDD = 5V. Simultaneously, the first capacitor C... 1. The gate voltage of the third NMOS transistor N3 is increased to approximately 5V, and the third NMOS transistor N3 is turned on. The power supply charges the upper plate of the third capacitor C3 through the body diodes of the third NMOS transistor N3 and the fourth NMOS transistor N4, so that the voltage of the upper plate of the third capacitor C3 becomes VDD. Since the voltage of the lower plate of the first capacitor C1 changes from GND to VDD, the third capacitor C3 pumps VCP1 from VDD to 9V. Then, the first terminal of the third capacitor C3 is used as the high-side output terminal of the first-stage charge pump circuit 1 to output the voltage signal VCP1. At the same time, the third capacitor C3 pumps VCP1 from VDD to 9V. Thus, when the clock signal is a low-level signal, the first-stage charge pump circuit 1 boosts the voltage signal provided by the power supply to obtain the boosted voltage signals VCP1 and VSS1.

[0086] The other-stage charge pump circuit 1 includes a first dead-time control circuit 11 and a first voltage adjustment circuit 12. The first dead-time control circuit 11 includes a first logic subunit 111 and a second logic subunit 112. The first voltage adjustment circuit 12 includes a first PMOS transistor P1, a first NMOS transistor N1, a first capacitor C1, a second capacitor C2, a second NMOS transistor N2, a third NMOS transistor N3, and a fourth NMOS transistor N4. The power supply terminal VDD of the other-stage charge pump circuit 1 is connected to the high-side output terminal of the first-stage charge pump circuit 1. Therefore, the voltage signal VCP1 output by the first-stage charge pump circuit 1 to the power supply terminal VDD of the other-stage charge pump circuit 1 through the high-side output terminal is the first-stage charge pump circuit. The voltage signal VSS1 is output to the ground terminal GND of the other stage charge pump circuit 1 through the low-side output terminal. Similarly, the other stage charge pump circuit 1 boosts the voltage signal VCP1 output by the first stage charge pump circuit 1 through the third capacitor C3 to obtain the boosted voltage signal VCP2. Then, the first terminal of the third capacitor C3 is used as the high-side output terminal of the other stage charge pump circuit 1 to output the voltage signal VCP2, where VCP2 = VCP1 + 4V = VDD + 8V = 13V. Similarly, the second terminal of the third capacitor C3 is used as the low-side output terminal of the other stage charge pump circuit 1 to output the voltage signal VSS2, where VSS2 = VCP1 = VDD + 4V = 9V.

[0087] If the boost circuit 2 contains only one other stage charge pump circuit 1 besides the first stage charge pump circuit 1, then the other stage charge pump circuit 1 acts as the final stage charge pump circuit 1, outputting boosted voltage signals VSS2 and VCP2. The output voltage signals VCP2 and VSS2 are the driving voltage signals. The voltage input terminal 44 of the driving output circuit 4 is connected to the high-side output terminal of the final stage charge pump circuit 1, meaning the voltage input terminal 44 of the driving output circuit 4 is connected to the first terminal of the third capacitor C3. Therefore, the driving voltage signal received by the voltage input terminal 44 of the driving output circuit 4 is VCP2. The voltage input terminal 44 of the drive output circuit 4 is connected to the low-side output terminal of the final stage charge pump circuit 1, that is, the voltage input terminal 44 of the drive output circuit 4 is connected to the second terminal of the third capacitor C3. The drive voltage signal received by the voltage input terminal 44 of the drive output circuit 4 is VSS2. Under the action of the clock signal, the drive output circuit 4 selectively outputs the boosted drive voltage signal through the second output terminal. The boosted drive voltage signal output by the drive output circuit 4 is the differential signal. For example, the differential signal can be VCP2 or VSS2, that is, the differential signal can be 13V or 9V.

[0088] If there are multiple other charge pump circuits 1 in the boost circuit 2 besides the first-stage charge pump circuit 1, then each other-stage charge pump circuit 1 boosts the voltage signals at the high-side output and low-side output of the previous-stage charge pump circuit 1 until the high-side output and low-side output of the final-stage charge pump circuit 1 jointly output at least one voltage value greater than the supply voltage of multiple drive voltage signals.

[0089] Alternatively, when the clock signal is a high-level signal, the boost circuit 2 outputs multiple drive voltage signals with voltage values ​​less than or equal to the supply voltage through the multi-stage charge pump circuit 1. That is, the first-stage charge pump circuit 1 includes a first dead-time control circuit 11 and a first voltage adjustment circuit 12. The first dead-time control circuit 11 includes a first logic subunit 111 and a second logic subunit 112. The first voltage adjustment circuit 12 includes a first PMOS transistor P1, a first NMOS transistor N1, a first capacitor C1, a second capacitor C2, a second NMOS transistor N2, a third NMOS transistor N3, and a fourth NMOS transistor N4. When the clock signal received by the second logic subunit 112 and the first logic subunit 111 of the first-stage charge pump circuit 1 is a high-level signal, that is, when the clock signal CLK received by the input terminal A of the first NOR gate I1 is a high-level signal, the first NOR gate I1 outputs a low-level signal. The first NOT gate I2 then flips the low-level signal output by the first NOR gate I1 to a high-level signal. The gate of the first PMOS transistor P1 receives the high-level signal output by the first NOT gate I2 and is turned off. The gate of the third NMOS transistor N3 receives the low-level signal output by the first NOR gate I1, and the first capacitor C1 pulls down the gate voltage of the third NMOS transistor N3 to approximately equal to VDD. At this time, the third NMOS transistor N3 is turned off. The input terminal A of the first NAND gate I3 receives the high-level signal output by the first NOT gate I2. The clock signal received by the input terminal B of the first NAND gate I3 is a high-level signal. At this time, the first NAND gate I3 outputs a low-level signal. The second NOT gate I4 then flips the low-level signal to a high-level signal. The gate of the OS transistor N1 is turned on by receiving a high-level signal from the output of the second NOT gate I4, while the source of the first NMOS transistor N1 is grounded. At this time, the drain of the first NMOS transistor N1 outputs the ground voltage GND to the second terminal of the third capacitor C3. Then, the second terminal of the third capacitor C3 is used as the low-side output terminal of the first-stage charge pump circuit 1 to output the voltage signal VSS1, where VSS1 = GND = 0V. At the same time, the second capacitor C2 raises the gate voltage of the second NMOS transistor N2 and the fourth NMOS transistor N4 by about 5V, so the second NMOS transistor N2 and the fourth NMOS transistor N4 are turned on. At this time, the power supply outputs the voltage signal VCP1 through the drain of the fourth NMOS transistor N4, where VCP1 = VDD = 5V. That is, the power supply charges the third capacitor C3 under the conduction of the fourth NMOS transistor N4, so that the voltage of the first terminal of the third capacitor C3, i.e., the upper plate, becomes VDD. Then, the first terminal of the third capacitor C3 is used as the high-side output terminal of the first-stage charge pump circuit 1 to output the voltage signal VCP1.

[0090] The other stage charge pump circuit 1 includes a first dead-time control circuit 11 and a first voltage adjustment circuit 12. The first dead-time control circuit 11 includes a first logic subunit 111 and a second logic subunit 112. The first voltage adjustment circuit 12 includes a first PMOS transistor P1, a first NMOS transistor N1, a first capacitor C1, a second capacitor C2, a second NMOS transistor N2, a third NMOS transistor N3, and a fourth NMOS transistor N4. Based on this, the power supply terminal of the other stage charge pump circuit 1 is connected to the high-side output terminal of the first stage charge pump circuit 1, and the ground terminal of the other stage charge pump circuit 1 is connected to the low-side output terminal of the first stage charge pump circuit 1. Therefore, the voltage signal of the power supply terminal of the other stage charge pump circuit 1 is VCP1. Similarly, the other stage charge pump circuit 1 outputs the voltage signal VCP2 through the drain of the fourth NMOS transistor N4, where VCP2 = VCP1 = 5V. That is, the first terminal of the third capacitor C3 is used as the high-side output terminal of the charge pump 2 to output the voltage signal VCP2. The other stage charge pump circuit 1 outputs the voltage signal VSS1 of the ground terminal through the source of the first NMOS transistor N1 to the second terminal of the third capacitor C3. Then, the second terminal of the third capacitor C3 is used as the low-side output terminal of the other stage charge pump circuit 1 to output the voltage signal VSS2, where VSS2 = GND = 0V. That is, the second terminal of the third capacitor C3 is used as the low-side output terminal of the charge pump 2 to output the voltage signal VSS2.

[0091] If the boost circuit 2 contains only one other stage charge pump circuit 1 besides the first stage charge pump circuit 1, then the other stage charge pump circuit 1 outputs voltage signals VSS2 and VCP2 as the final stage charge pump circuit 1. Voltage signals VCP2 and VSS2 are drive voltage signals with voltage values ​​less than or equal to the supply voltage. If the boost circuit 2 contains multiple other stage charge pump circuits 1 besides the first stage charge pump circuit 1, then each other stage charge pump circuit 1 outputs unboosted voltage signals VSSn and VCPn to the high-side and low-side output terminals of the previous stage charge pump circuit 1, until the final stage charge pump circuit 1 outputs unboosted voltage signals VSSn and VCPn to its high-side and low-side output terminals. VCPn = VCP2 = 5V, VSSn = VSS2 = 0V. Voltage signals VCP2 and VSS2 are drive voltage signals with voltage values ​​less than or equal to the supply voltage. The voltage input terminal 44 of the drive output circuit 4 is connected to the high-side output terminal of the other stage charge pump circuit 1, that is, the voltage input terminal 44 of the drive output circuit 4 is connected to the first terminal of the third capacitor C3. The drive voltage signal received by the voltage input terminal 44 of the drive output circuit 4 is VCP2. The voltage input terminal 44 of the drive output circuit 4 is connected to the low-side output terminal of the other stage charge pump circuit 1, that is, the voltage input terminal 44 of the drive output circuit 4 is connected to the second terminal of the third capacitor C3. The drive voltage signal received by the voltage input terminal 44 of the drive output circuit 4 is VSS2. Under the action of the clock signal, the drive output circuit 4 selectively outputs the unboosted drive voltage signal through the second output terminal. The unboosted drive voltage signal output by the drive output circuit 4 is the differential signal. For example, the differential signal can be VCP2 or VSS2, that is, the differential signal can be 5V or 0V.

[0092] In some embodiments, the second voltage adjustment circuit 14 includes: a second voltage adjustment subunit 141, a second switching subunit 142, and a second energy storage subunit 143.

[0093] The second voltage adjustment subunit 141 has the following characteristics: its first terminal receives the supply voltage; its second terminal is connected to the second terminal of the second dead-time control circuit 15; its third terminal is connected to the fifth terminal of the second dead-time control circuit 15; and its fourth terminal is grounded. The second switching subunit 142 has its first connection terminal connected to the third terminal of the second dead-time control circuit 15; its second connection terminal is connected to the fourth terminal of the second dead-time control circuit 15. The second energy storage subunit 143 has its first terminal connected to the fifth terminal of the second voltage adjustment subunit 141 and outputs a high-side output terminal; and its second terminal connected to the third connection terminal of the second switching subunit 142 and outputs a low-side output terminal.

[0094] Specifically, the first-stage charge pump circuit 1 of the boost circuit 2 includes a second dead-time control circuit 15. The clock signal received by the second dead-time control circuit 15 controls the state of the second voltage adjustment subunit 141 and the second switch subunit 142, so that the power supply can charge the two ends of the second energy storage subunit 143 through the second voltage adjustment subunit 141 and output the boosted voltage signal through the two ends of the second energy storage subunit 143, thereby boosting the power supply voltage. Alternatively, the power supply can charge one end of the second energy storage subunit 143 through the second voltage adjustment subunit 141 and the second switch subunit 142, so that the power supply voltage can be directly output through the two ends of the second energy storage subunit 143.

[0095] In some embodiments, as shown in FIG3, the second voltage adjustment subunit 141 includes a second PMOS transistor P2 and a fifth NMOS transistor N5.

[0096] In this circuit, the source of the second PMOS transistor P2 receives the supply voltage, the gate of the second PMOS transistor P2 is connected to the second terminal of the second dead-time control circuit 15, and the drain of the second PMOS transistor P2 is connected to the first terminal of the second energy storage sub-unit 143. The gate of the fifth NMOS transistor N5 is connected to the fifth terminal of the second dead-time control circuit 15, the drain of the fifth NMOS transistor N5 is connected to the drain of the second PMOS transistor P2 and the first terminal of the second energy storage sub-unit 143, and the source of the fifth NMOS transistor N5 is grounded. In other words, the gate of the second PMOS transistor P2 controls the conduction state of the second PMOS transistor P2 according to the clock signal output by the second dead-time control circuit 15, and the gate of the fifth NMOS transistor N5 controls the conduction state of the fifth NMOS transistor N5 according to the clock signal output by the second dead-time control circuit 15.

[0097] In some embodiments, as shown in FIG3, the second switching subunit 142 includes: a fourth capacitor C4, a fifth capacitor C5, a third PMOS transistor P3, a fourth PMOS transistor P4, and a fifth PMOS transistor P5.

[0098] In this circuit, the first terminal of the fourth capacitor C4 is connected to the third terminal of the second dead-time control circuit 15; the first terminal of the fifth capacitor C5 is connected to the fourth terminal of the second dead-time control circuit 15; the gate of the third PMOS transistor P3 is connected to the second terminal of the fourth capacitor C4, and the drain of the third PMOS transistor P3 is connected to the second terminal of the fifth capacitor C5; the gate of the fourth PMOS transistor P4 is connected to the second terminal of the fifth capacitor C5, and the drain of the fourth PMOS transistor P4 is connected to the second terminal of the fourth capacitor C4; the gate of the fifth PMOS transistor P5 is connected to the second terminal of the fourth capacitor C4, and the drain of the fifth PMOS transistor P5 is connected to the second terminal of the second energy storage sub-unit 143; and the sources of the third PMOS transistor P3, the fourth PMOS transistor P4, and the fifth PMOS transistor P5 are all grounded. Therefore, by changing the gate voltages of the third PMOS transistor P3 and the fifth PMOS transistor P5 through the fourth capacitor C4, the conduction state of the third PMOS transistor P3 and the fifth PMOS transistor P5 is controlled. Similarly, by changing the gate voltage of the fourth PMOS transistor P4 through the fifth capacitor C5, the conduction state of the fourth PMOS transistor P4 is controlled.

[0099] In some embodiments, as shown in FIG3, the second energy storage sub-unit 143 includes a sixth capacitor C6.

[0100] The first terminal of the sixth capacitor C6 is connected to the drain of the second PMOS transistor P2 and the drain of the fifth NMOS transistor N5, and the second terminal of the sixth capacitor C6 is connected to the drain of the fifth PMOS transistor P5.

[0101] In some embodiments, the second dead-time control circuit 15 includes a third logic subunit 151 and a fourth logic subunit 152.

[0102] The third logic subunit 151 has a first terminal that is a charge pump input terminal, a second terminal that is connected to the gate of the second PMOS transistor P2 and the first terminal of the fourth capacitor C4, and is used to control the conduction state of the second PMOS transistor P2 according to a clock signal. The fourth logic subunit 152 has a first terminal that is connected to the first terminal of the third logic subunit 151, a second terminal that is connected to the second terminal of the third logic subunit 151, a third terminal that is connected to the first terminal of the fifth capacitor C5, and a fourth terminal that is connected to the third terminal of the third logic subunit 151 and the gate of the fifth NMOS transistor N5, and is used to control the conduction state of the fifth NMOS transistor N5 according to a clock signal.

[0103] Specifically, the second dead-time control circuit 15 receives a clock signal, the third logic subunit 151 and the fourth logic subunit 152 perform logical operations on the received clock signal and output the logical operation result, and then control the conduction state of the second PMOS transistor P2 and the fifth NMOS transistor N5 through the logical operation result.

[0104] In some embodiments, as shown in FIG3, the third logic subunit 151 includes a second NOR gate I5 and a third NOT gate I6.

[0105] In this system, the first input terminal of the second NOR gate I5 is the charge pump input terminal, and the second input terminal of the second NOR gate I5 is connected to the fourth terminal of the fourth logic subunit 152. The input terminal of the third NOT gate I6 is connected to the output terminal of the second NOR gate I5, and the output terminal of the third NOT gate I6 is connected to the gate of the second PMOS transistor P2, the first terminal of the fourth capacitor C4, and the second terminal of the fourth logic subunit 152. That is, when the clock signal CLK / CLK- received at the input terminal A of the second NOR gate I5 is a high-level signal, the second NOR gate I5 outputs a low-level signal, and the third NOT gate I6 then flips the low-level signal output by the second NOR gate I5 to a high-level signal.

[0106] In some embodiments, as shown in FIG3, the fourth logic subunit 152 includes a second NAND gate I7 ​​and a fourth NOT gate I8.

[0107] In this configuration, the first input of the second NAND gate I7 ​​is connected to the output of the third NOT gate I6; the second input of the second NAND gate I7 ​​is connected to the first input of the second NOR gate I5; and the output of the second NAND gate I7 ​​is connected to the first terminal of the fifth capacitor C5. The input of the fourth NOT gate I8 is connected to the output of the second NAND gate I7, and the output of the fourth NOT gate I8 is connected to the second input of the second NOR gate I5 and the gate of the fifth NMOS transistor N5. When the clock signal CLK / CLK- received by pin B of the second NAND gate I7 ​​is low, the second NAND gate I7 ​​outputs a high-level signal. The fourth NOT gate I8 then flips the high-level signal output by the second NAND gate I7 ​​back to a low-level signal.

[0108] Furthermore, the level signal output by the third NOT gate I6 is first sent to the second PMOS transistor P2 to control the second PMOS transistor P2 to turn on or off. At the same time, the level signal output by the third NOT gate I6 is sent to the second NAND gate I7. The second NAND gate I7 ​​performs a logical operation on the clock signal and the level signal output by the third NOT gate I6. The fourth NOT gate I8 performs a logical operation on the level signal output by the first NAND gate I3 to output the logical operation result. Only then can the fifth NMOS transistor N5 turn on or off according to the logical operation result. Similarly, the level signal output by the fourth NOT gate I8 is first sent to the fifth NMOS transistor N5, so the conduction state of the fifth NMOS transistor N5 is controlled first and then the conduction state of the second PMOS transistor P2 is controlled. Therefore, there is a time delay in controlling the conduction states of the second PMOS transistor P2 and the fifth NMOS transistor N5.

[0109] Specifically, the boost circuit 2 boosts the supply voltage when the clock signal is low to obtain at least one drive voltage signal with a voltage value greater than the supply voltage. That is, the first-stage charge pump circuit 1 includes a second dead-time control circuit 15 and a second voltage adjustment circuit 14. The second dead-time control circuit 15 includes a third logic subunit 151 and a fourth logic subunit 152. The second voltage adjustment circuit 14 includes a second PMOS transistor P2, a fifth NMOS transistor N5, a fourth capacitor C4, a fifth capacitor C5, a third PMOS transistor P3, a fourth PMOS transistor P4, a fifth PMOS transistor P5, and a sixth capacitor C6. Based on this, the clock signal received by the third logic subunit 151 and the fourth logic subunit 152 of the first-stage charge pump circuit 1 is a low-level signal. The third logic subunit 151 includes a second NOR gate I5 and a third NOT gate I6, and the fourth logic subunit 152 includes a second NAND gate I7 ​​and a fourth NOT gate I8. When the clock signal CLK / CLK- received at input B of the second NAND gate I7 ​​is low, the second NAND gate I7 ​​outputs a high-level signal. The gate of the fourth PMOS transistor P4 receives the high-level signal from the second NAND gate I7 ​​and pulls the gate voltage of the fourth PMOS transistor P4 up to approximately GND through the fifth capacitor C5, thus turning off the fourth PMOS. Then, the fourth NOT gate I8 flips the high-level signal output from the second NAND gate I7 ​​to a low-level signal. The gate of the fifth PMOS transistor receives the low-level signal output from the fourth NOT gate I8 and is turned off. Then, the input B of the second NOR gate I5 receives the low-level signal output from the fourth NOT gate I8. When the clock signal received at input A of the second NOR gate I5 is low, the second NOR gate I5 outputs a high-level signal. The third NOT gate I6 then flips the second NOR gate... The high-level signal output by I5 flips to a low-level signal, and the gate of the second PMOS transistor P2 receives the low-level signal output by the third NOT gate I6 and turns on. At this time, the output voltage VDD of the power supply is output through the first terminal of the sixth capacitor C6 under the conduction of the second PMOS transistor P2, and the output voltage value VCP3 = VDD = 5V. At the same time, the gates of the third PMOS transistor P3 and the fifth PMOS transistor P5 receive the low-level signal output by the third NOT gate I6, and the fourth capacitor C4 pulls down the gate voltage of the third PMOS transistor P3 and the fifth PMOS transistor P5 to about 5V, and the third PMOS transistor P3 and the fifth PMOS transistor P5 turn on. At this time, the drain output voltage of the fifth PMOS transistor P5 is VSS3, and the voltage value output by the first terminal of the sixth capacitor C6 is VSS3, where VSS3 = GND = 0V.

[0110] The other-stage charge pump circuit 1 includes a first level shift circuit 13, a first dead-time control circuit 11, and a first voltage adjustment circuit 12. The first dead-time control circuit 11 includes a first logic subunit 111 and a second logic subunit 112. The first voltage adjustment circuit 12 includes a first PMOS transistor P1, a first capacitor C1, a second capacitor C2, a first NMOS transistor N1, a second NMOS transistor N2, a third NMOS transistor N3, a fourth NMOS transistor N4, and a third capacitor C3. Based on this, since the power supply terminal of the other-stage charge pump circuit 1 is connected to the first-stage power supply... The high-side output terminal of charge pump circuit 1 is connected, therefore the voltage signal output by the first-stage charge pump circuit 1 to the power supply terminal of other stage charge pump circuits 1 through the high-side output terminal is VCP3, and the voltage signal output by the first-stage charge pump circuit 1 to the ground terminal of other stage charge pump circuits 1 through the low-side output terminal is VSS3. Similarly, other stage charge pump circuits 1 boost the voltage signals VCP3 and VSS3 output by the first-stage charge pump circuit 1 through the first dead-time control circuit 11 and the first voltage adjustment circuit 12 to obtain the boosted voltage signals VCP4 and VSS3. VSS4, that is, the other stage charge pump circuit 1 outputs the voltage signal VSS4 through the first PMOS transistor P1 from the second terminal of the third capacitor C3, that is, the second terminal of the third capacitor C3 is used as the low-side output terminal of the charge pump 2 to output the voltage value VSS4, where VSS4 = VDD = 5V. The other stage charge pump circuit 1 also boosts the voltage signal VCP3 of the first stage charge pump circuit 1 through the third capacitor C3 to obtain the boosted voltage signal VCP4. Then, the first terminal of the third capacitor C3 is used as the high-side output terminal of the other stage charge pump circuit 1 to output the voltage value VCP4, where VCP4 = VCP3 + 4V = 9V, that is, the first terminal of the third capacitor C3 is used as the high-side output terminal of the other stage charge pump circuit 1 to output the voltage value VCP4. Thus, when the clock signal is a low level signal, the other stage charge pump circuit 1 boosts the voltage signal VCP3 provided by the power supply to use the boosted voltage signals VCP4 and VSS4 as driving voltage signals. At least one of VCP4 and VSS4 is a driving voltage signal with a voltage value greater than the supply voltage.

[0111] Based on this, if the boost circuit 2 contains only one other stage charge pump circuit 1 besides the first stage charge pump circuit 1, then the other stage charge pump circuit 1 acts as the final stage charge pump circuit 1, outputting boosted voltage signals VCP4 and VSS4. These voltage signals VCP4 and VSS4 are the driving voltage signals. The voltage input terminal 44 of the drive output circuit 4 is connected to the high-side output terminal of the final stage charge pump circuit 1, meaning the voltage input terminal 44 of the drive output circuit 4 is connected to the first terminal of the third capacitor C3. Therefore, the driving voltage signal received by the voltage input terminal 44 of the drive output circuit 4 is VCP4, and... The voltage input terminal 44 of the drive output circuit 4 is connected to the low-side output terminal of the final stage charge pump circuit 1, that is, the voltage input terminal 44 of the drive output circuit 4 is connected to the second terminal of the third capacitor C3. The drive voltage signal received by the voltage input terminal 44 of the drive output circuit 4 is VSS4. Under the action of the clock signal, the drive output circuit 4 selectively outputs the boosted drive voltage signal through the second output terminal. The boosted drive voltage signal output by the drive output circuit 4 is the differential signal. For example, the differential signal can be VCP4 or VSS4, that is, the differential signal can be 9V or 5V.

[0112] If there are multiple other charge pump circuits 1 in the boost circuit 2 besides the first-stage charge pump circuit 1, then each other-stage charge pump circuit 1 boosts the voltage signals at the high-side output and low-side output of the previous-stage charge pump circuit 1 until the high-side output and low-side output of the final-stage charge pump circuit 1 jointly output at least one voltage value greater than the supply voltage of multiple drive voltage signals.

[0113] In this embodiment, the boost circuit 2 outputs multiple drive voltage signals with voltage values ​​less than or equal to the supply voltage when the clock signal is a high-level signal. That is, the first-stage charge pump circuit 1 includes a second dead-time control circuit 15 and a second voltage adjustment circuit 14. The second dead-time control circuit 15 includes a third logic subunit 151 and a fourth logic subunit 152. The second voltage adjustment circuit 14 includes a second PMOS transistor P2, a fifth NMOS transistor N5, a fourth capacitor C4, a fifth capacitor C5, a third PMOS transistor P3, a fourth PMOS transistor P4, a fifth PMOS transistor P5, and a sixth capacitor C6. Based on this, the clock signal received by the third logic subunit 151 and the fourth logic subunit 152 of the first-stage charge pump circuit 1 is a high-level signal. The third logic subunit 151 includes a second NOR gate I5 and a third NOT gate I6, and the fourth logic subunit 152 includes a second NAND gate I7 ​​and a fourth NOT gate I8. When the clock signal CLK / CLK- received at input terminal A of the second NOR gate I5 is high, the second NOR gate I5 outputs a low-level signal. The third NOT gate I6 then flips the low-level signal output by the second NOR gate I5 to a high-level signal. The gate of the second PMOS transistor P2 receives the high-level signal output by the third NOT gate I6 and is turned off. At the same time, the gate voltages of the third PMOS transistor P3 and the fifth PMOS transistor P5 are pulled up to approximately GND through the fourth capacitor C4, and the third PMOS transistor P3 and the fifth PMOS transistor P5 are turned off. When the clock signal received at input terminal B of the second NAND gate I7 ​​is high, the input terminal A of the second NAND gate I7 ​​receives the high-level signal output by the third NOT gate I6. At this time, the second NAND gate I7 ​​outputs a low-level signal. The fourth NOT gate I8 then flips the low-level signal output by the second NAND gate I7 ​​to a high-level signal. When the low-level signal flips to a high-level signal, the gate of the fifth NMOS transistor N5 receives the high-level signal and turns on. The source of the fifth NMOS transistor N5 is grounded. At this time, the ground terminal voltage is output through the drain of the fifth NMOS transistor N5 and the first terminal of the sixth capacitor C6. That is, the first terminal of the sixth capacitor C6, i.e., the upper plate, is used as the high-side output terminal of the first-stage charge pump circuit 1 to output the voltage value VCP3, where VCP3 = GND = 0V. At the same time, the gate of the fourth PMOS transistor P4 receives the low-level signal output by the second NAND gate I7, and the gate voltage of the fourth PMOS transistor P4 is pulled down by about 5V through the fifth capacitor C5, and the fourth PMOS transistor P4 turns on. At the same time, VSS3 is pumped from GND to about GND-4V = -4V through the sixth capacitor C6, and then the voltage value VSS3 is output through the first terminal of the sixth capacitor C6.

[0114] The other-stage charge pump circuit 1 includes a first level shift circuit 13, a first dead-time control circuit 11, and a first voltage adjustment circuit 12. The first dead-time control circuit 11 includes a first logic subunit 111 and a second logic subunit 112. The first voltage adjustment circuit 12 includes a first PMOS transistor P1, a first capacitor C1, a second capacitor C2, a first NMOS transistor N1, a second NMOS transistor N2, a third NMOS transistor N3, a fourth NMOS transistor N4, and a third capacitor C3. Since the power supply terminal of the other-stage charge pump circuit 1 is connected to the high-side output terminal of the first-stage charge pump circuit 1, the voltage value output by the first-stage charge pump circuit 1 to the power supply terminal of the other-stage charge pump circuit 1 through the high-side output terminal is VCP. 3. The voltage value VSS3 output by the first-stage charge pump circuit 1 to the ground terminal of the other-stage charge pump circuit 1 through the low-side output terminal is similarly. The other-stage charge pump circuit 1 outputs the voltage VCP3 through the fourth NMOS transistor N4 from the first terminal of the third capacitor C3, that is, the first terminal of the third capacitor C3 is used as the high-side output terminal of the other-stage charge pump circuit 1 to output the voltage value VCP4, where VCP4 = VCP3 = 0V. The other-stage charge pump circuit 1 outputs the voltage signal VSS3 through the first NMOS transistor N1 from the second terminal of the third capacitor C3, that is, the second terminal of the third capacitor C3 is used as the low-side output terminal of the charge pump 2 to output the voltage signal VSS4, where VSS4 = -4V.

[0115] Based on this, if there is only one other stage charge pump circuit 1 besides the first stage charge pump circuit 1 in the boost circuit 2, then the other stage charge pump circuit 1 outputs unboosted voltage signals VCP4 and VSS4 as the final stage charge pump circuit 1. Alternatively, if there are multiple other stage charge pump circuits 1 besides the first stage charge pump circuit 1 in the boost circuit 2, then each other stage charge pump circuit 1 outputs unboosted voltage signals VCPn and VSSn to the high-side and low-side output terminals of the previous stage charge pump circuit 1, until the final stage charge pump circuit 1 outputs unboosted voltage signals VCPn and VSSn through the high-side and low-side output terminals, where VCPn = VCP4 = 0V and VSSn = VSS4 = -4V. The unboosted voltage signals VCP4 and VSS4 are the driving voltage signals, and the voltage input terminal 44 of the driving output circuit 4 is connected to the final stage. The high-side output terminal of charge pump circuit 1 is connected to the voltage input terminal 44 of drive output circuit 4, which is connected to the first terminal of the third capacitor C3. The drive voltage signal received by the voltage input terminal 44 of drive output circuit 4 is VCP4. The low-side output terminal of drive output circuit 4 is connected to the low-side output terminal of the final stage charge pump circuit 1, which is connected to the second terminal of the third capacitor C3. The drive voltage signal received by the voltage input terminal 44 of drive output circuit 4 is VSS4. Under the action of the clock signal, drive output circuit 4 selectively outputs the unboosted drive voltage signal through the second output terminal. The unboosted drive voltage signal output by drive output circuit 4 is the differential signal. For example, the differential signal can be VCP4 or VSS4, that is, the differential signal can be 0V or -4V.

[0116] In some embodiments, as shown in FIG4, the drive output circuit 4 includes: a second level shifting circuit 41, a third dead-time control circuit 42, and a signal processing circuit 43.

[0117] The second level shift circuit 41 receives a clock signal at its input and shifts the driving voltage signal to the input voltage of the driving output circuit 4. The third dead-time control circuit 42 is connected to the output of the second level shift circuit 41 and outputs a clock signal with a dead time based on the clock signal. The power supply of the signal processing circuit 43 is connected to the high-side output of the final stage charge pump circuit 1 in the corresponding boost circuit 2, and its ground is connected to the low-side output of the final stage charge pump circuit 1 in the corresponding boost circuit 2. The control of the signal processing circuit 43 is connected to the third dead-time control circuit 42, and it outputs a differential signal based on the clock signal with dead time and multiple driving voltage signals. The power supply VCP and ground VSS of the signal processing circuit 43 serve as the voltage input 44 of the driving output circuit 4. Specifically, the input terminal of the second level shift circuit 41 unit of the drive output circuit 4 receives a clock signal and shifts the drive voltage signal output by the final stage charge pump circuit 1 to the input voltage of the drive output circuit 4. The third dead-time control circuit 42 obtains the clock signal output by the second level shift circuit 41 unit and inputs the clock signal to the signal processing circuit 43 through the first input terminal. The signal processing circuit 43 outputs the drive voltage signal of the low-side output terminal of the final stage charge pump circuit 1 obtained by the ground terminal according to the clock signal with dead time, or outputs the drive voltage signal of the high-side output terminal of the final stage charge pump circuit 1 obtained by the power supply terminal according to the clock signal with dead time, so as to output the drive voltage signal as a differential signal through the output terminal of the signal processing circuit 43. Thus, the signal processing circuit 43 selectively outputs the drive voltage signal as a differential signal according to the clock signal with dead time.

[0118] Therefore, the MOSFET used in the drive output circuit 4 of this application is a low-voltage MOSFET, which can reduce the layout area and cost compared to the high-voltage MOSFET used in the existing drive output circuit 4.

[0119] In some embodiments, as shown in FIG4, the signal processing circuit 43 includes a sixth PMOS transistor P6 and a sixth NMOS transistor N6.

[0120] In this circuit, the gate of the sixth PMOS transistor P6 is connected to the first output terminal 21 of the third dead-time control circuit 42, the source of the sixth PMOS transistor P6 is connected to the high-side output terminal of the final stage charge pump circuit 1 in the corresponding boost circuit 2, the gate of the sixth NMOS transistor N6 is connected to the second output terminal of the third dead-time control circuit 42, the source of the sixth NMOS transistor N6 is connected to the low-side output terminal of the final stage charge pump circuit 1 in the corresponding boost circuit 2, and the drain of the sixth NMOS transistor N6 is connected to the drain of the sixth PMOS transistor P6 and used to output a differential signal. In other words, the sixth PMOS transistor P6 and the sixth NMOS transistor N6 selectively output the drive voltage signal as a differential signal according to the clock signal output by the third dead-time control circuit 42.

[0121] In some embodiments, as shown in FIG4, the third dead-time control circuit 42 includes a fifth logic subunit 421 and a sixth logic subunit 422.

[0122] The fifth logic subunit 421 has its first terminal connected to the output terminal of the second level shift circuit 41, and its second terminal connected to the gate of the sixth PMOS transistor P6. The fifth logic subunit 421 is used to control the conduction state of the sixth PMOS transistor P6 according to the clock signal. The sixth logic subunit 422 has its first terminal connected to the second terminal of the fifth logic subunit 421, and its second terminal connected to the output terminal of the second level shift circuit 41. The sixth logic subunit 422 has its third terminal connected to the third terminal of the fifth logic subunit 421 and the gate of the sixth NMOS transistor N6. The sixth logic subunit 422 is used to control the conduction state of the sixth NMOS transistor N6 according to the clock signal.

[0123] Specifically, the third dead-time control circuit 42 of the drive output circuit 4 receives the clock signal, and the fifth logic subunit 421 and the sixth logic subunit 422 perform logic operations on the received clock signal and output the logic operation result. Then, the conduction state of the sixth PMOS transistor P6 and the sixth NMOS transistor N6 is controlled by the logic operation result. When the sixth PMOS transistor P6 is turned on by the logic operation result, the drive voltage signal obtained by the power supply terminal of the signal processing circuit 43 from the high-side output terminal of the final stage charge pump circuit 1 is output through the sixth PMOS transistor P6. Alternatively, when the sixth NMOS transistor N6 is turned on by the logic operation result, the drive voltage signal obtained by the ground terminal of the signal processing circuit 43 from the low-side output terminal of the final stage charge pump circuit 1 is output through the sixth NMOS transistor N6. Thus, the drive output circuit 4 selectively outputs the drive voltage signal as a differential signal according to the clock signal.

[0124] In some embodiments, as shown in FIG4, the fifth logic subunit 421 includes a third NOR gate I9 and a fifth NOT gate I10.

[0125] In this circuit, the first input terminal of the third NOR gate I9 is ​​connected to the output terminal of the second level shift circuit 41, and the second input terminal of the third NOR gate I9 is ​​connected to the third terminal of the sixth logic subunit 422; the input terminal of the fifth NOT gate I10 is connected to the output terminal of the third NOR gate I9, and the output terminal of the fifth NOT gate I10 is connected to the gate of the sixth PMOS transistor P6 and the first terminal of the sixth logic subunit 422. That is, the input terminal A of the third NOR gate I9 receives a high-level signal output by the second level shift circuit 41, the third NOR gate I9 outputs a low-level signal, and the fifth NOT gate I10 then flips the low-level signal output by the third NOR gate I9 to a high-level signal.

[0126] In some embodiments, as shown in FIG4, the sixth logic subunit 422 includes a third NAND gate I11 and a sixth NOT gate I12.

[0127] Specifically, the first input terminal of the third NAND gate I11 is connected to the output terminal of the fifth NOT gate I10, and the second input terminal of the third NAND gate I11 is connected to the output terminal of the second level shift circuit 41; the input terminal of the sixth NOT gate I12 is connected to the output terminal of the third NAND gate I11, and the output terminal of the sixth NOT gate I12 is connected to the second input terminal of the third NOR gate I9 and the gate of the sixth NMOS transistor N6. That is, when the input terminal B of the third NAND gate I11 receives the clock signal CLK / CLK- output by the second level shift circuit 41 and is a low-level signal, the third NAND gate I11 outputs a high-level signal, and the sixth NOT gate I12 then flips the high-level signal output by the third NAND gate I11 to a low-level signal.

[0128] Furthermore, the level signal output by the fifth NOT gate I10 is first sent to the sixth PMOS transistor P6 to control the sixth PMOS transistor P6 to be turned on or off. At the same time, the level signal output by the fifth NOT gate I10 is sent to the third NAND gate I11. The third NAND gate I11 performs a logical operation on the clock signal and the level signal output by the fifth NOT gate I10. The sixth NOT gate I12 performs a logical operation on the level signal output by the third NAND gate I11 to output the logical operation result. Then the sixth NMOS transistor N6 can be turned on or off according to the logical operation result. Similarly, the level signal output by the sixth NOT gate I12 is first sent to the sixth NMOS transistor N6, so the conduction state of the sixth NMOS transistor N6 is controlled first and then the conduction state of the sixth PMOS transistor P6 is controlled. Therefore, there is a time delay in controlling the conduction state of the sixth PMOS transistor P6 and the sixth NMOS transistor N6. That is, the third dead-time control circuit 42 is used to output a clock signal with dead time according to the clock signal.

[0129] Specifically, the voltage signals VCP2 and VSS2 output from the boost circuit 2 are used as driving voltage signals. The voltage input terminal 44 of the driving output circuit 4 is connected to the high-side output terminal of the final stage charge pump circuit 1, so the driving voltage signal received by the voltage input terminal 44 of the driving output circuit 4 is VCP2. Similarly, when the voltage input terminal 44 of the driving output circuit 4 is connected to the low-side output terminal of the final stage charge pump circuit 1, the driving voltage signal received by the voltage input terminal 44 of the driving output circuit 4 is VSS2. Based on this, when the clock signal CLK / CLK- received by the third dead-time control circuit 42 of the driving output circuit 4 is a high-level signal (i.e., the input terminal A of the third NOR gate I9 receives a high-level signal), the third NOR gate I9 outputs a low-level signal. The fifth NOT gate I10 then flips the low-level signal output by the third NOR gate I9 back to a high-level signal. The gate of the sixth PMOS transistor P6 is turned off upon receiving the high-level signal output from the fifth NOT gate I10. The input terminal A of the third NAND gate I11 receives the high-level signal output from the fifth NOT gate I10, and the input terminal B of the third NAND gate I11 receives the clock signal CLK / CLK-, which is a high-level signal. The third NAND gate I11 outputs a low-level signal, and the sixth NOT gate I12 flips the low-level signal output from the third NAND gate I11 to a high-level signal. The gate of the sixth NMOS transistor N6 is turned on upon receiving the high-level signal output from the second NOT gate I4. At this time, the voltage input terminal 44 of the drive output circuit 4 outputs the drive voltage signal VSS2 received from the low-side output terminal of the final stage charge pump circuit 1 through the sixth NMOS transistor N6. The differential signal output by the drive output circuit 4 is the drive voltage signal VSS2, where VSS2 is 0V.

[0130] When the input B of the third NAND gate I11 receives a low-level clock signal CLK / CLK-, the third NAND gate I11 outputs a high-level signal. The sixth NOT gate I12 then flips the high-level signal output by the third NAND gate I11 to a low-level signal. The gate of the sixth NMOS transistor N6 receives the low-level signal output by the sixth NOT gate I12 and is turned off. The input A of the third NOR gate I9 receives a low-level clock signal, and the input B of the third NOR gate I9 receives the low-level signal output by the sixth NOT gate I12. The clock signal received at input terminal A of 9 is a low-level signal. The third NOR gate I9 outputs a high-level signal. The fifth NOT gate I10 then flips the high-level signal output by the third NOR gate I9 to a low-level signal. The gate of the sixth PMOS transistor P6 receives the low-level signal output by the fifth NOT gate I10 and turns on. At this time, the drive voltage signal VCP2 output by the high-side output terminal of the final stage charge pump circuit 1 is output through the sixth PMOS transistor P6. Then the differential signal output by the drive output circuit 4 is the drive voltage signal VCP2, where VCP2 is 13V.

[0131] Furthermore, if the power supply terminal of the drive output circuit 4 receives the drive voltage signal VCP4 from the high-side output terminal of the final stage charge pump circuit 1, and the ground terminal of the drive output circuit 4 receives the drive voltage signal VSS4 from the low-side output terminal of the final stage charge pump circuit 1, and if the clock signal CLK / CLK- is a high-level signal, then the drive voltage signal VSS4 from the ground terminal of the drive output circuit 4 is output through the sixth NMOS transistor N6, and the differential signal output by the drive output circuit 4 is the drive voltage signal VSS4, which is -4V. If the clock signal CLK / CLK- is a low-level signal, then the drive voltage signal VCP4 from the power supply terminal of the drive output circuit 4 is output through the sixth PMOS transistor P6, and the differential signal output by the drive output circuit 4 is the drive voltage signal VCP4, where VCP4 is 9V.

[0132] For example, the boost circuit 2 includes a first-stage charge pump circuit 1 and a last-stage charge pump circuit 1 as shown in Figure 2. The first-stage charge pump circuit 1 is the first charge pump circuit 1, and the last-stage charge pump circuit 1 is the second charge pump circuit 1. Based on the above circuit structure, if the clock signal CLK received by the first dead-time control circuit 11 of the first boost circuit 2 is a high-level signal, the drive voltage signal received by the power supply terminal of the drive output circuit 4 corresponding to the first boost circuit 2 is VCP2, where VCP2 = 5V. The drive voltage signal VSS2 received by the ground terminal of the drive output circuit 4 is VSS2, where VSS2 = 0V. The clock signal CLK received by the drive output circuit 4 is a high-level signal. At this time, the ground terminal of the drive output circuit 4 will receive the drive voltage signal VSS2 and output it through the sixth NMOS transistor N6. Then, the first differential signal output by the drive output circuit 4 is the drive voltage signal VSS2. Since the clock signal CLK and the clock signal CLK- are inversely related, the second boost circuit... The clock signal CLK- received by the first dead-time control circuit 11 of circuit 2 is a low-level signal. The driving voltage signal received by the power supply terminal of the driving output circuit 4 corresponding to the second boost circuit 2 is VCP2, where VCP2 is 13V. The driving voltage signal received by the ground terminal of the driving output circuit 4 is VSS2, where VSS2 = 9V. At this time, the power supply terminal of the driving output circuit 4 will receive the driving voltage signal VCP2 and output it through the sixth PMOS transistor P6. Then the second differential signal output by the driving output circuit 4 is the driving voltage signal VCP2. Based on this, since the first differential signal output by the driving output circuit 4 corresponding to the first boost circuit 2 is 0V, and the second differential signal output by the driving output circuit 4 corresponding to the second boost circuit 2 is 13V, the operating states of the driving components controlled by the first differential signal and the second differential signal are different. That is, the first driving component controlled by the first differential signal stops working, and the second driving component controlled by the second differential signal starts working.

[0133] Alternatively, the boost circuit 2 includes a first-stage charge pump circuit 1 and a last-stage charge pump circuit 1 as shown in Figure 3. The first-stage charge pump circuit 1 is the first charge pump circuit 1, and the last-stage charge pump circuit 1 is the second charge pump circuit 1. Based on the above circuit structure, if the clock signal CLK received by the first dead-time control circuit of the first boost circuit 2 is a low-level signal, the drive voltage signal received by the power supply terminal of the corresponding drive output circuit 4 of the first boost circuit 2 is VCP4, where VCP4 = 9V. The drive voltage signal received by the ground terminal of the drive output circuit 4 is VSS4, where VSS4 = 5V. At this time, the power supply terminal of the drive output circuit 4 outputs the received drive voltage signal VCP4 through the sixth PMOS transistor P6. Then, the first differential signal output by the drive output circuit 4 is the drive voltage signal VCP4. Since the clock signals CLK and CLK- are inverses of each other, the clock signal CLK- received by the first dead-time control circuit of the second boost circuit 2 is a high-level signal. The driving voltage signal received by the power supply terminal of the corresponding drive output circuit 4 of the second boost circuit 2 is VCP4, where VCP4 is 0V. The driving voltage signal received by the ground terminal of the drive output circuit 4 is VSS4, where VSS4 = -4V. At this time, the ground terminal of the drive output circuit 4 outputs the received driving voltage signal VSS4 through the sixth NMOS transistor N6. The second differential signal output by the drive output circuit 4 is the driving voltage signal VSS4. Based on this, since the first differential signal is 9V and the second differential signal is -4V, the operating states of the drive components controlled by the first differential signal and the second differential signal are different.

[0134] A second aspect of this disclosure provides a driving system 900, as shown in FIG5, which includes the differential signal output circuit 800 of the above embodiment.

[0135] According to the drive system 900 of this disclosure, the differential signal output circuit 800 of the above embodiment can output a higher voltage differential signal by setting a boost circuit 2.

[0136] A third aspect of this disclosure provides a vehicle 1000, as shown in FIG6, which includes the drive system 900 described in the above embodiments.

[0137] According to the vehicle of the present disclosure, the drive system of the above embodiment can output a higher voltage differential signal by setting up a boost circuit 2.

[0138] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of this disclosure. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example.

[0139] Although embodiments of this disclosure have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of this disclosure, the scope of which is defined by the claims and their equivalents.

Claims

1. A differential signal output circuit (800), characterized in that, include: The boost circuit (2) has a first input terminal for receiving a clock signal and a power supply terminal for receiving a supply voltage. The boost circuit (2) is used to control multiple first output terminals (21) to output at least one driving voltage signal with a voltage value greater than the supply voltage when the clock signal is a low-level signal, and to control multiple first output terminals (21) to output multiple driving voltage signals with a voltage value less than or equal to the supply voltage when the clock signal is a high-level signal. and The driving output circuit (4) has a second input terminal for receiving the clock signal. The multiple voltage input terminals (44) of the driving output circuit (4) are connected one-to-one with the multiple first output terminals (21). The multiple voltage input terminals (44) are used to receive multiple driving voltage signals. The driving output circuit (4) is used to control the second output terminal to output differential signals.

2. The circuit according to claim 1, characterized in that, The boost circuit (2) and the drive output circuit (4) each include two, and the boost circuit (2) and the drive output circuit (4) are connected in a one-to-one correspondence; The first input terminal of each of the boost circuits (2) is used to receive the clock signal, the power supply terminal of each of the boost circuits (2) is used to receive the supply voltage, and each of the boost circuits (2) is used to control the plurality of first output terminals (21) to output at least one of the plurality of driving voltage signals with a voltage value greater than the supply voltage when the clock signal is a low level signal, and to control the plurality of first output terminals (21) to output the plurality of driving voltage signals with a voltage value less than or equal to the supply voltage when the clock signal is a high level signal; The second input terminal of each of the drive output circuits (4) is used to receive the clock signal. The plurality of voltage input terminals (44) of each of the drive output circuits (4) are connected to the plurality of first output terminals (21) of the corresponding boost circuit (2). The plurality of voltage input terminals (44) of each of the drive output circuits (4) are used to receive the plurality of drive voltage signals output by the plurality of first output terminals (21) of the corresponding drive output circuits. Each of the drive output circuits (4) is used to control the second output terminal to output a differential signal.

3. The circuit according to claim 1 or 2, characterized in that, The boost circuit (2) includes a multi-stage charge pump circuit (1), each stage of the charge pump circuit (1) includes a charge pump input terminal, a high-side output terminal and a low-side output terminal, and the clock signal is input to the charge pump input terminal of each stage of the charge pump circuit (1); The power supply terminal of the first-stage charge pump circuit (1) in the multi-stage charge pump circuit (1) is used to receive the power supply voltage. The ground terminal of the first-stage charge pump circuit (1) is grounded. The power supply terminals of the other stage charge pump circuits (1) in the multi-stage charge pump circuit (1) other than the first-stage charge pump circuit (1) are connected to the high-side output terminal of the previous stage charge pump circuit (1) of the other stage charge pump circuit (1). The ground terminal of the other stage charge pump circuit (1) is connected to the low-side output terminal of the previous stage charge pump circuit (1). The high-side output terminal and the low-side output terminal of the last stage charge pump circuit (1) in the multi-stage charge pump circuit (1) jointly output multiple driving voltage signals.

4. The circuit according to claim 3, characterized in that, The first-stage charge pump circuit (1) includes a first dead-zone control circuit (11) and a first voltage adjustment circuit (12), and the other-stage charge pump circuits (1) include a first level shift circuit (13), the first dead-zone control circuit (11) and the first voltage adjustment circuit (12). The first terminal of the first dead-time control circuit (11) of the first-stage charge pump circuit (1) is the input terminal of the charge pump. The input terminal of the first level shift circuit (13) of the other-stage charge pump circuit (1) is the input terminal of the charge pump. The first terminal of the first dead-time control circuit (11) of the other-stage charge pump circuit (1) is connected to the output terminal of the first level shift circuit (13). The first dead-time control circuit (11) is used to output a clock signal with dead time according to the clock signal. The first connection terminal of the first voltage adjustment circuit (12) is connected to the second terminal of the first dead-zone control circuit (11), the second connection terminal of the first voltage adjustment circuit (12) is connected to the third terminal of the first dead-zone control circuit (11), the third connection terminal of the first voltage adjustment circuit (12) is connected to the fourth terminal of the first dead-zone control circuit (11), and the fourth connection terminal of the first voltage adjustment circuit (12) is connected to the fifth terminal of the first dead-zone control circuit (11). The power supply terminal of the first voltage adjustment circuit (12) in the first-stage charge pump circuit (1) is used to receive the power... The power supply voltage is described above. The ground terminal of the first voltage adjustment circuit (12) in the first stage charge pump circuit (1) is grounded. The power supply terminal of the first voltage adjustment circuit (12) in the other stage charge pump circuit (1) is connected to the high-side output terminal of the previous stage charge pump circuit (1). The ground terminal of the first voltage adjustment circuit (12) in the other stage charge pump circuit (1) is connected to the low-side output terminal of the previous stage charge pump circuit (1). The high-side output terminal and the low-side output terminal of the first voltage adjustment circuit (12) in the final stage charge pump circuit (1) jointly output multiple driving voltage signals. The first dead-time control circuit (11) is used to sequentially control the level state at the first connection terminal and the level state at the fourth connection terminal of the first voltage adjustment circuit (12) through the clock signal with dead time; The first voltage adjustment circuit (12) is used to control the voltage difference between the low-side output terminal and the high-side output terminal to be a preset difference value.

5. The circuit according to claim 3, characterized in that, The first-stage charge pump circuit (1) includes a second dead-zone control circuit (15) and a second voltage adjustment circuit (14), and the other-stage charge pump circuits (1) include a first level shift circuit (13), a first dead-zone control circuit (11) and a first voltage adjustment circuit (12). The first terminal of the second dead-time control circuit (15) is the input terminal of the charge pump. The input terminal of the first level shift circuit (13) of the other stage charge pump circuit (1) is the input terminal of the charge pump. The first terminal of the first dead-time control circuit (11) of the other stage charge pump circuit (1) is connected to the output terminal of the first level shift circuit (13). The second dead-time control circuit (15) or the first dead-time control circuit (11) is used to output a clock signal with dead time according to the clock signal. The first connection terminal of the second voltage adjustment circuit (14) is connected to the second terminal of the second dead zone control circuit (15), the second connection terminal of the second voltage adjustment circuit (14) is connected to the third terminal of the second dead zone control circuit (15), the third connection terminal of the second voltage adjustment circuit (14) is connected to the fourth terminal of the second dead zone control circuit (15), the fourth connection terminal of the second voltage adjustment circuit (14) is connected to the fifth terminal of the second dead zone control circuit (15), the power supply terminal of the second voltage adjustment circuit (14) is used to receive the power supply voltage, and the ground terminal of the second voltage adjustment circuit (14) is grounded. The first connection terminal of the first voltage adjustment circuit (12) is connected to the second terminal of the first dead zone control circuit (11), the second connection terminal of the first voltage adjustment circuit (12) is connected to the third terminal of the first dead zone control circuit (11), the third connection terminal of the first voltage adjustment circuit (12) is connected to the fourth terminal of the first dead zone control circuit (11), the fourth connection terminal of the first voltage adjustment circuit (12) is connected to the fifth terminal of the first dead zone control circuit (11), the power supply terminal of the first voltage adjustment circuit (12) is connected to the high-side output terminal of the previous stage charge pump circuit (1), the ground terminal of the first voltage adjustment circuit (12) is connected to the low-side output terminal of the previous stage charge pump circuit (1), and the high-side output terminal and the low-side output terminal of the first voltage adjustment circuit (1) in the final stage charge pump circuit (1) jointly output multiple driving voltage signals. The second dead-time control circuit (15) is used to sequentially control the level state at the first connection terminal and the level state at the fourth connection terminal of the second voltage adjustment circuit (14) by means of the clock signal having a dead time. The first dead-time control circuit (11) is used to sequentially control the level state at the first connection terminal and the level state at the fourth connection terminal of the first voltage adjustment circuit (12) through the clock signal with dead time; The first voltage adjustment circuit (12) or the second voltage adjustment circuit (14) is used to control the voltage difference between the low-side output terminal and the high-side output terminal to be a preset difference value.

6. The circuit according to claim 4 or 5, characterized in that, The first voltage adjustment circuit (12) includes: The first voltage adjustment subunit (121) has a first terminal that is the power supply terminal of the first voltage adjustment circuit (12), a second terminal that is connected to the second terminal of the first dead zone control circuit (11), a third terminal that is connected to the fifth terminal of the first dead zone control circuit (11), and a fourth terminal that is grounded. The first switching subunit (122) has its power supply terminal connected to the first terminal of the first voltage adjustment subunit (121), its first connection terminal connected to the third terminal of the first dead-zone control circuit (11), and its second connection terminal connected to the fourth terminal of the first dead-zone control circuit (11). The first energy storage subunit (123) has its first end connected to the third connection end of the first switch subunit (122) and has the high-side output end therefrom. The second end of the first energy storage subunit (123) is connected to the fifth end of the first voltage adjustment subunit (121) and has the low-side output end therefrom.

7. The circuit according to claim 6, characterized in that, The first voltage adjustment subunit (121) includes: The first PMOS transistor (P1) has its source at the power supply terminal of the first voltage adjustment circuit (12), and its gate is connected to the second terminal of the first dead-time control circuit (11); and The first NMOS transistor (N1) has its gate connected to the fifth terminal of the first dead-time control circuit (11), its drain connected to the drain of the first PMOS transistor (P1) and the second terminal of the first energy storage sub-unit (123), and its source grounded.

8. The circuit according to claim 7, characterized in that, The first switch subunit (122) includes: The first capacitor (C1) has its first terminal connected to the third terminal of the first dead zone control circuit (11). The second capacitor (C2) has its first terminal connected to the fourth terminal of the first dead zone control circuit (11). The second NMOS transistor (N2) has its gate connected to the second terminal of the second capacitor (C2) and its drain connected to the second terminal of the first capacitor (C1). A third NMOS transistor (N3), the gate of which is connected to the second terminal of the first capacitor (C1), and the drain of which is connected to the second terminal of the second capacitor (C2); and The fourth NMOS transistor (N4) has its gate connected to the second terminal of the second capacitor (C2) and its drain connected to the first terminal of the first energy storage sub-unit (123). The source of the second NMOS transistor (N2), the source of the third NMOS transistor (N3), and the source of the fourth NMOS transistor (N4) are connected together to the source of the first PMOS transistor (P1).

9. The circuit according to claim 8, characterized in that, The first energy storage subunit (123) includes: The third capacitor (C3) has its first terminal connected to the drain of the fourth NMOS transistor (N4), and its second terminal connected to the drain of the first NMOS transistor (N1) and the drain of the first PMOS transistor (P1).

10. The circuit according to claim 8 or 9, characterized in that, The first dead-time control circuit (11) includes: A first logic subunit (111) has a first terminal that is the charge pump input terminal, a second terminal that is connected to the gate of the first PMOS transistor (P1), a third terminal that is connected to the first terminal of the first capacitor (C1), and a fourth terminal that is connected to the first terminal of the second capacitor (C2). The first logic subunit (111) is used to control the conduction state of the first PMOS transistor (P1) according to the clock signal. The second logic subunit (112) has a first terminal connected to the first terminal of the first logic subunit (111), a second terminal connected to the second terminal of the first logic subunit (111), and a third terminal connected to the gate of the first NMOS transistor (N1) and the first terminal of the second capacitor (C2). The second logic subunit (112) is used to control the conduction state of the first NMOS transistor (N1) according to the clock signal.

11. The circuit according to claim 10, characterized in that, The first logic subunit (111) includes: A first NOR gate (I1), the first input terminal of which is the charge pump input terminal, the second input terminal of which is connected to the first terminal of the second capacitor (C2) and the third terminal of the second logic subunit (112), and the output terminal of which is connected to the first terminal of the first capacitor (C1); and The first NOT gate (I2) has its input terminal connected to the output terminal of the first NOR gate (I1), and its output terminal connected to the gate of the first PMOS transistor (P1) and the second terminal of the second logic sub-unit (112).

12. The circuit according to claim 11, characterized in that, The second logic subunit (112) includes: The first NAND gate (I3) has its first input connected to the output of the first NOT gate (I2), and its second input connected to the first input of the first NOR gate (I1); and The second NOT gate (I4) has its input terminal connected to the output terminal of the first NAND gate (I3), and its output terminal connected to the second input terminal of the first NOR gate (I1), the first terminal of the second capacitor (C2), and the gate of the first NMOS transistor (N1).

13. The circuit according to any one of claims 5-12, characterized in that, The second voltage adjustment circuit (14) includes: The second voltage adjustment subunit (141) has a first terminal for receiving the power supply voltage, a second terminal for being connected to the second terminal of the second dead zone control circuit (15), a third terminal for being connected to the fifth terminal of the second dead zone control circuit (15), and a fourth terminal for being grounded. The second switching subunit (142) has its first connection terminal connected to the third terminal of the second dead-zone control circuit (15), and its second connection terminal connected to the fourth terminal of the second dead-zone control circuit (15); and The second energy storage subunit (143) has its first end connected to the fifth end of the second voltage regulation subunit (141) and has the high-side output terminal. The second end of the second energy storage subunit (143) is connected to the third connection terminal of the second switch subunit (142) and has the low-side output terminal.

14. The circuit according to claim 13, characterized in that, The second voltage regulation subunit (141) includes: The second PMOS transistor (P2) has its source receiving the supply voltage, its gate connected to the second terminal of the second dead-time control circuit (15), and its drain connected to the first terminal of the second energy storage sub-unit (143); and The fifth NMOS transistor (N5) has its gate connected to the fifth terminal of the second dead-time control circuit (15), its drain connected to the drain of the second PMOS transistor (P2) and the first terminal of the second energy storage sub-unit (143), and its source grounded.

15. The circuit according to claim 14, characterized in that, The second switching subunit (142) includes: The fourth capacitor (C4) has its first terminal connected to the third terminal of the second dead zone control circuit (15). The fifth capacitor (C5) has its first terminal connected to the fourth terminal of the second dead zone control circuit (15). The third PMOS transistor has its gate connected to the second terminal of the fourth capacitor (C4) and its drain connected to the second terminal of the fifth capacitor (C5). A fourth PMOS transistor (P4), the gate of which is connected to the second terminal of the fifth capacitor (C5), and the drain of which is connected to the second terminal of the fourth capacitor (C4); and The fifth PMOS transistor (P5) has its gate connected to the second terminal of the fourth capacitor (C4), and its drain connected to the second terminal of the second energy storage sub-unit (143). The sources of the third PMOS transistor, the fourth PMOS transistor (P4), and the fifth PMOS transistor (P5) are all grounded.

16. The circuit according to claim 15, characterized in that, The second energy storage subunit (143) includes: The sixth capacitor (C6) has its first terminal connected to the drain of the second PMOS transistor (P2) and the drain of the fifth NMOS transistor (N5), and its second terminal connected to the drain of the fifth PMOS transistor (P5).

17. The circuit according to claim 15 or 16, characterized in that, The second dead-time control circuit (15) includes: The third logic subunit (151) has its first terminal as the charge pump input terminal, and its second terminal connected to the gate of the second PMOS transistor (P2) and the first terminal of the fourth capacitor (C4). The third logic subunit (151) is used to control the conduction state of the second PMOS transistor (P2) according to the clock signal. The fourth logic subunit (152) has its first terminal connected to the first terminal of the third logic subunit (151), its second terminal connected to the second terminal of the third logic subunit (151), its third terminal connected to the first terminal of the fifth capacitor (C5), and its fourth terminal connected to the third terminal of the third logic subunit (151) and the gate of the fifth NMOS transistor (N5). The fourth logic subunit (152) is used to control the conduction state of the fifth NMOS transistor (N5) according to the clock signal.

18. The circuit according to claim 17, characterized in that, The third logic subunit (151) includes: The second NOR gate (I5), the first input of which is the charge pump input, and the second input of which is connected to the fourth terminal of the fourth logic subunit (152); and The third NOT gate (I6) has its input terminal connected to the output terminal of the second NOR gate (I5), and its output terminal connected to the gate of the second PMOS transistor (P2), the first terminal of the fourth capacitor (C4), and the second terminal of the fourth logic sub-unit (152).

19. The charge pump circuit (1) according to claim 18, characterized in that, The fourth logic subunit (152) includes: The second NAND gate (I7) has its first input connected to the output of the third NOT gate (I6), its second input connected to the first input of the second NOR gate (I5), and its output connected to the first terminal of the fifth capacitor (C5). The fourth NOT gate (I8) has its input terminal connected to the output terminal of the second NAND gate (I7), and its output terminal connected to the second input terminal of the second NOR gate (I5) and the gate of the fifth NMOS transistor (N5).

20. The circuit according to any one of claims 3-19, characterized in that, The drive output circuit (4) includes: The second level shift circuit (41) has an input terminal for receiving the clock signal and for shifting the driving voltage signal to the input voltage of the driving output circuit (4). A third dead-time control circuit (42), the input of which is connected to the output of the second level shift circuit (41), is used to output a clock signal with a dead time according to the clock signal; and The signal processing circuit (43) has its power supply terminal connected to the high-side output terminal of the final stage charge pump circuit (1) in the corresponding boost circuit (2), its ground terminal connected to the low-side output terminal of the final stage charge pump circuit (1) in the corresponding boost circuit (2), and its control terminal connected to the third dead-time control circuit (42). The signal processing circuit (43) is used to output a differential signal based on a clock signal with a dead time and multiple driving voltage signals.

21. The circuit according to claim 20, characterized in that, The signal processing circuit (43) includes: The sixth PMOS transistor (P6) has its gate connected to the first output terminal (21) of the third dead-time control circuit (42), and its source connected to the high-side output terminal of the final stage charge pump circuit (1) in the corresponding boost circuit (2); and The sixth NMOS transistor (N6) has its gate connected to the second output terminal of the third dead-time control circuit (42), its source connected to the low-side output terminal of the final stage charge pump circuit (1) in the corresponding boost circuit (2), and its drain connected to the drain of the sixth PMOS transistor (P6) and used to output the differential signal.

22. The circuit according to claim 21, characterized in that, The third dead zone control circuit (42) includes: The fifth logic subunit (421) has its first terminal connected to the output terminal of the second level shift circuit (41), and its second terminal connected to the gate of the sixth PMOS transistor (P6). The fifth logic subunit (421) is used to control the conduction state of the sixth PMOS transistor (P6) according to the clock signal. The sixth logic subunit (422) has its first terminal connected to the second terminal of the fifth logic subunit (421), its second terminal connected to the output terminal of the second level shift circuit (41), and its third terminal connected to the third terminal of the fifth logic subunit (421) and the gate of the sixth NMOS transistor (N6). The sixth logic subunit (422) is used to control the conduction state of the sixth NMOS transistor (N6) according to the clock signal.

23. The circuit according to claim 22, characterized in that, The fifth logic subunit (421) includes: The third NOR gate (I9), the first input of which is connected to the output of the second level shift circuit (41), and the second input of which is connected to the third terminal of the sixth logic subunit (422); and The fifth NOT gate (I10) is connected to the output of the third NOR gate (I9), and the output of the fifth NOT gate (I10) is connected to the gate of the sixth PMOS transistor (P6) and the first end of the sixth logic sub-unit (422).

24. The circuit according to claim 23, characterized in that, The sixth logic subunit (422) includes: The third NAND gate (I11), the first input of which is connected to the output of the fifth NOT gate (I10), and the second input of which is connected to the output of the second level shift circuit (41); and The sixth NOT gate (I12) has its input terminal connected to the output terminal of the third NAND gate (I11), and its output terminal connected to the second input terminal of the third NOR gate (I9) and the gate of the sixth NMOS transistor (N6).

25. A drive system (900), characterized in that, Includes the differential signal output circuit (800) according to any one of claims 1-24.

26. A vehicle (1000), characterized in that, Includes the drive system (900) as described in claim 25.

Images