Embedded multi-layer half-bridge circuit and multi-phase bridge circuit consisting thereof

Abstract

An embedded half-bridge circuit is equipped with a multilayer printed circuit board (PCB) which comprises the following stacked layers: a contact conductor layer (L1) having at least three contact surfaces (KP, KN, KW), a first and a second connecting conductor layer (L2), and a semiconductor layer (HI) in which a first and a second group of semiconductor elements (HS, LS) are provided. The semiconductor layer (HI) is between the first connecting conductor layer (L2) and the second connecting conductor layer (L3). A first portion (A1) of the second connecting conductor layer (L3) is connected to lower faces of the first group of semiconductor elements (HS) via vias (D1, D2), and a second portion (A2) of the second connecting conductor layer (L3) is connected to lower faces of the second group of semiconductor elements (LS) via vias (D3, D4). A first portion (A3) of the first connecting conductor layer (L2) is connected to upper faces of the first group of semiconductor elements (HS) via vias (D11, D12), and a second portion (A4) of the first connecting conductor layer (L2) is connected to upper faces of the second group of semiconductor elements (LS) via vias (D13, D14). The first portion (A3) of the first connecting conductor layer (L2) is electrically connected to the second portion (A2) of the second connecting conductor layer (L3). One of the contact surfaces (KN) is connected to the second portion (A4) of the first connecting conductor layer (L2), and at least one second contact surface of the contact surfaces (KP) is connected to the second connecting conductor layer (L3). A multi-phase bridge circuit may include a plurality of such circuits.

Description

[0001] Description

[0002] Multilayer embedded half-bridge circuit and multiphase bridge circuit derived from this

[0003] Vehicles with electric drive systems feature power electronics in the form of a traction inverter, which, at power outputs significantly exceeding 100 kW and voltages of, for example, 400 or 800 V, converts the DC voltage from the traction battery into a multi-phase AC voltage. This AC voltage is supplied to an electric motor, which in turn generates torque.

[0004] To implement such a traction inverter, power semiconductors like power transistors are used. These transistors have high current-carrying capacity interconnections and connections, and they generate significant heat that must be dissipated. Finally, especially with high switching slew rates, these transistors generate interference that needs to be reduced, preferably through efficient routing (particularly of the DC supply voltage).

[0005] Therefore, one challenge is to achieve a high current-carrying capacity in a half-bridge with clever cable routing, which is particularly suitable for traction inverters.

[0006] This problem is solved by the subject matter of claim one. Further properties, features, embodiments and advantages become apparent with regard to the dependent claims, the description and the figures.

[0007] An embedded half-bridge circuit with a multilayer, specifically single-piece, printed circuit board is proposed. It consists of a first group of semiconductor elements and a second group of semiconductor elements. The first group forms the high-side transistor and the second group forms the low-side transistor. The first and second groups are connected in series (with respect to the power path), with the junction forming an AC terminal or phase connection. The outer ends (the ends not connected to each other or to the junction) can be connected to two DC supply potentials. The first and second groups of home elements are integrated into the printed circuit board and are thus "embedded," a technical term for the placement of components (here: semiconductor elements) within or between layers of a printed circuit board.

[0008] The printed circuit board has at least three conductor layers: a contact conductor layer, a first interconnect conductor layer, and a second interconnect conductor layer. A semiconductor layer is provided, in which the semiconductor elements are located. The semiconductor layer is typically made of electrically insulating material, with the semiconductor elements embedded within this insulating material. Furthermore, the semiconductor layer can include a conductive layer that has a recess in which the semiconductor elements are arranged, preferably also embedded in insulating material within the recess. The insulating material is, in particular, a resin material, for example, prepreg. The conductor layers are preferably layers of copper or an alloy thereof. The insulating material is also provided in layer form between the conductor layers, resulting in a laminated structure.

[0009] The conductor layers are structured, meaning they have physically separated sections that, due to this physical separation, allow for different voltage potentials. This enables the formation of conductor tracks in a known manner. Insulating layers are provided between the conductor layers, through which vias can extend. These vias connect different conductor layers and, in particular, can individually connect different sections of one conductor layer to different sections of another conductor layer.

[0010] The proposed half-bridge circuit has a contact conductor layer. This can be the uppermost layer of the circuit and thus form an externally accessible surface (optionally covered by a protective lacquer). Alternatively, this layer is covered by an insulating layer, on which a conductive connection layer follows. This connection layer is electrically connected to the contact conductor layer through the insulating layer and also covers the contact conductor layer. The contact conductor layer is structured and has at least a first, a second, and a third contact surface. The first contact surface is preferably implemented multiple times. This also applies to the second and third contact surfaces.In the case of multiple first contact surfaces, these are interconnected, preferably via conductive traces provided by the conductor layer, or by placing the contact surfaces in the same (continuously conductive) section of the conductor layer. This can also be implemented for the second and third contact surfaces if multiple copies of these are provided. The contact conductor layer has grooves extending through its entire thickness, separating the one or more first contact surfaces from the one or more second contact surfaces and the one or more third contact surfaces, as well as grooves separating the one or more second contact surfaces from the one or more third contact surfaces.

[0011] The half-bridge circuit further comprises a first interconnect layer, a semiconductor layer, and a second interconnect layer. The semiconductor layer is positioned between the two interconnect layers. Thus, the first interconnect layer is above the semiconductor layer, and the second interconnect layer is below the semiconductor layer. The terms "above" and "below" do not refer to a horizon or a gravitational field, but serve for the usual visual orientation, which may refer to a diagram. The first interconnect layer is provided via an insulating layer on the semiconductor layer, or the first interconnect layer is provided directly on the semiconductor layer, provided the latter has an insulating layer above the semiconductor elements.The second interconnect layer is provided via an insulating layer on the semiconductor layer, or the first interconnect layer is provided directly on the semiconductor layer, provided that the latter has an insulating layer beneath the semiconductor elements. In other words, the semiconductor elements of the semiconductor layer are (insulating) sandwiched between the two interconnect layers. The semiconductor elements are connected to the interconnect layers on both sides (i.e., top and bottom), in particular via vias that extend from the interconnect layers to the semiconductor element or its surface, and that pass through the insulating layers between the semiconductor element and the interconnect layers.

[0012] The layers mentioned here are arranged one above the other. The semiconductor layer is placed between the interconnection layers (first and second interconnection layers). Each interconnection layer has at least two physically separate sections, which can therefore carry different potentials or are not connected to each other by the respective interconnection layer.

[0013] A first section of the second interconnect layer (below the semiconductor layer) is electrically connected to the undersides (i.e., surfaces of the semiconductor elements facing the second interconnect layer) of the first group of semiconductor elements. This connection is provided by vias extending from the underside of the first group of semiconductor elements to the first section of the second interconnect layer. Because all the vias lead to the first section, all the undersides of the first group of semiconductor elements are electrically connected. This results in part of a parallel circuit of these semiconductor elements (first group).

[0014] The second interconnect layer has a second section. This section lies adjacent to the first. "Adjacent" means offset in a direction that aligns with the orientation of the circuit board. This second section of the interconnect layer is also connected to the undersides of semiconductor devices, specifically to the undersides of the second group of semiconductor devices. The two groups do not overlap. Thus, the undersides of the two groups of semiconductor devices are connected to (electrically) different sections of the second interconnect layer. The connection between the underside and the section is the same as for the first section, i.e., it is provided by vias that lead from the second section to the undersides of the second group of semiconductors.Since the undersides of the second group of semiconductor elements are all connected to the same section, namely the second section, they are all electrically connected. This results in part of a parallel circuit of these semiconductor elements (second group).

[0015] The undersides of the semiconductors are electrically conductive and lead to an electrode of the semiconductor. Preferably, the semiconductor elements incorporate transistors, such that, for example, the underside represents a drain terminal (or a collector terminal) of the first or second group. These electron connections are carried away via the different sections of the second interconnect layer. The first group of semiconductor elements can be considered a common first switching element. The second group of semiconductor elements can be considered a common second switching element. The first section serves to electrically connect a first terminal of the first switching element, and the second section serves to electrically connect a first terminal of the second switching element.

[0016] The same functionality is provided above the semiconductor layer by the first interconnect layer. This layer also has a first and a second section. The first section of the first interconnect layer is connected to the top surfaces of the first group of semiconductor elements. The second section of the first interconnect layer is connected to the top surfaces of the second group of semi-elements. These connections are provided by vias, resulting, as with the second interconnect layer, in a connection between the top surfaces of the first group of semi-elements and the first section. Additionally, the top surfaces of the second group of semiconductor elements are connected to the second section of the first interconnect layer. These connections each form part of a parallel connection.Since the top and bottom surfaces of the first group of semiconductor elements are connected to the first sections of the two aforementioned interconnect layers, the elements are connected in parallel by virtue of their connection to the same first sections of both interconnect layers. The same applies to the second group of semiconductor elements and their second sections.

[0017] The first section of the first interconnect layer (connected to the top surfaces of the first group of semiconductor elements) is connected to the second section of the second interconnect layer (connected to the bottom surfaces of the second group of semiconductor elements). This creates a series connection of the first group of semiconductor elements with the second group. The result is a series connection of the first switching element (represented by the parallel connection of the first group of semiconductor elements) and the second switching element (represented by the parallel connection of the second group of semiconductor elements). This series connection of two switching elements is also called a half-bridge. The connection itself corresponds to the junction of the half-bridge, the potential of which is dissipated via a third contact surface.The ends of the two switching elements, which are not connected to each other, are connected to different contact surfaces, namely to (at least) a first contact surface and (at least) a second contact surface. The first and second contact surfaces serve to apply a supply voltage, in particular a DC supply voltage. The connection between the first section of the first interconnect layer and the second section of the second interconnect layer extends through the semiconductor layer, preferably without making contact with the semiconductors. The connection can be provided by one or more (parallel) vias. The connection can be considered the connection point between the two switches or transistors of the half-bridge. The connection extends in a section of the printed circuit board between the first group of semiconductor elements and the second group of semiconductor elements.

[0018] The first contact surface (or at least one) is connected to the second section of the first interconnect layer. This, in turn, is connected to the top surface of the second group of semiconductor elements. The top surface of the semiconductor elements can represent a source (or emitter) terminal. The first contact surface thus serves to connect the source or emitter of the second group of semiconductor elements. The second group of semiconductor elements, or the second switching element, can be considered the low-side switch of the half-bridge; the first group therefore forms the high-side switch of this half-bridge.Since the first contact surface is formed by the contact conductor layer, to which the first interconnect conductor layer is connected (in an insulated manner), the connection between the first contact surface and the relevant section of the first interconnect conductor layer can be provided by a via that extends only through the insulating layer between the contact conductor layer and the first interconnect conductor layer.

[0019] The (at least one) second contact surface is connected to the second interconnect layer, specifically to its first section. Since this section is connected to the underside of the first group of semiconductor elements, this second contact surface (of the second interconnect layer) can represent the drain (or collector) connection. The second contact surface thus serves to connect the drain or collector of the first group of semiconductor elements. The second contact surface therefore forms the positive supply voltage connection, while the first contact surface forms the negative supply voltage connection. This assumes that the semiconductor elements are transistors, although a similar arrangement can be made for diodes. It is important to note that the opposite sides of the semiconductor element (top and bottom) represent different electrodes or connections of the semiconductor element's power path.Then, as shown, a half-bridge can be easily formed by dividing the first and second interconnection conductor layers, with the semiconductor layer between them, into a first and second section. The internal connection of this half-bridge is provided by a connection between corresponding sections of different interconnection conductor layers. The corresponding contact is achieved by the three contact pads, which are connected to the aforementioned interconnection (phase), as well as to the second section of the first interconnection conductor layer and the first section of the second interconnection conductor layer, respectively. The internal connection can thus be arranged between the different groups of semiconductor elements, with the third contact pad being located on one side, while the first contact pads are located in the middle and on the opposite side of the three contact pads.This enables a low-induction supply of the supply potentials to the first and a second contact surface, especially since the third contact surface (phase) is located at the edge compared to the other two potentials, and not between the contact surfaces of the supply potentials.

[0020] The multilayer printed circuit board described above is formed in a single piece, as described above and below, specifically through a lamination and coating process in which the aforementioned layers are laminated or coated on top of each other, including an embedding process in which the semiconductor elements mentioned are embedded between the corresponding layers of the printed circuit board. The lamination and coating process here refers specifically to the process by which conductive and insulating layers are bonded together to form a single-piece multilayer printed circuit board.

[0021] Therefore, the multilayer printed circuit board described above is not a sandwich composite of several circuit boards initially manufactured separately and subsequently stacked on top of each other. Consequently, the multilayer printed circuit board with embedded semiconductor elements described above is not a sandwich structure of several circuit boards and semiconductor elements initially manufactured separately, stacked on top of each other and bonded together by soldering, sintering, welding, or gluing. The electrical contacts between the different electrical layers, i.e., the various conductor layers and the semiconductor layer, are established by vias that pass through (to be described below) electrical insulation layers formed between the electrical layers, which electrically isolate these layers from one another.

[0022] Embodiments provide that the (at least one) third contact surface is connected to the second interconnection conductor layer via vias. These vias extend from the contact layer (i.e., from the third contact surface of this layer) to the second section of the second interconnection conductor layer. The second section of the second interconnection conductor layer is thus connected (via vias) not only to the underside of the second group of hybrid elements but also to the third contact surface. The second section of the second interconnection conductor layer is accordingly wide. In particular, the vias extend from the second section of the second interconnection conductor layer through an additional section of the first interconnection conductor layer, which is electrically isolated from the other sections of the first interconnection conductor layer. This isolation is provided by the first vias.Second vias connect this additional section to the third contact surface. This results in a series connection of the first and second vias. In specific embodiments, there is only one via and / or only one second via, so that the first vias can be provided once or multiple times, and the second vias can also be provided once or multiple times.

[0023] An alternative embodiment provides that the (at least one) third contact surface is connected to the first section of the first interconnection conductor layer via (at least one) via. This via extends from the third contact surface to the first section of the first interconnection conductor layer, thus passing only through the insulating layer between the contact conductor layer and the first interconnection conductor layer. This is preferably implemented when the second or first contact surface does not extend over the entire first section of the first interconnection conductor layer, thus providing sufficient space for the third contact surface. Furthermore, the contact surfaces can each be designed as a free, conductive area configured for surface contacts of the half-bridge circuit.In this context, "free" refers to a surface whose conductive area extends into the free space outside the half-bridge circuit and can therefore be directly contacted from there. A contact surface with a protective coating that can be pierced for contact can also be considered a free, conductive surface (since it was contacted from the outside by removing the protective coating). An alternative embodiment provides a bonding layer that is arranged on the contact surfaces or on the contact conductor layer by means of an insulating layer. The bonding layer can provide external bonding surfaces. These are individually connected to the contact surfaces. The connection can be provided by vias that lead from the bonding layer to the contact conductor layer.The various contact surfaces are individually connected to the outer connection surfaces, which are provided by sections of the bonding layer. These connection surfaces are formed by the bonding layer, which can also be described as an additional conductor layer. The contact layer itself is physically protected by the bonding layer and the underlying insulating layer. The application surfaces can be provided by sections of the bonding layer or by metal inserts, such as copper inserts, which form busbars.

[0024] In particular, the printed circuit board can have an interconnect layer as mentioned above, in addition to the contact layer and the two interconnect layers. This would result in a five-layer structure, especially if the semiconductor layer is designed as a separate layer (conductor layer). An insulating layer below the second interconnect layer can be used to provide a (conductive) heat dissipation layer, resulting in a six-layer structure. The heat dissipation layer can be completely isolated from the second interconnect layer, or it can itself have sections that are connected to components (sections, semiconductor elements) of the rest of the circuit.

[0025] According to another aspect, the second contact surface (for a positive supply potential) is arranged above the first section of the first interconnect layer or above the second section of the first interconnect layer. In this case, the second contact surface can be located above the (second) section of the first interconnect layer, which is connected to the top surfaces of the second group of semiconductor elements via vias. If the second contact surface also extends laterally to the second section of the first interconnect layer, for example as a lateral projection, then the at least one second contact surface can also be located above the first section of the first interconnect layer, particularly in close proximity to the first contact surface. This reduces the connection inductance.

[0026] Furthermore, the (at least one) first contact pad (for a negative supply potential) can be arranged between the first and second sections of the first interconnection conductor layer, i.e., over a point between these sections. Here, the connection between the contact pad and the first section of the second interconnection conductor layer penetrates the first section. Thus, an opening can be provided in the first interconnection conductor layer through which a connection extends between the first contact pad and the second interconnection conductor layer (i.e., its first section). This enables electrical insulation between the second section of the first interconnection conductor layer and the connection leading from the second interconnection conductor layer to the first contact pad. Alternatively, the first contact pad can be provided next to the semiconductor elements.in an edge region of the printed circuit board. The third contact surface can be provided in an opposite edge region. In particular, the first contact surface can be provided above a location adjacent to the first and second sections of the first interconnect conductor layer. In particular, a third section of the first interconnect conductor layer can be provided adjacent to the first and second sections of this conductor layer, for example at an edge region, wherein in particular the first contact surface is arranged above the third section and is connected to it via vias.

[0027] One embodiment provides that the at least one third contact surface is located above the first section of the first interconnect conductor layer. Alternatively, the at least one third contact surface can be arranged next to this section, particularly in an edge region above a point adjacent to the sections of the first interconnect conductor layer. The at least one third contact surface is specifically designed for connecting a phase. The third contact surface can also be considered an AC connection, particularly if the half-bridge is used in an inverter. The circuit board can have a cooling layer. This is preferably made of a metallic material such as copper or a copper alloy, or alternatively of aluminum or an aluminum alloy. The cooling layer is located beneath the second interconnect conductor layer. An insulating layer is provided between these two layers.The cooling layer may be completely electrically insulated from the second interconnect conductor layer by an insulating layer. However, the aforementioned conductor layer, or the cooling layer itself, may be divided into sections that are connected to sections of the second interconnect conductor layer via vias. The cooling layer may generally be electrically connected to the second interconnect conductor layer, or sections thereof, particularly by means of vias. These vias extend through the insulating layer between the cooling layer and the second interconnect conductor layer. Vias may be provided that extend through the insulating layer. These connect the cooling layer to the second interconnect conductor layer electrically, either completely or section by section.

[0028] The semiconductor elements can be bare or packaged power transistors, for example in the form of chips (bare dies). Preferably, the semiconductor elements each comprise a metal body and a bare power transistor, namely a semiconductor chip. The semiconductor elements can be designed as metal bodies that support one or more power transistors. In this case, the power transistors are in the form of bare dies, i.e., semiconductor chips. The semiconductor chips have two electrodes arranged on opposite sides, namely the top and bottom, of the semiconductor element. The semiconductor chips each have a bottom surface by which the semiconductor chip is attached to the metal body, particularly in an electrically conductive manner. The semiconductor chips can be soldered or sintered onto the metal body. In particular, the semiconductor chip can be embedded in the surface of the metal body.For this purpose, a metal body has a recess (blind hole) in which the semiconductor chip is arranged, wherein the underside of the semiconductor chip is connected to the bottom of the recess in an electrically conductive manner, in particular by sintering or soldering.

[0029] The half-bridge circuit can include an intermediate circuit capacitor.

[0030] This is preferably arranged above the contact pads, in particular above the first and second contact pads. The intermediate circuit capacitor is preferably arranged above those contact pads that are connected to the first section of the second interconnect conductor layer and to the top surfaces of the second group of semiconductor elements. The intermediate circuit capacitor can have two contacts on its underside. A first of these contacts can be connected to the first contact pad, and a second of these contacts can be connected to the second contact pad. This allows the intermediate circuit capacitor to be connected directly and with low inductance (to the supply potentials that are routed in the printed circuit board).

[0031] Signal lines or sections thereof can be integrated into the printed circuit board. In particular, the first interconnect layer or the contact layer can incorporate such signal lines or sections thereof through structuring. The signal lines or sections thereof lead to the semiconductor elements, for example, to a control terminal, but can also lead to a temperature sensor. Temperature sensors can be located directly below or directly above the semiconductor elements. The signal lines can be integrated into the semiconductor layer. They can also be configured as drain or source taps, or as collector or emitter taps, for example, to carry back corresponding signals.

[0032] The circuit board may also have an area where a control circuit is provided, which is connected to the elements in a controlling manner.

[0033] A multiphase bridge circuit, for example a B6C bridge, or a fully controllable AC bridge with more or fewer than three phases, can incorporate several of the half-bridge circuits described here. The contact pads of the individual half-bridge circuits connected to the first section of the second interconnect conductor layer (oriented towards the first contact pad, i.e., oriented for connection to a positive supply potential) are preferably electrically interconnected. This latter connection can be provided by a connection within a module frame that supports the half-bridge circuits. Likewise, the contact pads of the individual half-bridge circuits connected to the top surfaces of the second group of semiconductor elements (second contact pads, for connection to a negative supply potential) can also be electrically interconnected.This can also be achieved by a connection within a module frame that supports the half-bridge circuits. The third contact surfaces, or the relevant potentials of the multiple half-bridge circuits, are preferably contacted individually, particularly by different phases of a component that can be connected to the bridge circuit.

[0034] Another possibility is to place the half-bridge circuits of the multiphase bridge circuit in different sections of the same printed circuit board (PCB). In this case, the half-bridge circuits are located next to each other. Furthermore, the half-bridge circuits can be implemented on physically independent, individual PCB sections. These two PCB sections then form the respective PCB of the half-bridge circuit. The half-board sections, or the individual PCBs, can be supported together by a module frame (as shown).

[0035] The layers can be arranged in the following sequence (with an insulating layer in between): contact conductor layer, first interconnection conductor layer, second interconnection conductor layer, then, if applicable, a cooling layer. If present, a bonding layer can precede the contact conductor layer in this sequence. Further cover or protective layers can be provided, in particular above the contact conductor layer, above the bonding layer, below the cooling layer, or below the second interconnection conductor layer or the subsequent insulating layer. An insulating layer can precede the contact conductor layer. An insulating layer can follow the second contact conductor layer.

[0036] The first interconnect layer can be placed as an insulator between the contact layer and the second interconnect layer. A semiconductor layer can be located between the first and second interconnect layers.

[0037] Furthermore, “electrically isolated” means in particular that there is no direct electrical connection in the layer in question; however, connections via semiconductor elements may be provided.

[0038] "Insulating" means electrically insulating, and may include thermal conductivity. An insulating layer beneath the second interconnect conductor layer may have a higher thermal conductivity coefficient than the insulating material between the other layers, particularly in the form of a ceramic layer. "Interposed insulatingly" means that the layers in question are connected to each other via insulating layers. The layers extend along a principal direction (length, width, not thickness) of the printed circuit board. This also applies to the semiconductor elements.

[0039] The term "section" refers to a section along the main direction (width, length) of the printed circuit board (PCB) and specifically encompasses the entire thickness of the PCB. The term "connected" refers specifically to a direct connection between the aforementioned components, with the connection extending from one connection to the other. The vias run perpendicular to the plane of the PCB. The contact surfaces are, in particular, circular, oval, elongated, or polygonal, such as square or rectangular.

[0040] The semiconductor components include power transistors designed for continuous currents exceeding 10 A or more. Specifically, the power transistors have a reverse voltage rating of at least 200 volts, and particularly more than 400 V, for example, more than 600 V. The power transistors are MOSFETs or IGBTs. Specifically, the conduction transistors can be SiC MOSFETs or GaN MOSFETs.

[0041] Figures 1 and 2 serve to further illustrate exemplary embodiments of the half-bridge circuit described here. Figures 1 and 2 are cross-sectional views. Figure 3 schematically shows an embodiment of a multiphase bridge circuit with the circuits described here.

[0042] Figures 1 and 2 each show a printed circuit board (PCB) with a contact conductor layer L1, which is arranged insulatingly above a first interconnection conductor layer L2. The first interconnection conductor layer L2 is in turn provided insulatingly above a semiconductor layer H1, beneath which (electrically insulated) a second interconnection conductor layer L3 is located.

[0043] Within the semiconductor layer Hl, a first group HS and a second group LS of semiconductor elements extend. Each semiconductor element encloses a metal body in which a semiconductor chip T (configured as a transistor) is embedded. The underside of the chip T is connected to the metal body M.

[0044] The contact conductor layer L1 is divided into several sections, which implement the first, second, and third contact surfaces KP, KN, and KW. Each contact surface can be represented multiple times, for example, by repeating itself in a direction perpendicular to the plane of the drawing. This applies to the first, second, and third contact surfaces KP, KN, and KW. A corresponding connecting element VP is located on the first contact surface KP. This also applies to the connecting element VN on the second contact surface KN and to the connecting element PH above the third contact surface KW. The connecting elements can also be conductor tracks or contact surfaces located on an insulating layer ISO. This insulating layer ISO can carry another conductor layer L, also referred to as the connection layer. This additional conductor layer L can form contact surfaces KN (line) or corresponding connecting elements.The connecting bodies can extend directly through the insulating layer ISO to the relevant contact surfaces, or the contact surfaces, such as the contact surface KN', can be provided as a section of the further conductor layer L, which is connected to the relevant surface of the contact conductor layer L1 via a via KNV.

[0045] On this conductor layer L, or directly on the contact conductor layer L1, an intermediate contact ZK can be provided. This is located above the first contact surface VP and below the second contact surface VN. These two contact surfaces serve to supply the supply potential. The capacitor can therefore have contacts on its underside that are directly connected to these surfaces, or that are connected to connections leading to them.

[0046] It can be seen that the first interconnect layer L2 is divided into two sections: section A3 and section A4. These are electrically isolated from each other by a gap. The second interconnect layer also has two sections, isolated by a gap: section A1 and section A2. Section A3 of the first interconnect layer L2 is connected on its upper side to the first group of semiconductor elements HS, specifically to their transistors T (or rather, their top-side contacts). Section A1 of the second interconnect layer L3 is connected on its lower side to the first group of semiconductor elements HS, specifically to their transistors T (or rather, the underside of the metal body M in which the transistor T is mounted). Thus, sections A1 and A3 contact the two ends of the first group of semiconductor elements HS. HS stands for "highside".

[0047] Accordingly, the second section A4 of the first interconnection conductor layer L1 is connected on its upper side to the surface contacts of the second group of semiconductor elements LS. On their lower side, these semiconductor elements LS are connected to the second section A2 of the second interconnection conductor layer L3. LS stands for "lowside".

[0048] The connection V connects the first section A3 of the first interconnect layer L2 with the second section of the second interconnect layer L3. This connection V, as well as the connections between the aforementioned sections and the semiconductor elements, are vias between the respective layers.

[0049] Semiconductor elements. The diagram shows examples of vias D1 to D4, where D1 and D2 connect the first section A1 of the second interconnect layer L3 to the underside of the first group of semiconductor elements HS, and D3 and D4 connect the second section A2 of the second interconnect layer L3 to the underside of the first group of semiconductor elements HS. As with other vias, it can be seen that these can be provided by several parallel via elements.

[0050] Connection V creates a connection point between the two elements of the half-bridge: the first switching element formed by the first group HS of half-elements and the second switching element formed by the second group LS of switching elements. The semiconductor elements of the first group HS are connected in parallel. This also applies to the second group LS. The connection point in question is connected to the third contact surface KW.

[0051] In Figure 1, this is achieved by connecting the second section of the second interconnection conductor layer L3 to the third contact pad KW via two consecutive vias D0', DU'. The vias D0', DU' are connected to a third section of the first interconnection conductor layer L1. This results in the third contact pad KW being positioned at one end, while the contact pads KP, KN for the supply voltage (DC voltage) are located at the opposite end.

[0052] In Figure 2, the third contact surface KW is formed by a section of the contact conductor layer L1, which is directly connected to the first section A3 of the first interconnect conductor layer L2 via several adjacent vias DP. Thus, in Figure 2, the contact surface KW is located above the semiconductor elements of the first group HS and directly above section A3.

[0053] The first contact pad KP is shown in Figure 1 at the left edge of the printed circuit board (PCB) as a section of the contact layer L1. The first contact pad KP is connected to section A1 of the second interconnect layer L3 via successive first and second vias DO and DU. For this purpose, the first interconnect layer L2 provides an additional section that is connected upwards to the contact pad KP (as a section of layer L1) via the vias DO. This additional section is further connected downwards to section A1 of layer L3 via the vias DU. This results in the first contact pad KP being positioned next to the location of the semiconductor elements, i.e., at the edge, with the bottom contact of the semiconductor elements occurring via the vias D1 and D2, section A2, and the vias DU and DO.

[0054] In Figure 2, the first contact surface KP is located in a region between the groups of semiconductor elements HS, LS. Similarly, the first contact surface KP is connected to section A1 of layer L3 via an additional section of layer L2 and two successive vias DO, DU. The additional section of layer L2 connected to the first contact surface KP is located in an opening 0 provided in section A3. However, section A3 is not intersected by opening 0; instead, conductor sections or conductor areas are formed in regions of layer L2 that lie outside opening 0. Thus, section A3 can be considered a continuous surface extending to opening 0. Opening 0 is located within the perimeter of section A3. In Figure 1, the second contact surface KN is provided as a section in the contact conductor layer.In an area above the second group of semiconductor elements LS, there is a second section A4 of layer L2. This section is connected to the section representing surface KN via vias DN. The vias DN connect the section of L1 representing surface KN to section A4 (second section of the first interconnect layer L2). The contact surface KN could also be located at a different location than shown, for example, above the elements LS, although there would be a greater distance to the first contact surface KP. Thus, extending from the location of the semiconductor elements LS, there is a projection towards the first contact surface KP, with the second contact surface KN, or a corresponding connecting element VN, being provided at a point on the projection opposite the first contact surface KP.

[0055] In Figure 2, contact surface KN is provided by a section of the contact conductor layer L1. This section lies above section A4, i.e., the second section of the first connection conductor layer L2. These sections in contact conductor layer L1 and in the first connection conductor layer L2 (= section A4) are stacked on top of each other and connected by vias between them. A similar connection is provided in Figure 2 for contact surface KW, which is formed by a section of contact conductor layer L1, which in turn is connected via vias DP to the underlying section A3 of the first connection conductor layer L2.

[0056] Figure 2 illustrates that a cooling layer KS can be connected. This layer is formed, for example, below layer L3, particularly on an insulating layer ISO' that connects the cooling layer KS to layer L3. The insulating layer ISO' can also be attached to the underside of the second connecting conductor layer L3 without a subsequent cooling layer KS. The cooling layer KS is shown only for a small section. The KS layer can be made of copper or aluminum. The cooling layer KS can be thicker than layers L1 to L3 (individually).

[0057] In contrast to Figure 1, the section of layer L1, which forms the third contact surface KW, is located in Figure 2 above a section A3 of the first interconnect conductor layer L2, which is connected to the semiconductor elements (reference sign HS) by means of vias D11, D12.

[0058] Further vias in Figure 2 are shown with reference numerals D13, D14, which connect section A4 of layer L2 to the surface contacts of the hybrid elements LS.

[0059] In contrast to Figure 1, the second contact surface KN in Figure 2 is located above section A4 of layer L2 and thus above those of the semiconductor elements LS to which this section A4 is also connected. In Figure 2, this results in a connection of the second contact surface KN that runs essentially in the thickness direction. In Figure 1, however, a projection extends from the region of the conductor layer L1, which lies above section A4, towards the first contact surface KP, so that the second contact surface KN does not lie above section A4 of layer L2, which is connected to the semiconductor elements LS via vias. The connection of the second contact surface in Figure 1 therefore has a significant horizontal component, i.e., a path that runs along the orientation of the printed circuit board (PCB).Although this results in a longer conductor run, it allows the second contact surface KN to be directly attached to the first contact surface KP. This, in turn, enables a low-inductance connection of supply busbars.

[0060] Figure 3 schematically shows a multiphase bridge circuit with several embedded half-bridge circuits. The bridge circuit is three-phase, with each phase implemented by a half-bridge circuit 1, 2, 3. The bridge circuit has a module frame R (electrically insulating, for example, made of plastic) in or on which two busbars HV+ and HV- are provided. The frame also has three individual phase contacts P1, P2, and P3. Each of the depicted half-bridge circuits 1, 2, and 3 has a group of first contact surfaces KP, second contact surfaces KN, and third contact surfaces KW. The contact surfaces KP of the half-bridge circuits 1, 2, and 3 are connected to the positive busbar HV+. The contact surfaces KN of the half-bridge circuits 1, 2, and 3 are connected to the positive busbar HV-. This allows a supply voltage (DC voltage) to be easily applied to the bridge circuit by connecting the busbars HV-, HV+.The contact surfaces KP and KN of the half-bridge circuits 1, 2, 3 are arranged at the upper end of the respective half-bridge circuit as shown. This corresponds to an embodiment according to Figure 1. Accordingly, the third contact surfaces KW are provided at the opposite end. These are connected to individual phase contacts P1, P2, P3. The windings of an electric machine or the phases of a three-phase system can be connected to these, depending on whether the bridge circuit is operated, for example, as an inverter for an electric machine, or as a rectifier, for example, for three-phase alternating current.

[0061] Finally, the semiconductor elements HS, LS of each half-bridge circuit are shown with dashed lines. These semiconductor elements are located in a plane below the contact pads KP, KN, KW, hence their dashed lines. It can be seen that the lower half contains the group of low-side semiconductor elements, and the upper half contains the high-side semiconductor elements. Reference is made to Figure 1 regarding the connections between these elements and also to the contact pads. The connections between the first and second contact pads KN, KP and the associated busbars HV+, HV- are shown as individual connections, although preferably a common band can be used.For example, all second contact surfaces KN can be connected to the busbar HV- via a conductive strip (approximately one strip per half-bridge circuit), and all first contact surfaces KP can be connected to the busbar HV+ via another conductive strip (approximately another strip per half-bridge circuit). Figure 3 and Figure 1 show that these strips, respectively,

[0062] General connections between the half-bridge circuits 1, 2, 3 and the module frame R can be routed close together, for example as overlapping strips with an insulating layer in between. Since the first and second contact surfaces are located close to each other, the area between the positive and negative supply potentials can be kept very small, resulting in a low-inductance connection to a DC voltage source (such as an intermediate circuit capacitor and / or a high-voltage battery). A common intermediate circuit capacitor can be arranged on the contact surfaces KP, KN of the half-bridge circuits 1, 2, 3 to enable a low-inductance connection of the intermediate circuit capacitor.

Claims

Patent claims 1. Embedded half-bridge circuit with a multilayer printed circuit board (PCB), the PCB comprising: a) a contact conductor layer (L1) with at least one first, one second and one third contact pad (KP, KN, KW) which are electrically isolated from each other; b) a first interconnect conductor layer (L2); c) a semiconductor layer (Hl) in which a first and a second group of semiconductor elements (HS, LS) are provided; and d) a second interconnect conductor layer (L3), wherein the layers (L1, L2, HI, L3) are arranged one above the other, the semiconductor layer (Hl) is located between the first interconnect conductor layer (L2) and the second interconnect conductor layer (L3), and a first section (A1) of the second interconnect conductor layer (L3) is connected via vias (D1,D2) is connected to the bottom surfaces of the first group of semiconductor elements (HS), and a second section (A2) of the second interconnection conductor layer (L3) is connected via vias (D3, D4) to the bottom surfaces of the second group of semiconductor elements (LS), wherein the first and second sections (A1, A2) of the second interconnection conductor layer (L3) are electrically separated from each other, and a first section (A3) of the first interconnection conductor layer (L2) is connected via vias (D11, D12) to the top surfaces of the first group of semiconductor elements (HS), and a second section (A4) of the first interconnection conductor layer (L2) is connected via vias (D13, D14) to the top surfaces of the second group of semiconductor elements (LS), wherein the first and second sections (A3,A4) first interconnection conductor layer (L2) are electrically separated from each other; wherein the first section (A3) of the first interconnection conductor layer (L2) is electrically connected to the second section (A2) of the second interconnection conductor layer (L3), at least one first contact surface (KN) is connected to the second section (A4) of the first interconnection conductor layer (L2) via vias (DN), and at least one second contact surface (KP) is connected to the first section (A1) of the second interconnection conductor layer (L3) via vias (DO, DU) extending from the contact conductor layer (L1) to the first section (A1) of the second interconnection conductor layer (L3).

2. Embedded half-bridge circuit according to claim 1, wherein at least one third of the contact surfaces (KW) is connected to the second interconnection conductor layer (L3) via vias (D0', DU') leading from the contact conductor layer (L1) to the second section (A2) of the second interconnection conductor layer (L3), or at least one third of the contact surfaces (KW) is connected to the first section (A3) of the first interconnection conductor layer (L2) via vias (DP).

3. Embedded half-bridge circuit according to claim 1 or 2, wherein the contact surfaces (KP, KN, KW) provide a free, conductive area for surface contacting of the half-bridge circuit, or an insulating layer (ISO) is provided on the contact surfaces (KP, KN, KW), on which external connection surfaces (KN') are provided that are individually connected to the contact surfaces (KP, KN, KW), wherein the connection surfaces (KN') are formed by a further conductor layer (L).

4. Embedded half-bridge circuit according to claim 1, 2 or 3, wherein the at least one second contact surface (KN) is arranged over the first or the second section (A3, A4) of the first interconnect conductor layer (L2) or over a location between these sections (A3, A4).

5. Embedded half-bridge circuit according to one of the preceding claims, wherein the at least one first contact surface (KP) is arranged over a location between the first or the second section (A3, A4) of the first interconnect conductor layer (L2) or next to these sections (A3, A4).

6. Embedded half-bridge circuit according to one of the preceding claims, wherein the at least one third contact surface (KW) is provided above the first section (A3) of the first interconnect conductor layer (L2), or is arranged next to this section (A3).

7. Embedded half-bridge circuit according to one of the preceding claims, wherein a cooling layer (KS) provided of metallic material is attached to the second interconnect conductor layer (L3) via an insulating layer (ISO'). is wherein the cooling layer (KS) is electrically insulated from the second interconnection conductor layer (L3) by the insulating layer (ISO'), or wherein vias extending through the insulating layer electrically connect the cooling layer (KS) to the second interconnection conductor layer (L3).

8. Embedded half-bridge circuit according to any of the preceding claims, wherein the semiconductor elements (HS, LS) are unpackaged or packaged power transistors, or wherein the semiconductor elements (HS, LS) each comprise a metal body and at least one power transistor semiconductor chip (T), wherein the power transistor semiconductor chip (T) is applied to the metal body (M) or the power transistor semiconductor chip (T) is embedded in the surface of the metal body (M).

9. Embedded half-bridge circuit according to one of the preceding claims, further comprising an intermediate circuit capacitor (ZK) arranged across the contact surfaces (KP, KN) connected to the first section (A1) of the second interconnect conductor layer (L3) and to the top surfaces of the second group of semiconductor elements (LS), or at least electrically connected to these contact surfaces.

10. Embedded half-bridge circuit according to one of the preceding claims, wherein the first interconnect conductor layer (L2) and / or the contact conductor layer (L1) form signal lines or sections thereof leading to the semiconductor elements (HS, LS) and / or to at least one temperature sensor arranged directly below, next to or directly above the semiconductor elements (HS, LS).

11. Multiphase bridge circuit with several embedded half-bridge circuits according to one of the preceding claims, wherein the contact surfaces (KP, KN) of the individual half-bridge circuits which are connected to the first section (A1 ) of the second interconnect conductor layer (L3) are electrically connected to each other, and the contact surfaces (KP, KN) of the individual half-bridge circuits which are connected to the top surfaces of the second group of semiconductor elements (LS) are likewise electrically connected to each other.

12. Multiphase bridge circuit according to claim 11, wherein the embedded half-bridge circuits are provided in different sections of the same continuous printed circuit board, or wherein the embedded half-bridge circuits are provided by physically independent, individual printed circuit board sections that form the respective printed circuit board of the half-bridge circuit.

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