Integrated circuit device having an etch-stop layer and its processing.

Abstract

An integrated circuit device (100) has a functional layer (101), which comprises an electrical circuit (108), and a bulk substrate layer (102) of semiconductor material having a substantially homogeneous chemical composition. An etch-stop layer (104) is present between the functional layer (101) and the bulk substrate layer (102). The etch-stop layer (104) is in contact with the bulk substrate layer (102). To improve effectiveness of an electrochemical treatment of the bulk substrate layer (102), the bulk substrate layer (102) comprises a zone (109) extending to the etch-stop layer (104), in which electrical resistivity decreases towards the etch-stop layer (104).

Description

[0001] Integrated circuit device having an etch-stop layer and its processing.

[0002] FIELD OF THE INVENTION

[0003] An aspect of the invention relates to an integrated circuit device having an etch-stop layer between a functional layer, which comprises an electrical circuit, and a bulk substrate layer. The electrical circuit in the integrated circuit device may be arranged to operate at a relatively high frequency, higher than, for example, 1 Gigahertz (GHz) or even 10 GHz. The integrated circuit device thus may be used in, for example, a product capable of emitting a radiofrequency signal, or receiving a radiofrequency signal, or both. Other aspects of the invention relate to a method of processing an integrated circuit device, wherein the bulk substrate layer is, at least partially, electrochemically altered, and to a processed integrated circuit device, which may be obtained by such a method.

[0004] BACKGROUND ART

[0005] An integrated circuit device is generally manufactured from a semiconductor substrate, which is typically in the form of a wafer. In the form of a wafer, a plurality of copies of the integrated circuit device may be formed therein. Manufacturing the integrated circuit device typically involves subjecting the semiconductor substrate to multiple chemical and photographic processing steps. These processing steps are generally applied to one side of the semiconductor substrate, which may be referred to as the front side. A functional layer comprising one or more electrical circuits is then formed at the front side.

[0006] The semiconductor substrate may remain untouched or, at least, may be processed only slightly, at a back side, which is opposite to the front side. The integrated circuit device will then comprise a bulk substrate layer at its back side. The bulk substrate layer is of semiconductor material having a substantially homogeneous chemical composition. The semiconductor material that makes up the bulk substrate layer may be similar to that of the semiconductor substrate from which the integrated circuit device is manufactured.

[0007] The bulk substrate layer may adversely affect operation of an electrical circuit in the functional layer of the integrated circuit device. This is especially the case if the electrical circuit operates at a relatively high frequency, such as, for example, 1 GHz or higher. High-frequency signals processed by the electrical circuit radiate power into the bulk substrate layer. Free charge carriers in the bulk substrate layer absorb some of this signal power. The bulk substrate layer then constitutes a lossy medium, which is close to the electrical circuit. For example, in case the electrical circuit comprises an inductor, the inductor may have a significantly lower quality factor than if the bulk substrate layer were to be replaced by a substantially lossless medium. What is more, the bulk substrate layer may cause signal distortion because signal power absorption may be nonlinear.

[0008] Several techniques have been proposed to mitigate adverse effects that the bulk substrate layer may have on the operation of an electrical circuit in the functional layer of the integrated circuit device. One of these techniques consists in making the bulk substrate layer at least partially porous. A porous bulk substrate layer has a significantly lower concentration of free charge carriers than a nonporous bulk substrate layer and, therefore, a significantly higher electrical resistivity. A porous bulk substrate layer thus absorbs significantly less power than a nonporous bulk substrate layer. A porous bulk substrate also causes significantly less signal distortion than a nonporous bulk substrate.

[0009] The bulk substrate layer can be made porous by electrochemical treatment. For example, patent publication US11538689 describes a technique in which a substrate is electrochemically treated by laterally applying an electrical potential at least to an exposed zone on a back side of the substrate, while the exposed zone is in contact with a chemically reactive substance. The electrical potential causes an electrical current that flows laterally in the exposed zone and passes through the chemically reactive substance. The electrical current and the chemically reactive substance alter the substrate starting from the exposed zone on the back side inwardly toward a front side, which comprises an electrical circuit. The substrate may comprise an alteration stop layer disposed between the electrical circuit at the front side of the substrate and the exposed zone on its back side. The alteration stop layer comprises a material that is relatively resistant to the chemically reactive substance used for altering the substrate. For example, high resistivity polycrystalline silicon, commonly called polysilicon, is particularly suited.

[0010] SUMMARY OF THE INVENTION

[0011] There is a need for a technique that allows to improve effectiveness of an electrochemical treatment of a bulk substrate layer of an integrated circuit device, in particular to better mitigate adverse effects that the bulk substrate layer may have on operation of an electrical circuit in a functional layer of the integrated circuit device.

[0012] The invention takes into consideration the following aspects. In order to optimally mitigate the aforementioned adverse effects, the bulk substrate layer should be entirely porous, at least in a zone underneath the electrical circuit. An alteration stop layer, which may also be referred to as etch-stop layer, may contribute to achieving this goal. The electrochemical treatment may bring about a process of pore creation that starts at an external surface of the bulk substrate layer, which is generally at the back side of the integrated circuit device. Pore creation advances inwardly towards the etch-stop layer, which is in contact with the bulk substrate layer. Ideally, the bulk substrate layer is then entirely porous from its external surface to its opposite surface that is in contact with the etch-stop layer.

[0013] However, in practice, pore creation in the bulk substrate layer may stop before the etch-stop layer is reached. A residual sublayer of nonporous semiconductor material, which is directly adjacent to the etch-stop layer, may remain in the bulk substrate layer. This residual nonporous sublayer may adversely affect the operation of the electrical circuit, albeit to a lesser extent than if the bulk substrate layer were entirely nonporous. The thicker the residual nonporous sublayer is, the greater the extent to which the operation of the electrical circuit is adversely affected. It is therefore desirable that the residual nonporous sublayer in the bulk substrate layer is as thin as possible.

[0014] Two main factors may account for pore creation not reaching the etch-stop layer, thereby leaving the residual nonporous sublayer. A first main factor concerns the etch-stop layer chemically affecting the bulk substrate layer, particularly in the vicinity of the etch-stop layer. One or more other layers, between the functional layer and the etchstop layer, may also chemically affect the bulk substrate layer. For example, in case the etch-stop layer comprises high resistivity polysilicon, whereby a silicon oxide layer may be present between the etch-stop layer and the functional layer, the polysilicon may tend to capture one or more dopants in the bulk substrate layer, which are near the polysilicon. This dopant-capturing effect may be exacerbated by heating in manufacturing the integrated circuit device. For example, it has been observed that heating may cause boron atoms to diffuse into the polysilicon. Boron is widely used as a semiconductor substrate dopant.

[0015] The layer interactions described in the preceding paragraph may thus make that dopant concentration in the bulk substrate layer decreases when approaching the etch- stop layer. As a result, electrical resistivity in the bulk substrate layer may increase when approaching the etch-stop layer. This increase in electrical resistivity may cause pore creation to stop before the etch-stop layer is reached. Namely, the pore creation process depends on an electrical current flowing through the bulk substrate layer so that an electrochemical reaction occurs that creates pores. The increase in resistivity locally weakens the electrical current that is necessary for creating pores. The increase in resistivity close to the etch-stop layer may weaken the electrical current to an extent that pores are no longer created there. The first main factor accounting for the pore creation process not reaching the etch-stop layer may thus be qualified as a resistive effect.

[0016] A second main factor that may account for pore creation not reaching the etch-stop layer concerns a geometrical effect. The geometrical effect occurs when pore creation starts from a confined area on the external surface of the bulk substrate layer due to, for example, the presence of a mask on this surface. The geometrical effect may also make that the residual nonporous sublayer is of nonuniform thickness. Specifically, in many cases, the residual nonporous sublayer is thickest at its center, becoming gradually thinner when moving away from the center. In experiments that have been carried out, the residual nonporous sublayer had a thickness of about 1.2 pm to 2 pm at its center, decreasing to about 200 nm to 500 nm at its edges.

[0017] The geometrical effect was found to be related to a contour of pore creation migrating inwardly into the bulk substrate layer starting from the confined area on its external surface. Pore creation process occurs where an already porous region in the bulk substrate layer interfaces with a remaining nonporous region. A transversal cross-section of this porous-nonporous interface may initially have a somewhat semielliptical profile, expanding inward toward the etch-stop layer. Pore creation continues in a given area at the porous-nonporous interface as long as sufficient electrical current flows through this given area.

[0018] A center area at the porous-nonporous interface will generally be substantially parallel to the etch-stop layer and first to come close thereto. As this center area approaches the etch-stop layer, the remaining nonporous region in the bulk substrate layer, in between the center area of the porous-nonporous interface and the etch-stop layer, becomes thinner. As a result, the electrical current flowing through the center area meets an increasingly greater resistance, making this electrical current weaker. At a certain point, the electrical current is too weak for pore creation to continue. Pore creation then stops in the center area of the porous-nonporous interface, which may still have a somewhat semielliptical profile at this point.

[0019] Pore creation will continue in areas at the porous-nonporous interface that are more or less laterally located. Contrary to the center area, these areas are generally more or less inclined with respect to the etch-stop layer, rather than being parallel thereto. The more laterally an area at the porous-nonporous interface is located, the more inclined this area is with respect to the etch-stop layer. Consequently, the more laterally an area at the porous-nonporous interface is located, the lesser the extent to which the electrical current flowing through this area will meet resistance when approaching the etch-stop layer. When pore creation stops altogether, the more laterally located areas at the porous- nonporous interface will therefore have gotten closer to the etch-stop layer than the more centrally located areas. The residual nonporous sublayer thus has a corresponding nonuniform thickness.

[0020] In general, far from its center, the residual nonporous sublayer in the bulk substrate layer will mainly be due to the resistive effect described hereinbefore, the geometric effect being of less importance there. At its center, the residual nonporous sublayer will mainly be due to a combination of the resistive effect and the geometric effect described hereinbefore. As explained, the residual nonporous sublayer will generally be thickest at its center. In all, as mentioned hereinbefore, it is desirable that the residual nonporous sublayer is as thin as possible while having a substantially uniform thickness.

[0021] An aspect of the invention, which is defined in claim 1, relates to an integrated circuit device comprising: a functional layer comprising an electrical circuit; a bulk substrate layer of semiconductor material having a substantially homogeneous chemical composition; and an etch-stop layer between the functional layer and the bulk substrate layer, whereby the etch-stop layer is in contact with the bulk substrate layer, wherein the bulk substrate layer comprises a zone extending to the etch-stop layer in which electrical resistivity decreases towards the etch-stop layer.

[0022] A further aspect of the invention, which is defined in claim 9, relates to wafer comprising at least one integrated circuit device as defined hereinbefore.

[0023] Yet a further aspect of the invention, which is defined in claim 10, relates to a method of processing an integrated circuit device as defined hereinbefore, the method comprising: electrochemically treating at least part of the bulk substrate layer by bringing an external surface of the bulk substrate layer into contact with a chemically reactive substance and passing an electrical current through the chemically reactive substance and the bulk substrate layer, thereby creating pores in the bulk substrate layer starting from the external surface toward the etch-stop layer.

[0024] Yet a further aspect of the invention, which is defined in claim 13, relates to a processed integrated circuit device obtained by applying a method as defined hereinbefore to an integrated circuit device as defined hereinbefore, the bulk substrate layer in the processed integrated circuit device being porous at least in a section extending between the external surface and an internal border proximate to the etch-stop layer and underlaying the electrical circuit in the functional layer.

[0025] In each of these aspects, the resistivity in the bulk substrate layer decreases when approaching the etch-stop layer. This favors a flow of electrical current close to the etch-stop layer. In turn, this prevents pore creation from significantly weakening when approaching the etch-stop layer and then stopping at a relatively large distance from the etch-stop layer. Rather, the decrease in the resistivity when approaching the etch-stop layer stimulates pore creation to continue up to the etch-stop layer. The resistive effect described hereinbefore is eliminated or, at least, significantly mitigated. As a result, once pore creation stops altogether, a residual nonporous sublayer, if any, in the bulk substrate layer may be significantly thinner compared with an integrated circuit device that suffers from the resistive effect as described hereinbefore.

[0026] The geometric effect described hereinbefore may also be significantly mitigated. Since the resistivity decreases when approaching the etch-stop layer, the electrical current flowing through a centrally located area at the porous-nonporous interface, which is substantially parallel to the etch-stop layer, need not meet significantly greater resistance than the electrical current flowing through a laterally located area at this interface that is inclined with respect to the etch-stop layer. Consequently, the decrease in resistivity when approaching the etch-stop layer also prevents the residual nonporous sublayer from having significantly nonuniform thickness.

[0027] These and other factors allow to improve effectiveness of an electrochemical treatment of a bulk substrate layer of an integrated circuit device. Specifically, a residual nonporous sublayer, which may remain after completion of the electrochemical treatment, can be significantly thinner and more uniform in thickness than what may be achievable using prior art techniques. This in turn, allows to better mitigate adverse effects that the bulk substrate layer may have on operation of an electrical circuit in a functional layer of the integrated circuit device. Boldly stated, better performing integrated circuit devices may be manufactured.

[0028] For the purpose of illustration, some embodiments of the invention are described in detail with reference to accompanying drawings. In this description, additional features will be presented, some of which are defined in the dependent claims, and advantages will be apparent.

[0029] BRIEF DESCRIPTION OF THE DRAWINGS

[0030] FIG. l is a schematic cross-sectional view of a first exemplary integrated circuit device.

[0031] FIG. 2 is a graph in which dopant concentration in the first exemplary integrated circuit device is plotted as a function of depth in this device.

[0032] FIG. 3 is a graph in which resistivity in the first exemplary integrated circuit device is plotted as a function of depth in this device.

[0033] FIG. 4 is a schematic cross-sectional view of a second exemplary integrated circuit device.

[0034] FIG. 5 is a graph in which dopant concentration in the second exemplary integrated circuit device is plotted as a function of depth in this device.

[0035] FIG. 6 is a graph in which resistivity in the second exemplary integrated circuit device is plotted as a function of depth in this device.

[0036] FIG. 7 is a schematic flow chart diagram of an exemplary method of processing the integrated circuit device.

[0037] FIG. 8 is a schematic cross-sectional view of a processed integrated circuit device.

[0038] DESCRIPTION OF SOME EMBODIMENTS

[0039] FIG. 1 schematically illustrates a first exemplary integrated circuit device 100. FIG. 1 provides a schematic cross-sectional view of the first exemplary integrated circuit device 100. The first exemplary integrated circuit device 100 may be manufactured from a basic substrate of semiconductor material using conventional techniques. The first exemplary integrated circuit device 100 may be an intermediate product. Specifically, the first exemplary integrated circuit device 100 may undergo further processing steps before being packaged so as to be ready for application in a product. An example of such further processing steps will be presented hereinafter.

[0040] The first exemplary integrated circuit device 100 comprises various layers. These include a functional layer 101, a bulk substrate layer 102 and, between these, an electrically insulating layer 103, and an etch-stop layer 104. The first exemplary integrated circuit device 100 comprises two main sides 105, 106, one of which will be referred to as the front side 105, whereas the other one will be referred to as the back side 106 for ease of reading. The functional layer 101 lies at the front side 105. The bulk substrate layer 102 lies at the back side 106. Specifically, the bulk substrate layer 102 has an external surface 107 at the back side 106 of the first exemplary integrated circuit device 100 in this embodiment. The etch-stop layer 104 is in contact with the bulk substrate layer 102. In this embodiment, the electrically insulating layer 103 lies in between the functional layer 101 and the etch-stop layer 104.

[0041] The etch-stop layer 104 may comprise a material that is chemically resistant to a chemically reactive substance that may be used for altering the bulk substrate layer 102, for example, in a manner that will be described hereinafter. The etch-stop layer 104 may comprise, for example, high resistivity polycrystalline silicon, commonly called polysilicon, or silicon nitride, or aluminum nitride, or any other suitable chemically resistant material or composition of materials. However, the etch-stop layer 104 need not necessarily comprise a material that is chemically resistant to a later-used chemically reactive substance. This will be discussed in greater detail hereinafter. The electrically insulating layer 103 may comprise, for example, silicon oxide, or any other suitable electrically insulating material or composition of materials.

[0042] The functional layer 101 comprises an electrical circuit 108, which may have been formed by processing a top layer of the basic substrate. The bulk substrate layer 102, however, may not have undergone any significant processing. The bulk substrate layer 102 has a substantially homogeneous chemical composition, which may be similar to, or even identical to, the semiconductor material of the basic substrate. For example, the bulk substrate layer 102 may be comprised of monocrystalline silicon that is relatively lightly doped by a P-type dopant. The P-type dopant may be, for example, boron, or aluminum, or gallium, or indium or another suitable chemical element, or a combination of chemical elements.

[0043] The bulk substrate layer 102 comprises a zone 109 extending to the etchstop layer 104 in which the electrical resistivity decreases towards the etch-stop layer 104. This zone 109 will be referred to as the etch-stimulus zone 109 in correspondence with its function, which will be discussed hereinafter. In the etch-stimulus zone 109, the electrical resistivity may decrease toward the etch-stop layer 104 by at least an order of magnitude. The electrical resistivity may decrease by two orders of magnitude, or even more, depending on a desired result to be achieved, which will be described hereinafter. An appropriate amount by which the electrical resistivity decreases in the etch-stimulus zone 109 may be empirically determined.

[0044] The etch-stimulus zone 109 may be at least 100 nm thick. Specifically, the etch-stimulus zone 109 may be at least 200 nm, 300 nm, 400 nm, or 500 nm thick. The etch-stimulus zone 109 may even be 1 pm thick, or even thicker. An appropriate thickness may depend on the desired result to be achieved. The appropriate thickness of the etchstimulus zone 109 may be empirically determined.

[0045] The decrease in electrical resistivity in the etch-stimulus zone 109 toward the etch-stop layer 104 may be due to, for example, the etch-stimulus zone 109 having a dopant profile that varies with depth. Depth is a position between the front side 105 and the back side 106 along a dash-dotted line in FIG. 1, which is orthogonal to these two main sides. For example, in the etch-stimulus zone 109, the aforementioned P-type dopant may have a concentration that increases with decreasing depth. That is, in the etch-stimulus zone 109, the concentration of the P-type dopant increases towards the etch-stop layer 104. The higher the concentration of the P-type dopant is at a given location in the etch-stimulus zone 109 and, more generally, in the bulk substrate layer 102, the lower the electrical resistivity is at this location in the etch-stimulus zone 109 and, more generally, in the bulk substrate layer 102.

[0046] There are various manners to create a varying dopant profile that decreases the electrical resistivity towards the etch-stop layer 104. For example, the varying dopant profile may be created by means of ion implantation. The ion implementation may be carried out while manufacturing the basic substrate, or while manufacturing the integrated circuit device from the basic substrate, or both of these. Another manner to create a varying dopant profile is to incorporate a solid dopant source layer in the basic substrate, or a partially processed version thereof, during manufacturing of the integrated circuit device. The dopant source layer may comprise one or more suitable dopants, which may diffuse into the bulk substrate layer 102 due to, for example, heating that is applied in manufacturing the integrated circuit device. As another example, the dopant profile may be created by epitaxial deposition of a doped layer on top of the bulk substrate layer 102. FIG. 2 schematically illustrates a dopant concentration in the first exemplary integrated circuit device 100 varying as a function of depth. FIG. 2 is a graph having a horizontal axis, which represents depth (d), and a vertical axis, which represents dopant concentration (D). A curve represents the dopant concentration varying as a function of depth over a depth range indicated in FIG. 1 by two arrows on the aforementioned dash- dotted line. This depth range includes the bulk substrate layer 102 and the etch-stop layer 104. The graph comprises three vertical sections. A middle section corresponds to the etchstimulus zone 109 in the bulk substrate layer 102. A relatively wide rightmost vertical section corresponds to a main portion of the bulk substrate layer 102 excluding the etchstimulus zone 109. A leftmost portion corresponds to the etch-stop layer 104.

[0047] The graph of FIG. 2 shows that, in the etch-stimulus zone 109, the dopant concentration increases toward the etch-stop layer 104. In this example, the dopant concentration increases throughout almost the entire etch-stimulus zone 109, except for an insignificantly small portion where the bulk substrate layer 102 interfaces with the etchstop layer 104. The dopant concentration may increase by at least an order of magnitude in the etch-stimulus zone 109. This implies that the vertical axis has a logarithmic scale rather than a linear scale, although the latter is not excluded. For the sake of illustration, the graph of FIG 2 concerns an embodiment in which the etch-stop layer 104 comprises a material that is chemically resistant to a later-used chemically reactive substance, as discussed hereinbefore. The doping concentration in such a chemically resistant material may not be of importance.

[0048] FIG. 3 schematically illustrates the electrical resistivity in the first exemplary integrated circuit varying as a function of depth. FIG. 3 is a graph having a horizontal axis, which represents depth (d), and a vertical axis, which represents electrical resistivity (R). A curve represents the electrical resistivity varying as a function of depth over the depth range mentioned hereinbefore with regard to FIG. 2. The graph of FIG. 3 comprises the same three vertical sections as those in the graph of FIG. 2.

[0049] The graph of FIG. 3 shows that, in the etch-stimulus zone 109, the electrical resistivity decreases toward the etch-stop layer 104. In this example, the electrical resistivity decreases throughout almost the entire etch-stimulus zone 109, except for an insignificantly small portion where the bulk substrate layer 102 interfaces with the etchstop layer 104. This mirrors the variation in dopant concentration in the etch-stimulus zone 109 towards the etch-stop layer 104 as illustrated in FIG. 2. The electrical resistivity may decrease by at least an order of magnitude as mentioned hereinbefore. Like with FIG. 2, this implies that the vertical axis has a logarithmic scale rather than a linear scale, although the latter is not excluded.

[0050] FIG. 4 schematically illustrates a second exemplary integrated circuit device 400. FIG. 4 provides a schematic cross-sectional view of the second exemplary integrated circuit device 400. Basically, the second exemplary integrated circuit device 400 may be regarded as a modified version of the first exemplary integrated circuit device 100 in which the electrically insulating layer 103 has been omitted. Like elements are therefore denoted by like reference signs for the sake of simplicity and clarity. Like the first exemplary integrated circuit device 100, the second exemplary integrated circuit device 400 may be manufactured from a basic substrate of semiconductor material using conventional techniques. The further remarks made in this respect regarding the first exemplary integrated circuit device 100 may equally apply to the second exemplary integrated circuit device 400. FIG. 4 includes a dash-dotted line corresponding to the aforementioned dash- dotted line in FIG. 1 discussed hereinbefore.

[0051] Like the first exemplary integrated circuit device 100, the second exemplary integrated circuit device 400 also comprises a functional layer 101, a bulk substrate layer 102, and an etch-stop layer 104 in between these two aforementioned layers, whereby the etch-stop layer 104 is in contact with the bulk substrate layer 102. The functional layer 101 lies at a main side of the second exemplary integrated circuit device 400, which will also be referred to as the front side 105. The bulk substrate layer 102 lies at an opposite main side, which also be referred to the back side 106. The functional layer 101 comprises an electrical circuit 108. The bulk substrate layer 102 comprises an etch-stimulus zone 109, which may be similar to the etch-stimulus zone 109 in the first exemplary integrated circuit discussed hereinbefore with reference to FIGS. 1-3.

[0052] The etch-stop layer 104 may be composed of the same semiconductor material as that of the bulk substrate layer 102 and having a similar crystalline structure. For example, the bulk substrate layer 102 and the etch-stop layer 104 may both substantially be comprised of monocrystalline silicon. That is, the etch-stop layer 104 may be composed of a material that is not chemically resistant, at least not to a significant extent, to a later-used chemically reactive substance. In such an embodiment, the etch-stop layer 104 has an electrical resistivity that increases away from the bulk substrate layer 102. The aforementioned may thus also apply to the etch-stop layer 104 in the first exemplary integrated circuit device 100 illustrated in FIG. 1. The increase in electrical resistivity in the etch-stop layer 104 away from the bulk substrate layer 102 may be due to, for example, the etch-stop layer 104 having a dopant profile that varies with depth. In case the etch-stop layer 104 and the bulk substrate layer 102 have dopants of the same polarity, the dopant profile may be determined by a dopant concentration that varies with depth. For example, let it be assumed that the etchstop layer 104 is at least partially doped with a P-type dopant, like the bulk substrate layer 102. In the etch-stop layer 104, the P-type dopant may have a concentration that decreases with decreasing depth. That is, in the etch-stop layer 104, the concentration of the P-type dopant decreases away from the bulk substrate layer 102. The lower the concentration of the P-type dopant is at a given location in the etch-stop layer 104, the higher the electrical resistivity is at this location in the etch-stop layer 104. The aforementioned also applies when the etch-stop layer 104 and the bulk substrate layer 102 are both doped with an N- type dopant instead of a P-type dopant.

[0053] There are various manners to create a varying dopant profile in which the concentration of a dopant decreases away from the bulk substrate layer 102, thereby creating the etch-stop layer 104. For example, the basic substrate, or a partially processed version thereof, may undergo a thermal treatment while exposed to a suitable gas at a side corresponding to the front side 105. This will cause the dopant to leak out of the basic substrate, or the partially processed version thereof, at the side corresponding to the front side 105. As another example, the concentration of the dopant may be decreased away from the bulk substrate layer 102 by epitaxial deposition of semiconductor material that is less doped, or not doped at all, at least not significantly. As another example, the concentration of the dopant may be decreased away from the bulk substrate layer 102 by deposition of an adjacent layer that absorbs the dopant. Dopant absorption may especially occur during heating steps in manufacturing the second exemplary integrated circuit device 400 from the basic substrate.

[0054] Alternatively, the dopant profile in the etch-stop layer 104 may at least partially be determined by the etch-stop layer 104 and the bulk substrate layer 102 having dopants of opposite polarity. For example, let it be assumed that the bulk substrate layer 102 is doped with a P-type dopant. The etch-stop layer 104 may then be doped with an N- type dopant, at least in an upper portion of the etch-stop layer 104, which is closest to the front side 105. The N-type dopant may form a N-type zone adjacent to a P-type zone, at least partially formed by the P-type dopant in the bulk substrate layer 102. Between the N- type zone and the P-type zone, there is a zone where the electrical resistivity increases away from the bulk substrate layer 102. This zone then constitutes the etch-stop layer 104.

[0055] FIG. 5 schematically illustrates a dopant concentration in the second exemplary integrated circuit device 400 varying as a function of depth. Like FIG. 2, FIG. 5 is a graph having a horizontal axis, which represents depth (d), and a vertical axis, which represents dopant concentration (D). A curve represents the dopant concentration varying as a function of depth over a depth range indicated in FIG. 4 by two arrows on the dash- dotted line. This depth range includes the bulk substrate layer 102 and the etch-stop layer 104. Like FIG. 2, the graph comprises three vertical sections. A middle section corresponds to the etch-stimulus zone 109 in the bulk substrate layer 102. A relatively wide rightmost vertical section corresponds to a main portion of the bulk substrate layer 102 excluding the etch-stimulus zone 109. A leftmost portion corresponds to the etch-stop layer 104.

[0056] For the sake of illustration, the graph of FIG. 5 concerns an embodiment in which the etch-stop layer 104 is composed of the same semiconductor material as that of the bulk substrate layer 102 and has a similar crystalline structure, as discussed hereinbefore. The graph FIG. 5 shows that, in the etch-stop layer 104, the dopant concentration decreases away from the bulk substrate layer 102. The dopant concentration may decrease monotonously and rather gradually as illustrated in this graph. Concerning the etch-stimulus zone 109, the remarks made hereinbefore with reference to the graph of FIG. 2, may equally apply to the graph of FIG. 5. Like in the graph of FIG. 2, in the graph of FIG. 5, the vertical axis has a logarithmic scale rather than a linear scale, although the latter is not excluded.

[0057] FIG. 6 schematically illustrates the electrical resistivity in the second exemplary integrated circuit varying as a function of depth. Like FIG. 3, FIG. 6 is a graph having a horizontal axis, which represents depth (d), and a vertical axis, which represents resistivity (R). A curve represents the electrical resistivity varying as a function of depth over the depth range mentioned hereinbefore with regard to FIG. 5. The graph of FIG. 6 comprises the same three vertical sections as those in the graph of FIG. 5.

[0058] The graph of FIG. 6 shows that, in the etch-stop layer 104, the electrical resistivity increases away from the bulk substrate layer 102. In this example, the electrical resistivity increases rather monotonously and rather gradually throughout the etch-stop layer 104. This mirrors the decrease in dopant concentration in the etch-stop layer 104 away from the bulk substrate layer 102 illustrated in FIG. 5. Like in the graph of FIG. 3, in the graph of FIG. 6, the vertical axis has a logarithmic scale rather than a linear scale, although the latter is not excluded.

[0059] FIG. 7 illustrates an exemplary method 700 of processing an integrated circuit device 701, which may be the first exemplary integrated circuit device 100, or the second exemplary integrated circuit device 400, or another embodiment. FIG. 7 provides a flow chart diagram of the exemplary method 700, which comprises several steps 702, 703. The method 700 is applied to a wafer 704 of which the integrated circuit device 701 is a part. The wafer 704 may include further integrated circuit devices 705, which may be identical to the aforementioned integrated circuit device 701. The method 700 illustrated in FIG. 7 may be based on a technique that is described in patent publication US11538689 cited hereinbefore.

[0060] In FIG. 7, a very schematic cross-sectional view of the wafer 704 is provided by way of illustration. The wafer 704 has a front side 706 and a back side 707, which encompass a front side and a back side, respectively, of the integrated circuit device 701. Thus, the front side 706 and the back side 707 of the wafer 704 encompass the front side 105 and the back side 106 of the first exemplary integrated circuit device 100, or of the second exemplary integrated circuit device 400, whichever constitutes the integrated circuit device 701.

[0061] In this example, the back side 707 of the wafer 704 is provided with an etchresistant mask 708, which may have an open-grid pattern. The etch-resistant mask 708 defines exposed zones on the back side 707 of the wafer 704. Accordingly, the integrated circuit device 701 has an exposed zone 709 on its back side. The back side 707 of the wafer 704 is further provided with a peripheral electrode 710, which may be in the form of a ring. The peripheral electrode 710 may have been formed by deposition of a conductive material, which may be a metal, such as, for example, aluminum.

[0062] In a first step 702, the back side 707 of the wafer 704 is brought into contact with a chemically reactive substance 711. The chemically reactive substance 711 may comprise, for example, hydrofluoric acid. The chemically reactive substance 711 may be contained in a container 712. The container 712 may have a size and shape that allows placing the container 712 within the peripheral electrode 710 as illustrated in FIG. 7. The exposed zone 709 on the back side of the integrated circuit device 701 is in contact with the chemically reactive substance 711. In contrast, peripheral zones on the back side of the integrated circuit device 701 may not be in contact with the chemically reactive substance 711 due to the presence of the etch resisting mask mentioned hereinbefore. In a second step 703, an electrical current 713 is made to flow through the wafer 704 and the chemically reactive substance 711. Specifically, the electrical current 713 flows from the peripheral electrode 710 to the exposed zones on the back side 707 of the wafer 704, in a lateral direction, and then to another electrode 714 that is present in the chemically reactive substance 711. Focusing on the integrated circuit device 701, the electrical current 713 thus flows in a lateral direction through the exposed zone 709 on the back side into the chemically reactive substance 711 towards the electrode 714 in the chemically reactive substance 711. In this example, the peripheral electrode 710 may be regarded as constituting an anode, whereas the electrode 714 in the chemically reactive substance 711 constitutes a cathode.

[0063] The case where the first exemplary integrated circuit device 100 constitutes the integrated circuit device 701 in the wafer 704 is now discussed, with reference to both FIGS. 1 and 7. The electrical current 713 flows in a lateral direction through the bulk substrate layer 102 and then into the chemically reactive substance 711 passing through the exposed zone 709 on the back side 106. The electrical current 713 causes the chemically reactive substance 711 to alter the bulk substrate layer 102 starting from the exposed zone 709 towards the etch-stop layer 104. Specifically, this electrochemically-induced alteration of the bulk substrate layer 102 may consist in creation of pores. That is, pores may be created starting from the back side 106 up to the etch-stop layer 104. The pores are created within a region having a lateral cross-section that is substantially determined by the exposed zone 709.

[0064] The etch-stimulus zone 109 in the bulk substrate layer 102 discussed hereinbefore allows maintaining the creation of pores when this process comes relatively close to the etch-stop layer 104. The decrease in electrical resistivity in this zone towards the etch-stop layer 104 prevents the electrical current 713 from becoming too weak in a relatively thin region of the bulk substrate layer 102 in which pores have not yet been created. This allows the creation of pores to continue relatively close to the etch-stop layer 104, while otherwise the creation of pores might have already stopped.

[0065] Accordingly, if there is any residual nonporous sublayer remaining in the bulk substrate layer 102 at the end of the method 700 illustrated in FIG. 7, this residual nonporous sublayer will be relatively thin. Moreover, the residual nonporous sublayer will have a substantially uniform thickness. Accordingly, since the bulk substrate layer 102 can be made porous to a greater extent in the vicinity of the electrical circuit 108, the electrical circuit 108 may achieve better performance as discussed hereinbefore. FIG. 8 illustrates a processed integrated circuit device 800 that may be obtained by applying the method 700 illustrated in FIG. 7 to the first exemplary integrated circuit device 100 illustrated in FIG. 1. FIG. 8 provides a schematic cross-sectional view of the processed integrated circuit device 800. The processed integrated circuit device 800 corresponds to the first exemplary integrated circuit device 100 in which a region 801 in the bulk substrate layer 102 has been made porous. This porous bulk substrate region 801 underlies the electrical circuit 108. The porous bulk substrate region 801 extends from the back side 106 to the etch-stop layer 104, leaving only a relatively thin residual nonporous sublayer, if any, just underneath the etch-stop layer 104. The porous bulk substrate region 108 may have a lateral cross-section that is substantially determined by the exposed zone 709 illustrated in FIG. 7, discussed hereinbefore. In this embodiment, the etch-resistant mask 708 used in the method 700 illustrated in FIG. 7 has been removed. In another embodiment, this mask 708 may still be present on a processed integrated circuit device.

[0066] The remarks made hereinbefore regarding the case where the first exemplary integrated circuit device 100 constitutes the integrated circuit device 701, equally apply to the case where the second exemplary integrated circuit device 400 constitutes the integrated circuit device 701 in the wafer 704. This particularly concerns the etch-stimulus zone 109, which is also present in the bulk substrate layer 102 of the second exemplary integrated circuit device 400.

[0067] As discussed hereinbefore, the etch-stop layer 104 need not be chemically resistant to the chemically reactive substance 711. The etch-stop layer 104 may be capable of stopping a process of pore creation if the electrical resistivity in this layer increases away from the bulk substrate layer 102. This prevents the electrical current 713 from flowing in the etch-stop layer 104 or, at least, significantly weakens the electrical current 713 at this point. The absence, or the significant weakening, of the electrical current 713 in the etch-stop layer 104 by itself may thus stop the pore creation process, even if the etchstop layer 104 is not chemically resistant to the chemically reactive substance 711.

[0068] An advantage of such an embodiment is that there is no need for a chemically resistant layer to stop an electrochemically-induced process of altering the bulk substrate layer 102 at a desired depth. Incorporating a chemically resistant layer, such as, for example, a a high resistivity polysilicon layer or an aluminum nitride layer, in an integrated circuit device is relatively expensive. An embodiment in which the etch-stop layer 104 has an electrical resistivity that increases away from the bulk substrate layer 102 offers thus an additional advantage, namely a cost advantage. The etch-stop layer 104 may be composed of the same semiconductor material as that of the bulk substrate layer 102 and having a similar crystalline structure, such as, for example, monocrystalline silicon.

[0069] NOTES

[0070] The embodiments described hereinbefore with reference to the drawings are presented by way of illustration. The invention may be implemented in numerous different ways. In order to illustrate this, some alternatives are briefly indicated.

[0071] The invention may be applied in numerous types of products or methods related to electrochemically altering a substrate. The embodiments presented hereinbefore concern an electrochemical alteration that creates pores in a substrate. However, the invention may be applied to advantage in other types of electrochemical alteration, such as, for example, etching away a part of the substrate.

[0072] There are numerous different ways of implementing an integrated circuit device in accordance with the invention. There are many possible embodiments different from those presented hereinbefore. For example, embodiments may comprise one or more additional layers. The etch-stop layer need not span the entire width of an integrated circuit device, but may be locally present between the bulk substrate layer and another layer. This other layer need not be in an electrically insulating layer. Also, in case the etch-stop layer is in between the bulk substrate layer and an electrically insulating layer, the etch-stop layer need not be chemically resistant. The etch-stop layer, which is adjacent to the electrically insulating layer, may be composed of the same semiconductor material as that of the bulk substrate layer and have a similar crystalline structure, in which electrical resistivity increases away from the bulk substrate layer.

[0073] There are numerous different ways of implementing a zone in a bulk substrate layer extending to an etch-stop layer, in which electrical resistivity decreases towards the etch-stop layer. In the presented embodiments, this is essentially achieved by doping. In other embodiments, this may be achieved by, for example, modulating the carrier concentration or the carrier mobility, or both. The carrier mobility can be modulated by, for example, introducing trap states in the semiconductor material. Trap states may result from impurities that create energy states deep in the band gap or by some form of compensation doping. Another way to modulate carrier concentration or mobility, or both, mobility, consists in modifying the number of crystal imperfections, so-called defects, or by introducing strain in a semiconductor crystal lattice, or by including a material with a different band gap energy. The term etch-stop layer should be interpreted broadly. This term encompasses any layer that is capable of stopping an electrochemically induced alteration of the substrate, which need not necessarily comprise etching.

[0074] The remarks made hereinbefore demonstrate that the embodiments described with reference to the drawings illustrate the invention, rather than limit the invention. The invention can be implemented in numerous alternative ways that are within the scope of the appended claims. All changes that come within the meaning and range of equivalency of the claims are to be embraced within their scope. Any reference sign in a claim should not be construed as limiting the claim. The verb “comprise” in a claim does not exclude the presence of other elements or other steps than those listed in the claim. The same applies to similar verbs such as “include” and “contain”. The mention of an element in singular in a claim pertaining to a product, does not exclude that the product may comprise a plurality of such elements. Likewise, the mention of a step in singular in a claim pertaining to a method does not exclude that the method may comprise a plurality of such steps. The mere fact that respective dependent claims define respective additional features, does not exclude combinations of additional features other than those reflected in the claims.

Claims

CLAIMS:

1. An integrated circuit device (100, 400) comprising: a functional layer (101) comprising an electrical circuit (108); a bulk substrate layer (102) of semiconductor material having a substantially homogeneous chemical composition; and an etch-stop layer (104) between the functional layer and the bulk substrate layer, whereby the etch-stop layer is in contact with the bulk substrate layer, wherein the bulk substrate layer comprises a zone (109) extending to the etch-stop layer, in which electrical resistivity (R) decreases towards the etch-stop layer.

2. An integrated circuit device according to claim 1, wherein the zone (109) in the bulk substrate layer (102) in which the electrical resistivity (R) decreases is at least 100 nm thick.

3. An integrated circuit device according to any of claims 1 and 2, wherein the electrical resistivity (R) in the zone (109) in the bulk substrate layer (109) decreases by at least an order of magnitude towards the etch-stop layer (104).

4. An integrated circuit device according to any of claims 1 to 3, wherein the zone (109) in the bulk substrate layer (102) has a dopant profile that varies with depth (d).

5. An integrated circuit device according to any of claims 1 to 4, comprising: an electrically insulating layer (103) between the functional layer (101) and the etch-stop layer (104).6 An integrated circuit device according to any of claims 1 to 5, wherein: the etch-stop layer (104) is composed of the same semiconductor material as that of the bulk substrate layer (102) and has a similar crystalline structure; and the etch-stop layer has an electrical resistivity (R) that increases away from the bulk substrate layer.

7. An integrated circuit device according to claim 6, wherein the etch-stop layer (104) has a dopant profile that varies with depth (d).

8. An integrated circuit device according to claim 7, wherein the dopant profile is at least partially determined by the etch-stop layer (104) and the bulk substrate layer (102) having dopants of opposite polarity.

9. A wafer (704) comprising at least one integrated circuit device (100, 400) according to any of claims 1 to 8.

10. A method (700) of processing an integrated circuit device (100, 400) according to any of claims 1 to 8, the method comprising: electrochemically treating (703) at least part of the bulk substrate layer (102) by bringing an external surface (107) of the bulk substrate layer into contact with a chemically reactive substance (711) and passing an electrical current (713) through the chemically reactive substance and the bulk substrate layer, thereby creating pores in the bulk substrate layer starting from the external surface toward the etch-stop layer (104).

11. A method of processing an integrated circuit device according to claim 10, wherein the electrical current passes (713) through the bulk substrate layer (102) at least partially in a lateral direction.

12. A method of processing an integrated circuit device according to any of claims 10 and 11, wherein the integrated circuit device (100, 400) forms part of a wafer (704) comprising further integrated circuit devices (705) according to any of claims 1 to 8, the electrochemically treating (703) being applied jointly to the integrated circuit device and the further integrated circuit devices as part of the wafer.

13. A processed integrated circuit device (800) obtained by applying the method (700) of processing according to any of claims 10 to 12 to an integrated circuit device (100, 400) according to any of claims 1 to 10, the bulk substrate layer (102) in the processed integrated circuit device (800) being porous at least in a region (801) extendingbetween the external surface (107) and an internal border proximate to the etch-stop layer (104) and underlaying the electrical circuit (108) in the functional layer (102).

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