Integrated circuit device having an etch-stop layer and its processing

Abstract

A processing is applied to an integrated circuit device (100) that has a functional layer (101), which comprises an electrical circuit (108), a bulk substrate layer (102) of semiconductor material, and an etch-stop layer (104) between the functional layer (101) and the bulk substrate layer (102). The etch-stop layer (104) contacts the bulk substrate layer (102). The processing comprises electrochemically treating at least part of the bulk substrate layer (102) by bringing an external surface (107) of the bulk substrate layer (102) into contact with a chemically reactive substance. An electrical current passes through the chemically reactive substance and the bulk substrate layer (102), thereby electrochemically altering the bulk substrate layer (102) starting from the external surface (107) toward the etch-stop layer (104). In the integrated circuit device (100) to which the processing is applied, a layer that is chemically resistant to the chemically reactive substance is absent between the bulk substrate layer (102) and the functional layer (101). The etch-stop layer (104) has an electrical resistivity that increases away from the bulk substrate layer (102). The etch-stop layer (104) may be composed of the same semiconductor material as that of the bulk substrate layer (102) and may have a similar crystalline structure.

Description

[0001] Integrated circuit device having an etch-stop layer and its processing.

[0002] FIELD OF THE INVENTION

[0003] An aspect of the invention relates to a method of processing an integrated circuit device by electrochemically altering a bulk substrate layer in the integrated circuit device starting from an external surface thereof toward an etch-stop layer in the integrated circuit device. The integrated circuit device may comprise an electrical circuit arranged to operate at a relatively high frequency, higher than, for example, 1 Gigahertz (GHz) or even 10 GHz. The integrated circuit device thus may be used in, for example, a product capable of emitting a radiofrequency signal, or receiving a radiofrequency signal, or both. Another aspect of the invention relates to a processed integrated circuit device, which may be obtained by such a method.

[0004] BACKGROUND ART

[0005] An integrated circuit device is generally manufactured from a semiconductor substrate, which is typically in the form of a wafer. In the form of a wafer, a plurality of copies of the integrated circuit device may be formed therein. Manufacturing the integrated circuit device typically involves subjecting the semiconductor substrate to multiple chemical and photographic processing steps. These processing steps are generally applied to one side of the semiconductor substrate, which may be referred to as the front side. A functional layer comprising one or more electrical circuits is then formed at the front side.

[0006] The semiconductor substrate may remain untouched or, at least, may be processed only slightly, at a back side, which is opposite to the front side. The integrated circuit device will then comprise a bulk substrate layer at its back side. The bulk substrate layer generally has a substantially homogeneous crystalline structure. The semiconductor material that makes up the bulk substrate layer may be similar to that of the semiconductor substrate from which the integrated circuit device is manufactured.

[0007] The bulk substrate layer may adversely affect operation of an electrical circuit in the functional layer of the integrated circuit device. This is especially the case if the electrical circuit operates at a relatively high frequency, such as, for example, 1 GHz or higher. High-frequency signals processed by the electrical circuit radiate power into the bulk substrate layer. Free charge carriers in the bulk substrate layer absorb some of this signal power. The bulk substrate layer then constitutes a lossy medium, which is close to the electrical circuit. For example, in case the electrical circuit comprises an inductor, the inductor may have a significantly lower quality factor than if the bulk substrate layer were to be replaced by a substantially lossless medium. What is more, the bulk substrate layer may cause signal distortion because signal power absorption may be nonlinear.

[0008] Several techniques have been proposed to mitigate adverse effects that the bulk substrate layer may have on the operation of an electrical circuit in the functional layer of the integrated circuit device. One of these techniques consists in making the bulk substrate layer at least partially porous. A porous bulk substrate layer has a significantly lower concentration of free charge carriers than a nonporous bulk substrate layer and, therefore, a significantly higher electrical resistivity. A porous bulk substrate layer thus absorbs significantly less power than a nonporous bulk substrate layer. A porous bulk substrate also causes significantly less signal distortion than a nonporous bulk substrate.

[0009] The bulk substrate layer can be made porous by electrochemical treatment. For example, patent publication US11538689 describes a technique in which a substrate is electrochemically treated by laterally applying an electrical potential at least to an exposed zone on a back side of the substrate, while the exposed zone is in contact with a chemically reactive substance. The electrical potential causes an electrical current that flows laterally in the exposed zone and passes through the chemically reactive substance. The electrical current and the chemically reactive substance alter the substrate starting from the exposed zone on the back side inwardly toward a front side, which comprises an electrical circuit. The substrate may comprise an alteration stop layer disposed between the electrical circuit at the front side of the substrate and the exposed zone on its back side. The alteration stop layer comprises a material that is relatively resistant to the chemically reactive substance used for altering the substrate. For example, high resistivity polycrystalline silicon, commonly called polysilicon, is particularly suited.

[0010] SUMMARY OF THE INVENTION

[0011] There is a need for a technique that offers an improvement in the processing of an integrated circuit device by electrochemically altering a bulk substrate layer in the integrated circuit, the improvement concerning at least a reduction of costs associated with such processing. The invention takes into consideration the following aspects. The following phenomenon has been observed in processes in which a bulk substrate layer is electrochemically altered starting from an external surface thereof, moving inward toward an alteration stop layer composed of high resistivity polysilicon. Electrochemical alteration of the bulk substrate layer generally does not reach the alteration stop layer, which may also be referred to as the etch-stop layer. The electrochemical alteration stops somewhat before the etch-stop layer, such as, for example, a few hundreds of nanometers before the etch-stop layer as has been observed. This phenomenon indicated that something else than chemical resistance stopped the electrochemical alteration from moving further inward.

[0012] The following explanation was found through analysis, which was confirmed by computer simulation. The high resistivity polysilicon, which composes the etch-stop layer, absorbs a part of dopants that are present in the bulk substrate layer. This dopant absorption creates a zone in the bulk substrate layer in which resistivity increases toward the high resistivity polysilicon. This zone in which resistivity increases is directly adjacent to high resistivity polysilicon, lying just before what is considered to constitute the etch-stop layer. The resistivity in the zone increases to a point where the electrical current necessary for electrochemically altering the bulk substrate becomes too weak to support the electrochemical alteration. Increasing resistivity stops the electrochemical alteration rather than the chemical resistance of the high resistivity poly silicon. It is the zone in which resistivity increases that actually constitutes the etch-stop layer rather than the high resistivity polysilicon, which is considered to constitute the etch-stop layer.

[0013] An aspect of the invention, which is defined in claim 1, relates to a method of processing an integrated circuit device comprising: a functional layer comprising an electrical circuit; a bulk substrate layer of semiconductor material; and an etch-stop layer between the functional layer and the bulk substrate layer, the etch-stop layer contacting the bulk substrate layer, the method comprising: electrochemically treating at least part of the bulk substrate layer by bringing an external surface of the bulk substrate layer into contact with a chemically reactive substance and passing an electrical current through the chemically reactive substance and the bulk substrate layer, thereby electrochemically altering the bulk substrate layer starting from the external surface toward the etch-stop layer, whereby, in the integrated circuit device: a layer that is chemically resistant to the chemically reactive substance is absent between the bulk substrate layer and the functional layer; and the etch-stop layer has an electrical resistivity that increases away from the bulk substrate layer.

[0014] A further aspect of the invention, which is defined in claim 13, relates to a processed integrated circuit device obtained by applying a method as defined hereinbefore, the bulk substrate layer in the processed integrated circuit device being porous at least in a section extending between the external surface and the etch-stop layer and underlaying the electrical circuit in the functional layer.

[0015] In each of these aspects, the etch-stop layer stops an electrochemical alteration process moving inward by the electrical resistivity increasing in this layer away from the substrate layer. There is no need for the integrated circuit device to comprise a chemically resistant layer between its bulk substrate layer and its functional layer where the electrical circuit is present. Embedding a chemically resistant layer, such as, for example, high resistivity polysilicon in an integrated circuit is relatively expensive. Since there is no need for embedding a chemically resistant layer, an appreciable cost saving is possible.

[0016] For the purpose of illustration, some embodiments of the invention are described in detail with reference to accompanying drawings. In this description, additional features will be presented, some of which are defined in the dependent claims, and advantages will be apparent.

[0017] BRIEF DESCRIPTION OF THE DRAWINGS

[0018] FIG. l is a schematic cross-sectional view of a first exemplary integrated circuit device.

[0019] FIG. 2 is a graph in which dopant concentration in the first exemplary integrated circuit device is plotted as a function of depth in this device.

[0020] FIG. 3 is a graph in which electrical resistivity in the first exemplary integrated circuit device is plotted as a function of depth in this device.

[0021] FIG. 4 is a schematic cross-sectional view of a second exemplary integrated circuit device.

[0022] FIG. 5 is a schematic flow chart diagram of an exemplary method of processing the integrated circuit device. FIG. 6 is a schematic cross-sectional view of a processed integrated circuit device.

[0023] DESCRIPTION OF SOME EMBODIMENTS

[0024] FIG. 1 schematically illustrates a first exemplary integrated circuit device 100. FIG. 1 provides a schematic cross-sectional view of the first exemplary integrated circuit device 100. The first exemplary integrated circuit device 100 may be manufactured from a basic substrate of semiconductor material using conventional techniques. The first exemplary integrated circuit device 100 may be an intermediate product. Specifically, the first exemplary integrated circuit device 100 may undergo further processing steps before being packaged so as to be ready for application in a product. An example of such further processing steps will be presented hereinafter.

[0025] The first exemplary integrated circuit device 100 comprises various layers. These include a functional layer 101, a bulk substrate layer 102 and, between these, an electrically insulating layer 103, and an etch-stop layer 104. The first exemplary integrated circuit device 100 comprises two main sides 105, 106, one of which will be referred to as the front side 105, whereas the other one will be referred to as the back side 106 for ease of reading. The functional layer 101 lies at the front side 105. The bulk substrate layer 102 lies at the back side 106. Specifically, the bulk substrate layer 102 has an external surface 107 at the back side 106 of the first exemplary integrated circuit device 100 in this embodiment. The etch-stop layer 104 is in contact with the bulk substrate layer 102. In this embodiment, the electrically insulating layer 103 lies in between the functional layer 101 and the etch-stop layer 104.

[0026] The functional layer 101 comprises an electrical circuit 108, which may have been formed by processing a top layer of the basic substrate. The bulk substrate layer 102, however, may not have undergone any significant processing. The bulk substrate layer 102 has a substantially homogeneous chemical composition, which may be similar to, or even identical to, the semiconductor material of the basic substrate. For example, the bulk substrate layer 102 may be comprised of monocrystalline silicon that is relatively lightly doped by a P-type dopant. The P-type dopant may be, for example, boron, or aluminum, or gallium, or indium or another suitable chemical element, or a combination of chemical elements.

[0027] The etch-stop layer 104 may be composed of the same semiconductor material as that of the bulk substrate layer 102 and having a similar crystalline structure. For example, the bulk substrate layer 102 and the etch-stop layer 104 may both substantially be comprised of monocrystalline silicon. That is, the etch-stop layer 104 may be composed of a material that is not chemically resistant, at least not to a significant extent, to a later-used chemically reactive substance, In such an embodiment, the etch-stop layer 104 has an electrical resistivity that increases away from the bulk substrate layer 102. The aforementioned may thus also apply to the etch-stop layer 104 in the first exemplary integrated circuit device 100 illustrated in FIG. 1.

[0028] The increase in electrical resistivity in the etch-stop layer 104 away from the bulk substrate layer 102 may be due to, for example, the etch-stop layer 104 having a dopant profile that varies with depth. Depth is a position between the front side 105 and the back side 106 along a dash-dotted line in FIG. 1, which is orthogonal to these two main sides. In case the etch-stop layer 104 and the bulk substrate layer 102 have dopants of the same polarity, the dopant profile may be determined by a dopant concentration that varies with depth. For example, let it be assumed that the etch-stop layer 104 is at least partially doped with a P-type dopant, like the bulk substrate layer 102. In the etch-stop layer 104, the P-type dopant may have a concentration that decreases with decreasing depth. That is, in the etch-stop layer 104, the concentration of the P-type dopant decreases away from the bulk substrate layer 102. The lower the concentration of the P-type dopant is at a given location in the etch-stop layer 104, the higher the electrical resistivity is at this location in the etch-stop layer 104. The aforementioned also applies when the etch-stop layer 104 and the bulk substrate layer 102 are both doped with an N-type dopant instead of a P-type dopant.

[0029] There are various manners to create a varying dopant profile in which the concentration of a dopant decreases away from the bulk substrate layer 102, thereby creating the etch-stop layer 104. For example, the basic substrate, or a partially processed version thereof, may undergo a thermal treatment while exposed to a suitable gas at a side corresponding to the front side 105. This will cause the dopant to leak out of the basic substrate, or the partially processed version thereof, at the side corresponding to the front side 105. As another example, the concentration of the dopant may be decreased away from the bulk substrate layer 102 by epitaxial deposition of semiconductor material that is less doped, or not doped at all, at least not significantly. As another example, the concentration of the dopant may be decreased away from the bulk substrate layer 102 by deposition of an adjacent layer that absorbs the dopant. Dopant absorption may especially occur during heating steps in manufacturing the second exemplary integrated circuit device 400 from the basic substrate.

[0030] Alternatively, the dopant profile in the etch-stop layer 104 may at least partially be obtained by introduction of a dopant having a polarity opposite to that in the aforementioned basic substrate in which the etch-stop layer 104 is formed, leaving the bulk substrate layer 102 as a remainder. For example, let it be assumed that the basic substrate is doped with a P-type dopant. The etch-stop layer 104 may then be formed, at least partially, by introduction of an N-type dopant in a portion of the basic substrate adjacent to that where the electrically insulating layer 103 lies. In an embodiment, which may differ somewhat from that illustrated in FIG. 1, the N-type dopant may be introduced in such a large quantity that an N-type zone is formed adjacent to a P-type zone. Between the N-type zone and the P-type zone, there is a zone where the electrical resistivity increases away from the bulk substrate layer 102. This zone then constitutes the etch-stop layer.

[0031] In this embodiment, the bulk substrate layer 102 comprises a zone 109 extending to the etch-stop layer 104 in which in the electrical resistivity decreases toward the etch-stop layer 104. This zone 109 will be referred to as the etch-stimulus zone 109 in correspondence with its function, which will be discussed hereinafter. In the etch-stimulus zone 109, the electrical resistivity may decrease toward the etch-stop layer 104 by at least an order of magnitude. The electrical resistivity may decrease by two orders of magnitude, or even more, depending on a desired result to be achieved, which will be described hereinafter. An appropriate amount by which the electrical resistivity decreases in the etchstimulus zone 109 may be empirically determined.

[0032] The etch-stimulus zone 109 may be at least 100 nm thick. Specifically, the etch-stimulus zone 109 may be at least 200 nm, 300 nm, 400 nm, or 500 nm thick. The etch-stimulus zone 109 may even be 1 pm thick, or even thicker. An appropriate thickness may depend on the desired result to be achieved. The appropriate thickness of the etchstimulus zone 109 may be empirically determined.

[0033] The decrease in electrical resistivity in the etch-stimulus zone 109 toward the etch-stop layer 104 may be due to, for example, the etch-stimulus zone 109 having a dopant profile that varies with depth. Specifically, in the etch-stimulus zone 109, the aforementioned P-type dopant may have a concentration that increases with decreasing depth. That is, in the etch-stimulus zone 109, the concentration of the P-type dopant increases toward the etch-stop layer 104. The higher the concentration of the P-type dopant is at a given location in the etch-stimulus zone 109 and, more generally, in the bulk substrate layer 102, the lower the electrical resistivity is at this location in the etch-stimulus zone 109 and, more generally, in the bulk substrate layer 102.

[0034] There are various manners to create a varying dopant profile that decreases the electrical resistivity toward the etch-stop layer 104. For example, the varying dopant profile may be created by means of ion implantation. The ion implementation may be carried out while manufacturing the basic substrate, or while manufacturing the integrated circuit device from the basic substrate, or both of these. Another manner to create a varying dopant profile is to incorporate a solid dopant source layer in the basic substrate, or a partially processed version thereof, during manufacturing of the integrated circuit device. The dopant source layer may comprise one or more suitable dopants, which may diffuse into the bulk substrate layer 102 due to, for example, heating that is applied in manufacturing the integrated circuit device. As another example, the dopant profile may be created by epitaxial deposition of a doped layer on top of the bulk substrate layer 102.

[0035] FIG. 2 schematically illustrates a dopant concentration in the first exemplary integrated circuit device 100 varying as a function of depth. FIG. 2 is a graph having a horizontal axis, which represents depth (d), and a vertical axis, which represents dopant concentration (D). A curve represents the dopant concentration varying as a function of depth over a depth range indicated in FIG. 1 by two arrows on the aforementioned dash- dotted line. This depth range includes the bulk substrate layer 102 and the etch-stop layer 104. The graph comprises three vertical sections. A middle section corresponds to the etchstimulus zone 109 in the bulk substrate layer 102. A relatively wide rightmost vertical section corresponds to a main portion of the bulk substrate layer 102 excluding the etchstimulus zone 109. A leftmost portion corresponds to the etch-stop layer 104.

[0036] The graph FIG. 2 shows that, in the etch-stop layer 104, the dopant concentration decreases away from the bulk substrate layer 102. In this embodiment, the dopant concentration may decrease monotonously and rather gradually as illustrated in this graph.

[0037] The graph of FIG. 2 further shows that, in the etch-stimulus zone 109, the dopant concentration increases toward the etch-stop layer 104. In this embodiment, the dopant concentration increases throughout almost the entire etch-stimulus zone 109, except for an insignificantly small portion where the bulk substrate layer 102 interfaces with the etch-stop layer 104. The dopant concentration may increase by at least an order of magnitude in the etch-stimulus zone 109. This implies that the vertical axis has a logarithmic scale rather than a linear scale, although the latter is not excluded FIG. 3 schematically illustrates the electrical resistivity in the first exemplary integrated circuit varying as a function of depth. FIG. 3 is a graph having a horizontal axis, which represents depth (d), and a vertical axis, which represents electrical resistivity (R). A curve represents the electrical resistivity varying as a function of depth over the depth range mentioned hereinbefore with regard to FIG. 2. The graph of FIG. 3 comprises the same three vertical sections as those in the graph of FIG. 2.

[0038] The graph of FIG. 3 shows that, in the etch-stop layer 104, the electrical resistivity increases away from the bulk substrate layer 102. In this example, the electrical resistivity increases rather monotonously and rather gradually throughout the etch-stop layer 104. This mirrors the decrease in dopant concentration in the etch-stop layer 104 away from the bulk substrate layer 102 illustrated in FIG. 2.

[0039] The graph of FIG. 3 further shows that, in the etch-stimulus zone 109, the electrical resistivity decreases toward the etch-stop layer 104. In this example, the electrical resistivity decreases throughout almost the entire etch-stimulus zone 109, except for an insignificantly small portion where the bulk substrate layer 102 interfaces with the etch-stop layer 104. This mirrors the variation in dopant concentration in the etch-stimulus zone 109 toward the etch-stop layer 104 as illustrated in FIG. 2. The electrical resistivity may decrease by at least an order of magnitude in the entire etch-stimulus zone 109, as mentioned hereinbefore. The electrical resistivity in the etch-stop layer 104 then increases. Like with FIG. 2, this implies that the vertical axis has a logarithmic scale rather than a linear scale, although the latter is not excluded.

[0040] FIG. 4 schematically illustrates a second exemplary integrated circuit device 400. FIG. 4 provides a schematic cross-sectional view of the second exemplary integrated circuit device 400. Basically, the second exemplary integrated circuit device 400 may be regarded as a modified version of the first exemplary integrated circuit device 100 in which the electrically insulating layer 103 has been omitted. Like elements are therefore denoted by like reference signs for the sake of simplicity and clarity. Like the first exemplary integrated circuit device 100, the second exemplary integrated circuit device 400 may be manufactured from a basic substrate of semiconductor material using conventional techniques. The further remarks made in this respect regarding the first exemplary integrated circuit device 100 may equally apply to the second exemplary integrated circuit device 400.

[0041] FIG. 5 illustrates an exemplary method 500 of processing an integrated circuit device 501, which may be the first exemplary integrated circuit device 100, or the second exemplary integrated circuit device 400, or another embodiment. FIG. 5 provides a flow chart diagram of the exemplary method 500, which comprises several steps 502, 503. The method 500 is applied to a wafer 504 of which the integrated circuit device 501 is a part. The wafer 504 may include further integrated circuit devices 505, which may be identical to the aforementioned integrated circuit device 501. The method 500 illustrated in FIG. 5 may be based on a technique that is described in patent publication US11538689 cited hereinbefore.

[0042] In FIG. 5, a very schematic cross-sectional view of the wafer 504 is provided by way of illustration. The wafer 504 has a front side 506 and a back side 507, which encompass a front side and a back side, respectively, of the integrated circuit device 501. Thus, the front side 506 and the back side 507 of the wafer 504 encompass the front side 105 and the back side 106 of the first exemplary integrated circuit device 100, or of the second exemplary integrated circuit device 400, whichever constitutes the integrated circuit device 501.

[0043] In this example, the back side 507 of the wafer 504 is provided with an etchresistant mask 508, which may have an open-grid pattern. The etch-resistant mask 508 defines exposed zones on the back side 507 of the wafer 504. Accordingly, the integrated circuit device 501 has an exposed zone 509 on its back side. The back side 507 of the wafer 504 is further provided with a peripheral electrode 510, which may be in the form of a ring. The peripheral electrode 510 may have been formed by deposition of a conductive material, which may be a metal, such as, for example, aluminum.

[0044] In a first step 502, the back side 507 of the wafer 504 is brought into contact with a chemically reactive substance 511. The chemically reactive substance 511 may comprise, for example, hydrofluoric acid. The chemically reactive substance 511 may be contained in a container 512. The container 512 may have a size and shape that allows placing the container 512 within the peripheral electrode 510 as illustrated in FIG. 5. The exposed zone 509 on the back side of the integrated circuit device 501 is in contact with the chemically reactive substance 511. In contrast, peripheral zones on the back side of the integrated circuit device 501 may not be in contact with the chemically reactive substance 511 due to the presence of the etch resisting mask mentioned hereinbefore.

[0045] In a second step 503, an electrical current 513 is made to flow through the wafer 504 and the chemically reactive substance 511. Specifically, the electrical current 513 flows from the peripheral electrode 510 to the exposed zones on the back side 507 of the wafer 504, in a lateral direction, and then to another electrode 514 that is present in the chemically reactive substance 511. Focusing on the integrated circuit device 501, the electrical current 513 thus flows in a lateral direction through the exposed zone 509 on the back side into the chemically reactive substance 511 toward the electrode 514 in the chemically reactive substance 511. In this example, the peripheral electrode 510 may be regarded as constituting an anode, whereas the electrode 514 in the chemically reactive substance 511 constitutes a cathode.

[0046] The case where the first exemplary integrated circuit device 100 constitutes the integrated circuit device 501 in the wafer 504 is now discussed, with reference to both FIGS. 1 and 5. The electrical current 513 flows in a lateral direction through the bulk substrate layer 102 and then into the chemically reactive substance 511 passing through the exposed zone 509 on the back side 106. The electrical current 513 causes the chemically reactive substance 511 to alter the bulk substrate layer 102 starting from the exposed zone 509 toward the etch-stop layer 104. Specifically, this electrochemically-induced alteration of the bulk substrate layer 102 may consist in creation of pores. That is, pores may be created starting from the back side 106 up to the etch-stop layer 104. The pores are created within a region having a lateral cross-section that is substantially determined by the exposed zone 509.

[0047] The etch-stop layer 104 is capable of stopping a process of pore creation because the electrical resistivity in this layer increases away from the bulk substrate layer 102. This prevents the electrical current 513 from flowing in the etch-stop layer 104 or, at least, significantly weakens the electrical current 513 at this point. The absence, or the significant weakening, of the electrical current 513 in the etch-stop layer 104 by itself may thus stop the pore creation process, even if the etch-stop layer 104 is not chemically resistant to the chemically reactive substance 511.

[0048] Accordingly, there is no need for a chemically resistant layer to stop an electrochemically-induced process of altering the bulk substrate layer 102 at a desired depth. Incorporating a chemically resistant layer, such as, for example, a high electrical resistivity polysilicon layer or an aluminum nitride layer, in an integrated circuit device is relatively expensive. An embodiment in which the etch-stop layer 104 has an electrical resistivity that increases away from the bulk substrate layer 102 offers thus an additional advantage, namely a cost advantage. The etch-stop layer 104 may be composed of the same semiconductor material as that of the bulk substrate layer 102 and having a similar crystalline structure, such as, for example, monocrystalline silicon. The etch-stimulus zone 109 in the bulk substrate layer 102 discussed hereinbefore allows maintaining the creation of pores when this process comes relatively close to the etch-stop layer 104. The decrease in electrical resistivity in this zone towards the etch-stop layer 104 prevents the electrical current 513 from becoming too weak in a relatively thin region of the bulk substrate layer 102 in which pores have not yet been created. This allows the creation of pores to continue relatively close to the etch-stop layer 104, while otherwise the creation of pores might have already stopped.

[0049] Accordingly, if there is any residual nonporous sublayer remaining in the bulk substrate layer 102 at the end of the method 500 illustrated in FIG. 5, this residual nonporous sublayer will be relatively thin. Moreover, the residual nonporous sublayer will have a substantially uniform thickness. Accordingly, since the bulk substrate layer 102 can be made porous to a greater extent in the vicinity of the electrical circuit 108, the electrical circuit 108 may achieve better performance as discussed hereinbefore.

[0050] FIG. 6 illustrates a processed integrated circuit device 600 that may be obtained by applying the method 500 illustrated in FIG. 5 to the first exemplary integrated circuit device 100 illustrated in FIG. 1. FIG. 6 provides a schematic cross-sectional view of the processed integrated circuit device 600. The processed integrated circuit device 600 corresponds to the first exemplary integrated circuit device 100 in which a region 601 in the bulk substrate layer 102 has been made porous. This porous bulk substrate region 601 underlies the electrical circuit 108. The porous bulk substrate region 601 extends from the back side 106 to the etch-stop layer 104, leaving only a relatively thin residual nonporous sublayer, if any, just underneath the etch-stop layer 104. The porous bulk substrate region 108 may have a lateral cross-section that is substantially determined by the exposed zone 509 illustrated in FIG. 5, discussed hereinbefore.

[0051] The remarks made hereinbefore regarding the case where the first exemplary integrated circuit device 100 constitutes the integrated circuit device 501, equally apply to the case where the second exemplary integrated circuit device 400 constitutes the integrated circuit device 501 in the wafer 504. Namely, both these embodiments, as well as other embodiments, are characterized by the following. A layer that is chemically resistant to the chemically reactive substance is absent between the bulk substrate layer 102 and the functional layer 101. Providing an integrated circuit with an etch-stop layer that is chemically resistant is relatively expensive. As discussed, there is no need for such an expensive etch-stop layer. In the embodiments presented hereinbefore an etch-stop effect is obtained in the etch-stop layer 104 by the electrical resistivity increasing therein away from the bulk substrate layer 102. These embodiments, as well as other embodiments that have a similar etch-stop layer, therefore allow a more cost-effective electrochemical alteration of a bulk substrate in an integrated circuit device.

[0052] NOTES

[0053] The embodiments described hereinbefore with reference to the drawings are presented by way of illustration. The invention may be implemented in numerous different ways. In order to illustrate this, some alternatives are briefly indicated.

[0054] The invention may be applied in numerous types of products or methods related to electrochemically altering a substrate. The embodiments presented hereinbefore concern an electrochemical alteration that creates pores in a substrate. However, the invention may be applied to advantage in other types of electrochemical alteration, such as, for example, etching away a part of the substrate.

[0055] There are numerous different ways of implementing an integrated circuit device in accordance with the invention. There are many possible embodiments different from those presented hereinbefore. For example, embodiments may comprise one or more additional layers. The etch-stop layer need not span the entire width of an integrated circuit device, but may be locally present between the bulk substrate layer and another layer. This other layer need not be an electrically insulating layer. Moreover, in the presented embodiments, the bulk substrate layer comprises a so-called etch stimulus zone in which the electrical resistivity decreases toward the etch-stop layer. In other embodiments, the bulk substrate layer need not comprise such an etch stimulus zone; resistivity in the bulk substrate may be essentially constant up to the etch-stop layer.

[0056] There are numerous different ways of implementing a zone in a bulk substrate layer extending to an etch-stop layer, in which electrical resistivity increases away from the bulk substrate layer. In the presented embodiments, this is essentially achieved by doping. In other embodiments, this may be achieved by, for example, modulating the carrier concentration or the carrier mobility, or both. The carrier mobility can be modulated by, for example, introducing trap states in the semiconductor material. Trap states may result from impurities that create energy states deep in the band gap or by some form of compensation doping. Another way to modulate carrier concentration or mobility, or both, mobility, consists in modifying the number of crystal imperfections, so- called defects, or by introducing strain in a semiconductor crystal lattice, or by including a material with a different band gap energy. The remarks made hereinbefore demonstrate that the embodiments described with reference to the drawings illustrate the invention, rather than limit the invention. The invention can be implemented in numerous alternative ways that are within the scope of the appended claims. All changes that come within the meaning and range of equivalency of the claims are to be embraced within their scope. Any reference sign in a claim should not be construed as limiting the claim. The verb “comprise” in a claim does not exclude the presence of other elements or other steps than those listed in the claim. The same applies to similar verbs such as “include” and “contain”. The mention of an element in singular in a claim pertaining to a product, does not exclude that the product may comprise a plurality of such elements. Likewise, the mention of a step in singular in a claim pertaining to a method does not exclude that the method may comprise a plurality of such steps. The mere fact that respective dependent claims define respective additional features, does not exclude combinations of additional features other than those reflected in the claims.

Claims

CLAIMS:

1. A method (500) of processing an integrated circuit device (100, 400) comprising: a functional layer (101) comprising an electrical circuit (108); a bulk substrate layer (102) of semiconductor material; and an etch-stop layer (104) between the functional layer and the bulk substrate layer, the etch-stop layer contacting the bulk substrate layer, the method comprising: electrochemically treating (503) at least part of the bulk substrate layer (102) by bringing an external surface (107) of the bulk substrate layer into contact with a chemically reactive substance (511) and passing an electrical current (513) through the chemically reactive substance and the bulk substrate layer, thereby electrochemically altering the bulk substrate layer starting from the external surface toward the etch-stop layer (104), whereby, in the integrated circuit device: a layer that is chemically resistant to the chemically reactive substance is absent between the bulk substrate layer and the functional layer; and the etch-stop layer has an electrical resistivity (R) that increases away from the bulk substrate layer.

2. A method of processing an integrated circuit device according to claim 1, whereby, in the integrated circuit device (100, 400), the etch-stop layer (104) is composed of the same semiconductor material as that of the bulk substrate layer (102) and has a similar crystalline structure.

3. A method of processing an integrated circuit device according to any of claims 1 and 2, whereby, in the integrated circuit device (100, 400), the etch-stop layer (104) has a dopant profile that varies with depth (d).

4. A method of processing an integrated circuit device according to claim 3, whereby, in the integrated circuit device(100, 400), the dopant profile is at least partially determined by the etch-stop layer (104) and the bulk substrate layer (102) having dopants of opposite polarity.

5. A method of processing an integrated circuit device according to any of claims 1 to 4, whereby the integrated circuit (100, 400) comprises: an electrically insulating layer (103) between the functional layer and the etch-stop layer (104).

6. A method of processing an integrated circuit device according to any of claims 1 to 5, whereby, in the integrated circuit device (100, 400), the bulk substrate layer (102) comprises a zone (109) extending to the etch-stop layer (104), in which electrical resistivity (R) decreases toward the etch-stop layer.

7. A method of processing an integrated circuit device according to claim 6, whereby, in the integrated circuit device (100, 400), the zone (109) in the bulk substrate layer (102) in which the electrical resistivity (R) decreases is at least 100 nm thick.

8. A method of processing an integrated circuit device according to any of claims 6 and 7, whereby, in the integrated circuit device, (100, 400) the electrical resistivity (R) in the zone (109) in the bulk substrate layer (102) decreases by at least an order of magnitude toward the etch-stop layer (104).

9. A method of processing an integrated circuit device according to any of claims 6 to 8 whereby, in the integrated circuit device (100, 400), the zone (109) in the bulk substrate layer (102) has a dopant profile that varies with depth (d).

10. A method of processing an integrated circuit device according to any of claims 1 to 9, wherein the electrical current (513) passes through the bulk substrate layer (102) at least partially in a lateral direction.

11. A method of processing an integrated circuit device according to any of claims 1 to 10, wherein the integrated circuit device (100, 400) forms part of a wafer (504)comprising further integrated circuit devices (505) having the same features, the electrochemically treating (503) being applied jointly to the integrated circuit device and the further integrated circuit devices as part of the wafer.

12. A method of processing an integrated circuit device according to any of claims 1 to 11, wherein electrochemically altering the bulk substrate layer (102) comprises creation of pores in the bulk substrate layer.

13. A processed integrated circuit device (600) obtained by applying the method (500) of processing according to claim 12, the bulk substrate layer (102) in the processed integrated circuit device (600) being porous at least in a region (601) extending between the external surface (107) and the etch-stop layer (104) and underlying the electrical circuit (108) in the functional layer (102).

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