Semiconductor device

Abstract

Provided is a semiconductor device with a high operating speed. The semiconductor device includes first to third cells. The first cell has the function of holding a first potential corresponding to first data, the function of drawing a first current, corresponding to the first potential, from first wiring, and the function of drawing a second current, corresponding to the product of the first data and second data, from the first wiring by changing the potential of second wiring according to the second data. The second cell has the function of holding a second potential corresponding to reference data, the function of drawing a third current, corresponding to the second potential, from the second wiring, and the function of changing the third current flowing in the second wiring to a fourth current corresponding to the second data by changing the potential of the second wiring in response to a change from the reference data to the second data. The third cell has the function of holding a third potential corresponding to the product of the first data and the second data, and the function of supplying a fifth current corresponding to the third potential to the first wiring or third wiring.

Description

Semiconductor Devices

[0001] One embodiment of the present invention relates to a semiconductor device.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. The technical field of the invention disclosed in this specification relates to an object, an operating method, or a manufacturing method. Alternatively, one embodiment of the present invention relates to a process, a machine, manufacture, or a composition of matter. Therefore, specific examples of the technical field of one embodiment of the present invention disclosed in this specification include semiconductor devices, display devices (including liquid crystal display devices), light-emitting devices, power storage devices, imaging devices, memory devices, processing devices, signal processing devices, sensors, arithmetic devices (including processors), electronic devices, systems, driving methods thereof, manufacturing methods thereof, and inspection methods thereof.

[0003] Currently, the development of integrated circuits that mimic the workings of the human brain is actively progressing. Such integrated circuits incorporate the workings of the brain as electronic circuits, and have circuits that mimic the "neurons" and "synapses" of the human brain. For this reason, such integrated circuits are sometimes called "neuromorphic," "brainmorphic," or "brain-inspired." Such integrated circuits have a non-von Neumann architecture, and are expected to be able to perform parallel processing with extremely low power consumption, compared to von Neumann architectures, which consume more power as processing speed increases.

[0004] An information processing model that mimics a neural network having "neurons" and "synapses" is called an artificial neural network (ANN). For example, Non-Patent Documents 1 and 2 disclose a computing device that configures an artificial neural network using an SRAM (Static Random Access Memory).

[0005] As an example of a computing device that configures an artificial neural network, Patent Document 1 discloses a computing device including a multiplication cell that performs multiplication using a current flowing in the subthreshold region of a transistor. Patent Document 1 also discloses a method for adjusting weighting coefficients to correct variations in the computation results.

[0006] JP 2024-65044 A

[0007] M. Kang et al., "IEEE Journal of Solid-State Circuits", 2018, Volume 53, No. 2, pp. 642-655. J. Zhang et al., "IEEE Journal of Solid-State Circuits", 2017, Volume 52, No. 4, pp. 915-924. Takashi Koida, "High-Mobility Transparent Conductive Film", National Institute of Advanced Industrial Science and Technology, AIST Photovoltaic Power Generation Research Results Report 2019, Internet <URL: https: / / unit.aist.go.jp / jp / rpd-envene / PV / ja / results / 2019 / oral / T13. pdf>

[0008] An example of an arithmetic device that configures an artificial neural network is an arithmetic device described in Patent Document 1, which performs a product-sum operation by adding analog currents corresponding to the products of weighting coefficients and input data. Because this arithmetic device uses analog currents for calculations, the circuit scale and circuit area can be smaller than those of arithmetic devices configured with digital circuits. Furthermore, by designing this arithmetic device to reduce the analog currents used in the calculations, the power consumption of the arithmetic device can be reduced.

[0009] The above-mentioned arithmetic device may have, for example, a configuration having a cell array in which arithmetic cells are arranged in a matrix, each of which multiplies a weighting factor by input data and outputs the result of the multiplication as an analog current. By configuring the arithmetic cells arranged in a column in this way to add up the analog currents output from the arithmetic cells, the amount of the added up analog current can be treated as the value resulting from a product-sum operation of the weighting factor and the input data.

[0010] On the other hand, when the analog current used in the calculation is reduced, the amount of charge accumulated per unit time in the wiring that carries the analog current decreases, and it may take time to change the potential of the wiring to the desired potential. For this reason, a calculation device that performs product-sum calculations using a small analog current is required to have a configuration that can achieve a high driving speed.

[0011] An object of one embodiment of the present invention is to provide a semiconductor device with high driving speed.An object of one embodiment of the present invention is to provide a semiconductor device with reduced power consumption.An object of one embodiment of the present invention is to provide a semiconductor device with a reduced circuit area.An object of one embodiment of the present invention is to provide a novel semiconductor device.An object of one embodiment of the present invention is to provide an electronic device including the above-described semiconductor device.

[0012] Note that the problem of one embodiment of the present invention is not limited to the above problem. The above problem does not preclude the existence of other problems. Note that the other problems are problems not mentioned in this section, which will be described below. Problems not mentioned in this section can be derived by a person skilled in the art from the description in the specification or drawings, and can be appropriately extracted from these descriptions. Note that one embodiment of the present invention solves at least one of the above problem and other problems, and does not necessarily solve all of the above problem and other problems.

[0013] As described above, if the amount of charge accumulated per unit time in a wiring that carries an analog current is small, it may take a long time to change the potential of the wiring to the desired potential. In particular, the longer the wiring, the longer the time required because the parasitic capacitance included in the wiring increases.

[0014] For this reason, in a cell array in which arithmetic cells capable of performing multiplication are arranged in a matrix, it is preferable that the wiring through which the analog current flows can be divided as necessary, and that the divided wirings be configured to be controlled to be conductive or non-conductive by a switch circuit or the like.

[0015] A structural example of a semiconductor device according to one embodiment of the present invention in which the wiring can be divided will be described below.

[0016] (1) One aspect of the present invention is a semiconductor device including a first cell, a second cell, and a third cell. The first cell has a function of holding a first potential corresponding to first data, a function of passing a first current corresponding to the first potential between the first cell and a first wiring, and a function of passing a second current corresponding to a product of the first data and the second data between the first cell and the first wiring by changing the potential of the second wiring in accordance with the second data. The second cell has a function of holding a second potential corresponding to reference data, a function of passing a third current corresponding to the second potential between the second cell and the second wiring, and a function of changing the third current flowing between the second cell and the second wiring to a fourth current corresponding to the second data by changing the potential of the second wiring in accordance with the change from the reference data to the second data. In addition, the third cell has a function of holding a third potential corresponding to the product of the first data and the second data, and a function of passing a fifth current corresponding to the third potential between the third cell and the first wiring or the third wiring.

[0017] (2) Alternatively, in one aspect of the present invention, in the above (1), the third cell may include a first transistor, a second transistor, a third transistor, a fourth transistor, and a first capacitor. In particular, the first transistor, the third transistor, and the fourth transistor are preferably n-channel transistors, and the second transistor is preferably a p-channel transistor.

[0018] One of the source and drain of the first transistor is preferably electrically connected to the gate of the second transistor and the first terminal of the first capacitor. The other of the source and drain of the first transistor, one of the source and drain of the second transistor, one of the source and drain of the third transistor, and one of the source and drain of the fourth transistor are preferably electrically connected to one another. The other of the source and drain of the third transistor is preferably electrically connected to the first wiring, and the other of the source and drain of the fourth transistor is preferably electrically connected to the third wiring.

[0019] (3) Alternatively, in one embodiment of the present invention, in the above-described (2), a gate of the first transistor and a gate of the third transistor may be electrically connected to a fourth wiring.

[0020] (4) Alternatively, in one embodiment of the present invention, in the above-described (2), the third cell may include a fifth transistor that is an n-channel transistor. In particular, it is preferable that one of a source or a drain of the fifth transistor is electrically connected to the other of the source or the drain of the first transistor, the one of the source or the drain of the second transistor, the one of the source or the drain of the third transistor, and the one of the source or the drain of the fourth transistor.

[0021] (5) In another aspect of the present invention, in the above (1), the third cell may include a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a first capacitor. In particular, the first transistor, the fourth transistor, and the fifth transistor are preferably n-channel transistors, and the second transistor and the third transistor are preferably p-channel transistors.

[0022] One of the source or drain of the first transistor is preferably electrically connected to the gate of the second transistor and the first terminal of the first capacitor. Also, one of the source or drain of the second transistor is preferably electrically connected to one of the source or drain of the third transistor. Also, the other of the source or drain of the first transistor, the other of the source or drain of the third transistor, one of the source or drain of the fourth transistor, and one of the source or drain of the fifth transistor are preferably electrically connected to one another. Also, the other of the source or drain of the fourth transistor is preferably electrically connected to the first wiring, and the other of the source or drain of the fifth transistor is preferably electrically connected to the third wiring.

[0023] (6) Alternatively, in one embodiment of the present invention, in the above-described (5), a gate of the first transistor and a gate of the fourth transistor may be electrically connected to a fourth wiring.

[0024] (7) Alternatively, in one embodiment of the present invention, in the above-described (5), the third cell may include a sixth transistor that is an n-channel transistor. In particular, it is preferable that one of a source or a drain of the sixth transistor is electrically connected to the other of the source or the drain of the first transistor, the other of the source or the drain of the third transistor, the one of the source or the drain of the fourth transistor, and the one of the source or the drain of the fifth transistor.

[0025] (8) In another embodiment of the present invention, in any one of (2) to (7), the first cell may include a seventh transistor, an eighth transistor, and a second capacitor, and the second cell may include a ninth transistor, a tenth transistor, and a third capacitor. In particular, each of the seventh to tenth transistors is preferably an n-channel transistor.

[0026] One of the source or drain of the seventh transistor is preferably electrically connected to the gate of the eighth transistor and the first terminal of the second capacitor. Also, one of the source or drain of the ninth transistor is preferably electrically connected to the gate of the tenth transistor and the first terminal of the third capacitor. Also, the other of the source or drain of the seventh transistor and one of the source or drain of the eighth transistor are preferably electrically connected to a first wiring. Also, the other of the source or drain of the ninth transistor, one of the source or drain of the tenth transistor, the second terminal of the second capacitor, and the second terminal of the third capacitor are preferably electrically connected to a second wiring. Also, the gate of the seventh transistor and the gate of the ninth transistor are preferably electrically connected to a fifth wiring.

[0027] (9) In another embodiment of the present invention, in the above (6), the n-channel transistor may have a channel formation region formed of an oxide semiconductor, and the p-channel transistor may have a channel formation region formed of silicon. In particular, the oxide semiconductor preferably contains an oxide containing indium.

[0028] (10) Alternatively, according to one aspect of the present invention, in the above (9), the device may include a first drive circuit, a second drive circuit, and a third drive circuit. In particular, the first drive circuit preferably has a function of causing a current corresponding to first data to flow through the first wiring, the second drive circuit preferably has a function of causing a current corresponding to reference data or second data to flow through the second wiring, and the third drive circuit preferably has a function of calculating a function into which a value corresponding to the amount of current flowing through the third wiring is substituted and outputting the calculation result of the function.

[0029] (11) Alternatively, according to one embodiment of the present invention, in any one of (2) to (7), the first cell may include a seventh transistor, an eighth transistor, a ninth transistor, and a second capacitor, and the second cell may include a tenth transistor, an eleventh transistor, a twelfth transistor, and a third capacitor. In particular, each of the seventh to twelfth transistors is preferably an n-channel transistor.

[0030] One of the source or drain of the seventh transistor is preferably electrically connected to the gate of the eighth transistor and the first terminal of the second capacitor. Also, one of the source or drain of the eighth transistor is preferably electrically connected to one of the source or drain of the ninth transistor. Also, one of the source or drain of the tenth transistor is preferably electrically connected to the gate of the eleventh transistor and the first terminal of the third capacitor. Also, one of the source or drain of the eleventh transistor is preferably electrically connected to one of the source or drain of the twelfth transistor. Also, the other of the source or drain of the seventh transistor and the other of the source or drain of the ninth transistor are preferably electrically connected to a first wiring. Also, the other of the source or drain of the tenth transistor, the other of the source or drain of the twelfth transistor, the second terminal of the second capacitor, and the second terminal of the third capacitor are preferably electrically connected to a second wiring. Also, the gate of the seventh transistor and the gate of the tenth transistor are preferably electrically connected to a fifth wiring.

[0031] (12) In another embodiment of the present invention, in the above (11), the n-channel transistor may have a channel formation region formed of an oxide semiconductor, and the p-channel transistor may have a channel formation region formed of silicon. In particular, the oxide semiconductor preferably contains an oxide containing indium.

[0032] (13) Alternatively, according to one aspect of the present invention, in the above (12), the device may further include a first drive circuit, a second drive circuit, and a third drive circuit. In particular, the first drive circuit preferably has a function of causing a current corresponding to first data to flow through the first wiring, the second drive circuit preferably has a function of causing a current corresponding to reference data or second data to flow through the second wiring, and the third drive circuit preferably has a function of calculating a function using a value corresponding to the amount of current flowing through the third wiring as an input value and outputting the calculation result of the function.

[0033] By using the above configurations (1) to (13) as an arithmetic circuit, the wiring through which the analog current flows can be divided according to the situation. The divided wiring can reduce the parasitic capacitance, thereby shortening the time required to change the potential of the wiring to the required potential. This can increase the driving speed of the semiconductor device.

[0034] According to one embodiment of the present invention, a semiconductor device with high driving speed can be provided. According to one embodiment of the present invention, a semiconductor device with reduced power consumption can be provided. According to one embodiment of the present invention, a semiconductor device with a reduced circuit area can be provided. According to one embodiment of the present invention, a novel semiconductor device can be provided. According to one embodiment of the present invention, an electronic device including the above-described semiconductor device can be provided.

[0035] Note that the effects of one embodiment of the present invention are not limited to the above-described effects. The above-described effects do not preclude the existence of other effects. Furthermore, the other effects are effects not mentioned in this section, which will be described below. Effects not mentioned in this section can be derived by a person skilled in the art from the description in the specification or drawings, and can be extracted as appropriate from these descriptions. Note that one embodiment of the present invention has at least one of the above-described effects and other effects. Therefore, one embodiment of the present invention may not have the effects listed above in some cases.

[0036] FIG. 1 is a block diagram showing an example of the configuration of a arithmetic device. FIG. 2 is a circuit diagram showing an example of the configuration of a arithmetic device. FIG. 3 is a timing chart showing an example of the operation of the arithmetic device. FIG. 4 is a circuit diagram showing an example of the configuration of a arithmetic device. FIG. 5 is a circuit diagram showing an example of the configuration of a arithmetic device. FIG. 6 is a block diagram showing an example of the configuration of a arithmetic device. FIG. 7 is a circuit diagram showing an example of the configuration of a arithmetic device. FIG. 8 is a circuit diagram showing an example of the configuration of a arithmetic device. FIGS. 9A, 9B, and 9C are timing charts showing an example of the operation of the arithmetic device. FIG. 10 is a block diagram showing an example of the configuration of a arithmetic device. FIG. 11 is a circuit diagram showing an example of the configuration of a arithmetic device. FIG. 12 is a circuit diagram showing an example of the configuration of a arithmetic device. FIGS. 13A, 13B, and 13C are timing charts showing an example of the operation of the arithmetic device. FIG. 14 is a block diagram showing an example of the configuration of a arithmetic device. FIG. 15 is a circuit diagram showing an example of the configuration of a circuit included in the arithmetic device. FIG. 16 is a circuit diagram showing an example of the configuration of a circuit included in the arithmetic device. FIG. 17 is a circuit diagram showing an example of the configuration of a circuit included in the arithmetic device. 18A and 18B are planar schematic diagrams showing an example of a circuit included in a computing device. FIG. 19 is a cross-sectional schematic diagram showing an example of the configuration of the computing device. FIG. 20 is a cross-sectional schematic diagram showing an example of the configuration of a transistor included in the computing device. FIGS. 21A and 21B are cross-sectional schematic diagrams showing an example of the configuration of a transistor included in the computing device. FIG. 22A is a planar schematic diagram showing an example of the configuration of a transistor included in the computing device, and FIGS. 22B and 22C are cross-sectional schematic diagrams showing an example of the configuration of a transistor included in the computing device. FIG. 23 is a perspective schematic diagram showing an example of the configuration of a transistor included in the computing device. FIGS. 24A and 24B are diagrams explaining the carrier concentration dependence of Hall mobility. FIG. 24C is a cross-sectional diagram explaining an indium oxide film. FIGS. 25A, 25B, 25C, and 25D are diagrams showing an example of an electronic component. FIG. 26 is a diagram showing an example of an information processing system. FIG. 27 is a diagram showing an example of space equipment. FIG. 28 is a diagram showing an example of a storage system applicable to a data center.29A1, 29A2, 29A3, 29A4, 29A5, 29A6, 29A7 and 29B1, 29B2, 29B3, 29B4, 29B5, and 29B6 are circuit diagrams for explaining electrical connections.

[0037] (Additional Notes Related to the Present Specification) In the present specification, a semiconductor device is a device that utilizes semiconductor characteristics, and refers to a circuit including a semiconductor element (for example, a transistor, a diode, and a photodiode), or a device having such a circuit. A semiconductor device also refers to any device that can function by utilizing semiconductor characteristics. An example of a semiconductor device is an integrated circuit. Another example of a semiconductor device is a chip equipped with an integrated circuit. Another example of a semiconductor device is an electronic component that houses a chip in a package. For example, a memory device, a display device, a light-emitting device, a lighting device, and an electronic device may themselves be a semiconductor device, or may include a semiconductor device.

[0038] In this specification, "connection" includes, for example, "electrical connection."

[0039] When the term "electrical connection" is used to define the connection relationship between circuit elements as an object, it includes, for example, "direct connection" and "indirect connection." For example, "A and B are directly connected" refers to a connection between A and B without the intervention of a circuit element (e.g., a transistor or a switch; wiring is not considered a circuit element). On the other hand, for example, "A and B are indirectly connected" refers to a connection between A and B via one or more circuit elements. Note that A, B, and C, which will be described later, represent objects such as elements, circuits, wiring, electrodes, terminals, semiconductor layers, and conductive layers.

[0040] Here, when "A and B are indirectly connected," it refers to the following connection relationship, for example. That is, assuming that a circuit is operating, if there is a time during the operation of the circuit when electrical signal transmission or potential interaction occurs between A and B, such a circuit can be defined as an entity, and "A and B are indirectly connected." Note that even if there is a time when electrical signal transmission or potential interaction does not occur between A and B, if there is a time during the operation of the circuit when electrical signal transmission or potential interaction occurs between A and B, it can be defined as "A and B are indirectly connected." Note that "A and B are indirectly connected" is a definition of the connection relationship between circuit elements as an entity. Therefore, for example, even when a power supply voltage is not supplied to a circuit and the circuit is not operating, the circuit can be defined as "A and B are indirectly connected" (however, for example, this is limited to the case where electrical signal transmission or potential interaction occurs between A and B during the operation of the circuit when a power supply voltage is supplied to the circuit and the circuit is operating).

[0041] Specific examples of "indirect connection" are shown below. First, an example of "A and B are indirectly connected" is when A and B are connected via the source and drain of one or more transistors, as shown in FIGS. 29A1 and 29A2. Another example of "A and B are indirectly connected" is when A and B are connected via one or more switches. When "A and B are indirectly connected," it is assumed that, assuming the circuit is operating, there is at least one time when one transistor between A and B is in an on state, a conductive state, or a state in which current can flow. Note that "A and B are indirectly connected" also includes cases where one transistor between A and B is in an off state or a non-conductive state. When "A and B are indirectly connected," if multiple transistors are connected between A and B, it is assumed that, assuming the circuit is operating, each of the multiple transistors between A and B is in an on state, a conductive state, or a state in which current can flow. In other words, when "A and B are indirectly connected," it is not necessary for all of the multiple transistors to be in an on state, a conductive state, or a state in which current can flow simultaneously. Therefore, when "A and B are indirectly connected," it also includes cases in which the multiple transistors between A and B are in an off state or a non-conductive state at the same time or at different times. As another example, as shown in FIG. 29A3, when A and C are connected via the source and drain of transistor TrP and B and C are connected via the source and drain of transistor TrQ, it can be defined as "A and C are indirectly connected," "B and C are indirectly connected," or "A and B are indirectly connected." However, as will be described later, when a constant potential V is supplied to C from a power supply, GND, or the like, it can be said that "A and C are indirectly connected" or "B and C are indirectly connected," but it cannot be said that "A and B are indirectly connected."

[0042] While we have provided examples of cases where an "indirect connection" can and cannot be established, we will now present another example of a case where an "indirect connection" cannot be established. Even if an electrical signal exchange or potential interaction occurs between A and B during the operation of the circuit, there are exceptional cases where it cannot be said that "A and B are indirectly connected." An example of such an exceptional case is when A and B are connected via an insulator. In other words, when A and B are connected via an insulator, it cannot be said that "A and B are indirectly connected." A specific example of a case where A and B are connected via an insulator is when a capacitive element is connected between A and B, as shown in FIG. 29A4. Another example of a case where A and B are connected via an insulator is when a gate insulating film of a transistor is interposed between A and B, as shown in FIG. 29A5. In this case, it cannot be said that "A (the gate of the transistor) and B (the source or drain of the transistor) are indirectly connected."

[0043] Another example of a case where it cannot be said that "A and B are indirectly connected" is a case where there is no timing when an electrical signal is exchanged or when potential interaction occurs between A and B. An example of this is when, as shown in Figures 29A6 and 29A7, multiple transistors are connected via their sources and drains to the path from A to B, and a constant potential V is supplied to a node between the transistors from a power supply, GND, or the like. In this case, it cannot be said that "A and B are indirectly connected," but it is possible to say that "A and V are indirectly connected" or "B and V are indirectly connected." In addition, in Figure 29A3, if A and C are connected via the source and drain of transistor TrP, and B and C are connected via the source and drain of transistor TrQ, and a constant potential V is supplied to C from a power supply or GND, the connection relationship will be the same as in Figures 29A6 and 29A7, so it cannot be said that "A and B are indirectly connected," but it can be said that "A and C are indirectly connected," or "B and C are indirectly connected."

[0044] Although an example of "indirect connection" has been given above, as an example, the provision of "indirect connection" is included in the provision of "electrical connection," so when "A and B are indirectly connected," it can also be said that "A and B are electrically connected."

[0045] Next, specific examples of "direct connection" are shown. Examples of "A and B are directly connected" include cases where A and B are connected without any circuit element between them, as shown in FIGS. 29B1, 29B2, and 29B3. When A and B are connected to a power supply that supplies a constant potential V or to GND without any circuit element between them, as shown in FIGS. 29B4 and 29B5, it can be said that "A and B are directly connected," "A and V are directly connected," or "B and V are directly connected." It can also be said that "A and B are directly connected," when A (or B) is connected to a constant potential V via the source and drain of a transistor, as shown in FIG. 29B6. Because A and V or B and V are connected via the source and drain of a transistor, they cannot be said to be directly connected, but rather that "A and V are indirectly connected" or "B and V are indirectly connected."

[0046] Although an example of "direct connection" has been given above, as an example, the definition of "direct connection" is included in the definition of "electrical connection," so when "A and B are directly connected," it can also be said that "A and B are electrically connected."

[0047] Even when independent components are shown connected to each other in a circuit diagram, a single component may have the functions of multiple components. For example, if a portion of a "wiring" also functions as an "electrode," a single conductive film has both the functions of a "wiring" and an "electrode." Furthermore, if a portion of a "wiring" also functions as a "terminal," a single conductive film has both the functions of a "wiring" and a "terminal." Therefore, two or more selected from "electrode," "wiring," and "terminal" may be said to be integrally formed with each other. Furthermore, the terms "electrode," "wiring," and "terminal" may be replaced with the term "region" in some cases. Therefore, the term "connection" in this specification also includes cases in which a single conductive film has the functions of multiple components.

[0048] The switches described in this specification are described as having the function of being turned on or off and controlling whether or not a current flows, or as having the function of selecting and switching the path through which a current flows.

[0049] In this specification, a "conductive state" refers to a state in which a current can flow between two input / output terminals, and a "non-conductive state" refers to a state in which the two input / output terminals are considered to be electrically disconnected. In this specification, the on state of a switch falls under the category of a "conductive state," and the off state of a switch falls under the category of a "non-conductive state." Therefore, in this specification, the "conductive state" and the "on state" of a switch are interchangeable, and the "non-conductive state" and the "off state" are interchangeable.

[0050] In addition, in this specification, the terms "conductive" or "conductive state" used when conductive layers are in direct contact with each other refer to a state in which a current can flow between the conductive layers, for example.

[0051] Furthermore, the switch may have two or more terminals for passing current in addition to the control terminal. For example, an electrical switch, a mechanical switch, or the like may be used. In other words, the switch is not limited to a specific type as long as it has the function of controlling current.

[0052] Examples of electrical switches include transistors (e.g., bipolar transistors, MOS transistors, etc.), diodes (e.g., PN diodes, PIN diodes, Schottky diodes, MIM (Metal Insulator Metal) diodes, MIS (Metal Insulator Semiconductor) diodes, and diode-connected transistors), or logic circuits combining these. An example of a mechanical switch is a switch using MEMS (Micro Electro Mechanical Systems) technology. Such a switch has a mechanically movable electrode, and operates by controlling the on state and off state by the movement of the electrode.

[0053] In this specification, a transistor has three terminals called a gate, a source, and a drain. The gate is a control terminal that controls switching between a conductive state and a non-conductive state of the transistor. The two terminals that function as a source or a drain are input / output terminals of the transistor. One of the two input / output terminals serves as a source and the other as a drain depending on the conductivity type (n-channel or p-channel) of the transistor and the level of potential applied to the three terminals of the transistor. Therefore, in this specification, the terms "source" and "drain" are sometimes interchangeable. In addition, in this specification, when describing the connection relationship of a transistor, the terms "one of the source and the drain" and "the other of the source and the drain" are used. In this specification, one of the source and the drain is sometimes referred to as a "first electrode of the transistor" or a "first terminal of the transistor," and the other of the source and the drain is sometimes referred to as a "second electrode of the transistor" or a "second terminal of the transistor." Note that, depending on the structure of a transistor, a backgate may be provided in addition to the three terminals described above. In this case, in this specification, one of the gate or back gate of the transistor may be referred to as a first gate, and the other of the gate or back gate of the transistor may be referred to as a second gate. Furthermore, for the same transistor, the terms "gate" and "back gate" may be interchangeable. Furthermore, in this specification, when a transistor has three or more gates, the respective gates may be referred to as a first gate, a second gate, a third gate, etc.

[0054] For example, an example of a transistor described herein may include a multi-gate transistor with two or more gate electrodes. The multi-gate structure connects the channel formation regions in series, resulting in a structure in which multiple transistors are connected in series. Therefore, the multi-gate structure can reduce the off-state current and improve the transistor's breakdown voltage (reliability). Alternatively, the multi-gate structure can provide a flat Id-Vds characteristic when operating in the saturation region of the Id (source-drain current)-Vds (drain-source voltage) characteristic, whereby the current between the drain and source does not change significantly even when the voltage between the drain and source changes. By utilizing the flat Id-Vds characteristic, an ideal current source circuit or an active load with a very high resistance value can be realized. As a result, a differential circuit or a current mirror circuit with excellent characteristics can be realized.

[0055] Generally, the threshold voltage of a transistor is a voltage between the subthreshold region (weak inversion region) and the strong inversion region, and can also be said to be the voltage at which switching between the subthreshold region and the strong inversion region occurs. In addition, as an example of a method for measuring the threshold voltage, Id is calculated based on the Id-Vgs (gate-source voltage) characteristic. １／２ -Vgs characteristics are plotted, and Id １／２ Id on the tangent line where the slope of the -Vgs characteristic is maximum １／２ As another example, in the Id-Vgs characteristic where the drain potential is 1.2 V, Id=1.0×10 −１２ A is set as the threshold voltage.

[0056] In this specification, the term "operation in the subthreshold region" refers to a case where the gate-source voltage of the transistor is lower than the threshold voltage, more preferably a case where the drain current of the transistor increases exponentially with the gate-source voltage. In this case, the gate potential, source potential, and drain potential applied to the transistor include a case where potentials in the subthreshold region are appropriately applied.

[0057] In this specification, the subthreshold region refers to a region in a graph showing the Id-Vgs characteristics of a transistor where Vgs is lower than the threshold voltage. Alternatively, the subthreshold region refers to a region where current flows due to carrier diffusion, which deviates from the gradual channel approximation (a model that only considers drift current). Alternatively, the subthreshold region refers to a region where Id increases exponentially with increasing Vgs. Alternatively, the subthreshold region includes regions that can be considered as the regions described above.

[0058] In this specification, the source-drain current when a transistor operates in the subthreshold region is referred to as the “subthreshold current.” The subthreshold current increases exponentially with the gate-source voltage, regardless of the drain potential.

[0059] In general, the off-state current of a transistor may refer to a source-drain current that flows when the gate-source voltage Vgs of the transistor is lower than the threshold voltage. Therefore, the off-state current may include a subthreshold current. Note that, in this specification, since a circuit driven by a subthreshold current is described, the off-state current will be described as a current lower than the subthreshold current unless otherwise specified.

[0060] Furthermore, in this specification, ordinal numbers such as "first," "second," and "third" are used to avoid confusion between components. Therefore, they do not limit the number of components. Furthermore, they do not limit the order of components, such as the order of processes or stacking. Furthermore, even if a term does not have an ordinal number in this specification, an ordinal number may be added in the claims to avoid confusion between components. Furthermore, even if a term has an ordinal number in this specification, a different ordinal number may be added in the claims. Furthermore, even if a term has an ordinal number in this specification, the counter may be omitted in the claims. For example, a component with an ordinal number "first" in one embodiment of this specification may be a component with a different ordinal number such as "second" or "third" in other embodiments or claims. Furthermore, for example, a component with an ordinal number "first" in one embodiment of this specification may be omitted in other embodiments or claims.

[0061] In addition, timing charts may be used in this specification to explain an operation method of a semiconductor device. The timing charts used in this specification illustrate ideal operation examples, and the periods, magnitudes, and timings of signals (e.g., potentials or currents) described in the timing charts are not limited unless otherwise specified. The magnitudes and timings of signals (e.g., potentials or currents) input to each wiring (including a node) in the timing charts described in this specification may be changed depending on the situation. For example, even if two periods are shown at equal intervals in a timing chart, the lengths of the two periods may be different. For example, even if one period is shown as long and the other as short, the lengths of the two periods may be equal, or one period may be short and the other period may be long. For example, to clearly illustrate the timing charts, two or more overlapping signals may be intentionally shifted.

[0062] The embodiments described in this specification are described with reference to the drawings. However, it will be readily understood by those skilled in the art that the embodiments can be implemented in many different ways, and that various changes in form and details can be made without departing from the spirit and scope of the invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiments. Note that in the configuration of the invention of the embodiments, the same reference numerals are used in different drawings for the same parts or parts having similar functions, and repeated description thereof may be omitted. Also, in perspective views and the like, the description of some components may be omitted to ensure clarity of the drawings.

[0063] In this specification, when the same reference numeral is used for multiple elements, and particularly when it is necessary to distinguish between them, an identification symbol such as "_1", "[n]", "[m, n]" may be added to the reference numeral. Furthermore, when an identification symbol such as "_1", "[n]", "[m, n]" is added to the reference numeral in the drawings or the like, the identification symbol may not be added if it is not necessary to distinguish between them in this specification.

[0064] In addition, in the drawings of this specification, the size, layer thickness, or region may be exaggerated for clarity. Therefore, the drawings are not necessarily limited to the scale. Note that the drawings are schematic illustrations of ideal examples, and are not limited to the shapes or values ​​shown in the drawings. For example, variations in signals, voltages, or currents due to noise, or variations in signals, voltages, or currents due to timing differences may be included.

[0065] Embodiment 1 In this embodiment, a semiconductor device of one embodiment of the present invention will be described.

[0066] <Configuration Example 1 of Arithmetic Device> FIG. 1 is a block diagram illustrating a configuration example of an arithmetic device that is a semiconductor device according to one embodiment of the present invention. For example, the arithmetic device has a function of calculating the sum of products of a plurality of first data and a plurality of second data. For example, the arithmetic device may also have a function of calculating a function using the result of the sum of products as an input value. This enables the arithmetic device to perform, for example, calculations of a hierarchical neural network. In this case, the plurality of first data are treated as weight coefficients (which may be referred to as weight data, connection strengths, etc.), and the plurality of second data are treated as data to be input to neurons (which may be referred to as input data).

[0067] In addition, in this specification, the first data may be referred to as a multiplier, and the second data may be referred to as a multiplicand. Note that the multiplier and the multiplicand can be interchangeable due to the commutative law of products. For example, the first data may be referred to as a multiplicand, and the second data may be interchangeable as a multiplier.

[0068] As an example, the calculation device CDV shown in FIG. 1 includes a cell array CA, a driver circuit WCD, driver circuits XCD_1 to XCD_p (p is an integer greater than or equal to 1), driver circuits WSD_1 to WSD_p, a driver circuit WIOD, and a driver circuit ITS.

[0069] The cell array CA is divided into areas CAa_1 to CAa_p.

[0070] Each of the regions CAa_1 to CAa_p includes, for example, computation cells IM[1] to IM[m] (where m is an integer equal to or greater than 1) and driving cells IMD[1] to IMD[m]. In this specification, a cell selected from computation cells IM[1] to IM[m] is referred to as computation cell IM[i] (not shown) using i (where i is an integer equal to or greater than 1 and less than or equal to m). Similarly, a cell selected from driving cells IMD[1] to IMD[m] is referred to as driving cell IMD[i] (not shown) using i.

[0071] The region CAa_1 has a memory cell IMP_1, and the region CAa_p has a memory cell IMP_p. That is, it can be said that the cell array CA has memory cells IMP_1 to IMP_p.

[0072] In the region CAa_1, the wirings XCL[1]_1 to XCL[m]_1 extend in the row direction, and the wirings WSL[1]_1 to WSL[m]_1 extend in the row direction. In the region CAa_1, the wirings WIL_1 and WOL_1 extend in the row direction, and the wiring WCL_1 extends in the column direction.

[0073] In the region CAa_1, a wiring WCL_1 is connected to each of the computation cells IM[1] to IM[m] and the memory cell IMP_1. A wiring XCL[1]_1 is connected to each of the driving cell IMD[1] and the computation cell IM[1]. A wiring WSL[1]_1 is connected to each of the driving cell IMD[1] and the computation cell IM[1]. A wiring XCL[m]_1 is connected to each of the driving cell IMD[m] and the computation cell IM[m]. A wiring WSL[m]_1 is connected to each of the driving cell IMD[m] and the computation cell IM[m].

[0074] In the region CAa_p, the wirings XCL[1]_p to XCL[m]_p extend in the row direction, and the wirings WSL[1]_p to WSL[m]_p extend in the row direction. In the region CAa_p, the wirings WIL_p and WOL_p extend in the row direction, and the wiring WCL_p extends in the column direction.

[0075] In the region CAa_p, the computation cells IM[1] to IM[m] and the memory cell IMP_1 are each connected to a wiring WCL_p. The driving cell IMD[1] and the computation cell IM[1] are each connected to a wiring XCL[1]_p. The driving cell IMD[1] and the computation cell IM[1] are each connected to a wiring WSL[1]_p. The driving cell IMD[m] and the computation cell IM[m] are each connected to a wiring XCL[m]_p. The driving cell IMD[m] and the computation cell IM[m] are each connected to a wiring WSL[m]_p.

[0076] In addition, in the cell array CA, wirings WCPL extend in the column direction and are connected to the memory cells IMP_1 to IMP_p, respectively.

[0077] The driver circuit WCD is connected to each of the wirings WCL_1 to WCL_p. The driver circuit XCD_1 is connected to each of the wirings XCL[1]_1 to XCL[m]_1. The driver circuit WSD_1 is connected to each of the wirings WSL[1]_1 to WSL[m]_1. The driver circuit XCD_p is connected to each of the wirings XCL[1]_p to XCL[m]_p. The driver circuit WSD_p is connected to each of the wirings WSL[1]_p to WSL[m]_p. The driver circuit WIOD is connected to each of the wirings WIL_1 to WIL_p and the wirings WOL_1 to WOL_p. The driver circuit ITS is connected to the wirings WCPL and OL.

[0078] Each of the arithmetic cells IM[1] to IM[m] included in the region CAa_k (k is an integer greater than or equal to 1 and less than or equal to p) has, for example, a function of holding a potential corresponding to the first data and a function of absorbing a current corresponding to the potential from the wiring WCL_k. That is, the arithmetic cells IM[1] to IM[m] can be said to have a function as a memory circuit and a function as a current sink circuit. Note that, depending on the situation, the arithmetic cells IM[1] to IM[m] may function as a current source circuit that outputs a current corresponding to the potential to the wiring WCL_k, rather than as a current sink circuit. Furthermore, each of the arithmetic cells IM[1] to IM[m] functions as a current sink circuit or a current source circuit, and therefore can be said to have a function of flowing a current corresponding to the potential between the arithmetic cells IM[1] to IM[m] and the wiring WCL_k.

[0079] Specifically, when a current corresponding to the first data flows between the computation cell IM[i] and the wiring WCL_k, the gate and drain of the amplifier transistor included in the computation cell IM[i] are brought into a conductive state, and the current flows between the source and drain of the amplifier transistor. In particular, the current flow amount is set to the amount of current that flows when the amplifier transistor operates in the subthreshold region. This causes the gate potential of the amplifier transistor to reach a potential corresponding to the current. Here, by floating the gate of the amplifier transistor using the write transistor included in the computation cell IM[i], the potential corresponding to the first data can be maintained in the computation cell IM[i]. Furthermore, because a current corresponding to the first data continues to flow between the source and drain of the amplifier transistor, the computation cell IM[i] also functions as a current sink circuit or a current source circuit.

[0080] Furthermore, the computation cell IM[i] has the function of absorbing a current corresponding to the product of the first data and the second data from the wiring WCL_k by changing the potential of the wiring XCL[i]_k in accordance with the second data. Furthermore, if the computation cell IM[i] is a current source circuit rather than a current sink circuit, the current flows from the computation cell IM[i] to the wiring WCL_k.

[0081] Specifically, the amplifier transistor included in the computation cell IM[i] is operated in the subthreshold region. This causes the current flowing between the source and drain of the amplifier transistor to exponentially increase or decrease with changes in the gate-source voltage. Here, by varying the potential of the wiring XCL[i]_k by an amount corresponding to the second data and varying the potential of the gate of the amplifier transistor through capacitive coupling or the like, the current flowing between the source and drain of the amplifier transistor can be changed from a current corresponding to the first data to a current corresponding to the product of the first data and the second data. Therefore, a current corresponding to the product of the first data and the second data flows between the computation cell IM[i] and the wiring WCL_k.

[0082] The driver cell IMD[i] has the function of holding a potential corresponding to reference data and the function of absorbing a current corresponding to the potential from the wiring XCL[i]_k. In other words, the driver cell IMD[i] functions as a current sink circuit. The reference data will be described later. Furthermore, when the driver circuit XCD_k changes the reference data provided to the wiring XCL[i]_k to second data, the driver cell IMD[i] changes the amount of the current flowing from the wiring XCL[i]_k to an amount corresponding to the second data. The driver cell IMD[i] can also be a current source circuit instead of a current sink circuit. In this case, the current flows from the driver cell IMD[i] to the wiring WCL_k. In other words, the driver cell IMD[i] also functions as a memory circuit and a current sink circuit or current source circuit.

[0083] Specifically, similar to the operation of the computation cell IM[i] to hold the first data, when a current corresponding to the reference data flows between the driver cell IMD[i] and the wiring XCL[i]_k, the driver cell IMD[i] establishes a conductive state between the gate and drain of the amplifier transistor included in the driver cell IMD[i], thereby allowing the current to flow between the source and drain of the amplifier transistor. Note that the current is the amount of current that flows when the amplifier transistor operates in the subthreshold region. This causes the gate potential of the amplifier transistor to reach a potential corresponding to the current. By floating the gate of the amplifier transistor using the write transistor included in the driver cell IMD[i], the potential corresponding to the reference data can be maintained in the driver cell IMD[i]. Furthermore, because a current corresponding to the reference data continues to flow between the source and drain of the amplifier transistor, the driver cell IMD[i] also functions as a current sink circuit or a current source circuit.

[0084] Furthermore, the amplifier transistor included in the driver cell IMD[i] is operated in the subthreshold region. Here, the amount of current flowing through the wiring XCL[i]_k is changed from the reference data to an amount corresponding to the second data, and the potential of the gate of the amplifier transistor is changed by capacitive coupling or the like, so that the amount of current flowing between the source and drain of the amplifier transistor can be set to an amount corresponding to the second data.

[0085] The memory cell IMP_k has a function of holding a potential corresponding to the product of the first data and the second data by flowing a current corresponding to the product to the wiring WCL_k, and a function of discharging a current corresponding to the potential to the wiring WCPL or absorbing a current corresponding to the potential from the wiring WCPL. In other words, it can be said that the memory cell IMP_k also has a function as a memory circuit and a function as a current sink circuit or a current source circuit.

[0086] Each of the computation cells IM[1] to IM[m] sources or sinks a current corresponding to the product of the first data and the second data to the wiring WCL_k. Therefore, the amount of current flowing through the wiring WCL_k is the sum of the amounts of current generated by each of the computation cells IM[1] to IM[m]. When a current corresponding to the sum of the current amounts flows between the wiring WCL_k and the memory cell IMP_k, the gate and drain of the amplifier transistor included in the memory cell IMP_k are brought into a conductive state, and the current flows between the source and drain of the amplifier transistor, causing the potential of the gate of the amplifier transistor to reach a potential corresponding to the current. Here, by floating the gate of the amplifier transistor using the write transistor included in the memory cell IMP_k, a potential corresponding to the product of the first data and the second data can be held in the memory cell IMP_k. Furthermore, since a current corresponding to the product of the first data and the second data continues to flow between the source and drain of the amplifying transistor, the memory cell IMP_k also functions as a current sink circuit or a current source circuit.

[0087] As shown in the arithmetic device CDV of Figure 1, by dividing the m x p arithmetic cells IM arranged in a row into regions CAa_1 to CAa_p, the parasitic capacitance of each of the wirings WCL_1 to WCL_p can be made smaller than in a wiring in which the m x p arithmetic cells IM are connected in parallel. Details of the operation will be described later, but for example, in region CAa_1, the potential of wiring WCL_1 can be made to quickly reach the potential required to pass current from memory cell IMP_1 to each of arithmetic cells IM[1] to IM[m]. In other words, the charging time for wiring WCL_1 is shortened, and the operating speed of the arithmetic device can be increased.

[0088] The computation cell IM[i] also functions as a memory circuit and as an arithmetic circuit that supplies a current corresponding to the product of the first data and the second data. For this reason, the computation device CDV including the computation cell IM[i] may be referred to as in-memory computing. In in-memory computing, once first data is written to the computation cell IM[i], the first data can always be used for computation until the first data is rewritten to another value. Therefore, unlike conventional circuits, the number of times data is input to a circuit having a computation function can be reduced, thereby reducing the power consumption required for data transmission. Therefore, the computation cell IM[i] is preferably configured to retain data for a long period of time. Similarly, the driver cell IMD[i] and the memory cell IMP_k are preferably configured to retain data for a long period of time. While a specific configuration will be described later, for example, a transistor including an oxide semiconductor in a channel formation region (hereinafter referred to as an OS transistor) is preferably used as a write transistor used in the computation cell IM[i], the driver cell IMD[i], and the memory cell IMP_k, as a transistor with very low off-state current. The oxide semiconductor may be indium oxide. Note that in this specification, a transistor having indium oxide in a channel formation region is referred to as an IO transistor. IO transistors are included in the category of OS transistors.

[0089] A specific configuration example of the arithmetic unit CDV shown in Fig. 1 is shown in Fig. 2. Fig. 2 shows an example of the configuration of each cell included in the area CAa_k included in the cell array CA, and the drive circuits connected to each cell. Specifically, Fig. 2 shows the drive circuits WCD, XCD_k, WSD_k, WIOD, and ITS as the drive circuits.

[0090] In the region CAa_k, the calculation cells IM[1] to IM[m] each include, for example, a transistor M1, a transistor M3, a transistor M4, and a capacitor C1. The driving cells IMD[1] to IMD[m] each include a transistor M1d, a transistor M3d, a transistor M4d, and a capacitor C1d. The memory cell IMP_k includes a transistor F1, a transistor F3, a transistor F4, a transistor F5, a transistor F6, and a capacitor C6.

[0091] 2, the transistors M1, M3, M4, M1d, M3d, M4d, F1, F5, and F6 are n-channel transistors, and the transistors F3 and F4 are p-channel transistors.

[0092] Furthermore, each of transistors M1, M1d, and F1 functions as a write transistor (sometimes called a holding transistor or a switching transistor) for the cell that includes that transistor, and each of transistors M3 and M3d functions as a transistor (sometimes called an amplifying transistor) for outputting the result of multiplication performed in the cell that includes that transistor as a current.

[0093] The transistor M4 also functions as a clamp transistor to prevent a decrease in the threshold voltage of the transistor M3 due to drain-induced barrier lowering (DIBL). Similarly, the transistor M4d also functions as a clamp transistor to prevent a decrease in the threshold voltage of the transistor M3d due to DIBL, and the transistor F4 also functions as a clamp transistor to prevent a decrease in the threshold voltage of the transistor F3 due to DIBL.

[0094] The transistor F3 functions as an amplifying transistor for passing a source-drain current according to the gate-source voltage of the transistor F3. The transistors F5 and F6 each function as a switching transistor.

[0095] The switching transistor can be, for example, an OS transistor. In particular, by using, for example, indium-gallium-zinc oxide as an oxide semiconductor included in a channel formation region of the OS transistor, the OS transistor can have a very low off-state current. Furthermore, by using an IO transistor as the OS transistor, the switching transistor can have a very low off-state current and a high on-state current. Note that indium oxide included in the channel formation region of the IO transistor will be described in detail in Embodiment 4.

[0096] As a switching transistor, other than an OS transistor, a transistor including silicon in a channel formation region (hereinafter referred to as a Si transistor) having a large on-state current can be used.

[0097] As the amplifying transistor, for example, a transistor capable of improving on-state current can be preferably used. Therefore, the above-described IO transistor can be used as the amplifying transistor. In addition to the IO transistor, an OS transistor or a Si transistor including an oxide semiconductor other than indium oxide in a channel formation region can be used as the amplifying transistor.

[0098] In the computation cell IM[i], the first terminal of the transistor M1 is connected to the gate of the transistor M3 and the first terminal of the capacitor C1, and the gate of the transistor M1 is connected to the wiring WSL[i]_k. The first terminal of the transistor M3 is connected to the first terminal of the transistor M4, and the second terminal of the transistor M3 is connected to the wiring VEL. The first terminal of the transistor M1 and the second terminal of the transistor M4 are each connected to the wiring WCL_k. The gate of the transistor M4 is connected to the wiring VEB. The second terminal of the capacitor C1 is connected to the wiring XCL[i]_k.

[0099] In the driving cell IMD[i], the first terminal of the transistor M1d is connected to the gate of the transistor M3d and the first terminal of the capacitance element C1d, and the gate of the transistor M1d is connected to the wiring WSL[i]_k. The first terminal of the transistor M3d is connected to the first terminal of the transistor M4d, and the second terminal of the transistor M3d is connected to the wiring VEL. The first terminal of the transistor M1d and the second terminal of the transistor M4d are each connected to the wiring XCL[i]_k. The gate of the transistor M4d is connected to the wiring VEB. The second terminal of the capacitance element C1d is connected to the wiring XCL[i]_k.

[0100] In this specification, in the calculation cell IM[i], the connection point between the first terminal of the transistor M1, the gate of the transistor M3, and the first terminal of the capacitance element C1 is referred to as the node N. In addition, in the driving cell IMD[i], the connection point between the first terminal of the transistor M1d, the gate of the transistor M3d, and the first terminal of the capacitance element C1d is referred to as the node Nd.

[0101] In memory cell IMP_k, the first terminal of transistor F1 is connected to the gate of transistor F3 and the first terminal of capacitor C6, and the gate of transistor F1 is connected to wiring WIL_k. The first terminal of transistor F3 is connected to the first terminal of transistor F4, and the second terminal of transistor F3 is connected to wiring VEH. The second terminal of transistor F1, the first terminal of transistor F5, the second terminal of transistor F4, and the first terminal of transistor F6 are connected to one another. The second terminal of transistor F5 is connected to wiring WCL_k, and the second terminal of transistor F6 is connected to wiring WCPL. The gate of transistor F4 is connected to wiring VEC, the gate of transistor F5 is connected to wiring WIL_k, and the gate of transistor F6 is connected to wiring WOL_k. The second terminal of capacitor C6 is connected to wiring VEA.

[0102] In this specification, in the memory cell IMP_k, the connection point between the first terminal of the transistor F1, the gate of the transistor F3, and the first terminal of the capacitance element C6 is referred to as a node Ns.

[0103] For example, the wiring VEL functions as a wiring that applies a fixed potential. Specifically, the wiring VEL functions as a wiring that applies the fixed potential to the second terminals of the transistors M3 and M3d. In particular, the fixed potential is a potential in the subthreshold region of each of the transistors M3 and M3d. Specifically, the potential may be a ground potential, a negative potential, or the like. Depending on the situation, the potential may be a positive potential, or the like. Alternatively, depending on the situation, the wiring VEL may function as a wiring that applies a variable potential such as a pulse potential (sometimes referred to as a pulse signal) or a clock potential (sometimes referred to as a clock signal) instead of a fixed potential.

[0104] For example, the wiring VEH functions as a wiring that applies a fixed potential. Specifically, the wiring VEH functions as a wiring that applies the fixed potential to the second terminal of the transistor F3. In particular, the fixed potential is a potential in the subthreshold region of the transistor F3. Specifically, the potential may be a positive potential or the like. Depending on the situation, the potential may be a ground potential, a negative potential, or the like. Alternatively, depending on the situation, the wiring VEH may function as a wiring that applies a variable potential such as a pulse potential or a clock potential instead of a fixed potential.

[0105] For example, the wiring VEB functions as a wiring that applies a fixed potential. Note that the fixed potential can be, for example, a positive potential. This turns on the transistors M4 and M4d, which are n-channel clamp transistors. Note that, depending on the situation, the fixed potential applied by the wiring VEB can be a ground potential, a negative potential, or the like. For example, the wiring VEB may also function as a wiring that applies a variable potential instead of a fixed potential.

[0106] For example, the wiring VEC functions as a wiring that applies a fixed potential. Note that the fixed potential can be, for example, a ground potential or a negative potential. This causes each of the transistors F4, which are p-channel clamp transistors, to be turned on. Note that, depending on the situation, the fixed potential applied by the wiring VEC can be a positive potential or the like. For example, the wiring VEC may also function as a wiring that applies a variable potential instead of a fixed potential.

[0107] For example, the wiring VEA functions as a wiring that applies a fixed potential. Note that the fixed potential may be, for example, a ground potential, a negative potential, etc. Furthermore, for example, the wiring VEA may function as a wiring that applies a variable potential instead of a fixed potential.

[0108] The driving circuit WCD is connected to the wiring IWL_k, the wiring WCL_k, and the wiring SWLA. The driving circuit WCD has, for example, a function of converting first data, which is digital data transmitted from the wiring IWL_k, into an analog current and causing the analog current to flow through the wiring WCL_k.

[0109] As will be described in detail later, the analog current flowing through the wiring WCL_k flows to a selected one of the computation cells IM[1] to IM[m] in the region CAa_k, and the selected computation cell IM holds a potential corresponding to the analog current, thereby enabling the selected computation cell IM to acquire and store first data corresponding to the analog current.

[0110] The driver circuit WCD includes, for example, a circuit WCDa_k and a circuit SWCA. The circuit SWCA includes a switch SA_k.

[0111] The switch SA_k may be, for example, an electrical switch such as an analog switch or a transistor. Alternatively, a mechanical switch may be used instead of an electrical switch.

[0112] When a transistor is used as the switch SA_k as an electrical switch, the transistor can be an OS transistor, particularly an IO transistor. Since the OS transistor can have an extremely small off-state current, an increase in power consumption due to leakage current when the switch SA_k is in an off state can be prevented. Furthermore, by using the transistor as an IO transistor, the on-state current can be increased, thereby increasing the operating speed of the semiconductor device.

[0113] An input terminal of the circuit WCDa_k is connected to the wiring IWL_k, an output terminal of the circuit WCDa_k is connected to a first terminal of the switch SA_k, a second terminal of the switch SA_k is connected to the wiring WCL_k, and a control terminal of the switch SA_k is connected to the wiring SWLA.

[0114] For example, the wiring SWLA functions as a wiring for transmitting a signal for controlling switching between an on state and an off state of the switch SA_k. Note that in this specification, when a high-level potential is applied from the wiring SWLA to the control terminal of the switch SA_k, the switch SA_k is turned on, and when a low-level potential is applied from the wiring SWLA to the control terminal of the switch SA_k, the switch SA_k is turned off.

[0115] For example, the circuit WCDa_k has a function of acquiring first data, which is digital data transmitted from the wiring IWL_k, and generating an analog current corresponding to the first data. Note that the analog current flows to the wiring WCL_k via the switch SA_k.

[0116] A specific example of the circuit configuration of the circuit WCDa_k will be described in the second embodiment.

[0117] The driver circuit XCD_k is connected to the wirings IXL[1]_k to IXL[m]_k and the wirings XCL[1]_k to XCL[m]_k. For example, the driver circuit XCD_k has a function of converting second data or reference data, which is digital data transmitted from the wiring IXL[i]_k (not shown), into an analog current and causing the analog current to flow through the wiring XCL[i]_k (not shown).

[0118] The driver circuit XCD_k includes, for example, circuits XCDa[1] to XCDa[m].

[0119] An input terminal of the circuit XCDa[i]_k (not shown) is connected to a wiring IXL[i]_k, and an output terminal of the circuit XCDa[i]_k is connected to a wiring XCL[i]_k.

[0120] For example, the circuit XCDa[i]_k has a function of converting second data, which is digital data transmitted from the wiring IXL[i]_k, into an analog current and flowing the analog current through the wiring XCL[i]_k.

[0121] The specific circuit configuration of the circuit XCDa[i] will be described in the second embodiment.

[0122] When writing first data to the computation cell IM[i] in the area CAa_k, the drive circuit WSD_k has the function of turning on the transistor M1, which is a write transistor included in the computation cell IM[i], by supplying a predetermined signal to the wiring WSL[i]_k. Similarly, the drive circuit WSD_k also has the function of turning on the transistor M1d, which is a write transistor included in the drive cell IMD[i] in the area CAa_k. In other words, the drive circuit WSD_k functions as a write word line driver circuit for the computation cell IM and drive cell IMD included in the area CAa_k.

[0123] For example, when the driver circuit WSD_k supplies a high-level potential to the wiring WSL[i]_k as a selection signal, the transistor M1 included in the computation cell IM[i] and the transistor M1d included in the driving cell IMD[i] can be turned on. When the driver circuit WSD_k supplies a low-level potential to the wiring WSL[i]_k as a non-selection signal, the transistor M1 of the computation cell IM[i] and the transistor M1d of the driving cell IMD[i] can be turned off.

[0124] As described above, the drive circuit WSD_k can select either writing data or retaining data in each of the computation cells IM[i] and the drive cells IMD[i] of the area CAa_k by transmitting a selection signal or a non-selection signal to the wiring WSL[i]_k. Note that the data here refers to the first data in the computation cells IM[i] and the second data in the drive cells IMD[i].

[0125] The driver circuit WIOD has a function of controlling the switching between on and off of the transistors F1, F5, and F6 included in the memory cell IMP_k. Specifically, the driver circuit WIOD can turn on the transistors F1 and F5 by supplying a high-level potential as a selection signal to the wiring WIL_k, and can turn off the transistors F1 and F5 by supplying a low-level potential as a non-selection signal to the wiring WIL_k. The driver circuit WIOD can turn on the transistor F6 by supplying a high-level potential as a selection signal to the wiring WIL_k, and can turn off the transistor F6 by supplying a low-level potential as a non-selection signal to the wiring WIL_k.

[0126] The driver circuit ITS is connected to the wiring WCPL and the wiring OL. For example, the driver circuit ITS has a function of calculating a function using a value corresponding to the sum of analog currents transmitted from the wiring WCPL as an input value and outputting the calculation result of the function to the wiring OL.

[0127] The driver circuit ITS includes, for example, a circuit ITSa. The circuit ITSa has an input terminal and an output terminal, and the input terminal is connected to a wiring WCPL and the output terminal is connected to a wiring OL.

[0128] The circuit ITSa includes, for example, a circuit that performs a calculation of a function system (e.g., a nonlinear function system) and an analog current-to-digital potential conversion circuit (ADC). In particular, the circuit that performs the calculation of the function system preferably has a function of performing the calculation of the function system using, as an input value, a value corresponding to the amount of current input to an input terminal of the circuit ITSa, and outputting digital data (e.g., a digital potential) corresponding to the result of the calculation to an output terminal of the circuit ITSa.

[0129] The above-mentioned function may be a nonlinear function such as a sigmoid function, a tanh function, a softmax function, a ReLU function, or a threshold function. When the calculation device CDV performs calculations for a model such as a multilayer neural network, the above-mentioned function may be called an activation function.

[0130] In addition, when the calculation device CDV does not need to perform function calculations using the drive circuit ITS, the drive circuit ITS can obtain a current amount corresponding to the sum of products of multiple first data and multiple second data and convert the current into a digital potential. Alternatively, when the calculation device CDV does not need to perform function calculations using the drive circuit ITS, the calculation device CDV may be configured without providing a drive circuit ITS. In other words, the current flowing through the wiring WCPL and corresponding to the calculation results performed in the cell array CA may be directly passed through the wiring OL.

[0131] Note that a specific circuit configuration of the circuit ITSa will be described in Embodiment 2.

[0132] <Operation Example 1 of Calculation Device> Next, an operation example of the calculation device CDV shown in FIGS. 1 and 2 will be described.

[0133] 3 is a timing chart showing an example of an operation method of the arithmetic device CDV focusing on the region CAa_k in FIG. 2. The timing chart shows fluctuations in the potentials of the wiring SWLA, the wiring WSL[1]_k, the wiring WSL[m]_k, the wiring XCL[1]_k, the wiring XCL[m]_k, the wiring WIL_k, and the wiring WOL_k during and around the periods T01 to T15. The timing chart also shows fluctuations in the source-drain current I flowing through the transistor M3 of the arithmetic cell IM[1]. Ｍ３ [1] and the source-drain current I flowing through the transistor M3d of the driving cell IMD[1]. Ｍ３ｄ [1] and the source-drain current I flowing through the transistor M3 of the processing cell IM[m]. Ｍ３ [m] and the source-drain current I flowing through the transistor M3d of the driving cell IMD[m]. Ｍ３ｄ The amount of [m] and the respective variations of [m] are also shown.

[0134] 3, the types of wiring, nodes, etc. are listed on the left side, and the potential levels are listed on the right side. In particular, "High" in the timing chart means a high-level potential on the wiring, and "Low" means a low-level potential on the wiring. The same applies to the timing charts in FIGS. 9A to 9C and 13A to 13C, which will be described later.

[0135] In addition, the potential applied by the wiring VEL is V Ｎ In addition, V Ｎ can be at ground potential (GND) or a negative potential.

[0136] Before the period T01, a low-level potential is applied to the wiring SWLA, the wirings WSL[1]_k to WSL[m]_k, the wirings WIL_k, and the wiring WOL_k. In addition, the potentials of the nodes N of the calculation cells IM[1] to IM[m] and the nodes Nd of the driving cells IMD[1] to IMD[m] are set to V Ｎ Also, I Ｍ３ [1] to I Ｍ３ [m] and I Ｍ３ｄ [1] to I Ｍ３ｄ Each of [m] is set to 0.

[0137] A low-level potential is applied to the wiring SWLA, so that a low-level potential is applied to the control terminal of the switch SA_k, turning the switch SA_k off.

[0138] Since the wirings WSL[1]_k to WSL[m]_k are supplied with a low-level potential, the transistor M1 in each of the calculation cells IM[1] to IM[m] and the transistor M1d in each of the driving cells IMD[1] to IMD[m] are turned off. Also, since the wirings WIL_k and WOL_k are supplied with a low-level potential, the transistors F1, F5, and F6 in the memory cell IMP_k are turned off.

[0139] Furthermore, before the period T01, the second data X[1]_k to X[m]_k, which are digital data, may not be applied to the wirings IXL[1]_k to IXL[m]_k, respectively. Alternatively, the second data X[1]_k to X[m]_k, which represent digital data "0", may be applied to the wirings IXL[1]_k to IXL[m]_k, respectively. In this operation example, the circuit XCDa[1]_k applies the digital data "0" to the wiring XCL[1]_k, and supplies the potential V Ｎ The circuit XCDa[m]_k outputs digital data “0” to the wiring XCL[m]_k, and the potential V Ｎ shall be given.

[0140] [Period T01] In the period T01, a high-level potential is applied to the wiring SWLA, and therefore a high-level potential is applied to the control terminal of the switch SA_k, turning the switch SA_k on.

[0141] In addition, in the period T01, the first data W_k, which is digital data, may not be applied to the wiring IWL_k. Alternatively, the first data W_k indicating "0" as digital data may be applied to the wiring IWL_k. In this case, the amount of current generated by the circuit WCDa of the driver circuit WCD is set to 0. At this time, the circuit WCDa applies a potential V Ｎ shall be given.

[0142] During period T02, a high-level potential is applied from the driver circuit WSD_k to the wiring WSL[1]_k, turning on the transistor M1 of the processing cell IM[1] and the transistor M1d of the driver cell IMD[1].

[0143] In the calculation cell IM[1], the transistor M1 is turned on, and thus the potential V Ｎ is applied to the gate of the transistor M3 and the first terminal (node ​​N) of the capacitor C1. At this time, the potential V ＮThe second terminal of the transistor M3 is supplied with a potential V Ｎ Since I is given, Ｍ３ [1] becomes 0.

[0144] Similarly, in the driving cell IMD[1], the transistor M1d is turned on, and the potential V Ｎ is applied to the gate of the transistor M3d and the first terminal (node ​​Nd) of the capacitor C1d. At this time, the potential V Ｎ The second terminal of the transistor M3d is supplied with a potential V Ｎ Since I is given, Ｍ３ｄ [1] becomes 0.

[0145] [Period T03] During period T03, digital reference data r[1]_k is applied from wiring IXL[1]_k. Therefore, the amount of current generated by circuit XCDa[1]_k corresponds to r[1]_k. Here, the amount of current is calculated as r[1]_k×I Ｘｕｔ In addition, I Ｘｕｔ is the amount of current that flows when r[1]_k=1. This allows the amount r[1]_k×I generated by the circuit XCDa[1]_k to be Ｘｕｔ A current of flows through the wiring XCL[1]_k.

[0146] In addition, in the driving cell IMD[1], the transistor M1d is in the on state, so the quantity r[1]_k×I Ｘｕｔ The current flows through the source-drain of the transistor M3d to the wiring VEL. At this time, the potentials of the node Nd and the wiring XCL[1]_k are each determined by a quantity r[1]_k×I Ｘｕｔ The potential is V ｇｍ (r[1]_k).

[0147] In addition, in the period T03, the first data W[1]_k, which is digital data, is supplied from the wiring IWL_k. Therefore, the amount of current generated in the circuit WCDa_k is an amount corresponding to W[1]_k. Here, the amount of current is W[1]_k×I Ｗｕｔ In addition, I Ｗｕｔ is the amount of current that flows when W[1]_k=1. Also, since the switch SA_k is in the on state, the amount W[1]_k×I generated by the circuit WCDa_k Ｗｕｔ A current of flows through the wiring WCL_k.

[0148] In addition, in the calculation cell IM[1], the transistor M1 is in the on state, so the quantity W[1]_k×I Ｗｕｔ The current flows through the source-drain of the transistor M3 to the wiring VEL. At this time, the potential of the node N is W[1]_k×I Ｗｕｔ The potential is V ｇ (W[1]_k).

[0149] In addition, I Ｘｕｔ I Ｗｕｔ From now on, I Ｘｕｔ and I Ｗｕｔ Each of these is I ０ It will be explained as follows.

[0150] Also, the amount of current generated by the circuit XCDa[1]_k is r[1]_k×I ０ is the current in the subthreshold region of the transistor M3d of the driving cell IMD[1], and the gate-source voltage of the transistor M3d is V ｇｍ (r[1]_k)-V Ｎ Therefore, r[1]_k×I ０ can be expressed as the following equation (1.1).

[0151]

[0152] In addition, V ｔｈ is the threshold voltage of the transistor M3d, and J is a correction coefficient determined by temperature, device structure, etc. ａis the gate-source voltage of the transistor M3d is V ｔｈ is the amount of current that flows when

[0153] Also, the quantity W[1]_k×I generated by the circuit WCDa_k ０ The current is a current in the subthreshold region of the transistor M3, and the gate-source voltage of the transistor M3 is V ｇ (W[1]_k)-V Ｎ Therefore, W[1]_k×I ０ can be expressed as the following equation (1.2).

[0154]

[0155] For the sake of simplicity, V ｔｈ and J and I ａ are the V of the transistor M3d. ｔｈ and J and I ａ The values ​​are equal to each of the following:

[0156] Here, I ０ can be expressed as the following equation (1.3).

[0157]

[0158] Therefore, by using equations (1.2) and (1.3), W[1]_k can be expressed as in the following equation (1.4).

[0159]

[0160] During period T04, a low-level potential is applied to the wiring WSL[1]_k, turning off the transistor M1 of the processing cell IM[1] and the transistor M1d of the driving cell IMD[1].

[0161] In the calculation cell IM[1], the transistor M1 is turned off, and the potential V ｇ(W[1]_k) is held by the capacitance element C1. As a result, the node N is in a floating state. Furthermore, since the potential of the node N is held, the gate-source voltage of the transistor M3 is fixed, and therefore the amount W[1]_k×I continues to flow between the source and drain of the transistor M3. ０ A current of flows.

[0162] Similarly, in the driving cell IMD[1], the transistor M1d is turned off, so that the node Nd is in a floating state, and the potential V ｇｍ (r[1]_k) is held by the capacitance element C1d. Furthermore, since the potential of the node Nd is held, the gate-source voltage of the transistor M3d is fixed, and therefore the quantity r[1]_k×I continues to flow between the source and drain of the transistor M3d. ０ A current of flows.

[0163] As in the above-described transistors M3 and M3d, by passing a current of the amount I between the source and drain and holding a potential corresponding to that current at the gate, it is possible to continue to pass a current of the amount I between the source and drain. In this specification, this operation is referred to as "setting (programming) the amount of current flowing between the source and drain of a transistor to I."

[0164] [Period T05] In the period T05, the potential V Ｎ That is, the potential of the wiring XCL[1]_k is V ｇｍ (r[1]_k) to V Ｎ At this time, the amount of current flowing from the circuit XCDa[1]_k to the wiring XCL[1]_k is r[1]_k×I ０ It is assumed that the value changes from 0 to 0.

[0165] In the driving cell IMD[1], the node Nd is in a floating state, and therefore the potential of the node Nd fluctuates in accordance with the change in the potential of the wiring XCL[1]_k due to capacitive coupling in the capacitor C1d. For example, the potential of the wiring XCL[1]_k is V ｇｍ (r[1]_k) to VＮ The changed voltage is V ｇｍ (r[1]_k)-V Ｎ In the following, V ｇｍ (r[1]_k)-V Ｎ = ΔV ｇｍ (r[1]_k). When the capacitive coupling coefficient of the capacitive element C1d is p, the change in the potential of the node Nd is pΔV ｇｍ (r[1]_k). Therefore, the potential of the node Nd during the period T05 is V ｇｍ (r[1]_k)−pΔV ｇｍ (r[1]_k).

[0166] At this time, the gate-source voltage of the transistor M3d is V ｇｍ (r[1]_k)−pΔV ｇｍ (r[1]_k)-V Ｎ In this example of operation, the amount of current I flowing through the transistor M3d due to this gate-source voltage is Ｍ３ｄ [1] becomes 0.

[0167] In the calculation cell IM[1], the node N is also in a floating state, and therefore the potential of the node N also fluctuates in accordance with the change in the potential of the wiring XCL[1]_k due to capacitive coupling in the capacitor C1. ｇｍ (r[1]_k), and if the capacitive coupling coefficient of the capacitive element C1 is p, the same as that of the capacitive element C1d, the change in potential of the node N is pΔV ｇｍ (r[1]_k). Therefore, the potential of the node N during the period T05 is V ｇ (W[1]_k)−pΔV ｇｍ (r[1]_k).

[0168] At this time, the gate-source voltage of the transistor M3 is V ｇ (W[1]_k)−pΔV ｇｍ (r[1]_k)-V Ｎ In this example of operation, the amount of current I flowing through the transistor M3 due to this gate-source voltage is Ｍ３ [1] is also set to 0.

[0169] [Period T06] During period T06, similar to the writing of W[1]_k to the computation cell IM[1] of region CAa_k and the writing of r[1]_k to the driving cell IMD[1] of region CAa_k performed during periods T02 to T05, first data is written to the computation cell IM and reference data is written to the driving cell IMD in the second to (m-1)th rows of region CAa_k. Specifically, where i is 2 to (m-1), in the ith row of region CAa_k, W[i]_k is written to the computation cell IM[i] and r[i]_k is written to the driving cell IMD[i].

[0170] During period T07, similarly to period T02, a high-level potential is applied from the driver circuit WSD_k to the wiring WSL[m]_k, turning on the transistor M1 of the processing cell IM[m] and the transistor M1d of the driver cell IMD[m].

[0171] In the calculation cell IM[m], the transistor M1 is turned on, and thus the potential V Ｎ is applied to the node N. At this time, the potential V Ｎ The second terminal of the transistor M3 is supplied with a potential V Ｎ Since I is given, Ｍ３ [m] is 0.

[0172] Similarly, in the driving cell IMD[m], the transistor M1d is turned on, and the potential V Ｎ is applied to the gate of the transistor M3d and the first terminal (node ​​Nd) of the capacitor C1d. At this time, the potential V Ｎ The second terminal of the transistor M3d is supplied with a potential V Ｎ Since I is given, Ｍ３ｄ [m] is 0.

[0173] [Period T08] In the period T08, similarly to the period T03, the reference data r[m]_k, which is digital data, is supplied from the wiring IXL[m]_k. Therefore, the amount of current generated in the circuit XCDa[m]_k is r[m]_k×I Ｘｕｔ and r[m]_k×I is sent from the circuit XCDa[1]_k to the wiring XCL[1]_k. Ｘｕｔ A current of flows.

[0174] In addition, in the driving cell IMD[m], the transistor M1d is in the on state, so the quantity r[m]_k×I Ｘｕｔ The current flows through the source-drain of the transistor M3d to the wiring VEL. At this time, the potentials of the node Nd and the wiring XCL[m]_k are each determined by the quantity r[m]_k×I Ｘｕｔ The potential is V ｇｍ (r[m]_k).

[0175] In addition, in a period T07, the first data W[m]_k, which is digital data, is supplied from the wiring IWL_k. Therefore, the amount of current generated in the circuit WCDa_k is W[m]_k×I Ｗｕｔ In addition, since the switch SA_k is in the on state, W[m]_k×I Ｗｕｔ A current of flows from the circuit WCDa_k to the wiring WCL_k.

[0176] In addition, in the calculation cell IM[m], the transistor M1 is in the on state, so the quantity W[m]_k×I Ｗｕｔ The current flows through the source-drain of the transistor M3 to the wiring VEL. At this time, the potential of the node N is W[m]_k×I Ｗｕｔ The potential is V ｇ (W[m]_k).

[0177] The quantity r[m]_k×I generated by the circuit XCDa[m]_k ０ The current is the current in the subthreshold region of the transistor M3d of the driving cell IMD[m], and is calculated by referring to the above equation (1.1) as I Ｍ３ｄIt is as follows [m].

[0178] [Period T09] During period T09, as in period T04, a low-level potential is applied from the drive circuit WSD_k to the wiring WSL[m]_k. As a result, the transistor M1 of the processing cell IM[m] and the transistor M1d of the driving cell IMD[m] are both turned off. As a result, in the processing cell IM[m], the node N is brought into a floating state, the potential Vg (W[m]_k) of the node N is held by the capacitance element C1, and the gate-source voltage of the transistor M3 is fixed. Therefore, the amount W[m]_k×I continues to flow between the source and drain of the transistor M3. ０ Similarly, in the driving cell IMD[m], the node Nd is in a floating state, the potential Vgm(r[m]_k) of the node Nd is held by the capacitance element C1d, and the gate-source voltage of the transistor M3d is fixed. Therefore, a current of the amount r[m]_k×I continues to flow between the source and drain of the transistor M3d. ０ A current of flows.

[0179] In addition, in the period T09, a low-level potential is applied to the wiring SWLA. Therefore, a low-level potential is applied to the control terminal of the switch SA_k, and the switch SA_k is turned off.

[0180] [Period T10] In the period T10, similarly to the period T05, the potential V Ｎ is given, and the potential of the wiring XCL[m]_k is V ｇｍ (r[m]_k) to V Ｎ At this time, the amount of current flowing from the circuit XCDa[m]_k to the wiring XCL[m]_k is r[m]_k×I ０ It is assumed that the value changes from 0 to 0.

[0181] In the driving cell IMD[m], the node Nd is in a floating state, and therefore the potential of the node Nd fluctuates in accordance with the change in the potential of the wiring XCL[m]_k due to capacitive coupling in the capacitor C1d. Referring to the description of the period T05, the amount of change in the potential of the wiring XCL[m]_k is V ｇｍ(r[m]_k)-V Ｎ = ΔV ｇｍ (r[m]_k). When the capacitive coupling coefficient of the capacitive element C1d is p, the change in the potential of the node Nd is pΔV ｇｍ (r[m]_k). Therefore, the potential of the node Nd during the period T09 is V ｇｍ (r[m]_k)−pΔV ｇｍ (r[m]_k). At this time, the gate-source voltage of the transistor M3d is V ｇｍ (r[m]_k)−pΔV ｇｍ (r[m]_k)-V Ｎ At this time, the amount of current I Ｍ３ｄ [m] is set to 0.

[0182] In the calculation cell IM[m], the node N is also in a floating state, and therefore the potential of the node N also fluctuates in accordance with the change in the potential of the wiring XCL[m]_k due to capacitive coupling in the capacitor C1. Referring to the period T05, the amount of change in the potential of the wiring XCL[m]_k is ΔV ｇｍ (r[m]_k), the change in the potential of the node N is pΔV ｇｍ (r[m]_k). Therefore, the potential of the node N during the period T10 is V ｇ (W[m]_k)−pΔV ｇｍ (r[m]_k). At this time, the gate-source voltage of the transistor M3 is V ｇ (W[m]_k)−pΔV ｇｍ (r[m]_k)-V Ｎ In this example of operation, the amount of current I flowing through the transistor M3 due to this gate-source voltage is Ｍ３ [m] is also set to 0.

[0183] [Period T11] In the period T11, a high-level potential is applied to the wiring WIL_k from the driver circuit WIOD, so that the transistors F1 and F5 of the memory cell IMP_k are turned on.

[0184] At this time, the wiring WCL_k and the second terminal of the transistor F1 and the second terminal of the transistor F4 included in the memory cell IMP_k are electrically connected to each other.

[0185] [Period T12] In the period T12, the second data X[1]_k to X[m]_k, which are digital data, are applied from the wirings IXL[1]_k to IXL[m]_k, respectively. For example, in the circuit XCDa[1]_k, the amount X[1]_k×I ０ A current of X[m]_k×I is generated and flows from the circuit XCDa[1]_k to the wiring XCL[1]_k. Similarly, in the circuit XCDa[m]_k, a current of X[m]_k×I ０ is generated and flows from the circuit XCDa[m]_k to the wiring XCL[m]_k.

[0186] First, consider the first row of the area CAa_k. The amount of current flowing through the wiring XCL[1]_k is X[1]_k×I ０ The current flows through the wiring VEL via the transistor M3d of the driving cell IMD[1]. At this time, the potential of the wiring XCL is V Ｎ From V ｇｍ (X[1]_k). Since the node Nd is in a floating state, the potential of the node Nd varies in accordance with the change in the potential of the wiring XCL due to capacitive coupling in the capacitor C1d. For example, the potential of the wiring XCL[1]_k is V Ｎ From V ｇｍ (X[1]_k), the changed voltage is V ｇｍ (X[1]_k)-V Ｎ In the following, V ｇｍ (X[1]_k)-V Ｎ = ΔV ｇｍ (X[1]_k). In addition, since the capacitive coupling coefficient of the capacitive element C1d is p, the change in the potential of the node Nd is pΔV ｇｍ (X[1]_k)=p(V ｇｍ (X[1]_k)-V Ｎ ) Therefore, the potential of the node Nd during the period T12 is V ｇｍ (r[1]_k)−pΔV ｇｍ (r[1]_k)+pΔVｇｍ (X[1]_k)=V ｇｍ (r[1]_k)+p(ΔV ｇｍ (X[1]_k)−ΔV ｇｍ (r[1]_k)).

[0187] At this time, the gate-source voltage of the transistor M3d is V ｇｍ (r[1]_k)+p(ΔV ｇｍ (X[1]_k)−ΔV ｇｍ (r[1]_k))-V Ｎ As a result, the amount of current I flowing between the source and drain of the transistor M3d Ｍ３ｄ [1]=X[1]_k×I ０ Referring to the above equation (1.1), I Ｍ３ｄ [1]=X[1]_k×I ０ =I ａ exp[j{V ｇｍ (r[1]_k)+p(V ｇｍ (X[1]_k)-V ｇｍ (r[1]_k))-V Ｎ -V ｔｈ ].

[0188] In the calculation cell IM[1], the node N is also in a floating state. Therefore, due to a change in the potential of the wiring XCL[1]_k, the potential of the node N also fluctuates in accordance with the change in the potential of the wiring XCL[1]_k due to capacitive coupling in the capacitor C1. For example, the amount of change in the potential of the wiring XCL[1]_k is ΔV ｇｍ (X[1]_k), and the capacitive coupling coefficient of the capacitive element C1 is p, so the change in the potential of the node N is also pΔV ｇｍ (X[1]_k). Therefore, the potential of the node N during the period T12 is V ｇ (W[1]_k)−pΔV ｇｍ (r[1]_k)+pΔV ｇｍ (X[1]_k)=V ｇ (W[1]_k)−p(ΔV ｇｍ (X[1]_k)−ΔV ｇｍ (r[1]_k)).

[0189] At this time, the gate-source voltage of the transistor M3 is V ｇ(W[1]_k)−p(ΔV ｇｍ (X[1]_k)−ΔV ｇｍ (r[1]_k))-V Ｎ As a result, the amount of current I flowing between the source and drain of the transistor M3 Ｍ３ Referring to the above equation (1.1), I Ｍ３ [1] = I ａ exp[j{V ｇ (W[1]_k)+p(V ｇｍ (X[1]_k)-V ｇｍ (r[1]_k))-V Ｎ -V ｔｈ ].

[0190] Here, by defining r[1]_k as exp[JpVgm(r[1]_k)] and X[1]_k as exp[JpVgm(X[1]_k)], I Ｍ３ [1] can be expressed as the following equation (1.5) by using the above equations (1.3) and (1.4).

[0191]

[0192] Next, consider the m-th row of the area CAa_k. As in the above, the amount of current flowing through the wiring XCL[m]_k is X[m]_k×I ０ The current flows through the wiring VEL via the transistor M3d of the driving cell IMD[m], and the potential of the wiring XCL becomes V Ｎ From V ｇｍ Since the node Nd is in a floating state, the potential of the node Nd also changes in accordance with the change in the potential of the wiring XCL due to capacitive coupling in the capacitor C1d.

[0193] For example, the potential of the wiring XCL[m]_k is V Ｎ From V ｇｍ (X[m]_k), the changed voltage is V ｇｍ (X[m]_k)-V Ｎ = ΔV ｇｍ (X[m]_k). In addition, since the capacitive coupling coefficient of the capacitive element C1d is p, the change in the potential of the node Nd is pΔV ｇｍ (X[m]_k)=p(Vｇｍ (X[m]_k)-V Ｎ ), and the potential of the node Nd during the period T12 is V ｇｍ (r[m]_k)−pΔV ｇｍ (r[m]_k)+pΔV ｇｍ (X[m]_k)=V ｇｍ (r[m]_k)+p(ΔV ｇｍ (X[m]_k)−ΔV ｇｍ (r[m]_k)).

[0194] At this time, the gate-source voltage of the transistor M3d is V ｇｍ (r[m]_k)+p(ΔV ｇｍ (X[m]_k)−ΔV ｇｍ (r[m]_k))-V Ｎ and the amount of current I flowing between the source and drain of the transistor M3d Ｍ３ｄ [m]=X[m]_k×I ０ Referring to the above equation (1.1), I Ｍ３ｄ [m]=X[m]_k×I ０ =I ａ exp[j{V ｇｍ (r[m]_k)+p(V ｇｍ (X[m]_k)-V ｇｍ (r[m]_k))-V Ｎ -V ｔｈ ].

[0195] In the calculation cell IM[m], the node N is also in a floating state. Therefore, due to a change in the potential of the wiring XCL[m]_k, the potential of the node N also fluctuates in accordance with the change in the potential of the wiring XCL[m]_k due to capacitive coupling in the capacitor C1. For example, the amount of change in the potential of the wiring XCL[m]_k is ΔV ｇｍ (X[m]_k), and the capacitive coupling coefficient of the capacitive element C1 is p, so the change in potential of the node N is pΔV ｇｍ (X[m]_k). Therefore, the potential of the node N during the period T12 is V ｇ (W[m]_k)−pΔV ｇｍ (r[m]_k)+pΔV ｇｍ (X[m]_k)=V ｇ (W[m]_k)−p(ΔV ｇｍ(X[m]_k)−ΔV ｇｍ (r[m]_k)).

[0196] At this time, the gate-source voltage of the transistor M3 is V ｇ (W[m]_k)−p(ΔV ｇｍ (X[m]_k)−ΔV ｇｍ (r[m]_k))-V Ｎ and the amount of current I flowing between the source and drain of the transistor M3 Ｍ３ Referring to the above equation (1.1), I Ｍ３ [m] = I ａ exp[j{V ｇ (W[m]_k)+p(V ｇｍ (X[m]_k)-V ｇｍ (r[m]_k))-V Ｎ -V ｔｈ ].

[0197] Furthermore, by setting r[m]_k to exp[JpVgm(r[m]_k)] and X[m]_k to exp[JpVgm(X[m]_k)], I Ｍ３ [m] can be expressed as the following formula (1.6) by using the above formulas (1.3) and (1.4).

[0198]

[0199] As shown in the above formulas (1.5) and (1.6), the amount of current I flowing between the source and drain of the transistor M3 of the processing cell IM[i] Ｍ３ [i] is proportional to the product of W[i]_k and X[i]_k. This allows the amount of current I Ｍ３ [i] to obtain the multiplication result of the first data W[i]_k and the second data X[i]_k. Therefore, by using the arithmetic unit CDV of FIG. 1 or 2, the first data and the second data can be multiplied.

[0200] In particular, when multiplying the first data by the second data, it is preferable that the reference data r[i]_k is set to 1. That is, in the periods T03 and T04, and the periods T08 and T09, the amount of current that the circuit XCDa[i]_k passes through the wiring XCL[i]_k is set to I ０It is preferable to set the following.

[0201] Furthermore, from the above explanation, in the arithmetic unit CDV of FIG. 2, by setting the reference data r[i]_k to a positive number other than 1, it is possible to perform division using r[i]_k as the divisor and W[i]_k × X[i]_k as the dividend. In other words, it is possible to multiply W[i]_k by X[i]_k / r[i]_k. This allows the arithmetic unit CDV to increase the resolution of values ​​that can be input as second data. Furthermore, when considering multiplication of W[i]_k / r[i]_k by X[i]_k, it can also be said that the arithmetic unit CDV can increase the resolution of values ​​that can be input as first data.

[0202] In addition, during the period T12, the same operation as above is performed for the processing cells IM and the driving cells IMD in the rows other than the first row and the mth row of the area CAa_k, and the amount I Ｍ３ Therefore, a current of I flows through the transistor M3 of each of the processing cells IM[1] to IM[m]. Ｍ３ [1] to I Ｍ３ The current [m] flows from the wiring VEH through the transistors F3 to F5 of the memory cell IMP_k. Ｍ３ [1] to I Ｍ３ The total current flow is I Ｍ３Ｓ At this time, since the transistor F1 is also in an on state, the potential of the gate (node ​​Ns) of the transistor F1 is set to 1 / k when the source-drain current of the transistor F3 is I Ｍ３Ｓ At this time, I Ｍ３Ｓ _k can be expressed as in the following equation (1.7).

[0203]

[0204] [Period T13] During period T13, a low-level potential is applied to the wiring WIL_k from the driver circuit WIOD. As a result, the transistors F1 and F5 of the memory cell IMP_k are turned off. This also causes the gate-source voltage of the transistor F3 to be maintained, and the source-drain current of the transistor F3 is reduced to I Ｍ３Ｓ _k.

[0205] [Period T14] In the period T14, the potential V Ｎ is given, and the potential of the wiring XCL[1]_k is V ｇｍ (X[1]_k) to V Ｎ As a result, the potential of the node Nd of the driving cell IMD[1] changes to V ｇｍ (r[1]_k)−pΔV ｇｍ (r[1]_k), the source-drain current of the transistor M3d becomes 0, and the potential of the node N of the processing cell IM[1] becomes V ｇ (W[1]_k)−pΔV ｇｍ (r[1]_k), and the source-drain current of the transistor M3d becomes zero.

[0206] In addition, the potential V Ｎ is given, and the potential of the wiring XCL[m]_k is V ｇｍ (X[m]_k) to V Ｎ As a result, the potential of the node Nd of the driving cell IMD[m] changes to V ｇｍ (r[m]_k)−pΔV ｇｍ (r[m]_k), the source-drain current of the transistor M3d also becomes 0, and the potential of the node N of the processing cell IM[m] becomes V ｇ (W[m]_k)−pΔV ｇｍ (r[m]_k), and the source-drain current of the transistor M3d becomes zero.

[0207] The same operation as above is performed for the processing cells IM and driver cells IMD in the second to (m-1)th rows of the area CAa_k, thereby making the amount of current flowing through the wiring WCL_k zero.

[0208] [Period T15] During the period T15, a high-level potential is applied to the wiring WOL_k from the driver circuit WIOD, which turns on the transistor F6 of the memory cell IMP_k.

[0209] At this time, a state of conduction is established between the second terminal of the transistor F6 and the input terminal of the circuit ITSa included in the drive circuit ITS, so that the amount I set by the transistor F3 Ｍ３ The source-drain current of the transistor ._k is input to the input terminal of the circuit ITSa via the wiring WCPL.

[0210] In the circuit ITSa, the amount of current I flowing from the wiring WCPL Ｍ３ A potential according to the value of ._k is generated, and the potential is output from the output terminal of the circuit ITSa to the wiring OL.

[0211] Here, consider a case where the above-described example of operation in area CAa_k is simultaneously performed on each of areas CAa_1 to CAa_p of the calculation device CDV in Fig. 1. Specifically, consider a case where, in each of areas CAa_1 to CAa_p, first data is written to the calculation cell IM and reference data is written to the driving cell IMD between periods T02 and T09, and second data is input to the calculation cell IM and the driving cell IMD between periods T12 and T13.

[0212] At this time, the calculation of WX / r is performed in the calculation cells IM included in each of the areas CAa_1 to CAa_p, and the source-drain current I of the transistor M3 included in the calculation cells IM is calculated as the result of WX / r. Ｍ３ Furthermore, a current I that is the sum of the results of the calculations performed by the calculation cells IM in the areas CAa_1 to CAa_p flows through each of the memory cells IMP_1 to IMP_p. Ｍ３Ｓ _1 to I Ｍ３Ｓ A potential according to .sub._p is written.

[0213] Furthermore, during the period T15, the amount I Ｍ３Ｓ _1 to I Ｍ３ＳThe currents of the wirings WCPL and WCPL_p are added together and input to the driving circuit ITS. Ｓ When I Ｓ can be expressed as the following equation (1.8).

[0214]

[0215] The input terminal of the circuit ITSa of the driving circuit ITS is connected to the amount I Ｓ The current flows through the circuit ITSa. Ｓ The circuit ITSa generates a potential according to the amount I Ｓ By obtaining the current of Ｓ The voltage or current corresponding to the result of the calculation is output from the output terminal. Ｓ The function with the input value is F(I Ｓ ) and the result of the calculation is Z, Z can be expressed as in the following formula (1.9).

[0216]

[0217] As described above, the arithmetic unit CDV of Figures 1 and 2 can multiply first data by second data, add the results of multiple multiplications, and calculate functions using the results of multiple multiplications as input values. These are frequently used operations in artificial neural network models, and therefore the arithmetic unit CDV of Figures 1 and 2 can be said to be suitable for performing calculations on artificial neural network models. Furthermore, because the first data W and the reference data r can be held by the calculation cell IM and the driving cell IMD, respectively, the arithmetic unit CDV can also be said to have in-memory computing capabilities. Therefore, when the first data W and the reference data r are not rewritten, the arithmetic unit CDV does not need to transmit write data, thereby reducing the power consumption required for transmission.

[0218] Furthermore, in the arithmetic device CDV of FIG. 1, it can be said that the cell array CA has m×p arithmetic cells IM. By combining the wirings WCL_1 to WCL_p into a single wiring and connecting m×p arithmetic cells IM in parallel to the wiring, it is possible to perform multiplication, product-sum operations, and function calculations in the same manner as in the above-described operation example. However, as shown in the arithmetic device CDV of FIG. 1, by dividing the arithmetic cells IM arranged in a row into p regions, the parasitic capacitance of each of the wirings WCL_1 to WCL_p is reduced, and therefore the rate at which charges are accumulated in each of the wirings WCL_1 to WCL_p can be made faster than when the wirings are combined into a single wiring. In other words, the potentials of each of the wirings WCL_1 to WCL_p are applied to the wirings WCL_1 to WCL_p by a voltage I corresponding to the multiplication result. Ｍ３Ｓ _1 to I Ｍ３Ｓ _p, the time required to output a current corresponding to the multiplication result in each arithmetic cell IM can be shortened, and as a result, the driving speed of the arithmetic unit CDV can be increased.

[0219] <Configuration Example 2 of Arithmetic Device> Next, a configuration example of a arithmetic device which is a semiconductor device of one embodiment of the present invention and which is different from the arithmetic device CDV in FIG. 1 will be described.

[0220] Figure 4 is a circuit diagram showing the circuit configuration in which changes have been made to each of the calculation cells IM[1] to IM[m], the driving cells IMD[1] to IMD[m], and the memory cell IMP_k included in the calculation device CDV shown in Figure 2.

[0221] Specifically, compared to the calculation device CDV of Figure 2, the calculation device CDVA shown in Figure 4 has a circuit configuration in which transistor M4 is not provided in each of the calculation cells IM[1] to IM[m], transistor M4d is not provided in each of the driving cells IMD[1] to IMD[m], and transistor F4 is not provided in the memory cell IMP_k.

[0222] When the influence of DIBL on transistors M3, M3d, and F3 can be ignored, it is preferable to use a circuit configuration that does not include transistors M4, M4d, and F4, as in the calculation device CDV shown in Figure 4. Therefore, there is no need to provide wiring VEB connected to the gates of transistors M4 and M4d, and wiring VEC connected to the gate of transistor F4. As a result, compared to the calculation device CDV of Figure 2, the circuit area of ​​each of the calculation cells IM, driver cells IMD, and memory cells IMP_k can be reduced, and the density of the calculation cells IM in the cell array CA can be increased.

[0223] <Configuration Example 3 of Arithmetic Device> Next, a configuration example of an arithmetic device which is a semiconductor device of one embodiment of the present invention and which is different from the arithmetic device CDV in FIGS. 1 and 2 and the arithmetic device CDVA in FIG. 4 will be described.

[0224] The arithmetic device CDVB shown in FIG. 5 is a modified example of the arithmetic device CDV shown in FIG. 2, and differs from the arithmetic device CDV in that wiring WILa_k and wiring WILb_k are provided instead of the wiring WIL_k in FIG.

[0225] 5, the gate of the transistor F1 is connected to the wiring WILb_k instead of the wiring WIL_k. The gate of the transistor F5 is connected to the wiring WILa_k instead of the wiring WIL_k. The drive circuit WIOD is connected to the wiring WILa_k and the wiring WILb_k.

[0226] As an example, the driver circuit WIOD in Figure 5 has a function of transmitting a signal to the wiring WILa_k that controls the switching between the on state and the off state of the transistor F5, and a function of transmitting a signal to the wiring WILb_k that controls the switching between the on state and the off state of the transistor F1.

[0227] In other words, in the calculation device CDV of Figure 2, the on and off states of transistors F1 and F5 are switched synchronously with each other, but in the calculation device CDVB of Figure 5, the on and off states of transistors F1 and F5 can be switched independently of each other.

[0228] 5 can quickly reset (initialize) the potential of the node Ns of the memory cell IMP_k. For example, the potential of the node Ns of the memory cell IMP_k can be reset by turning on the transistor F1, turning off the transistors F5 and F6, and applying charge flowing from the wiring VEH to the node Ns. This allows the potential of the node Ns to be set to the potential at the time of initialization. When the transistor F5 is in the same on state as the transistor F1, charge applied from the wiring VEH also flows to the wiring WCL_k, which slows down the reset of the potential of the node Ns of the memory cell IMP_k.

[0229] As shown in the circuit configuration of FIG. 5, by making it possible to switch the on and off states of the transistors F1 and F5 independently of each other, the operation of resetting the potential of the node Ns of the memory cell IMP_k can be made faster than the operation of the calculation device CDV of FIG. 2.

[0230] <Configuration Example 4 of Arithmetic Device> Next, a configuration example of a semiconductor device of one embodiment of the present invention, which is different from the arithmetic device CDV in FIG. 1, will be described.

[0231] Fig. 6 is a circuit diagram showing a circuit configuration in which a change has been made to the arithmetic unit CDV shown in Fig. 1, and the cell array CA included in the arithmetic unit CDV1 in Fig. 6 is divided into areas CAa_1 to CAa_p in the same manner as the cell array CA shown in Fig. 1. Note that Fig. 6 shows only areas CAa_1 and CAa_2 out of areas CAa_1 to CAa_p.

[0232] 1 has a configuration in which the driver circuit WCD is connected to the wirings WCL_1 to WCL_p, while the driver circuit WCD is connected to the wiring WCL_1 in the arithmetic device CDV1 of FIG. 6. Also, focusing on the memory cell IMP_1, the arithmetic device CDV of FIG. 1 has a configuration in which the memory cell IMP_1 is connected to the wirings WIL_1 and WOL_1, while the arithmetic device CDV1 of FIG. 6 has a configuration in which the memory cell IMP_1 is connected to the wirings WILa_1, WILb_1, WILc_1, WRL_1, and WOL_1. The same is true for the memory cells IMP_2 to IMP_p included in the cell array CA of the arithmetic device CDV1.

[0233] Specifically, memory cell IMP_1 is connected to wiring WCL_1 and wiring WCL_2. Memory cell IMP_2 is connected to wiring WCL_2 and wiring WCL_3. That is, in area CAa_r (not shown), where r is an integer between 1 and p-1, memory cell IMP_r is connected to wiring WCL_r (not shown) and wiring WCL_r+1 (not shown). Memory cell IMP_p (not shown) is connected to wiring WCL_p (not shown) and wiring WCPL.

[0234] The driver circuit WIOD is connected to the wirings WILa_1, WILa_2, WILb_1, WILb_2, WILc_1, WILc_2, WRL_1, WRL_2, WOL_1, and WOL_2.

[0235] Fig. 7 shows an example of the circuit configuration of each of the calculation cells IM[1] to IM[m], the driver cells IMD[1] to IMD[m], and the memory cell IMP_r included in the region CAa_r of the cell array CA of the calculation device CDV1 in Fig. 6. Note that in Fig. 7, for the calculation cells IM[1] to IM[m], the driver cells IMD[1] to IMD[m], the driver circuit XCD_r, and the driver circuit WSD_r, the descriptions of the calculation cells IM[1] to IM[m], the driver cells IMD[1] to IMD[m], the driver circuit XCD_k, and the driver circuit WSD_k in Fig. 2 can be referred to.

[0236] 7, the drive circuit WCD provided in the arithmetic device CDV1 has a different configuration from the drive circuit WCD provided in the arithmetic device CDV in FIG. 2. Specifically, the drive circuit WCD in FIG. 2 has circuits WCDa_1 to WCDa_k and switches SA_1 to SA_k, but the drive circuit WCD in FIG. 7 has a circuit WCDa and a switch SA. Note that for the circuit WCDa and switch SA in the drive circuit WCD in FIG. 7, the descriptions of the circuit WCDa_k and switch SA_k in the drive circuit WCD in FIG. 2 can be referred to.

[0237] An example of the configuration of the memory cell IMP_r shown in Fig. 7 will be described below. The memory cell IMP_r provided in the arithmetic device CDV1 has a configuration in which a transistor F7, which is an n-channel transistor, is provided in the memory cell IMP_k provided in the arithmetic device CDV of Fig. 2. Furthermore, the memory cell IMP_r provided in the arithmetic device CDV1 has a configuration in which the gate of the transistor F5 is connected to a wiring WILa_r instead of a wiring WIL_k, the gate of the transistor F1 is connected to a wiring WILb_r instead of a wiring WIL_k, and the second terminal of the capacitance element C6 is connected to a wiring WRL_r instead of a wiring VEA.

[0238] In the memory cell IMP_r, the first terminal of transistor F7 is connected to the second terminal of transistor F1, the second terminal of transistor F4, the first terminal of transistor F5, and the first terminal of transistor F6. The second terminal of transistor F5 is connected to wiring WCL_r, and the second terminal of transistor F7 is connected to wiring WCL_r+1. The gate of transistor F7 is connected to wiring WILc_r. As with the memory cell IMP_k of FIG. 5, the second terminal of transistor F6 is connected to wiring WCPL.

[0239] Next, a configuration example of a memory cell IMP_p (not shown) included in an area CAa_p (not shown) of the cell array CA provided in the calculation device CDV1 of Fig. 6 will be described. As an example, the memory cell IMP_p provided in the calculation device CDV1 can have the configuration of the memory cell IMP_p shown in Fig. 8. Compared to the memory cell IMP_r of Fig. 7, the memory cell IMP_p of Fig. 8 does not have a transistor F7. As for the connection configuration of the memory cell IMP_p, the second terminal of the transistor F5 is connected to the wiring WCL_p.

[0240] Next, an example of the operation of the memory cell IMP_k included in the calculation device CDV1 of FIG. 6 will be described. FIGS. 9A and 9B are timing charts showing an example of the operation of the memory cell IMP_k when first data is written to the calculation cell IM of the region CAa_k of the cell array CA. In particular, FIG. 9A shows an example of the operation of the memory cells IMP_1 to IMP_k-1 included in the regions CAa_1 to CAa_k-1, respectively, during the operation of FIG. 9B. Note that in FIG. 9A, h is shown as an integer between 1 and k-1. Furthermore, when k = 1, only the operation example of FIG. 9B is considered, and the operation example of FIG. 9A is not considered. Furthermore, since the memory cell IMP_p does not have a transistor F7, when k = p, fluctuations in the potential of the wiring WILc_k shown in FIG. 9B are not considered.

[0241] 9A and 9B each show the potential fluctuations of the wirings during and around the periods T31 to T33. Specifically, FIG. 9A shows the potential fluctuations of the wirings SWLA, WILa_h, WILb_h, WILc_h, WOL_h, and WRL_h, while FIG. 9B shows the potential fluctuations of the wirings SWLA, WILa_k, WILb_k, WILc_k, WOL_k, and WRL_k. The potential fluctuations of the wiring SWLA shown in FIGS. 9A and 9B are the same.

[0242] 9A and 9B , when first data is written to any one of the calculation cells IM[1] to IM[m] included in the area CAa_k of the cell array CA, a high-level potential is applied to the wiring SWLA in periods T31 to T33. At this time, in the calculation device CDV1 of FIG. 7 , a current corresponding to the first data flows from the output terminal of the circuit WCDa to the wiring WCL_1 via the switch SA.

[0243] In particular, when the first data is not written to the operation cell IM included in the area CAa_h, the memory cell IMP_h included in the area CAa_h operates as shown in FIG. 9A . Specifically, during the period T32, the driver circuit WIOD applies a high-level potential to each of the wirings WILa_h and WILc_h. This turns on the transistors F5 and F7 of the memory cell IMP_h, and the wirings WCL_h and WCL_h+1 become conductive to each other. In other words, the wirings WCL_1 to WCL_k become conductive to each other.

[0244] In the memory cell IMP_h, a low-level potential is applied to the wirings WILb_h, WOL_h, and WRL_h from the driver circuit WIOD during the periods T31 to T33, so that the transistors F1, F3, and F6 of the memory cell IMP_h are turned off.

[0245] Furthermore, the memory cell IMP_k included in the region CAa_k operates as shown in FIG. 9B . Specifically, during the period T32, the driver circuit WIOD applies a low-level potential to each of the wirings WILa_k, WILb_k, WILc_k, WOL_k, and WRL_k. Therefore, when k is an integer between 1 and p−1, the transistors F1, F3, and F4 to F7 of the memory cell IMP_k are turned off. This results in a non-conduction state between the wiring WCL_k and the wiring WCL_k+1. Furthermore, when k is p, the transistors F1, F3, and F4 to F6 of the memory cell IMP_p are turned off. In this case, the wirings WCL_1 to WCL_p are electrically connected to each other, as in the operation example of FIG. 9A .

[0246] 9A and the memory cell IMP_k performs the operation shown in FIG. 9B, the wirings WCL_1 to WCL_k are electrically connected to each other, so that a current of an amount corresponding to the first data can be flowed from the output terminal of the circuit WCDa to any one of the calculation cells IM[1] to IM[m] included in the region CAa_k via the switch SA and the wirings WCL_1 to WCL_k. This allows a potential corresponding to the current to be written to the selected calculation cell IM, and the current can be set as the source-drain current flowing through the transistor M3.

[0247] 9C shows the sum of the multiplication results of the first data and the second data performed in each of the calculation cells IM[1] to IM[m] in the area CAa_k of the cell array CA, as a current I Ｍ３Ｓ .sub.k to the memory cell IMP_k, and the I flowing from each of the memory cells IMP_1 to IMP_p. Ｍ３Ｓ _1 to I Ｍ３Ｓ9C shows changes in the potentials of the wirings SWLA, WILa_k, WILb_k, WILc_k, WOL_k, and WRL_k in and around the periods T41 to T44.

[0248] In particular, the period T41 can be the period T10 in the timing chart of Fig. 3, the period T42 can be the period T11 and the period T12 in the timing chart of Fig. 3, the period T43 can be the period T13 and the period T14 in the timing chart of Fig. 3, and the period T44 can be the period T15 in the timing chart of Fig. 3.

[0249] In each of the memory cells IMP_1 to IMP_p, during the period T42, a high-level potential is applied to the wirings WILa_1 to WILa_p (referred to as wirings WILa_k in FIG. 9C ) and the wirings WLb_1 to WILb_p (referred to as wirings WILb_k in FIG. 9C ), turning on the transistors F5 and F1. Also, a low-level potential is applied to the wirings WILc_1 to WILc_p-1 (referred to as wirings WILc_k in FIG. 9C ) and the wirings WOL_1 to WOL_p, turning off the transistors F6 and F7.

[0250] In addition, in the period T42, a high-level potential is applied to each of the wirings WRL_1 to WRL_p (denoted as wiring WRL_k in FIG. 9C). At this time, the source-drain current of the transistor F3 of the memory cell IMP_k is equal to or larger than the amount I Ｍ３Ｓ A current of _k flows.

[0251] In each of the memory cells IMP_1 to IMP_p, during the period T43, a low-level potential is applied to the wiring WILa_k, the wiring WLb_k, and the wiring WRL_k, turning off the transistors F5 and F1. In addition, since the potential of the wiring WRL_k drops from a high-level potential to a low-level potential, the potential of the node Ns also drops due to capacitive coupling of the capacitor C6, turning off the transistor F3.

[0252] In each of the memory cells IMP_1 to IMP_p, a high-level potential is applied to the wiring WOL_k and the wiring WRL_k in the period T44, and the transistor F6 is turned on. At this time, the potential of the wiring WRL_k rises from a low-level potential to a high-level potential, and the potential of the node Ns also rises due to capacitive coupling of the capacitor C6. As a result, the amount of the source-drain current of the transistor F3 increases by I Ｍ３Ｓ _k flows.

[0253] In addition, in the period T44, conduction is established between the first terminal of the transistor F3 of each of the memory cells IMP_1 to IMP_p and the wiring WCPL. Therefore, the wiring WCPL is connected to the first terminal of the transistor F3. Ｍ３Ｓ _1 to I Ｍ３Ｓ 1, the result of the calculation performed in the cell array CA can be transmitted to the drive circuit ITS, and a function can be calculated using the result of the calculation as an input value.

[0254] In the arithmetic device CDV of FIG. 1, the wirings WCL_1 to WCL_p are each connected to the driver circuit WCD, so the area in which the wirings WCL_1 to WCL_p extend in the cell array CA tends to be wide. On the other hand, in the arithmetic device CDV1 shown in FIGS. 6 to 8, only the wiring WCL_1 is connected to the driver circuit WCD, and the wirings WCL_r and WCL_r+1 are indirectly connected via the memory cell IMP_r. This allows the circuit area of ​​the cell array CA to be reduced more than that of the arithmetic device CDV of FIG. 1. This allows the arithmetic device CDV1 and electronic devices including the arithmetic device CDV1 to be miniaturized.

[0255] <Configuration Example 5 of Arithmetic Device> The arithmetic device CDV2 shown in FIG. 10 is an example of an arithmetic device in which the circuit configuration of the arithmetic device CDV1 shown in FIG. 6 is modified.

[0256] The cell array CA included in the arithmetic device CDV2 in Fig. 10 is divided into areas CAa_1 to CAa_p, similar to the cell array CA shown in Fig. 1 and Fig. 6. Note that Fig. 10 shows only areas CAa_1 and CAa_2 from among areas CAa_1 to CAa_p, similar to Fig. 6.

[0257] 6 is configured such that the wiring WOL_k is connected to the memory cell IMP_k, whereas the computing device CDV2 in Fig. 10 is configured such that the wiring WOL_k is not provided in the cell array CA. Also, the computing device CDV1 in Fig. 6 is configured such that the wiring WCPL is connected to the memory cell IMP_k, whereas the computing device CDV2 in Fig. 10 is configured such that the wiring WCPL is connected only to the memory cell IMP_p among the memory cells IMP_1 to IMP_p.

[0258] 10, similarly to the arithmetic device CDV1 of FIG. 6, memory cell IMP_1 is connected to wiring WCL_1 and wiring WCL_2, and memory cell IMP_2 is connected to wiring WCL_2 and wiring WCL_3. Furthermore, in an area CAa_r (not shown), where r is an integer between 1 and p-1, memory cell IMP_r (not shown) is connected to wiring WCL_r (not shown) and wiring WCL_r+1 (not shown). Furthermore, memory cell IMP_p (not shown) is connected to wiring WCL_p (not shown) and wiring WCPL.

[0259] Fig. 11 shows an example of the circuit configuration of each of the calculation cells IM[1] to IM[m], the driving cells IMD[1] to IMD[m], and the memory cell IMP_r included in the area CAa_r of the cell array CA of the calculation device CDV2 in Fig. 10. Note that in Fig. 11, the calculation cells IM[1] to IM[m], the driving cells IMD[1] to IMD[m], the driving circuit XCD_r, and the driving circuit WSD_r have the same circuit configuration as the calculation cells IM[1] to IM[m], the driving cells IMD[1] to IMD[m], the driving circuit XCD_r, and the driving circuit WSD_r in Fig. 7.

[0260] The memory cell IMP_r in the arithmetic unit CDV2 is configured such that the memory cell IMP_k in the arithmetic unit CDV1 in Fig. 7 does not have the transistor F6. Therefore, the cell array CA does not have the wiring WOL_k. Also, unlike the arithmetic unit in Fig. 6, the wiring WCPL is not connected to the memory cell IMP_r.

[0261] As an example, a memory cell IMP_p (not shown) included in the calculation device CDV2 can have the configuration of the memory cell IMP_p shown in Fig. 12. The memory cell IMP_p in Fig. 12 differs from the memory cell IMP_r in Fig. 11 in that a wiring WCPL is connected to the second terminal of the transistor F7.

[0262] Next, an example of the operation of the memory cell IMP_k included in the calculation device CDV2 of Figure 10 will be described. Figures 13A and 13B are timing charts showing an example of the operation of the memory cell IMP_k when first data is written to the calculation cell IM of the area CAa_k of the cell array CA. In particular, Figure 13A shows an example of the operation of the memory cells IMP_1 to IMP_k-1 included in the areas CAa_1 to CAa_k-1, respectively, during the operation of Figure 13B. Note that in Figure 13A, h is shown as an integer between 1 and k-1. Furthermore, when k = 1, only the example of operation of Figure 13B is considered, and the example of operation of Figure 13A is not considered.

[0263] 13A and 13B show the potential fluctuations of the wirings during and around the periods T51 to T53. Specifically, FIG. 13A shows the potential fluctuations of the wirings SWLA, WILa_h, WILb_h, WILc_h, and WRL_h, while FIG. 13B shows the potential fluctuations of the wirings SWLA, WILa_k, WILb_k, WILc_k, and WRL_k. The potential fluctuations of the wiring SWLA shown in FIGS. 13A and 13B are the same.

[0264] In particular, the potential fluctuations in each wiring shown in the timing chart of Fig. 13A are similar to the potential fluctuations in each wiring shown in the timing chart of Fig. 9A , excluding the wiring WOL_h. Furthermore, the potential fluctuations in each wiring shown in the timing chart of Fig. 13B are similar to the potential fluctuations in each wiring shown in the timing chart of Fig. 9B , excluding the wiring WOL_k. Therefore, the operations of the memory cells IMP_h and IMP_k can be explained with reference to the descriptions of Figs. 9A and 9B .

[0265] FIG. 13C shows the sum of the multiplication results of the first data and the second data performed in each of the calculation cells IM[1] to IM[m] in the area CAa_k of the cell array CA, as a current I Ｍ３Ｓ .sub.k to the memory cell IMP_k, and the I flowing from each of the memory cells IMP_1 to IMP_p. Ｍ３Ｓ _1 to I Ｍ３Ｓ 13C shows changes in the potentials of the wirings SWLA, WILa_k, WILb_k, WILc_k, and WRL_k during and around the periods T61 to T64.

[0266] In particular, the period T61 can be the period T10 in the timing chart of Fig. 3, the period T62 can be the period T11 and the period T12 in the timing chart of Fig. 3, the period T63 can be the period T13 and the period T14 in the timing chart of Fig. 3, and the period T64 can be the period T15 in the timing chart of Fig. 3.

[0267] In each of the memory cells IMP_1 to IMP_p, during the period T62, a high-level potential is applied to the wirings WILa_1 to WILa_p (referred to as wirings WILa_k in FIG. 13C) and the wirings WLb_1 to WILb_p (referred to as wirings WILb_k in FIG. 13C), turning on the transistors F5 and F1. Also, a low-level potential is applied to the wirings WILc_1 to WILc_p (referred to as wirings WILc_k in FIG. 13C), turning off the transistor F7.

[0268] In addition, in the period T62, a high-level potential is applied to each of the wirings WRL_1 to WRL_p (denoted as wiring WRL_k in FIG. 13C). At this time, the source-drain current of the transistor F3 of the memory cell IMP_k is equal to or larger than the amount I Ｍ３Ｓ A current of _k flows.

[0269] In each of the memory cells IMP_1 to IMP_p, during the period T63, a low-level potential is applied to the wiring WILa_k, the wiring WLb_k, and the wiring WRL_k, turning off the transistors F5 and F1. In addition, since the potential of the wiring WRL_k drops from a high-level potential to a low-level potential, the potential of the node Ns also drops due to capacitive coupling of the capacitor C6, turning off the transistor F3.

[0270] In each of the memory cells IMP_1 to IMP_p, a high-level potential is applied to the wiring WRL_k in the period T64, and the transistor F6 is turned on. At this time, the potential of the wiring WRL_k rises from a low-level potential to a high-level potential, and the potential of the node Ns also rises due to capacitive coupling of the capacitor C6. As a result, the amount of the source-drain current of the transistor F3 increases by I Ｍ３Ｓ _k flows.

[0271] In addition, in the period T64, conduction is established between the first terminal of each transistor F3 in the memory cell IMP_r and the wiring WCL_r and the wiring WCL_r+1, and conduction is established between the first terminal of each transistor F3 in the memory cell IMP_p and the wiring WCL_p and the wiring WCPL. Therefore, I Ｍ３Ｓ _1 to I Ｍ３Ｓ 1, the result of the calculation performed in the cell array CA can be transmitted to the drive circuit ITS, and a function can be calculated using the result of the calculation as an input value.

[0272] The arithmetic device CDV2 shown in Figures 10 to 12 has a configuration in which the number of circuit elements included in the memory cells IMP_r is smaller than that of the arithmetic device CDV1 shown in Figures 6 to 8. Therefore, by fabricating the arithmetic device CDV2 of Figures 10 to 12, the circuit area of ​​the cell array CA can be reduced more than when fabricating the arithmetic device CDV1 of Figures 6 to 8. This makes it possible to reduce the size of the arithmetic device CDV2 and electronic devices equipped with the arithmetic device CDV2.

[0273] <Configuration Example 6 of Arithmetic Device> The arithmetic device CDVS shown in FIG. 14 is an example of an arithmetic device in which the circuit configuration of the arithmetic device CDV shown in FIG. 1 is modified.

[0274] The calculation device CDVS is an arithmetic device having a cell array CA in the calculation device CDV of Figure 1, with n columns (n ​​is an integer greater than or equal to 2) of calculation cells IM[1] to IM[m] and memory cells IMP_1 to IMP_k in areas CAa_1 to CAa_p included in the cell array CA.

[0275] 1, the wiring WCL_1 is shown as wiring WCL[1]_1 to wiring WCL[n]_1, the wiring WCL_p is shown as wiring WCL[1]_p to wiring WCL[n]_p, the wiring WCPL is shown as wiring WCPL[1] to wiring WCPL[n], and the wiring OL is shown as wiring OL[1] to wiring OL[n].

[0276] 1, the calculation cells IM[1] in the areas CAa_1 to CAa_p are denoted as calculation cells IM[1,1] to IM[1,n], and the calculation cells IM[m] are denoted as calculation cells IM[m,1] to IM[m,n]. Also, the memory cells IMP_1 are denoted as memory cells IMP[1]_1 to IMP[n]_1, and the memory cells IMP_p are denoted as memory cells IMP[1]_p to IMP[n]_p.

[0277] As for the connection configuration between each of the processing cells IM and the memory cells IMP, the description of the processing unit CDV in FIG. 1 can be referred to.

[0278] The arithmetic unit CDV of FIG. 1 is capable of performing one sum-of-products operation. Furthermore, by changing the configuration of the arithmetic unit CDV of FIG. 1 to the arithmetic unit CDVS of FIG. 14, n sum-of-products operations can be performed simultaneously. For example, since the arithmetic cells IM are arranged in each of n columns of the cell array CA, the arithmetic cells IM arranged in the cell array CA can hold n sets of first data. Furthermore, since currents corresponding to one set of second data flow from each of the driving circuits XCD_1 to XCD_p, the arithmetic unit CDVS can simultaneously calculate the sum-of-products of each of the n sets of first data and one set of second data. Furthermore, the currents corresponding to the n sum-of-products operations, which are the calculation results, flow to the driving circuit ITS, similar to the arithmetic unit CDV of FIG. 1, and the circuits included in the driving circuit ITS perform calculations of n functions. The calculation results of the n functions are output to the wirings OL[1] to OL[n], respectively.

[0279] In particular, when performing calculations on a model of a multilayer neural network, as described above, it is necessary to simultaneously perform the sum of products of each of n sets of first data and one set of second data. Therefore, it is preferable to configure the calculation device to have n columns, as shown in Figure 14, with calculation cells IM[1] to IM[m] and memory cells IMP_1 to IMP_k as one column.

[0280] Note that this embodiment mode can be appropriately combined with the same or other embodiment modes described in this specification. For example, the configuration, structure, method, etc. described in this embodiment mode can be appropriately combined with another configuration, structure, method, etc. described in this embodiment mode. Furthermore, for example, the configuration, structure, method, etc. described in this embodiment mode can be appropriately combined with the configuration, structure, method, etc. described in other embodiment modes.

[0281] Second Embodiment In this embodiment, a driver circuit that can be provided in the arithmetic unit CDV, arithmetic unit CDVA, arithmetic unit CDVB, arithmetic unit CDV1, and arithmetic unit CDV2 described in the above embodiments will be described.

[0282] <Configuration example of driving circuit WCD> The driving circuit WCD included in the calculation device CDV, calculation device CDVA, calculation device CDVB, calculation device CDV1 and calculation device CDV2 described in the above embodiments can be configured, for example, as shown in Figure 15.

[0283] The driver circuit WCD shown in Figure 15 includes, as an example, a circuit WCDa and a circuit SWCA. The circuit WCDa in Figure 15 is a circuit that can be applied to the circuit WCDa_k shown in Figures 2, 4, and 5. The circuit WCDa in Figure 15 is a circuit that can be applied to the circuit WCDa shown in Figures 7 and 11. The circuit SWCA is the circuit SWCA shown in Figures 2, 4, 5, 7, and 11. Therefore, for the switch SA shown in Figure 15, the description of the switch SA_k in the first embodiment can be referred to.

[0284] 15 has a circuit configuration including n-channel transistors and p-channel transistors, and is a configuration example of a K-bit current-type ladder DAC (Digital-to-Analog Converter) (K is an integer equal to or greater than 1). The circuit WCDa in FIG. 15 has a function of applying a potential corresponding to the value of each bit of digital data to each of the wirings DW[0] to DW[K-1], thereby generating a current corresponding to the digital data and outputting the current to the wiring WCL. Note that the digital data can be the first data described in Embodiment 1.

[0285] The driver circuit WCD in FIG. 15 is connected to the wirings DW[0] to DW[K-1], the wiring WCL, and the wiring SWLA. The wirings DW[0] to DW[K-1] in FIG. 15 can be the wirings IWL_k in FIG. 2, FIG. 4, and FIG. 5. Therefore, the wiring IWL in FIG. 15 can be a wiring group including the wirings DW[0] to DW[K-1]. The wirings DW[0] to DW[K-1] in FIG. 15 can be the wirings IWL in FIG. 7 and FIG. 11. The wiring WCL in FIG. 15 can be the wiring WCL_k in FIG. 2, FIG. 4, and FIG. 5. The wiring WCL in FIG. 15 can be the wiring WCL_1 in FIG. 7 and FIG. 11. The wiring SWLA shown in FIG. 15 is the wiring SWLA shown in FIGS. 2, 4, 5, 7, and 11.

[0286] 15 includes, as an example, a plurality of current sources CS and a current mirror circuit CRM. Ｋ In this case, the circuit WCDa has K current sources CS. For example, the circuit WCDa has current sources CS corresponding to the 0th bit to the (K-1)th bit, respectively.

[0287] 15, each current source CS has a terminal T1 and a terminal T2, and the current mirror circuit CRM has a terminal CTi and a terminal CTo. Terminal T1 of each current source CS is connected to terminal CTi of the current mirror circuit CRM. Terminal CTo of the current mirror circuit CRM is connected to a first terminal of a switch SA. Terminal T2 of the current source CS for the 0th bit is connected to wiring DW[0], terminal T2 of the current source CS for the 1st bit is connected to wiring DW[1], and terminal T2 of the current source CS for the (K-1)th bit is connected to wiring DW[K-1].

[0288] 15, the transistors Tr1 and Tr2 included in the current source CS for the 0th bit are written as transistor Tr1[0] and transistor Tr2[0], respectively, the transistors Tr1 and Tr2 included in the current source CS for the 1st bit are written as transistor Tr1[1] and transistor Tr2[1], respectively, and the transistors Tr1 and Tr2 included in the current source CS for the K-1th bit are written as transistor Tr1[K-1] and transistor Tr2[K-1], respectively.

[0289] A first terminal of the transistor Tr1[s] (here, s is an integer greater than or equal to 0 and less than or equal to K-1) is electrically connected to the wiring VSSL, a second terminal of the transistor Tr1[s] is connected to the first terminal of the transistor Tr2[s], and a gate of the transistor Tr1[s] is connected to the wiring BIS. In addition, the gate of the transistor Tr2[s] is connected to the wiring DW[s].

[0290] For example, the wiring VSSL functions as a wiring that applies a fixed potential. The fixed potential may be, for example, a ground potential or a negative potential as a low-level potential. Depending on the situation, the fixed potential may also be a positive potential as a high-level potential.

[0291] 15, the transistors Tr2[0] to Tr2[K-1] function as transistors capable of adjusting the amount of current flowing between the source and drain of each of the transistors Tr1[0] to Tr1[K-1]. Therefore, the wiring BIS functions as a wiring that applies a fixed potential. Note that the fixed potential may be a high-level potential, such as a positive potential. Depending on the situation, the fixed potential may also be a low-level potential, such as a ground potential or a negative potential.

[0292] In FIG. 15, when the channel width of the transistor Tr1[0] is w[0], the channel width of the transistor Tr1[1] is w[1], and the channel width of the transistor Tr1[K-1] is w[K-1], the ratio of the respective channel widths is w[0]:w[1]:w[K-1]=1:2:2. Ｋ−１ 15 can output a current corresponding to the first data W, which is K-bit digital data input to the wirings DW[0] to DW[K-1], because the current flowing between the source and drain of a transistor operating in the subthreshold region is proportional to the channel width.

[0293] Next, the current mirror circuit CRM will be described. The current mirror circuit CRM has a function of outputting a current to the terminal CTo equal to the amount of current flowing through the terminal CTi. The current mirror circuit CRM also includes a transistor Tr5, a transistor Tr5m, a transistor Tr6, and a transistor Tr6m.

[0294] The first terminal of transistor Tr5 is connected to terminal CTi, the gate of transistor Tr6, and the gate of transistor Tr6m. The second terminal of transistor Tr5 is connected to the first terminal of transistor Tr6. The gate of transistor Tr5 is connected to the gate of transistor Tr5m and the wiring CPE. The second terminal of transistor Tr6 is connected to the wiring VEH. The first terminal of transistor Tr5m is connected to terminal CTo. The second terminal of transistor Tr5m is connected to the first terminal of transistor Tr6m. The second terminal of transistor Tr6m is connected to the wiring VEH.

[0295] The wiring VEH functions as a wiring that applies a fixed potential. The fixed potential can be, for example, a positive potential as a high-level potential. Depending on the situation, the fixed potential may also be a ground potential, a negative potential, or the like as a low-level potential.

[0296] For example, the wiring CPE functions as a wiring that applies a fixed potential. The fixed potential may be a ground potential, a negative potential, or the like as a low-level potential. Depending on the situation, the fixed potential may also be a positive potential or the like as a high-level potential.

[0297] In the current mirror circuit CRM, the second terminals of the transistors Tr6 and Tr6m are connected such that a potential is applied from the wiring VEH, and the gates of the transistors Tr6 and Tr6m are connected such that a potential of the terminal CTi is applied. Ideally, therefore, equal amounts of current flow between the source and drain of the transistors Tr6 and Tr6m.

[0298] Furthermore, transistor Tr5 functions as a transistor cascode-connected to transistor Tr6. Similarly, transistor Tr5m functions as a transistor cascode-connected to transistor Tr6m. This prevents the potential of terminal CTi from being directly input to the first terminal of transistor Tr6. In other words, this prevents the potential of the first terminal of transistor Tr6 from suddenly fluctuating, thereby stabilizing the operation of the current mirror circuit CRM.

[0299] 15 illustrates the circuit WCDa when K is an integer equal to or greater than 3, but when K is 1, it is preferable that the circuit WCDa in FIG. 15 does not have a current source CS connected to the wirings DW[2] to DW[K]. When K is 2, it is preferable that the circuit WCDa in FIG. 15 does not have a current source CS connected to the wirings DW[3] to DW[K].

[0300] <Configuration example of driving circuit XCD> The driving circuit XCD included in the calculation device CDV, calculation device CDVA, calculation device CDVB, calculation device CDV1 and calculation device CDV2 described in the above embodiments can be configured as shown in Figure 16, for example.

[0301] The driver circuit XCD shown in Fig. 16 includes a circuit XCDa, for example. The circuit XCDa in Fig. 16 can be applied to the circuits XCDa[1]_k to XCDa[m]_k shown in Fig. 2, Fig. 4, and Fig. 5. The circuit XCDa in Fig. 16 can be applied to the circuits XCDa[1]_r to XCDa[m]_r in Fig. 7 and Fig. 11 and the circuits XCDa[1]_p to XCDa[m]_p in Fig. 8 and Fig. 12.

[0302] The circuit XCDa in Figure 16 has the same circuit configuration as the circuit WCDa in Figure 15, which is a K-bit current-type ladder DAC. Therefore, for the current source CS and current mirror circuit CRM included in the circuit XCDa, the description of the circuit WCDa in Figure 15 can be referred to. The circuit WCDa in Figure 16 has a function of generating a current corresponding to the digital data and outputting it to the wiring XCL by applying a potential corresponding to the value of each bit of the digital data to each of the wirings DX[0] to DX[K-1]. Note that the digital data can be the reference data or the second data described in embodiment 1.

[0303] The value of K in the driving circuit XCD in FIG. 16 may be the same as or different from the value of K in the driving circuit WCD in FIG.

[0304] The driver circuit XCD in FIG. 16 is connected to wirings DX[0] to DX[K-1] and a wiring XCL. All of the wirings DX[0] to DX[K-1] shown in FIG. 16 can be any one of the wirings IXL[1]_k to IXL[m]_k shown in FIGS. 2, 4, and 5. Therefore, the wiring IXL shown in FIG. 16 can be a wiring group including the wirings DX[0] to DX[K-1]. All of the wirings DX[0] to DX[K-1] shown in FIG. 16 can be any one of the wirings IXL[1]_r to IXL[m]_r shown in FIGS. 7 and 11. All of the wirings DX[0] to DX[K-1] shown in FIG. 16 can be any one of the wirings IXL[1]_p to IXL[m]_p shown in FIGS. 8 and 12. 16 can be any one of the wirings XCL[1]_k to XCL[m]_k shown in FIGS. 2, 4, and 5. The wiring XCL shown in FIG. 16 can be any one of the wirings XCL[1]_r to XCL[m]_r shown in FIGS. 7 and 11. The wiring XCL shown in FIG. 16 can be any one of the wirings XCL[1]_p to XCL[m]_p shown in FIGS. 8 and 12.

[0305] As described above, the circuit XCDa in FIG. 16 can output a current according to the reference data r or the second data X, which is K-bit digital data input to the wirings DX[0] to DX[K-1].

[0306] <Configuration example of driving circuit ITS> The driving circuit ITS included in the calculation device CDV, calculation device CDVA, calculation device CDVB, calculation device CDV1 and calculation device CDV2 described in the above embodiments can be configured, for example, as shown in Figure 17.

[0307] 17 includes, as an example, a circuit RL and a circuit ATDC. The circuit ITSa in FIG. 17 is applicable to the circuits ITSa shown in FIGS. 2, 4, 5, 7, 8, 11, and 12.

[0308] The circuit RL in Fig. 17 functions as a circuit for performing the calculation of the ReLU function, and the circuit ATDC in Fig. 17 functions as an ADC for converting an analog current into a digital potential.

[0309] As an example, the circuit RL includes transistors MN1i, MN1o, MN2i, and MN2o, and a current source CNI. The circuit RL also includes a terminal RTi, which is an input terminal, and a terminal RTo, which is an output terminal. In the circuit RL, a current mirror circuit is formed by n-channel transistors MN1i, MN2i, MN1o, and MN2o.

[0310] The wiring WCPL is connected to the drain of the transistor MN2o via the terminal RTi. The drain of the transistor MN2o is connected to the input terminal of the circuit ATDC via the terminal RTo. The output terminal of the circuit ATDC is connected to the wiring OL. The output terminal of the current source CNI is connected to the drain of the transistor MN2i, the gate of the transistor MN1i, and the gate of the transistor MN1o. The input terminal of the current source CNI is connected to the wiring VDDL.

[0311] For example, the wiring VDDL functions as a wiring that applies a fixed potential. Note that the fixed potential can be, for example, a high-level potential such as a positive potential.

[0312] The current mirror circuit included in the circuit RL ideally has the function of passing a current between the source and drain of the transistor MN1o that is the same as the source-drain current corresponding to the gate-source potential of the transistor MN1i. In the case of the circuit RL in FIG. 17, a current of the same amount as the current generated by the current source CNI flows between the source and drain of the transistor MN1o.

[0313] In the current mirror circuit, transistor MN2i functions as a clamp transistor to prevent a decrease in the threshold voltage of transistor MN1i due to DIBL. Similarly, transistor MN2o also functions as a clamp transistor to prevent a decrease in the threshold voltage of transistor MN1o due to a drain-induced barrier lowering. Therefore, wiring RSWL1 that applies a desired bias potential is connected to the gates of transistors MN2i and MN2o.

[0314] Each of the transistors MN2i and MN2o can function as a switching transistor. In this case, the wiring RSWL1 preferably functions as a wiring for controlling the switching between the on state and the off state of each of the transistors MN2i and MN2o. By turning off each of the transistors MN2i and MN2o, the current mirror circuit of the circuit RL can be stopped, thereby reducing power consumption in the circuit RL.

[0315] In the current mirror circuit of the circuit RL, the source of the transistor MN1i and the source of the transistor MN1o are connected to the wiring VSSL. The current mirror circuit is configured with n-channel transistors, and therefore also functions as a current sink circuit. Therefore, the wiring VSSL functions as a wiring that applies a low-level potential as a low power supply potential of the first current mirror circuit.

[0316] The current source CNI is, for example, a quantity I ＩＢ The transistor MN1o has a function of passing a current of a quantity I from the wiring VDDL to the wiring VSSL via the transistor MN2i and the transistor MN1i. ＩＢ A current of I flows according to the calculation result of the cell array CA. Ｓ When a current of I flows through the wiring WCPL, according to Kirchhoff's current law, the amount of current flowing from the terminal RTo of the circuit RL to the circuit ATDC is I Ｓ and I ＩＢ As the difference current ofＳ -I ＩＢ =I ＯＬ In addition, I Ｓ Ga I ＩＢ When the following condition is satisfied, the current flowing between the source and drain of the transistor MN1o is I ＩＬ And also, I ＯＬ = 0. In other words, the circuit RL shown in FIG. 17 can perform the operation of the ReLU function.

[0317] Also, the circuit ATDC is designed to measure the amount of current I ＯＬ The circuit RL has a function of generating a potential according to the input voltage and applying it to the wiring OL through the output terminal. This allows the result of the operation of the ReLU function performed in the circuit RL to be output as a digital potential to the wiring OL.

[0318] Note that this embodiment mode can be appropriately combined with the same or other embodiment modes described in this specification. For example, the configuration, structure, method, etc. described in this embodiment mode can be appropriately combined with another configuration, structure, method, etc. described in this embodiment mode. Furthermore, for example, the configuration, structure, method, etc. described in this embodiment mode can be appropriately combined with the configuration, structure, method, etc. described in other embodiment modes.

[0319] Embodiment 3 In this embodiment, an example of a schematic plan view and an example of a cross-sectional structure of the semiconductor device described in the above embodiment will be described.

[0320] <Example of Layout of Semiconductor Device> FIG. 18A is a schematic plan view showing an example of the circuit configuration of an arithmetic cell IM included in the arithmetic device CDV, which is a semiconductor device described in the above embodiment.

[0321] The schematic plan view of Fig. 18A shows an example of a circuit layer including calculation cell IM[i] in a plan view, and the circuit layer includes conductive layer 232, conductive layer 233, conductive layer 234, conductive layer 235, and semiconductor layer 251. Note that, to clearly show the schematic plan view, Fig. 18A does not show insulating layers included in the circuit layer.

[0322] 18A , each of the transistors M1, M3, and M4 includes an island-shaped insulating layer, a semiconductor layer 251 formed on the insulating layer, a conductive layer 232 formed on the semiconductor layer 251, a gate insulating film formed on the semiconductor layer 251, and a conductive layer 233 formed on the gate insulating film. Each of the transistors M1, M3, and M4 can have a GL (Gate Last) structure, which will be described later.

[0323] For example, the semiconductor layer 251 is located below the conductive layer 232 and the conductive layer 233. For example, the conductive layer 234 is located above the conductive layer 232 and the conductive layer 233. For example, the conductive layer 235 is located above the conductive layer 234. Note that the order of formation can be as follows: first, the semiconductor layer 251; second, one of the conductive layer 232 and the conductive layer 233; third, the other of the conductive layer 232 and the conductive layer 233; fourth, the conductive layer 234; and fifth, the conductive layer 235.

[0324] 18A , for example, a portion of the conductive layer 232 functions as a source or drain of each of the transistors M1, M3, and M4. For example, a portion of the conductive layer 233 functions as a gate of each of the transistors M1, M3, and M4. For example, the conductive layer 234 functions as a wiring for electrically connecting the conductive layer 232 or the conductive layer 233 to the conductive layer 235. For this reason, the conductive layer 234 may be referred to as a contact plug, for example.

[0325] 18A , a part of the conductive layer 233 functions as one of a pair of electrodes of the capacitor C1, for example, and the conductive layer 235 functions as the other of the pair of electrodes of the capacitor C1, for example.

[0326] 18A , a portion of each of the conductive layers 233 and 235 functions as a wiring. For example, a portion of the conductive layer 233 is provided as a wiring XCL[i]_k and a wiring WSL[i]_k, extending in the left-right direction of the drawing. For example, a portion of the conductive layer 235 is provided as a wiring VEL, a wiring WCL_k, and a wiring VEB, extending in the up-down direction of the drawing. For this reason, it is preferable to use a highly conductive material for each of the conductive layers 233 and 235.

[0327] Each of the above-described conductive layers can be formed by, for example, lithography. Specifically, for example, when forming the conductive layer 232, a conductive material to be the conductive layer 232 can be formed by one or more methods selected from a sputtering method, a chemical vapor deposition (CVD) method, a pulsed laser deposition (PLD) method, and an atomic layer deposition (ALD) method, and then a desired pattern can be formed by lithography. Furthermore, conductive layers, semiconductor layers, and insulating layers other than the conductive layer 232 can also be formed by the same methods as above.

[0328] In this specification, the lithography method includes, for example, photolithography, ion beam lithography, X-ray lithography, electron beam lithography, multiphoton lithography, interference lithography, and nanoimprinting.

[0329] Furthermore, an insulating layer can be provided between the conductive layer 233 and the conductive layer 235. In particular, in the region where the capacitor C1 is provided, the insulating layer formed so as to overlap between the conductive layer 233 and the conductive layer 235 is preferably an insulating layer that functions as a dielectric in the capacitor C1.

[0330] 18A, the capacitance element C1 has a parallel plate structure. Furthermore, the capacitance element C1 can be provided in a region where the wiring XCL extends. This makes it easy to ensure the area for the capacitance element C1, thereby reducing the circuit area of ​​the calculation cell IM[i].

[0331] 18A , the width d1 of the conductive layer 235, which functions as the other of the pair of electrodes of the capacitor C1, is shorter than the width d2 of the conductive layer 233, which functions as one of the pair of electrodes of the capacitor C1. When an insulating layer functioning as a dielectric is formed on the conductive layer 233, the insulating layer may be poorly formed at the edge of the conductive layer 233 or its surrounding area. Specifically, the insulating layer formed at the edge of the conductive layer 233 or its surrounding area may have poor coverage. In this case, if the width d1 of the conductive layer 235 is longer than the width d2 of the conductive layer 233, the edge of the conductive layer 233 or its surrounding area may come into contact with the area of ​​the conductive layer 235 that overlaps it, resulting in a short circuit. For this reason, it is preferable that the width d1 of the conductive layer 235 be shorter than the width d2 of the conductive layer 233.

[0332] Conversely, if the coverage of the insulating layer formed on the edge of the conductive layer 233 or its surrounding area can be increased, it is preferable to make the width d1 longer than the width d2. Specifically, since the capacitance value of a capacitance element is proportional to the area of ​​the region where one of the pair of electrodes, the dielectric, and the other of the pair of electrodes overlap, it is preferable to increase the area of ​​that region if a higher capacitance value is desired. Therefore, by making the width d1 longer than the width d2, the width of that region can be increased from d1 to d2. As a result, the conductive layer 235 is formed above the edge of the conductive layer 233, which increases the area of ​​the other of the pair of electrodes of the capacitance element C1, thereby increasing the capacitance value of the capacitance element C1.

[0333] 1, since the transistors M3 and M4 are connected in series, as shown in the schematic plan view of the operation cell IM in Fig. 18A, the transistors M3 and M4 can be formed so as to share the island-shaped semiconductor layer 251. This makes it possible to reduce the formation area of ​​the operation cell IM, and as a result, it is possible to increase the cell density of the operation cell IM and also to reduce the circuit area of ​​the operation device CDVA.

[0334] 18B , by arranging the transistors M1 and M4 in the vertical direction of the drawing, it becomes easy to provide a wiring (back-gate wiring) that functions as a back-gate electrode for each of the transistors M1 and M4. For example, as shown in FIG. 18B , a conductive layer 231 can be extended as a wiring BGL1, which is a back-gate wiring, below a semiconductor layer 251 including the channel formation regions of the transistors M1 and M4. The conductive layer 231 can also be provided below the semiconductor layer 251 including the channel formation region of the transistor M3. This facilitates routing of the wiring BGL1 and shortens the wiring distance, thereby reducing parasitic resistance and power consumption.

[0335] Note that the schematic plan views of the semiconductor device of one embodiment of the present invention are not limited to those shown in Fig. 18A and Fig. 18B The schematic plan views of the arithmetic circuit of one embodiment of the present invention can be appropriately changed depending on the situation.

[0336] In addition, in the schematic plan views of Figures 18A and 18B, the sizes (including channel lengths and channel widths) of transistors M1, M3, and M4 are shown to be equal to each other, but the sizes of transistors M1, M3, and M4 may be different from each other.

[0337] For example, the channel width of the switching transistor is preferably shorter than the channel width of the amplification transistor. Specifically, in Figures 18A and 18B, the channel width d3 of the transistor M1 is preferably shorter than the channel width d5 ​​of the transistor M3. By shortening the channel width d3 of the transistor M1 that functions as a switching transistor, the off-state current of the transistor M1 can be reduced, and the potential of the gate of the transistor M3 can be held for a long period of time.

[0338] Furthermore, for example, the channel length of the switching transistor is preferably longer than the channel length of the amplification transistor. Specifically, in Figures 18A and 18B, the channel length d4 of the transistor M1 is preferably longer than the channel length d6 of the transistor M3. Increasing the channel length d4 of the transistor M1 that functions as a switching transistor can also reduce the off-state current of the transistor M1.

[0339] Furthermore, for example, the channel width of the amplification transistor is preferably longer than the channel width of the switching transistor. Specifically, the channel width d5 ​​of the transistor M3 is preferably shorter than the channel width d3 of the transistor M1. By shortening the channel width d5 ​​of the transistor M3 that functions as an amplification transistor, the on-current of the transistor M3 can be increased.

[0340] Furthermore, for example, it is preferable that the channel length of the amplification transistor be shorter than the channel length of the switching transistor. Specifically, it is preferable that the channel length d6 of the transistor M3 be shorter than the channel length d4 of the transistor M1. By shortening the channel length d6 of the transistor M3 that functions as an amplification transistor, it is possible to increase the on-current of the transistor M3.

[0341] Furthermore, because transistor M4 functions as a clamp transistor, it is preferable that the channel length d10 of transistor M4 be longer than the channel length d6 of transistor M3. By making the channel length d10 of transistor M4 longer than the channel length d6 of transistor M3, DIBL of transistor M3 can be prevented. Furthermore, even if the channel length d10 of transistor M4 is equal to or shorter than the channel length d6 of transistor M3, DIBL of transistor M3 can be prevented in some cases. Furthermore, because transistor M4 prevents a decrease in the amount of current flowing between the source and drain of transistor M3, it is preferable that the channel width d9 of transistor M4 be longer than the channel width d5 ​​of transistor M3. Furthermore, even if the channel width d9 of transistor M4 is equal to or shorter than the channel length d5 ​​of transistor M3, a decrease in the amount of current flowing between the source and drain of transistor M3 can be prevented in some cases.

[0342] <Example of Cross-Sectional Configuration of Semiconductor Device> Fig. 19 is a schematic cross-sectional view showing an example of the configuration of the arithmetic device CDVA described in the above embodiment. In Fig. 19, the arithmetic device CDVA includes, as an example, a circuit layer PHRL and a circuit layer OMAL located above the circuit layer PHRL.

[0343] 19, the transistor M1 is located above the transistors M3 and M4, so note that the cross-sectional view of FIG. 19 differs in configuration from the plan views of FIG. 18A and FIG. 18B.

[0344] The circuit layer PHRL can be formed by, for example, providing circuit elements such as transistors and capacitors on a substrate. The substrate can be a semiconductor substrate (e.g., a single-crystal substrate made of silicon or germanium). Other than a semiconductor substrate, for example, an SOI (Silicon-On-Insulator) substrate, a glass substrate, a quartz substrate, a plastic substrate, a sapphire glass substrate, a metal substrate, a stainless steel substrate, a substrate having stainless steel foil, a tungsten substrate, a substrate having tungsten foil, a flexible substrate, a laminated film, paper containing a fibrous material, or a base film can be used. In this embodiment, the substrate included in the circuit layer PHRL will be described as a semiconductor substrate having silicon.

[0345] By using a semiconductor substrate made of silicon as the substrate included in the circuit layer PHRL, the transistors included in each of the memory cells IMP_1 to IMP_p, the driver circuit WCD, the driver circuit XCD_k, the driver circuit ITS, the driver circuit WSD_k, and the driver circuit WIOD shown in FIG. 1 can be formed on the semiconductor substrate. In this case, the transistors are Si transistors. Si transistors have high field-effect mobility and can therefore pass large on-currents. This makes it possible to increase the drive speed of each of the driver circuits listed above and to widen the signal range.

[0346] 19 illustrates a transistor 100 included in the circuit layer PHRL as an example of a Si transistor. By using a Si transistor as the transistor 100, a CMOS (Complementary MOS) circuit including a p-channel transistor and an n-channel transistor can be configured in the circuit layer PHRL. In particular, since the memory cells IMP_1 to IMP_p, the driver circuit WCD, the driver circuit XCD_k, and the like described in the above embodiments include a p-channel transistor and an n-channel transistor, the memory cells IMP_1 to IMP_p, the driver circuit WCD, the driver circuit XCD_k, and the like are preferably provided in the circuit layer PHRL as CMOS circuits.

[0347] The stacked structure of the circuit layer PHRL and the circuit layer OMAL can be fabricated by directly forming the circuit layer OMAL on the circuit layer PHRL. Alternatively, the circuit layer OMAL can be fabricated by forming a substrate on which circuit elements such as transistors and capacitors are provided, and then mounting the substrate on the circuit layer PHRL. When the circuit layer OMAL is formed directly on the circuit layer PHRL, the circuit layer OMAL preferably includes an OS transistor. An IO transistor can be used as the OS transistor. Since an OS transistor can be formed on a substrate such as a semiconductor substrate, an insulating substrate, or a conductor substrate, or on a film such as a conductive film, an insulating film, or a semiconductor film, it can be easily provided on a semiconductor substrate (on the circuit layer PHRL) on which a Si transistor is formed.

[0348] Alternatively, the p-channel transistors may be provided as Si transistors in the circuit layer PHRL, and the n-channel transistors may be provided as OS transistors in the circuit layer OMAL. Specifically, for example, the transistors F3 and F4 included in the memory cell IMP_k shown in FIG. 2 may be provided in the circuit layer PHRL, the transistors F1, F5, and F6 included in the memory cell IMP_k may be provided in the circuit layer OMAL, the transistors M1, M3, and M4 included in the calculation cell IM[i] may be provided in the circuit layer OMAL, and the transistors M1d, M3d, and M4d included in the driver cell IMD[i] may be provided in the circuit layer OMAL. The configuration in which the p-channel transistors are provided as Si transistors in the circuit layer PHRL and the n-channel transistors are provided as OS transistors in the circuit layer OMAL can be applied not only to the calculation device CDV shown in FIG. 2 but also to other calculation devices.

[0349] Furthermore, when circuit elements such as transistors and capacitors are formed on a substrate as the circuit layer OMAL and the substrate is mounted on the circuit layer PHRL, flip-chip bonding or wire bonding can be used. Alternatively, a first bonding layer may be provided on the circuit layer PHRL side, a second bonding layer may be provided on the substrate of the circuit layer OMAL, and the first and second bonding layers may be bonded together using one or both of a surface activated bonding method and a hydrophilic bonding method, thereby mounting the circuit layer OMAL on the circuit layer PHRL. In particular, bonding in which copper (Cu) is used as the conductor contained in each of the first and second bonding layers and the copper is bonded to each other is called Cu-Cu (copper-copper) direct bonding.

[0350] The transistor 100 is provided over a substrate 101 and includes a conductive layer 131 that functions as a gate, an insulating layer 161 and an insulating layer 111 that function as gate insulating films, a semiconductor region 171 that includes a part of the substrate 101, and a low-resistance region 172a and a low-resistance region 172b that include a part of the substrate and function as a source region or a drain region.

[0351] 19 is formed by providing an element isolation layer 102 in the substrate 101. The element isolation layer 102 can also be said to be provided to isolate a plurality of transistors formed on the substrate 101. The element isolation layer 102 can be formed by using, for example, a local oxidation of silicon (LOCOS) method, a shallow trench isolation (STI) method, or a mesa isolation method.

[0352] 19 , for example, the semiconductor region 171 (part of the substrate 101) where a channel is formed can have a convex shape, as shown in the cross-sectional view of FIG. 20 . Note that FIG. 20 is a cross-sectional view of the transistor 100 in the channel width direction. A conductive layer 131 is provided to cover the side and top surfaces of the semiconductor region 171 with an insulating layer 161 interposed therebetween. Note that the conductive layer 131 may be made of a material that adjusts the work function. Note that in FIG. 20 , a conductive layer 136 is provided on the conductive layer 131. Note that the conductive layer 136 functions as a contact plug or wiring for connecting to a circuit element located above the transistor 100. Such a transistor 100 is also called a fin-type transistor because it utilizes a convex portion of the semiconductor substrate. Note that an insulating layer may be provided in contact with the top of the convex portion and function as a mask for forming the convex portion. While the case where the convex portion is formed by processing a part of the semiconductor substrate has been described, a semiconductor film having a convex shape may also be formed by processing an SOI substrate.

[0353] Note that the transistor 100 illustrated in FIGS. 19 and 20 is just an example, and the structure is not limited thereto. An appropriate transistor may be used depending on the circuit configuration or driving method.

[0354] The computing device CDV may be provided with a wiring layer provided with an interlayer film, wiring, and plugs. Furthermore, multiple wiring layers may be provided depending on the design. Furthermore, in this specification, the wiring and the plugs connected to the wiring may be integrated. That is, there are cases where a part of the conductive layer functions as the wiring, and cases where a part of the conductive layer functions as the plug.

[0355] For example, an insulating layer 112, an insulating layer 181, and an insulating layer 113 are stacked in this order as an interlayer film over the transistor 100. A conductive layer 132 and the like are embedded in the insulating layer 112. A conductive layer 133 and the like are embedded in the insulating layer 181 and the insulating layer 113. The conductive layer 132 and the conductive layer 133 function as contact plugs or wirings.

[0356] The insulating layer serving as an interlayer film may also serve as a planarizing film that covers the underlying unevenness. For example, the top surface of the insulating layer 112 may be planarized by a planarization treatment using a chemical mechanical polishing (CMP) method to improve the planarity.

[0357] 19, an insulating layer 182, an insulating layer 114, an insulating layer 115, and an insulating layer 116 are stacked in this order over the insulating layer 113 and the conductive layer 133. In addition, a conductive layer 134 is formed in the insulating layer 182, the insulating layer 114, and the insulating layer 115. The conductive layer 134 functions as a contact plug or a wiring.

[0358] An insulating layer 281 is provided on the insulating layer 116. It is preferable that contact plugs or wiring for connecting to an upper circuit (for example, a circuit element included in a circuit included in the circuit layer OMAL) be embedded in the insulating layer 116 and the insulating layer 281.

[0359] Next, a configuration example of the arithmetic cells included in the circuit layer OMAL shown in FIG. 19 will be described.

[0360] 19, the transistors M3 and M4 are formed on an insulating layer 281. The transistor M1 is formed on an insulating layer 284. The capacitance element C1 is formed on an insulating layer 287. The insulating layer 287 is located above the insulating layer 284, and the insulating layer 284 is located above the insulating layer 281. Therefore, it can be said that the capacitance element C1 is located above the transistor M1, and the transistor M1 is located above the transistors M3 and M4.

[0361] 19 preferably functions as a barrier insulating film that suppresses the permeation of impurities such as water and hydrogen. Therefore, the insulating layer 181, the insulating layer 182, the insulating layers 281 to 284, and the insulating layer 287 preferably functions as a barrier insulating film that suppresses the permeation of impurities such as water and hydrogen. Therefore, the insulating layer 181, the insulating layer 182, the insulating layers 281 to 284, and the insulating layer 287 preferably functions as a barrier insulating film that suppresses the permeation of impurities such as water and hydrogen. ２ O, NO or NO ２ It is preferable to use an insulating material that has a function of suppressing the diffusion of impurities such as copper atoms and copper atoms (i.e., through which the impurities are less likely to permeate). Alternatively, it is preferable to use an insulating material that has a function of suppressing the diffusion of oxygen (e.g., oxygen atoms and / or oxygen molecules) (i.e., through which the oxygen is less likely to permeate). Note that for materials that can be applied to the insulating layer 181, the insulating layer 182, the insulating layers 281 to 284, and the insulating layer 287, the description of the insulating layers in the section on constituent materials of transistors can be referred to.

[0362] A conductive layer that becomes a wiring VEL is connected to one of the source electrode or drain electrode of the transistor M3 through a conductive layer 234_1 that functions as a contact plug. The other of the source electrode or drain electrode of the transistor M3 is formed so as to be shared with one of the source electrode or drain electrode of the transistor M4. The other of the source electrode or drain electrode of the transistor M4 is connected to one of the source electrode or drain electrode of the transistor M1 through a conductive layer 234_2, a conductive layer 235_2, and a conductive layer 235_4 that function as contact plugs. Note that in FIG. 19, as an example, a conductive layer that becomes a wiring WCL_k is provided between the conductive layer 234_2 and the conductive layer 235_2.

[0363] Also, the gate electrode of the transistor M1 extends in the front-to-depth direction of FIG. 19 as a conductive layer that becomes the wiring WSL[i]_k, for example.

[0364] 19, for example, a conductive layer that serves as one of a pair of electrodes of the capacitor C1 is provided between the conductive layer 234_1 and the conductive layer 235_3.

[0365] A conductive layer that functions as one of a pair of electrodes of the capacitor C1 is formed so as to be embedded in the insulating layer 219 over the insulating layer 287. An insulating layer 441 that functions as a dielectric of the capacitor C1 is provided above the conductive layer that becomes one of the pair of electrodes of the capacitor C1. A conductive layer that becomes the wiring XCL[i]_k is provided above the insulating layer 441. Note that a region of the conductive layer that becomes the wiring XCL[i]_k, which overlaps with the conductive layer that becomes one of the pair of electrodes of the capacitor C1, functions as the other of the pair of electrodes of the capacitor C1.

[0366] By embedding the conductive layer that functions as one of the pair of electrodes of the capacitor C1 in the insulating layer 219, the conductive layer that functions as one of the pair of electrodes of the capacitor C1 and the insulating layer 219 can be made flush with each other. This allows the insulating layer that functions as a dielectric and the conductive layer that functions as the other of the pair of electrodes of the capacitor C1 to be formed with good flatness on the top surfaces of the conductive layer that functions as one of the pair of electrodes of the capacitor C1 and the insulating layer 219, which already have good flatness. By improving the flatness of both the pair of electrodes of the capacitor C1 and the insulating layer that functions as a dielectric, localized electric field concentration can be suppressed, thereby preventing leakage current between the pair of electrodes of the capacitor C1. Furthermore, one of the pair of electrodes of the capacitor C1 (here, the lower electrode) has a smaller area than the other of the pair of electrodes of the capacitor C1 (here, the upper electrode). This configuration makes it possible to suppress local electric field concentration that can occur in the dielectric film (insulating film sandwiched between a pair of electrodes) of the capacitance element C1, thereby realizing a highly reliable semiconductor device.

[0367] For example, in the computation cell IM[1] of FIG. 2 , by configuring the capacitance element C1 as described above, it is possible to prevent leakage current between the pair of electrodes of the capacitance element C1 that occurs between the gate of the transistor M3 and the wiring XCL[1]_k. Therefore, in the computation cell IM, fluctuations in the potential of the gate of the transistor M3 due to the leakage current can be prevented, and the potential can be maintained for a long period of time. Furthermore, localized electric field concentration on the dielectric of the capacitance element C1 can be suppressed, thereby improving the reliability of the computation cell IM. The same applies to the capacitance element C1d, the driving cell IMD including the capacitance element C1d, and the capacitance element C6 and the memory cell IMP_k including the capacitance element C6.

[0368] In the configuration example of FIG. 19, the conductive layer having the function of the wiring XCL and the conductive layer having the function of the wiring WSL each extend along the front-to-depth direction of FIG. 19.

[0369] As shown in FIG. 19 , a conductive layer functioning as a back gate may be provided below the island-shaped semiconductor layer of each of the transistors M1, M3, and M4. By providing a back gate for each transistor and changing the potential of the back gate, the threshold voltage of the transistor can be changed. For example, providing a back gate for each of the transistors M1, M2, M3, and M5 reduces the influence of an external electric field and allows the transistors to stably maintain an off state. Therefore, data written to the capacitance element C1 can be stably retained. Providing a back gate in this way stabilizes the operation of the calculation cell IM and improves the reliability of the circuit layer OMAL including the calculation cell IM.

[0370] Note that when a back gate is provided in a transistor, it is preferable not to provide a conductive layer near the back gate in order to avoid formation of parasitic capacitance with the back gate.

[0371] Each of the transistors M1, M3, and M4 is preferably a transistor (OS transistor) in which a semiconductor layer in which a channel is formed is made of an oxide semiconductor, which is a type of metal oxide. The band gap of an oxide semiconductor is 2 eV or more, and therefore the off-state current is significantly small. Therefore, the power consumption of the processing cell can be reduced. Therefore, the power consumption of the processing device CDV including the processing cell IM can be reduced.

[0372] Furthermore, OS transistors operate stably even in high-temperature environments and exhibit little fluctuation in their characteristics. For example, the off-state current hardly increases even in high-temperature environments. Specifically, the off-state current hardly increases even in environments at temperatures higher than room temperature (e.g., 25° C.) and lower than 200° C. Furthermore, the on-state current is unlikely to decrease even in high-temperature environments. Furthermore, the arithmetic cell shown in FIG. 19 can retain first data and therefore also functions as a memory device. Therefore, the arithmetic cell operates stably even in high-temperature environments and exhibits high reliability.

[0373] In particular, by using indium oxide as the oxide semiconductor, that is, by using each of the transistors M1, M3, and M4 as an IO transistor, the transistors M1, M3, and M4 can have a small off-state current and a large on-state current, which may enable realization of an arithmetic device that combines high reliability and high operating speed.

[0374] <<Transistor Structure Example 1>> Next, a specific structure example of a transistor called a GL structure (also referred to as a TGSA structure) that can be applied to the transistor M1, the transistor M3, and the transistor M4 shown in Fig. 19 will be described. A transistor 200 shown in Fig. 21A and Fig. 21B is an example of a transistor with a GL structure that can be applied to the transistor M1, the transistor M3, and the transistor M4 shown in Fig. 19. The GL structure will be described later.

[0375] In particular, FIG. 21A shows a schematic cross-sectional view of the transistor 200 in the channel length direction, and FIG. 21B shows a schematic cross-sectional view of the transistor 200 in the channel width direction.

[0376] 21A and 21B , for example, the transistor 200 includes a semiconductor layer 251a, a semiconductor layer 251b, a conductive layer 231, a conductive layer 232a, a conductive layer 232b, a conductive layer 233, an insulating layer 212, insulating layers 261 to 264, insulating layers 281 to 283, and insulating layers 212 to 214. Note that the transistor 200 does not necessarily include all of the above components. For example, the conductive layer 231 functions as a backgate electrode of the transistor 200, but the transistor 200 may not include the conductive layer 231.

[0377] The conductive layer 231 (conductive layer 231a and conductive layer 231b) and the insulating layer 212 are disposed above a substrate (not shown). In particular, the conductive layer 231 is preferably provided so as to be embedded in the insulating layer 212. Specifically, the conductive layer 231a is preferably provided in contact with a bottom surface and a sidewall of an opening provided in the insulating layer 212. The conductive layer 231b is preferably provided so as to be embedded in a recess formed in the conductive layer 231a. Note that in the transistor 200 shown in FIGS. 21A and 21B , the height of the top surface of the conductive layer 231b is approximately the same as the height of the top surface of the conductive layer 231a and the height of the top surface of the insulating layer 212.

[0378] The insulating layer 212 functions as a planarizing film that flattens steps caused by plugs, etc., similar to the insulating layer 112. Therefore, the insulating layer 212 can be made of a material that functions as a planarizing film, similar to the insulating layer 112.

[0379] Furthermore, by using a material with a low dielectric constant for the insulating layer 212, the parasitic capacitance between wirings can be reduced. For example, the insulating layer 212 can be made of silicon oxide, silicon oxynitride, silicon nitride oxide, or silicon nitride. Alternatively, the insulating layer 212 can be made of, for example, silicon oxide doped with fluorine, silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen, or silicon oxide having vacancies. Silicon oxide and silicon oxynitride are particularly preferred because they are thermally stable. Materials such as silicon oxide, silicon oxynitride, or silicon oxide having vacancies are particularly preferred because they can easily form regions containing oxygen that is released by heating. Alternatively, the insulating layer 212 can be made of, for example, a resin. The material used for the insulating layer 212 may be an appropriate combination of the above-mentioned insulating materials.

[0380] In this specification, an oxynitride refers to a material whose composition contains more oxygen than nitrogen, and a nitride oxide refers to a material whose composition contains more nitrogen than oxygen. For example, silicon oxynitride refers to a material whose composition contains more oxygen than nitrogen, and silicon nitride oxide refers to a material whose composition contains more nitrogen than oxygen.

[0381] The semiconductor layer 251 and the conductive layer 233 are disposed in a region overlapping the conductive layer 231. The semiconductor layer 251b is disposed on the semiconductor layer 251a. The conductive layers 232a and 232b are disposed on the semiconductor layer 251b, spaced apart from each other. The insulating layer 213 is disposed on the conductive layers 232a and 232b. In particular, an opening is formed in the insulating layer 213 in a region between the conductive layers 232a and 232b. The conductive layer 233 is disposed in the opening. The insulating layer 264 is disposed between the semiconductor layer 251b, the conductive layers 232a and 232b, and the insulating layer 213 and the conductive layer 233. Here, as shown in FIGS. 21A and 21B , it is preferable that the top surface of the conductive layer 233 substantially coincides with the top surfaces of the insulating layer 264 and the insulating layer 213. Note that hereinafter, the conductive layers 231a and 231b may be collectively referred to as conductive layers 231. The semiconductor layers 251a and 251b may be collectively referred to as semiconductor layers 251. The conductive layers 232a and 232b may be collectively referred to as conductive layers 232.

[0382] 21A , a region 271a may be formed as a low-resistance region at the interface between the semiconductor layer 251b and the conductive layer 232a and in its vicinity. Similarly, a region 271b may be formed as a low-resistance region at the interface between the semiconductor layer 251b and the conductive layer 232b and in its vicinity. In this case, the region 271a functions as one of a source region and a drain region, and the region 271b functions as the other of the source region and the drain region. A channel formation region is formed in a region sandwiched between the region 271a and the region 271b.

[0383] A metal oxide functioning as an oxide semiconductor including a channel formation region is preferably used for the semiconductor layer 251. In particular, indium oxide described in Embodiment 4 is suitable as the metal oxide. Note that in the following, not only indium oxide but also various metal oxides that serve as the channel formation region of the transistor 200 will be described.

[0384] The metal oxide to be used for the channel formation region of the transistor 200 preferably has a band gap of, for example, 2 eV or more, preferably 2.5 eV or more. Specifically, in the case of the transistor 200 in FIGS. 21A and 21B, the semiconductor layer 251 preferably includes a metal oxide that functions as an oxide semiconductor.

[0385] Note that the structure of a metal oxide can be divided into a single crystal structure and other structures (non-single crystal structures). Examples of non-single crystal structures include a c-axis aligned crystalline (CAAC) structure, a polycrystalline (polycrystalline) structure, a nanocrystalline (nc) structure, a pseudo-amorphous (a-like) structure, and an amorphous structure. The structure of the metal oxide of one embodiment of the present invention is not particularly limited, and any of the above structures may be used. However, the use of a crystalline metal oxide, typified by a CAAC structure or an nc structure, is preferable because a highly reliable semiconductor device can be obtained.

[0386] The metal oxide preferably contains at least indium. It may also contain indium and zinc. In addition to these, it may also contain element M. The element M may be one or more selected from aluminum, gallium, silicon, yttrium, tin, copper, vanadium, chromium, manganese, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, calcium, strontium, barium, cobalt, and antimony. In particular, the element M may be one or more selected from aluminum, gallium, yttrium, and tin. It is more preferable that the element M contains one or both of gallium and tin.

[0387] Examples of the metal oxide include indium oxide (also referred to as indium oxide, or IO), gallium oxide (also referred to as gallium oxide), zinc oxide (also referred to as zinc oxide), indium zinc oxide (In-Zn oxide), indium tin oxide, indium titanium oxide, indium gallium oxide (In-Ga oxide), indium gallium aluminum oxide, indium gallium tin oxide, gallium zinc oxide, aluminum zinc oxide, indium aluminum zinc oxide, indium tin zinc oxide, indium titanium zinc oxide, indium gallium zinc oxide (In-Ga-Zn oxide, also referred to as IGZO), indium gallium tin zinc oxide, and indium gallium aluminum zinc oxide. Alternatively, examples of the metal oxide include indium tin oxide, gallium tin oxide, and aluminum tin oxide containing silicon.

[0388] As described above, the metal oxide preferably contains indium. Specifically, it is preferable to use indium oxide as the metal oxide. It is particularly preferable to use crystalline indium oxide.

[0389] The metal oxide can be preferably formed by sputtering or ALD. When the metal oxide is formed by sputtering, a film with high crystallinity or high film density can be formed. Furthermore, when the metal oxide is formed by ALD, atoms can be deposited layer by layer, which has the advantages of enabling film formation with fewer defects such as pinholes, film formation with excellent coverage, and film formation at low temperatures. After the metal oxide is formed, it is preferable to perform an impurity removal treatment to remove impurities (typically, impurities such as water, hydrogen, carbon, and nitrogen) from the metal oxide film. Examples of impurity removal treatments include plasma treatment, microwave plasma treatment, and heat treatment.

[0390] In this specification, microwaves refer to electromagnetic waves having a frequency of 300 MHz to 300 GHz. Microwave plasma treatment refers to treatment using a device with a power source that generates high-density plasma using microwaves. Microwave plasma treatment can also be called microwave-excited high-density plasma treatment.

[0391] Note that the transistor 200 has a two-layer structure of the semiconductor layer 251a and the semiconductor layer 251b stacked in the region where a channel is formed (hereinafter also referred to as the channel formation region) and in the vicinity thereof, but the present invention is not limited to this. For example, the semiconductor layer 251b may have a single-layer structure or a stacked structure of three or more layers. Furthermore, each of the semiconductor layer 251a and the semiconductor layer 251b may have a stacked structure of two or more layers.

[0392] The conductive layer 233 functions as a first gate electrode (sometimes referred to as a top gate electrode or a front gate electrode) of the transistor, and as described above, the conductive layer 232a and the conductive layer 232b function as a source electrode and a drain electrode, respectively. As described above, the conductive layer 233 is formed so as to be embedded in the opening of the insulating layer 213 and in the region sandwiched between the conductive layer 232a and the conductive layer 232b. Here, the conductive layer 233, the conductive layer 232a, and the conductive layer 232b are formed in a self-aligned manner with respect to the opening of the insulating layer 213. That is, in the transistor 200, the first gate electrode can be disposed between the source electrode and the drain electrode in a self-aligned manner. Therefore, the conductive layer 233 can be formed without providing a margin for alignment, which reduces the area occupied by the transistor 200. This allows the density of arithmetic cells in the arithmetic device to be increased.

[0393] Note that the transistor 200 can be formed by forming an island-shaped stack of layers over an insulating layer 262, the stack of layers including an insulating layer 263 (described later), a semiconductor layer 251, and a conductive layer that will become the conductive layer 232a and the conductive layer 232b. Next, an insulating layer 282 and an insulating layer 213 (collectively referred to here as an interlayer film) are stacked in this order above the island-shaped stack of layers and above the insulating layer 262. An opening is then formed in a region of the insulating layer 213 that overlaps the island-shaped stack of layers, and an insulating layer 264 and a conductive layer 233 are provided in this order in the opening. In particular, it is preferable to simultaneously form the conductive layer 232a and the conductive layer 232b by forming the opening in the insulating layer 213. In this manner, a transistor structure in which an opening reaching the island-shaped stack of layers and an interlayer film are formed in the interlayer film, and a conductive layer that will become the first gate electrode of the transistor is provided to fill the opening is referred to as a GL structure in this specification. Such a structure may also be called a TGSA structure.

[0394] 21A and 21B , the conductive layer 233 is shown as having a two-layer structure. Here, the conductive layer 233 preferably includes a conductive layer 233a and a conductive layer 233b disposed on the conductive layer 233a. For example, the conductive layer 233a is preferably disposed so as to surround the bottom and side surfaces of the conductive layer 233b. In this case, it is preferable to use a conductive material that is resistant to oxidation or a conductive material that has a function of suppressing oxygen diffusion as the conductive layer 233a.

[0395] The conductive layer 233a is preferably made of a conductive material that has a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules, and copper atoms. Alternatively, it is preferably made of a conductive material that has a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms and oxygen molecules). Furthermore, since the conductive layer 233a has a function of suppressing the diffusion of oxygen, it is possible to suppress a decrease in conductivity due to oxidation of the conductive layer 233b caused by oxygen contained in the insulating layer 213 or the like. As a conductive material that has a function of suppressing the diffusion of oxygen, for example, titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, ruthenium oxide, or the like is preferably used.

[0396] The conductive layer 233b is preferably a conductive layer with high conductivity. For example, the conductive layer 233b can be formed using a conductive material containing tungsten, copper, or aluminum as a main component. The conductive layer 233b may have a stacked structure, for example, a stacked structure of titanium or titanium nitride and the above-mentioned conductive material.

[0397] For the conductive layers 232a and 232b, it is preferable to use, for example, a conductive material that is resistant to oxidation or a conductive material that has a function of suppressing oxygen diffusion. Examples of such conductive materials include a conductive material containing nitrogen and a conductive material containing oxygen. This can suppress a decrease in the conductivity of the conductive layers 232a and 232b. When a conductive material containing metal and nitrogen is used for the conductive layers 232a and 232b, the conductive layers 232a and 232b become conductive layers containing at least metal and nitrogen. For example, a conductive material that is resistant to oxidation or a conductive material that has a function of suppressing oxygen diffusion can be selected from the materials that can be used for the conductive layers 233a and 233b described above.

[0398] The conductive layer 235a and the conductive layer 235b can be formed using a conductive material containing tungsten, copper, or aluminum as a main component. The conductive layer 235a and the conductive layer 235b can have a stacked structure including multiple layers. In particular, the stacked structure is preferably a structure in which a conductive material having a function of suppressing permeation of impurities such as water and hydrogen and a material with high conductivity are stacked.

[0399] The conductive layer 231 may function as a second gate electrode (also referred to as a bottom gate electrode or a back gate electrode). In this case, the potential applied to the conductive layer 231 may be changed independently of the potential applied to the conductive layer 233, thereby reducing the threshold voltage V ｔｈ In particular, by applying a negative potential to the conductive layer 231, the V ｔｈTherefore, when a negative potential is applied to the conductive layer 231, the drain current when the potential applied to the conductive layer 233 is 0 V can be made smaller than when no negative potential is applied.

[0400] The conductive layer 231 is preferably provided to be larger than the channel formation region in the semiconductor layer 251. In particular, as shown in Fig. 21B, the conductive layer 231 preferably extends as a wiring also in a region outside the end portion intersecting with the channel width direction of the semiconductor layer 251. That is, outside the side surface of the semiconductor layer 251 in the channel width direction, the conductive layer 231 and the conductive layer 233 preferably overlap with each other with an insulating layer interposed therebetween.

[0401] 21A, the conductive layer 233 preferably includes a conductive layer 233a provided inside the insulating layer 264 and a conductive layer 233b provided so as to be embedded inside the conductive layer 233a. Although the conductive layer 233 is shown as having a two-layer stacked structure in FIGS. 21A and 21B, the present invention is not limited to this. For example, the conductive layer 233 may have a single-layer structure or a stacked structure of three or more layers.

[0402] For the conductive layer 231 and the conductive layer 233, for example, the above-described materials applicable to the conductive layer 232a and the conductive layer 232b can be selected and used.

[0403] 21A and 21B , the transistor 200 preferably includes an insulating layer 211 disposed on a substrate (not shown), an insulating layer 281 disposed on the insulating layer 211, an insulating layer 212 disposed on the insulating layer 281, a conductive layer 231 disposed so as to be embedded in the insulating layer 212, an insulating layer 261 disposed on the insulating layer 212 and the conductive layer 231, an insulating layer 262 disposed on the insulating layer 261, and an insulating layer 263 disposed on the insulating layer 262. A semiconductor layer 251 a is preferably disposed on the insulating layer 263.

[0404] 21A and 21B, an insulating layer 282 is preferably disposed between the insulating layer 262, the insulating layer 263, the semiconductor layer 251a, the semiconductor layer 251b, the conductive layer 232a, and the conductive layer 232b and the insulating layer 213. Here, the insulating layer 282 is preferably in contact with the side surfaces of the insulating layer 264, the top and side surfaces of the conductive layer 232a, the top and side surfaces of the conductive layer 232b, the side surfaces and top surfaces of the semiconductor layer 251a, the semiconductor layer 251b, and the insulating layer 263, and the top surface of the insulating layer 262, as shown in FIG.

[0405] The insulating layer 264 functions as a first gate insulating film in the transistor 200. The insulating layers 261 to 263 function as second gate insulating films. For these gate insulating films, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine has been added, silicon oxide to which carbon has been added, silicon oxide to which carbon and nitrogen have been added, or silicon oxide having vacancies can be used. In addition to the above, for example, aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO ３ ) or (Ba,Sr)TiO ３ An insulating layer containing a so-called high-k material such as BST can be used as a single layer or a stacked layer. Aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to the insulating layer material. Alternatively, these insulating layers may be nitrided.

[0406] An insulating layer 283 and an insulating layer 214 which function as interlayer films are preferably provided over the transistor 200. Here, the insulating layer 283 is preferably provided in contact with top surfaces of the conductive layer 233, the insulating layer 264, and the insulating layer 213. In this case, the top surface of the insulating layer 213 is preferably planarized.

[0407] It is preferable to provide a conductive layer 235 (conductive layer 235a and conductive layer 235b) that is connected to the transistor 200 and functions as a plug. For this reason, the conductive layer 235 is provided in contact with inner walls of the openings of the insulating layer 282, the insulating layer 213, the insulating layer 283, and the insulating layer 214. In particular, a first conductive layer of the conductive layer 235 may be provided in contact with the inner walls, and a second conductive layer of the conductive layer 235 may be provided on a side surface of the first conductive layer. Here, the height of the top surface of the conductive layer 235 can be made approximately the same as the height of the top surface of the insulating layer 214.

[0408] Specifically, for example, a first conductive layer of the conductive layer 235a is provided in contact with one of the inner walls of two openings of the insulating layer 214, the insulating layer 283, the insulating layer 213, and the insulating layer 282, and a second conductive layer of the conductive layer 235a is formed in contact with the side surface thereof. Note that the conductive layer 232a is located at a part of the bottom of the opening, and the conductive layer 235a is in contact with the conductive layer 232a. Similarly, for example, a first conductive layer of the conductive layer 235b is provided in contact with the other inner wall of the two openings of the insulating layer 214, the insulating layer 283, the insulating layer 213, and the insulating layer 282, and a second conductive layer of the conductive layer 235b is formed in contact with the side surface thereof. Note that the conductive layer 232b is located at a part of the bottom of the opening, and the conductive layer 235b is in contact with the conductive layer 232b.

[0409] Note that although the transistor 200 shows a structure in which the first conductive layer of the conductive layer 235 and the second conductive layer of the conductive layer 235 are stacked, the present invention is not limited to this. For example, the conductive layer 235 may be provided as a single layer or a stacked structure of three or more layers. When the structure has a stacked structure, the structures may be distinguished by assigning ordinal numbers to the order of formation.

[0410] 21B , in a region of the semiconductor layer 251b that does not overlap with the conductive layer 232, in other words, in the channel formation region of the semiconductor layer 251, the side surface of the semiconductor layer 251 is arranged to be covered with the conductive layer 233. This makes it easier for the electric field of the conductive layer 233, which functions as the first gate electrode, to act on the side surface of the semiconductor layer 251, and as a result, the channel formation region of the semiconductor layer 251 can be electrically surrounded by the electric field of the conductive layer 233. This increases the on-state current of the transistor 200 and improves its frequency characteristics.

[0411] For example, the insulating layer 213 preferably has a lower dielectric constant than the insulating layer 262. By using a material with a low dielectric constant as an interlayer film, parasitic capacitance occurring between wirings can be reduced. For this reason, the insulating layer 213 can be made of a material with a low dielectric constant that can be used for the insulating layer 212.

[0412] 19 , which illustrates a structural example of an arithmetic device that is a semiconductor device of one embodiment of the present invention, the transistors M1, M3, and M4 are each described as having a GL structure. Note that the structures of the transistors M1, M3, and M4 according to one embodiment of the present invention are not limited thereto. Instead of the GL structure, the transistors M1, M3, and M4 according to one embodiment of the present invention can each have a vertical channel transistor structure described below, for example.

[0413] 22A to 22C show examples of the configuration of a vertical channel transistor. In a vertical channel transistor, the source electrode and the drain electrode are located at different heights, and the current flowing through the semiconductor layer flows in the height direction. In other words, the channel length direction can be said to have a component in the height direction (vertical direction).

[0414] 22A to 22C may also be called a VFET (Vertical Field Effect Transistor), a vertical transistor, a vertical channel transistor, or the like, other than a vertical channel transistor. In this specification, in a vertical channel transistor, one of the source electrode and the drain electrode located at the bottom may be referred to as a lower electrode. In addition, the other of the source electrode and the drain electrode located at the top may be referred to as an upper electrode.

[0415] In particular, Fig. 22A shows a schematic plan view of an example of a transistor 300, which is a vertical channel transistor, and Figs. 22B and 22C show schematic cross-sectional views of the transistor 300. Fig. 22B is a schematic cross-sectional view taken along dashed line A1-A2 in Fig. 22A, and Fig. 22C is a schematic cross-sectional view taken along dashed line A3-A4 in Fig. 22A. Fig. 22B shows an excerpt of the transistor included in the circuit layer OMAL. Fig. 23 shows a schematic perspective view of the transistor 300 shown in Figs. 22A to 22C and the surrounding wiring.

[0416] 22A to 22C and 23 includes, as an example, a conductive layer 331 that functions as a wiring or an electrode, a conductive layer 332 that functions as a wiring or an electrode, a semiconductor layer 351 that is an active layer of the transistor 300, an insulating layer 361 that functions as a gate insulating film of the transistor 300, a conductive layer 333 that functions as a gate of the transistor 300, and a conductive layer 334 that functions as a wiring.

[0417] The conductive layer 331 is provided above the insulating layer 311, which functions as an interlayer film. Furthermore, the conductive layer 331 functions as wiring, and therefore extends along the direction of the dashed dotted line A3-A4 in the schematic plan view of FIG. 22A .

[0418] For example, a conductive layer that can be applied to the above-described transistors M1, M3, and M4 can be used for the conductive layer 331. The same applies to conductive layers 332 to 334 described later.

[0419] An insulating layer 312 functioning as an interlayer film and a conductive layer 332 are formed in this order on the insulating layer 311 and the conductive layer 331. The conductive layer 332 functions as a wiring and therefore extends along the direction of the dashed dotted line A1-A2 in the schematic plan view of FIG.

[0420] Furthermore, openings reaching the conductive layer 331 are formed in the insulating layer 312 and the conductive layer 332 in regions overlapping with the conductive layer 331. A semiconductor layer 351 is formed on the side surfaces and bottom of the openings. That is, the semiconductor layer 351 is formed on the top surface of the conductive layer 331, the side surfaces of the insulating layer 312, and the side surfaces of the conductive layer 332. The semiconductor layer 351 is also formed on part of the top surface of the conductive layer 332. An insulating layer 361 is provided so as to be in contact with the conductive layer 332, the semiconductor layer 351, and the insulating layer 312 inside and outside the openings. A conductive layer 333 is formed on the top surface and side surfaces of the insulating layer 361 so as to fill the openings.

[0421] An insulating layer 313 functioning as an interlayer film is formed on the top surface of the insulating layer 361 and the top surface of the conductive layer 333. An opening reaching the conductive layer 333 is formed in the insulating layer 313 in a region overlapping with the conductive layer 333. A conductive layer 334 is embedded in the side surface and bottom of the opening. Note that part of the conductive layer 334 may be formed on the top surface of the insulating layer 313. The insulating layer 314 functioning as an interlayer film is formed on the insulating layer 313 and the conductive layer 334.

[0422] Furthermore, the conductive layer 334 functions as wiring and therefore extends along the direction of the dotted line A3-A4 in the schematic plan view of FIG. 22A.

[0423] For example, an insulating material with a low dielectric constant is preferably used for the insulating layers 311 to 314. By using an insulating material with a low dielectric constant as an interlayer film, parasitic capacitance occurring between wirings can be reduced. For this reason, the insulating layers 311 to 314 can each be made of a material that can be used for the insulating layer 212 or the insulating layer 213 described above.

[0424] The insulating layer 361 has a function as a gate insulating film, and therefore, for example, the material that can be used for the insulating layer 264 can be used for the insulating layer 361 .

[0425] Part of the conductive layer 331 functions as one of the source electrode and the drain electrode of the transistor 300. Part of the conductive layer 332 functions as the other of the source electrode and the drain electrode of the transistor 300. Part or all of the conductive layer 333 functions as a gate electrode of the transistor 300.

[0426] As described above, by forming the insulating layer, the conductive layer, and the semiconductor layer, a vertical channel transistor can be formed in which the channel length direction has a component in the height direction (vertical direction). The channel length of the transistor 300 depends on the film thickness of the insulating layer 312. The thinner the insulating layer 312, the shorter the channel length, and therefore the larger the on-current of the transistor 300 can be. On the other hand, the thicker the insulating layer 312, the longer the channel length, and therefore the smaller the off-current of the transistor 300 can be.

[0427] Furthermore, the wirings connecting the source, drain, or gate of the vertical channel transistor are not formed in the same process but in different processes. As a result, the wirings connecting the source, drain, or gate of the vertical channel transistor have overlapping regions in a plan view. Since the wirings connecting the source, drain, or gate of the vertical channel transistor are provided at different heights, the parasitic capacitance generated in each wiring can be reduced. This allows the driving frequency of the transistor 300 to be increased, and the driving speed of the arithmetic unit CDV, etc., to be increased.

[0428] Note that this embodiment mode can be appropriately combined with the same or other embodiment modes described in this specification. For example, the configuration, structure, method, etc. described in this embodiment mode can be appropriately combined with another configuration, structure, method, etc. described in this embodiment mode. Furthermore, for example, the configuration, structure, method, etc. described in this embodiment mode can be appropriately combined with the configuration, structure, method, etc. described in other embodiment modes.

[0429] Embodiment 4 In this embodiment, indium oxide that can be used as the metal oxide of the channel formation region of the IO transistor according to one embodiment of the present invention described in the above embodiment will be described.

[0430] In this specification and the like, indium oxide having at least a crystalline portion or a crystalline region in a film is referred to as crystalline indium oxide (crystal IO) or crystalline indium oxide (crystalline IO). Examples of crystalline IO or crystalline IO include single-crystalline indium oxide, polycrystalline indium oxide, and microcrystalline indium oxide.

[0431] Indium oxide is a semiconductor material having physical properties that are completely different from those of oxide semiconductors such as In—Ga—Zn oxide (hereinafter also referred to as IGZO) and zinc oxide.

[0432] The carrier concentration dependence of the Hall mobility of indium oxide, silicon, and IGZO will be explained. Figure 24A shows the carrier concentration dependence of the Hall mobility of silicon (Si) and indium oxide (InO Ｘ ) and FIG. 24B is a schematic diagram showing the carrier concentration dependence of the hole mobility for IGZO.

[0433] First, IGZO tends to exhibit higher hole mobility as the carrier concentration increases, as shown by the arrows in Figure 24B. On the other hand, indium oxide tends to exhibit higher hole mobility as the carrier concentration decreases, as shown by the arrows in Figure 24A (see Non-Patent Document 3). This trend is similar to that of silicon; the lower the dopant (impurity) concentration in the material, the less impurity scattering there is and the higher the hole mobility. In other words, the higher the purity and intrinsic indium oxide, the higher the hole mobility. From these results, it can be said that indium oxide, unlike IGZO, is a material with physical properties similar to those of silicon. Note that the characteristics of indium oxide shown in Figure 24A are assumed to be single crystal. Therefore, when indium oxide is non-single crystal (e.g., polycrystalline), the characteristics may differ from those shown in Figure 24A.

[0434] 24A, the range R1 of low carrier concentration has extremely high hole mobility, and therefore can be said to be a range of carrier concentration suitable for the channel formation region of a transistor. For example, in the case of indium oxide, the range R1 is a range where the carrier concentration value is 1×10 １５ cm −３ The range includes, for example, 1×10 １４ cm −３ That's it, 1 x 10 １８ cm −３ By sufficiently reducing the carrier concentration, the Hall mobility value can be increased to 270 cm ２ It is expected that the resistance can be increased to about / (V·s).

[0435] In addition, in indium oxide, the region where the carrier concentration is in the range R1 may contain an element that lowers the carrier concentration. Examples of elements that lower the carrier concentration include magnesium, calcium, zinc, cadmium, and copper. By substituting these elements for indium, the carrier concentration can be lowered. Examples of elements that lower the carrier concentration include nitrogen, phosphorus, arsenic, and antimony. For example, by substituting nitrogen, phosphorus, arsenic, or antimony for oxygen, the carrier concentration can be lowered.

[0436] On the other hand, the range R2 with a high carrier concentration has a low electrical resistance, and can be said to be a range of carrier concentrations suitable for, for example, the source and drain regions of a transistor, a resistor, or a transparent conductive film. ２０ cm −３ The range includes, for example, 1×10 １９ cm −３ That's it, 1 x 10 ２２ cm −３ By increasing the carrier concentration sufficiently, the resistivity can be reduced to 1×10 −４ It is expected that the resistivity can be reduced to Ω·cm or less.

[0437] In the indium oxide, the region having a carrier concentration in the range R2 may contain an element that increases the carrier concentration. For example, it is preferable that the indium oxide contains an element that is common to the source electrode and drain electrode of the transistor. Examples of elements that increase the carrier concentration include titanium, zirconium, hafnium, tantalum, tungsten, molybdenum, tin, silicon, and boron. In particular, it is more preferable to use an element whose oxide has conductive or semiconductive properties. In addition to the above elements, examples include elements contained in the conductive layer that can be used for the source electrode or drain electrode of the transistor, as described in Embodiment 3.

[0438] In this way, indium oxide uses a region with a low carrier concentration as the channel formation region of a transistor, and a region with a high carrier concentration as the source and drain regions of the transistor. In other words, indium oxide can be said to be an oxide capable of valence electron control. Note that IGZO may experience strain in the source and drain regions due to stress from electrodes in contact with the IGZO, resulting in the formation of n-type regions. On the other hand, unlike IGZO, indium oxide is capable of valence electron control, and therefore does not require strain to be formed in the film as with IGZO. Less strain in the film is expected to improve reliability. For example, by separately creating a region with a carrier concentration in the range R1 shown in FIG. 24A and a region with a carrier concentration in the range R2 in the indium oxide film, a so-called n-i-n junction (a junction between an n-type region, an i-type region, and an n-type region) can be created. Note that valence electron control in transistors using silicon is generally known. On the other hand, valence electron control in transistors using indium oxide is a novel technical concept that would not normally be conceived.

[0439] By using the above technical concept, the transistor having indium oxide in this specification and the like has two or more, preferably three or more, more preferably four or more, and most preferably five of the following characteristics (1) to (5): (1) high on-current (in other words, high mobility); (2) low off-current; (3) normally-off operation; (4) high reliability; and (5) high cutoff frequency (fT). For example, the transistor having indium oxide in this specification and the like has high mobility, low off-current, and is normally-off operation. The transistor has high mobility and is different from a normally-on transistor.

[0440] Next, an indium oxide film applied to a transistor will be described. The indium oxide film preferably has crystallinity (i.e., has crystal grains). Examples of films having crystal grains include single-crystal films, polycrystalline films, and amorphous films containing crystal grains (also called microcrystalline films). In particular, the indium oxide film is preferably a polycrystalline film, and more preferably a single-crystal film. A single-crystal film does not have grain boundaries. Impurities (typically, insulating impurities, insulating oxides, etc.) that hinder carrier flow tend to segregate at grain boundaries. The use of a single-crystal film can suppress carrier scattering at grain boundaries, thereby realizing a transistor exhibiting high field-effect mobility. Furthermore, the use of a single-crystal film has the excellent effect of suppressing variations in transistor characteristics due to the grain boundaries.

[0441] Furthermore, polycrystalline films are preferable because they can reduce carrier scattering and exhibit high field-effect mobility compared to microcrystalline or amorphous films. When using a polycrystalline film, it is preferable to use a film with as large a crystal grain size as possible and with few crystal grain boundaries. Note that in a transistor using an indium oxide polycrystalline film, if there is no crystal grain boundary in the channel formation region or no crystal grain boundary is observed, the channel formation region is located within a single crystal region included in the polycrystalline film, and therefore the transistor can be considered to be using single-crystal indium oxide.

[0442] The crystallinity of indium oxide can be analyzed by, for example, X-ray diffraction (XRD), transmission electron microscope (TEM), or electron diffraction (ED). Alternatively, a combination of these methods may be used for analysis.

[0443] In this specification and the like, a semiconductor layer in which no crystal grain boundary is observed in the channel formation region, a semiconductor layer in which the channel formation region is included in one crystal grain, or a semiconductor layer in which the crystal axis direction is the same in at least two regions in the channel formation region can be called a single crystal film. Also, a semiconductor layer in which, in the channel formation region, within one crystal grain, the direction of another crystal axis continuously changes around a certain crystal axis or a certain crystal orientation as the axis of rotation can be called a single crystal film.

[0444] The channel formation region refers to a region of the semiconductor layer that overlaps (or faces) the gate electrode via the gate insulating layer, and is located between the region in contact with the source electrode and the region in contact with the drain electrode. The current path in the channel formation region is the shortest distance between the source electrode and the drain electrode. Therefore, the crystal grains, crystal grain boundaries, crystal axes, crystal orientation, etc. in the channel formation region can be confirmed by observing a cross section including the semiconductor layer, the source electrode, and the drain electrode.

[0445] The indium oxide film in the channel formation region preferably has a lower impurity concentration. Impurities in the indium oxide film in the channel formation region can be a scattering source of carriers, which can lead to a decrease in field-effect mobility. These impurities can also hinder the crystal growth of the indium oxide film. Examples of impurities in the indium oxide film include boron and silicon. The indium oxide film preferably contains these impurities at concentrations of 0.1% or less, and more preferably 0.01% (100 ppm) or less. Carbon, hydrogen, and other elements may be contained in the film-forming gas or precursor during film formation, and may remain in the indium oxide film in greater amounts than the above-mentioned impurities.

[0446] The indium oxide film in the channel formation region may contain an element that can become the same trivalent cation as indium, as long as the crystal maintains a cubic crystal structure (bixbyite type). Examples of such an element include Group 13 elements of the periodic table, such as gallium and aluminum, and Group 3 elements of the periodic table. These elements exist mainly as trivalent cations in oxides, and therefore the carrier concentration of indium oxide can be maintained low.

[0447] By using such an indium oxide film in a transistor, the field effect mobility of the transistor can be increased to 50 cm ２ / (V·s) or more, preferably 100 cm ２ / (V·s) or more, more preferably 150 cm ２ / (V·s) or more, more preferably 200 cm ２ / (V·s) or more, more preferably 250 cm ２ / (V·s) or more.

[0448] One of the features of an indium oxide film is that it has higher oxygen permeability (diffusibility) than an IGZO film. As shown in FIG. 24C, an indium oxide film (InO Ｘ Oxygen (O) diffusing into the indium oxide film passes through the indium oxide film and becomes oxygen molecules (O ２ ) and is released as water molecules (H ２ O) may be released in the film. Ｏ In the case where an indium oxide film is present, oxygen atoms diffuse to compensate for the oxygen vacancies. Since oxygen diffuses easily in the indium oxide film, it can be said that oxygen vacancies are more easily compensated for in the indium oxide film than in the IGZO film.

[0449] As described above, an indium oxide film can more easily reduce oxygen vacancies in the film than an IGZO film. Therefore, by using such an indium oxide film in a transistor, a transistor exhibiting extremely high reliability can be realized.

[0450] Furthermore, as shown in FIG. 24C, the indium oxide film diffuses hydrogen. Hydrogen that diffuses into the indium oxide film from the outside passes through the indium oxide film and becomes hydrogen molecules (H ２ ) or, as mentioned above, reacts with oxygen contained in the film and is released as water molecules.

[0451] A transistor using an indium oxide film is an accumulation-type transistor that uses electrons as majority carriers. Assuming that the carrier relaxation time is constant, the smaller the effective mass of the electrons (carriers), the higher the electron mobility. In other words, by using indium oxide, which has a small effective mass of electrons, for a transistor, the on-state current or field-effect mobility of the transistor can be increased.

[0452] The table below shows the properties of single crystal indium oxide (here, In ２ O ３ ) and single-crystal silicon (Si). As shown in the table below, indium oxide is characterized by a small effective mass of electrons and a large effective mass of holes. Indium oxide also has the characteristic that the effective mass of electrons is almost independent of the crystal orientation. Therefore, by using crystalline indium oxide in a transistor, a transistor with high field-effect mobility and high frequency characteristics (also called f characteristics) can be realized. Furthermore, because the effective mass of holes is large, a transistor with extremely small off-current can be realized. For example, by applying an indium oxide film to a vertical transistor, the off-current per 1 μm of channel width can be reduced to 1 fA (1×10) in an environment of 125° C. −１５ A) or less, or 1aA (1 x 10 −１８ A) or less, and under room temperature (25°C) conditions, −１８ A) or less, or 1zA (1 x 10 −２１ Furthermore, as shown in the table below, indium oxide has a smaller effective mass of electrons and a larger effective mass of holes than silicon, and therefore may be able to realize a transistor with higher field-effect mobility and lower off-state current than a Si transistor.

[0453]

[0454] It is preferable to provide a seed layer so as to be in contact with at least a portion of the crystalline indium oxide film. The seed layer is preferably made of a material containing crystals with a small difference in lattice constant (also called lattice mismatch) with indium oxide. This can improve the crystallinity of the indium oxide film. Note that a substrate (e.g., a single-crystal substrate) may be used as one of the layers in contact with at least a portion of the crystalline indium oxide film.

[0455] One method for evaluating the degree of lattice mismatch is to use the value of the lattice mismatch shown below. The lattice mismatch Δa [%] of the crystals of the formed film (here, the indium oxide film) with respect to the crystals of the seed layer is expressed as Δa = ((L １ -L ２ ) / L ２ ) × 100, where L １ is the length or lattice constant of the unit lattice vector of the crystal of the formed film, and L ２ is the length of the unit cell vector or the lattice constant of the crystal of the seed layer.

[0456] The smaller the absolute value of the lattice mismatch Δa between the seed layer and the indium oxide film, the more preferable, and it is most preferably 0. For example, Δa can be set to −5% or more and 5% or less, preferably −4% or more and 4% or less, more preferably −3% or more and 3% or less, and even more preferably −2% or more and 2% or less.

[0457] Here, the indium oxide crystal has a cubic crystal structure (bixbyite type). For example, the crystal of yttria-stabilized zirconia (YSZ) can have a cubic crystal structure (fluorite type). The lattice mismatch of the indium oxide crystal with the cubic YSZ crystal is in the range of −2% to 2%, and a single crystal film of indium oxide can be epitaxially grown on the YSZ substrate.

[0458] It should be noted that the crystal structure of the seed layer and the crystal structure of the indium oxide film may not necessarily have the same crystal system or crystal orientation. For example, a film having crystals of a hexagonal or trigonal structure may be used under an indium oxide film having crystals of a cubic structure. For example, by setting the crystal orientation of the surface of the seed layer to

[001] and the crystal orientation of the underside of the indium oxide film to

[111] , the requirements related to the crystal orientation necessary for epitaxial growth can be satisfied. Examples of hexagonal or trigonal crystals include wurtzite structure, YbFe ２ O ４ Type structure, Yb ２ Fe ３ O ７ YbFeFe alloys have the following structures: ２ O ４ Type structure or Yb ２ Fe ３ O ７ An example of a crystal having a ZnO-type structure is IGZO.

[0459] Note that this embodiment mode can be appropriately combined with the same or other embodiment modes described in this specification. For example, the configuration, structure, method, etc. described in this embodiment mode can be appropriately combined with another configuration, structure, method, etc. described in this embodiment mode. Furthermore, for example, the configuration, structure, method, etc. described in this embodiment mode can be appropriately combined with the configuration, structure, method, etc. described in other embodiment modes.

[0460] In this embodiment, an electronic component that can use the semiconductor device described in the above embodiment will be described. An electronic component that uses the semiconductor device of one embodiment of the present invention is effective in achieving high performance, such as low power consumption.

[0461] [Electronic Component] Fig. 25A shows a perspective view of electronic component 1700. Electronic component 1700 shown in Fig. 25A has substrate 1701, semiconductor device 1710 on substrate 1701, and mold 1711. In particular, semiconductor device 1710 is sealed by mold 1711. Note that Fig. 25A omits some parts in order to show the inside of electronic component 1700.

[0462] The substrate 1701 may be, for example, a ceramic substrate, a plastic substrate, or a glass epoxy substrate.

[0463] Electronic component 1700 is provided with, for example, lead frame 1712. A portion of lead frame 1712 located on substrate 1701 is covered with mold 1711, and another portion of lead frame 1712 is exposed to the outside of mold 1711. In particular, lead frame 1712 exposed to the outside of mold 1711 functions as, for example, a terminal for mounting electronic component 1700 on a printed circuit board.

[0464] Inside mold 1711, electrode pads 1713 are provided on lead frame 1712, and electrode pads 1713 are connected to semiconductor device 1710 via wires 1714. Electronic component 1700 is mounted on a printed circuit board, for example, by contacting lead frame 1712 with wiring on the printed circuit board. In this way, a mounted board is completed by combining multiple electronic components and connecting them on the printed circuit board.

[0465] Next, the semiconductor device 1710 will be described. For example, as shown in FIG. 25B , the semiconductor device 1710 includes a drive circuit layer 1715 and a memory layer 1716. The memory layer 1716 may be configured with a plurality of stacked cell arrays. The cell array may include the arithmetic cells, drive cells, memory cells, and the like described in the above embodiments. The stacked drive circuit layer 1715 and memory layer 1716 may be configured as a monolithic stack. In a monolithic stacked configuration, the layers can be connected without using through-electrode technology (e.g., TSV (Through Silicon Via)) or bonding technology such as Cu-Cu direct bonding. By configuring the drive circuit layer 1715 and the memory layer 1716 as a monolithic stack, for example, a so-called on-chip memory configuration can be achieved, in which memory is formed directly on a processor. The on-chip memory configuration enables the operation of the interface between the processor and memory to be faster. For example, by using the arithmetic unit described in the above embodiment as the processor, it is possible to increase the transmission speed of the first data (for example, weighting coefficients) from the memory to the arithmetic unit.

[0466] Furthermore, by configuring an on-chip memory, it is possible to reduce the size of connection wiring, etc., compared to technologies that use through electrodes such as TSVs, and therefore it is possible to increase the number of connection pins. Increasing the number of connection pins enables parallel operation, which makes it possible to improve the memory bandwidth (also called memory bandwidth).

[0467] Furthermore, it is preferable that the multiple memory cell arrays included in the memory layer 1716 are formed using IO transistors and the multiple memory cell arrays are monolithically stacked. By configuring the multiple memory cell arrays as a monolithic stack, it is possible to improve either or both of the memory bandwidth and the memory access latency. Note that the bandwidth is the amount of data transferred per unit time, and the access latency is the time from access to the start of data exchange. Note that when Si transistors are used in the memory layer 1716, it is more difficult to achieve a monolithic stacked configuration than IO transistors. Therefore, it can be said that IO transistors have a superior structure to Si transistors in a monolithic stacked configuration.

[0468] The semiconductor device 1710 may also be referred to as a die. In this specification, a die refers to a chip piece obtained by forming a circuit pattern on, for example, a disk-shaped substrate (also called a wafer) and cutting it into dices during the semiconductor chip manufacturing process. Semiconductor materials that can be used for the die include, for example, silicon (Si), silicon carbide (SiC), and gallium nitride (GaN). For example, a die obtained from a silicon substrate (also called a silicon wafer) may be called a silicon die.

[0469] Next, Fig. 25C shows a modified example of electronic component 1700. Electronic component 1700A shown in Fig. 25C differs from electronic component 1700 in that it does not use lead frame 1712, but has electrodes 1733 provided on the bottom of substrate 1701. Electrodes 1733 function as connection terminals for mounting electronic component 1700A on a printed circuit board.

[0470] 25C shows an example in which electrodes 1733 are formed using solder balls. By providing solder balls in a matrix on the bottom of substrate 1701, BGA (Ball Grid Array) mounting can be achieved. For this purpose, through-hole vias (penetrating vias) are provided in substrate 1701, and conductive layers 1732 that function as wiring are provided in these vias. Electrode pads 1713 are provided above conductive layer 1732 on substrate 1701 so as to be in contact with them, and electrodes 1733 are provided below conductive layer 1732 below substrate 1701 so as to be in contact with them.

[0471] Furthermore, the electrodes 1733 may be formed of conductive pins instead of solder balls. By providing conductive pins in a matrix on the bottom of the substrate 1701, PGA (Pin Grid Array) mounting can be achieved.

[0472] Furthermore, electronic component 1700A can be mounted on other substrates using various mounting methods, not limited to BGA and PGA, such as SPGA (Staggered Pin Grid Array), LGA (Land Grid Array), QFP (Quad Flat Package), QFJ (Quad Flat J-leaded package), and QFN (Quad Flat Non-leaded package).

[0473] The electronic component of one embodiment of the present invention may be in the form of a system in package (SiP) or a multi-chip module (MCM). For example, an electronic component 1700C illustrated in FIG. 25D includes an interposer 1731 over a package substrate 1734 (printed circuit board), and a semiconductor device 1735 and a plurality of semiconductor devices 1710 over the interposer 1731.

[0474] 25D illustrates an example in which the semiconductor device 1710 is used as a high bandwidth memory (HBM). For example, the semiconductor device 1735 can be used as an arithmetic circuit in an integrated circuit such as a CPU, a GPU, or an FPGA (Field Programmable Gate Array).

[0475] The package substrate 1734 may be, for example, a ceramic substrate, a plastic substrate, or a glass epoxy substrate, similar to the substrate 1701. The interposer 1731 may be, for example, a silicon interposer or a resin interposer.

[0476] The interposer 1731 has multiple wirings and functions to connect multiple integrated circuits with different terminal pitches. The multiple wirings are provided in a single layer or multiple layers. The interposer 1731 also functions to connect the integrated circuits provided on the interposer 1731 to electrodes provided on the package substrate 1734. For these reasons, the interposer is sometimes called a "rewiring substrate" or "intermediate substrate." In some cases, through electrodes are provided in the interposer 1731, and the integrated circuits and the package substrate 1734 are connected using the through electrodes. In addition, in a silicon interposer, TSVs can also be used as through electrodes.

[0477] In an HBM, many wirings must be connected to achieve a wide memory bandwidth. Therefore, the interposer on which the HBM is mounted must have fine and high-density wiring. Therefore, it is preferable to use a silicon interposer for the interposer on which the HBM is mounted.

[0478] Furthermore, in SiP and MCM using silicon interposers, a decrease in reliability due to differences in the coefficient of expansion between the integrated circuit and the interposer is unlikely to occur. Furthermore, since the silicon interposer has a highly flat surface, poor connection between the integrated circuit mounted on the silicon interposer and the silicon interposer is unlikely to occur. In particular, it is preferable to use silicon interposers in 2.5D packages (2.5-dimensional packaging) in which multiple integrated circuits are arranged horizontally on the interposer.

[0479] On the other hand, when connecting multiple integrated circuits with different terminal pitches using a silicon interposer and TSVs, space is required, such as the width of the terminal pitch. Therefore, when attempting to reduce the size of the electronic component 1700C, the width of the terminal pitch becomes an issue, and it may be difficult to provide the large number of wirings required to achieve a wide memory bandwidth. Therefore, as described above, a monolithic stacked configuration using IO transistors is preferable. Also, for example, a memory cell array stacked using TSVs and a monolithically stacked memory cell array can be combined. Furthermore, a structure combining a memory cell array stacked using TSVs and a monolithically stacked memory cell array is sometimes called a hybrid structure.

[0480] Furthermore, if the temperature of the electronic component 1700C increases due to heat generated during operation, the characteristics of the circuit elements (e.g., transistors) included in the electronic component 1700C may be degraded. Therefore, it is preferable to provide a heat sink (heat sink) on the electronic component 1700C. When providing a heat sink, it is preferable to align the height of the integrated circuit provided on the interposer 1731. For example, in the electronic component 1700C described in this embodiment, it is preferable to align the height of the semiconductor device 1710 and the semiconductor device 1735.

[0481] Note that this embodiment mode can be appropriately combined with the same or other embodiment modes described in this specification. For example, the configuration, structure, method, etc. described in this embodiment mode can be appropriately combined with another configuration, structure, method, etc. described in this embodiment mode. Furthermore, for example, the configuration, structure, method, etc. described in this embodiment mode can be appropriately combined with the configuration, structure, method, etc. described in other embodiment modes.

[0482] Sixth Embodiment In this embodiment, an electronic device using the electronic components described in the above embodiments and an information processing system using the electronic device will be described.

[0483] Fig. 26 is a diagram showing an example of the configuration of an information processing system 8000. The information processing system 8000 shown in Fig. 26 includes examples of electronic devices and a server located within a network.

[0484] 26 shows, as examples of the electronic devices, a portable information terminal 8200, a wearable information terminal 8300, a notebook personal computer 8400, an automobile 8500, an industrial robot 8600, and a camera 8700. Also shown in FIG. 26 is a network 8100 and a mainframe computer 8110 arranged within the network 8100.

[0485] As an example, the mainframe computer 8110 may refer to multiple computers installed in a server room or the like. For example, the mainframe computer 8110 may be a rack-mounted computer in which multiple computers are stored in a rack. The mainframe computer 8110 may also be called a supercomputer. In the information processing system 8000, the mainframe computer 8110 may also be called a server or a cloud server.

[0486] Each of the multiple computers included in the mainframe 8110 has a motherboard, which is provided with multiple slots, multiple connection terminals, and the like. For example, one or multiple PC cards can be inserted into the slots. The PC cards are an example of a processing board equipped with processing devices such as a CPU and a GPU. For example, the electronic component 1700 can be used as the processing device.

[0487] The mainframe computer 8110 can also function as a parallel computer. By using the mainframe computer 8110 as a parallel computer, it is possible to perform large-scale calculations necessary for learning and inference in artificial intelligence, for example.

[0488] When wired communication is performed as the network 8100, specifications standardized by IEEE such as Ethernet (registered trademark) can be used. In addition, types of communication include electrical communication using electric wires such as twisted pair cables, and optical communication using optical fibers.

[0489] On the other hand, when wireless communication is performed as network 8100, communication standards such as the fourth generation mobile communication system (4G), fifth generation mobile communication system (5G), and sixth generation mobile communication system (6G), or specifications standardized by IEEE such as Wi-Fi (registered trademark) and Bluetooth (registered trademark), can be used as communication protocols or communication technologies.

[0490] The network 8100 may be, for example, a PAN (Personal Area Network), a LAN (Local Area Network), a CAN (Campus Area Network), a MAN (Metropolitan Area Network), a WAN (Wide Area Network), a GAN (Global Area Network), etc. For example, by using a GAN for the network 8100, the Internet, which is the foundation of the World Wide Web (WWW), can be used.

[0491] If the information processing system 8000 is constructed on a LAN as the network 8100, the possibility of confidential information leaking can be reduced, for example, compared to when the Internet is used.

[0492] Furthermore, a company or individual managing the supercomputer 8110 can provide services using the information processing system 8000 to users of each electronic device, for example, using the network 8100. One example of such services is a form of use known as cloud computing. Cloud computing allows users of the above-mentioned electronic devices to utilize the functions of the supercomputer 8110, such as the ability to store large amounts of data, the ability to perform large-scale calculations, and other applications.

[0493] In particular, the semiconductor device according to one embodiment of the present invention can perform large-scale calculations such as an artificial neural network model by being provided in the above-described electronic devices and the mainframe computer 8110. This enables the information processing system 8000 to provide services to users in a usage form called cloud AI or edge AI.

[0494] Cloud AI is generally a form of service usage in which the supercomputer 8110 performs learning and inference of an artificial neural network. The supercomputer 8110 has previously learned collected data, and each electronic device sends input data to the artificial neural network to the supercomputer 8110, causing the supercomputer 8110 to perform inference on the input data. The supercomputer 8110 also sends the results of the inference to each electronic device, allowing each electronic device to use the results of the inference. Because learning and inference are performed by the supercomputer 8110, cloud AI is suitable for performing calculations on large amounts of data and processing including complex calculations.

[0495] On the other hand, edge AI generally refers to a service usage form in which each electronic device performs learning and inference of an artificial neural network. In this case, the mainframe 8110 provides each electronic device with an artificial neural network model, weight coefficients (sometimes referred to as weight data, coupling coefficients, etc.). The results of learning and inference performed on each electronic device are also transmitted to the mainframe 8110. A usage form in which the mainframe 8110 performs learning of an artificial neural network and each electronic device performs inference using the trained neural network may also be called edge AI.

[0496] Edge AI requires less communication time than cloud AI because each electronic device performs inference using an artificial neural network. In other words, edge AI is suitable for analyzing input data in real time. Furthermore, because the amount of data transmitted between each electronic device and the mainframe 8110 is reduced, data communication costs can be reduced, and the power consumption required for data communication can also be reduced. Furthermore, because the amount of data transmitted is reduced, security risks such as information leaks can be reduced. Therefore, edge AI is suitable for building small-scale systems, for example.

[0497] Note that the semiconductor device of one embodiment of the present invention consumes extremely little power during standby and can therefore be suitably used for an edge AI. An example of a specific system of the edge AI will be described below.

[0498] 26 is an electronic device in which a display device and a touch panel are integrated. The portable information terminal 8200 can include an electronic component 8201 as the electronic component 1700 described above, which allows the portable information terminal 8200 to perform large-scale calculations such as an artificial neural network. The portable information terminal 8200 can also include a camera.

[0499] By providing the mobile information terminal 8200 with a camera, image recognition by edge AI can be performed on images captured by the mobile information terminal 8200. Examples of objects to be recognized include humans, animals, plants, characters, pictograms, etc. In particular, image recognition can be used for biometric authentication by performing image recognition on images of human faces, fingerprints, palm prints, irises, veins, etc.

[0500] [Wearable Information Terminal] The wearable information terminal 8300 shown in Fig. 26 is an electronic device that can be worn on a human head. The wearable information terminal 8300 in Fig. 26 has a structure that covers the eyes, a display device, temples that are hooked onto the ears, and earphones, but other examples include an HMD (head-mounted display) and a glasses-type XR device. The wearable information terminal 8300 can also be equipped with a camera, similar to the portable information terminal 8200.

[0501] In addition, the wearable information terminal 8300 can be equipped with an electronic component 8301 as the electronic component 1700 described above, thereby enabling the wearable information terminal 8300 to perform large-scale calculations such as artificial neural networks.

[0502] By providing a camera in the wearable information terminal 8300, images captured by the wearable information terminal 8300 can be displayed on a display device in real time. Furthermore, by performing image recognition using edge AI, information about an object included in an image displayed on the display device can be additionally displayed on the display device. Furthermore, by performing image recognition of moving objects such as pedestrians, bicycles, cars, and trains displayed on the display device, risk prediction can be performed to determine whether or not there is a risk of contact.

[0503] 26 is an electronic device that is primarily used on a desk. The notebook personal computer 8400 can include an electronic component 8401 as the electronic component 1700 described above, which enables the notebook personal computer 8400 to perform large-scale calculations such as artificial neural networks.

[0504] For example, the notebook personal computer 8400 can use edge AI for its calculation processing when using an application, for example, for upconversion to increase the screen resolution of images (including still images and videos) displayed on a display device in real time, translation to convert text into another language, editing of text or images, etc.

[0505] 26 is an example of a moving body. The automobile 8500 can be equipped with an electronic component 8501 as the electronic component 1700 described above, and thus the automobile 8500 can be used as an electronic device for edge AI.

[0506] Edge AI in the automobile 8500 can be used for applications such as autonomous driving, hazard prediction during autonomous driving, and air conditioning management inside the vehicle.

[0507] In this specification, an automobile has been described as an example of a mobile object, but other mobile objects include, for example, trains, monorails, ships, and aircraft (for example, helicopters, unmanned aerial vehicles (drones), airplanes, and rockets). The above-mentioned mobile objects can also be used as electronic devices for edge AI.

[0508] [Industrial Robot] The industrial robot 8600 shown in FIG. 26 can be deployed in, for example, a production factory. The industrial robot 8600 preferably has multiple drive axes to precisely control the drive range. The industrial robot 8600 may have one or more functions, such as gripping, cutting, welding, coating, and pasting an object. In order to detect the object, the industrial robot 8600 is preferably equipped with a sensor such as an image detection module or a camera. The industrial robot 8600 is also preferably equipped with a sensor that detects minute currents to determine whether or not the object has been gripped.

[0509] The industrial robot 8600 can be equipped with the electronic component 8601 as the above-described electronic component 1700, thereby allowing the industrial robot 8600 to be used as an edge AI electronic device. The edge AI in the industrial robot 8600 can be used for applications such as image recognition of objects, classification by type, classification by size, and inspection to determine whether an item is good or bad.

[0510] 26 can be used as, for example, a surveillance camera, a security camera, a pet camera, etc. The housing of the camera 8700 is not limited to a ceiling-mounted type as shown in FIG. 26 , and there are various types such as a tabletop type and a wall-mounted type.

[0511] Note that the terms surveillance camera, security camera, and pet camera are common names and do not limit the intended use to the name. For example, a pet camera may be used as a surveillance camera or security camera, or vice versa. The camera 8700 may also be called a video camera.

[0512] The camera 8700 can also be provided with the electronic component 8701 as the electronic component 1700 described above, thereby enabling the camera 8700 to be used as an edge AI electronic device. The edge AI in the camera 8700 can be used, for example, for security purposes to detect moving objects displayed in images (still images and videos) captured by the camera 8700. The edge AI can also be used for disaster prevention purposes to detect river flooding, tsunamis, and the like.

[0513] Note that this embodiment mode can be appropriately combined with the same or other embodiment modes described in this specification. For example, the configuration, structure, method, etc. described in this embodiment mode can be appropriately combined with another configuration, structure, method, etc. described in this embodiment mode. Furthermore, for example, the configuration, structure, method, etc. described in this embodiment mode can be appropriately combined with the configuration, structure, method, etc. described in other embodiment modes.

[0514] In this embodiment, a space equipment and a data center (also referred to as a Data Center: DC) in which the semiconductor device described in the above embodiment can be used will be described. Note that the space equipment and the data center are effective in achieving high performance, such as low power consumption.

[0515] [Space Equipment] The semiconductor device of one embodiment of the present invention can be suitably used in space equipment (for example, equipment having a function of processing and storing information).

[0516] A semiconductor device according to one embodiment of the present invention can include an IO transistor. The IO transistor exhibits small changes in electrical characteristics due to radiation exposure. In other words, the IO transistor has high radiation resistance and can be suitably used in an environment where radiation may be incident. For example, the IO transistor can be suitably used in outer space.

[0517] Fig. 27 shows an artificial satellite 6800 as an example of space equipment. The artificial satellite 6800 has a body 6801, a solar panel 6802, an antenna 6803, a secondary battery 6805, and a control device 6807. In Fig. 27, a planet 6804 is shown in outer space. Note that outer space refers to an altitude of 100 km or higher, for example, but outer space described in this specification includes the thermosphere, mesosphere, and stratosphere.

[0518] 27 , a battery management system (also referred to as BMS) or a battery control circuit may be provided for the secondary battery 6805. The use of an IO transistor in the battery management system or the battery control circuit is preferable because it has low power consumption and high reliability even in space.

[0519] Furthermore, outer space is an environment with radiation levels 100 times higher than on Earth. Examples of radiation include electromagnetic waves (electromagnetic radiation) such as X-rays and gamma rays, and particle radiation such as alpha rays, beta rays, neutron rays, proton rays, heavy ion rays, and meson rays.

[0520] When sunlight is irradiated onto the solar panel 6802, the power required for the operation of the satellite 6800 is generated. However, for example, in a situation where sunlight is not irradiated onto the solar panel or where the amount of sunlight irradiating the solar panel is small, the generated power is small. Therefore, there is a possibility that the power required for the operation of the satellite 6800 will not be generated. In order to operate the satellite 6800 even in a situation where the generated power is small, it is preferable to provide a secondary battery 6805 in the satellite 6800. Note that the solar panel may be called a solar cell module.

[0521] The satellite 6800 can generate a signal. The signal is transmitted via an antenna 6803, and can be received, for example, by a receiver on the ground or another satellite. By receiving the signal transmitted by the satellite 6800, the position of the receiver that received the signal can be determined. As described above, the satellite 6800 can constitute a satellite positioning system.

[0522] The control device 6807 has a function of controlling the artificial satellite 6800. The control device 6807 is configured using, for example, one or more selected from a CPU, a GPU, and a memory circuit. Note that the semiconductor device of one embodiment of the present invention is preferably used for the control device 6807. An IO transistor has smaller fluctuations in electrical characteristics due to radiation exposure than a Si transistor. That is, an IO transistor has high reliability even in an environment where radiation may be incident, and can be preferably used.

[0523] The artificial satellite 6800 can also be configured to include a sensor. For example, by including a visible light sensor, the artificial satellite 6800 can have the function of detecting sunlight reflected from an object on the ground. Or, by including a thermal infrared sensor, the artificial satellite 6800 can have the function of detecting thermal infrared rays emitted from the earth's surface. As described above, the artificial satellite 6800 can function as, for example, an earth observation satellite.

[0524] Although an artificial satellite is given as an example of space equipment in this embodiment, the invention is not limited thereto. For example, the semiconductor device of one embodiment of the present invention can be suitably used in space equipment such as a spaceship, a space capsule, or a space probe.

[0525] As described above, IO transistors have the advantages of being able to achieve a wider memory bandwidth and having higher radiation resistance than Si transistors.

[0526] [Data Center] The semiconductor device of one embodiment of the present invention can be suitably used in a storage system applied to, for example, a data center. Data centers are required to perform long-term data management, such as ensuring data immutability. Managing long-term data requires large-scale buildings, such as the installation of storage and servers for storing huge amounts of data, ensuring a stable power supply for data retention, and ensuring cooling equipment required for data retention. In addition, the data center preferably has a function for performing data calculations, and more preferably, the calculation speed is high.

[0527] By using the semiconductor device of one embodiment of the present invention in a storage system applied to a data center, power required for operation can be reduced and the operation speed can be increased.

[0528] Furthermore, the semiconductor device of one embodiment of the present invention has low power consumption, which allows heat generation from the circuit to be reduced. Therefore, adverse effects of the heat generation on the circuit itself, peripheral circuits, and modules can be reduced. Furthermore, by using the semiconductor device of one embodiment of the present invention, a data center that operates stably even in a high-temperature environment can be realized. Therefore, the reliability of the data center can be improved.

[0529] Fig. 28 shows a storage system applicable to a data center. The storage system 7000 shown in Fig. 28 has a plurality of servers 7001sb as hosts 7001 (illustrated as Host computers). It also has a plurality of storage devices 7003md as storage 7003 (illustrated as Storage). The host 7001 and storage 7003 are shown connected via a storage area network 7004 (illustrated as SAN: Storage Area Network) and a storage control circuit 7002 (illustrated as Storage Controller).

[0530] The host 7001 can be a computer that accesses data stored in the storage 7003. The hosts 7001 may be connected to each other via a network.

[0531] Although the storage 7003 uses flash memory to reduce the data access speed, i.e., the time required to store and output data, this time is significantly longer than the time required for DRAM (Dynamic Random Access Memory), which can be used as cache memory within the storage. In order to solve the problem of the long access speed of the storage 7003, a storage system typically provides cache memory within the storage to reduce the time required to store and output data.

[0532] The above-mentioned cache memory is used in the storage control circuit 7002 and the storage 7003. Data exchanged between the host 7001 and the storage 7003 is stored in the cache memory in the storage control circuit 7002 and the storage 7003, and then output to the host 7001 or the storage 7003.

[0533] By using IO transistors as transistors for storing data in the cache memory and holding a potential corresponding to the data, the frequency of refresh operations can be reduced, and power consumption can be reduced.Furthermore, by using a stacked memory cell array, miniaturization is possible.

[0534] Note that by applying the semiconductor device of one embodiment of the present invention to one or more of the electronic components described in the above embodiments, the electronic devices described in the above embodiments, the large-scale computers, space equipment, and data centers described in the above embodiments, it is expected that power consumption can be reduced. Therefore, while energy demand is expected to increase with the improvement in performance or high integration of the above-described components, equipment, data centers, and the like, by using the semiconductor device of one embodiment of the present invention, carbon dioxide (CO ２ Furthermore, the semiconductor device of one embodiment of the present invention is effective as a countermeasure against global warming because it consumes low power.

[0535] Note that this embodiment mode can be appropriately combined with the same or other embodiment modes described in this specification. For example, the configuration, structure, method, etc. described in this embodiment mode can be appropriately combined with another configuration, structure, method, etc. described in this embodiment mode. Furthermore, for example, the configuration, structure, method, etc. described in this embodiment mode can be appropriately combined with the configuration, structure, method, etc. described in other embodiment modes.

[0536] ATDC: circuit, BIS: wiring, CA: cell array, CAa_1: region, CAa_2: region, CAa_k: region, CAa_p: region, CAa_r: region, CDV: calculation unit, CDVA: calculation unit, CDVB: calculation unit, CDVS: calculation unit, CNI: current source, CPE: wiring, CRM: current mirror circuit, CS: current source, CTi: terminal, CTo: terminal, d10: channel length, DW[0]: wiring, DW[1]: wiring, DW[K-1]: wiring, DX[0]: wiring, DX[1]: wiring, DX[K-1]: wiring, IM: calculation cell, IM[1,1]: calculation cell, IM [1,n]: calculation cell, IM[m,1]: calculation cell, IM[m,n]: calculation cell, IM[1]: calculation cell, IM[m]: calculation cell, IMD[1]: driving cell, IMD[m]: driving cell, IMD: driving cell, IMP: memory cell, IMP_1: memory cell, IMP_2: memory cell, IMP_k: memory cell, IMP_p: memory cell, IMP_r: memory cell, ITS: driving circuit, ITSa: circuit, IWL: wiring, IWL_k: wiring, IXL: wiring, Nd: node, Ns: node, OL[1]: wiring, OL[n]: wiring, OL: wiring, OMAL: circuit layer, PHRL: circuit Layer, RL: circuit, RTi: terminal, RTo: terminal, SA: switch, SA_1: switch, SA_k: switch, SWCA: circuit, SWLA: wiring, TrP: transistor, TrQ: transistor, VDDL: wiring, VEA: wiring, VEB: wiring, VEC: wiring, VEH: wiring, VEL: wiring, VSSL: wiring, WCD: driver circuit, WCDa: circuit, WCDa_1: circuit, WCDa_k: circuit, WCL[n]: wiring, WCL: wiring, WCL_1: wiring, WCL_2: wiring, WCL_3: wiring, WCL_h: wiring, WCL_k: wiring, WCL_p: wiring, WCL _r: wiring, WCPL[1]: wiring, WCPL[n]: wiring, WCPL: wiring, WIL_1: wiring, WIL_k: wiring, WIL_p: wiring, WILa_1: wiring, WILa_2: wiring, WILa_h: wiring, WILa_k: wiring, WILa_r: wiring, WILb_1: wiring, WILb_2: wiring, WILb_h: wiring, WILb_k: wiring, WILb_r: wiring, WILc_1: wiring, WILc_2: wiring, WILc_h: wiring, WILc_k: wiring, WILc_r: wiring, WIOD: driver circuit, WLb_1: wiring, WLb_k: wiring, WOL_1: wiring,WOL_2: wiring, WOL_h: wiring, WOL_k: wiring, WOL_p: wiring, WRL_1: wiring, WRL_2: wiring, WRL_h: wiring, WRL_k: wiring, WRL_r: wiring, WSD_1: driving circuit, WSD_k: driving circuit, WSD_p: driving circuit, WSD_r: driving circuit, WSL: wiring, XCD: driving circuit, XCD_1: driving circuit, XCD_k: driving circuit, XCD_p: driving circuit, XCD_r: driving circuit, XCDa[1]: circuit, XCDa[i]: circuit, XCDa[m]: circuit, XCDa: circuit, XCL: wiring, 100: transistor, 101 : substrate, 102: element isolation layer, 111: insulating layer, 112: insulating layer, 113: insulating layer, 114: insulating layer, 115: insulating layer, 116: insulating layer, 131: conductive layer, 132: conductive layer, 133: conductive layer, 134: conductive layer, 161: insulating layer, 171: semiconductor region, 172a: low resistance region, 172b: low resistance region, 181: insulating layer, 182: insulating layer, 200: transistor, 211: insulating layer, 212: insulating layer, 213: insulating layer, 214: insulating layer, 219: insulating layer, 231: conductive layer, 231a: conductive layer, 231b: conductive layer, 232: conductive layer, 232a: conductive layer, 232b : conductive layer, 233: conductive layer, 233a: conductive layer, 233b: conductive layer, 234: conductive layer, 234_1: conductive layer, 234_2: conductive layer, 234_3: conductive layer, 235: conductive layer, 235_1: conductive layer, 235_2: conductive layer, 235_3: conductive layer, 235_4: conductive layer, 235a: conductive layer, 235b: conductive layer, 251: semiconductor layer, 251a: semiconductor layer, 251b: semiconductor layer, 261: insulating layer, 262: insulating layer, 263: insulating layer, 264: insulating layer, 271a: region, 271b: region, 281: insulating layer, 282: insulating layer, 283: insulating layer, 284: insulating layer, 287: Insulating layer, 300: transistor, 311: insulating layer, 312: insulating layer, 313: insulating layer, 314: insulating layer, 331: conductive layer, 332: conductive layer, 333: conductive layer, 334: conductive layer, 351: semiconductor layer, 361: insulating layer, 441: insulating layer, 1700: electronic component, 1700A: electronic component, 1700C: electronic component, 1701: substrate, 1710: semiconductor device, 1711: mold, 1712: lead frame, 1713: electrode pad, 1714: wire, 1715: drive circuit layer, 1716: memory layer, 1731: interposer, 1732: conductive layer, 1733: electrode,1734: package substrate, 1735: semiconductor device, 6800: artificial satellite, 6801: aircraft, 6802: solar panel, 6803: antenna, 6804: planet, 6805: secondary battery, 6807: control device, 7000: storage system, 7001: host, 7001sb: server, 7002: storage control circuit, 7003: storage, 7003md: storage device, 8000: information processing system, 8100: network, 8110: mainframe computer, 8200: portable information terminal, 8201: electronic component, 8300: wearable information terminal, 8301: electronic component, 8400: notebook personal computer, 8401: electronic component, 8500: automobile, 8501: electronic component, 8600: industrial robot, 8601: electronic component, 8700: camera, 8701: electronic component,

Claims

A first cell, a second cell, and a third cell, The first cell is a function of holding a first potential according to first data; a function of causing a first current corresponding to the first potential to flow between the first cell and a first wiring; a function of causing a second current corresponding to a product of the first data and the second data to flow between the first cell and the first wiring by changing the potential of the second wiring according to second data; The second cell is a function of holding a second potential according to the reference data; a function of causing a third current corresponding to the second potential to flow between the second cell and the second wiring; a function of changing the potential of the second wiring in accordance with a change from the reference data to the second data, thereby changing the third current flowing between the second cell and the second wiring to a fourth current corresponding to the second data; The third cell is a function of holding a third potential according to a product of the first data and the second data; a function of causing a fifth current corresponding to the third potential to flow between the third cell and the first wiring or the third wiring; Semiconductor device. 　 In claim 1, the third cell includes a first transistor, a second transistor, a third transistor, a fourth transistor, and a first capacitance element; the second transistor is a p-channel transistor, each of the first transistor, the third transistor, and the fourth transistor is an n-channel transistor; one of the source and the drain of the first transistor is electrically connected to the gate of the second transistor and the first terminal of the first capacitive element; the other of the source or the drain of the first transistor, the one of the source or the drain of the second transistor, the one of the source or the drain of the third transistor, and the one of the source or the drain of the fourth transistor are electrically connected to each other; the other of the source and the drain of the third transistor is electrically connected to the first wiring; the other of the source and the drain of the fourth transistor is electrically connected to the third wiring; Semiconductor device. 　 In claim 2, a gate of the first transistor and a gate of the third transistor are each electrically connected to a fourth wiring; Semiconductor device. 　 In claim 2, the third cell has a fifth transistor that is an n-channel transistor; one of the source and the drain of the fifth transistor is electrically connected to the other of the source and the drain of the first transistor, one of the source and the drain of the second transistor, one of the source and the drain of the third transistor, and one of the source and the drain of the fourth transistor; Semiconductor device.

2. The semiconductor device according to claim 1, wherein the third cell includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a first capacitance element; the second transistor and the third transistor are p-channel transistors, each of the first transistor, the fourth transistor, and the fifth transistor is an n-channel transistor; one of the source and the drain of the first transistor is electrically connected to the gate of the second transistor and the first terminal of the first capacitive element; one of the source and the drain of the second transistor is electrically connected to one of the source and the drain of the third transistor; the other of the source or the drain of the first transistor, the other of the source or the drain of the third transistor, one of the source or the drain of the fourth transistor, and one of the source or the drain of the fifth transistor are electrically connected to each other; the other of the source and the drain of the fourth transistor is electrically connected to the first wiring; the other of the source and the drain of the fifth transistor is electrically connected to the third wiring; Semiconductor device. In claim 5, a gate of the first transistor and a gate of the fourth transistor are electrically connected to a fourth wiring; Semiconductor device. 　 In claim 5, the third cell has a sixth transistor that is an n-channel transistor; one of the source or the drain of the sixth transistor is electrically connected to the other of the source or the drain of the first transistor, the other of the source or the drain of the third transistor, one of the source or the drain of the fourth transistor, and one of the source or the drain of the fifth transistor; Semiconductor device. 　 In any one of claims 2 to 7, the first cell includes a seventh transistor, an eighth transistor, and a second capacitive element; the second cell includes a ninth transistor, a tenth transistor, and a third capacitive element; each of the seventh to tenth transistors is an n-channel transistor; one of the source and the drain of the seventh transistor is electrically connected to the gate of the eighth transistor and the first terminal of the second capacitive element; one of the source and the drain of the ninth transistor is electrically connected to the gate of the tenth transistor and the first terminal of the third capacitive element; the other of the source or the drain of the seventh transistor and the one of the source or the drain of the eighth transistor are electrically connected to the first wiring, the other of the source or the drain of the ninth transistor, the one of the source or the drain of the tenth transistor, the second terminal of the second capacitance element, and the second terminal of the third capacitance element are each electrically connected to the second wiring; a gate of the seventh transistor and a gate of the ninth transistor are electrically connected to a fifth wiring; Semiconductor device. 　 In claim 8, the n-channel transistor has an oxide semiconductor in a channel formation region, the p-channel transistor has silicon in a channel formation region, the oxide semiconductor has an oxide containing indium; Semiconductor device. 　 In claim 9, a first drive circuit, a second drive circuit, and a third drive circuit; the first driving circuit has a function of causing a current corresponding to the first data to flow through the first wiring; the second driving circuit has a function of causing a current corresponding to the reference data or the second data to flow through the second wiring; the third driving circuit has a function of calculating a function using a value corresponding to the amount of current flowing through the third wiring as an input value, and outputting the result of the calculation. Semiconductor device. 　 In any one of claims 2 to 7, the first cell includes a seventh transistor, an eighth transistor, a ninth transistor, and a second capacitive element; the second cell includes a tenth transistor, an eleventh transistor, a twelfth transistor, and a third capacitive element; each of the seventh transistor to the twelfth transistor is an n-channel transistor; one of the source and the drain of the seventh transistor is electrically connected to the gate of the eighth transistor and the first terminal of the second capacitive element; one of the source and the drain of the eighth transistor is electrically connected to one of the source and the drain of the ninth transistor; one of the source and the drain of the tenth transistor is electrically connected to the gate of the eleventh transistor and the first terminal of the third capacitance element; one of the source and the drain of the eleventh transistor is electrically connected to one of the source and the drain of the twelfth transistor; the other of the source or the drain of the seventh transistor and the other of the source or the drain of the ninth transistor are electrically connected to the first wiring, the other of the source or the drain of the tenth transistor, the other of the source or the drain of the twelfth transistor, a second terminal of the second capacitance element, and a second terminal of the third capacitance element are each electrically connected to the second wiring; a gate of the seventh transistor and a gate of the tenth transistor are electrically connected to a fifth wiring; Semiconductor device. 　 In claim 11, the n-channel transistor has an oxide semiconductor in a channel formation region, the p-channel transistor has silicon in a channel formation region, the oxide semiconductor has an oxide containing indium; Semiconductor device. 　 In claim 12, a first drive circuit, a second drive circuit, and a third drive circuit; the first driving circuit has a function of causing a current corresponding to the first data to flow through the first wiring; the second driving circuit has a function of causing a current corresponding to the reference data or the second data to flow through the second wiring; the third driving circuit has a function of calculating a function using a value corresponding to the amount of current flowing through the third wiring as an input value, and outputting the result of the calculation. Semiconductor device.

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