Chip structure and manufacturing method therefor

Abstract

The present disclosure relates to a chip structure and a manufacturing method thereof. The chip structure comprises: an epitaxial structure, comprising a semiconductor layer of a first doping type, a semiconductor layer of a second doping type, and an active layer, and further comprising a confinement layer. The confinement layer is made of a semiconductor material which is composed of any one of group III elements Ga, In, and Al and any one of group V elements N, As, and P, and a space charge region is formed between the confinement layer and the semiconductor layer of the second doping type. When the confinement layer has the second doping type, the doping concentration of the confinement layer is lower than that of the semiconductor layer of the second doping type in contact with the confinement layer; and when the confinement layer contains Al, the Al content is less than 0.5%.

Description

Chip structure and preparation method thereof

[0001] Related applications

[0002] The present application claims priority to the Chinese patent application No. 202411090628.5, filed on August 9, 2024, and entitled "Chip structure and preparation method thereof", the contents of which are hereby incorporated by reference in its entirety. TECHNICAL FIELD

[0003] The present application belongs to the technical field of semiconductor devices, and specifically relates to a Micro-LED chip structure and a preparation method thereof. BACKGROUND

[0004] Micro-LED display technology is a new type of display technology, which has the advantages of high brightness, high contrast, high resolution, energy saving and environmental protection, long service life, and easy realization of flexible display and transparent display.

[0005] For example, the pixel size of Micro-LED is in the micron level, which can realize the characteristics of self-emission, so it has very high performance in brightness. This technology can maintain clarity when used in sunlight, making the display content brighter and more vivid.

[0006] For example, due to its self-emission characteristics, independent control of each pixel can be achieved, making black darker and white brighter, thereby achieving higher contrast. This technology can present a clearer and more realistic effect when watching dynamic images or high-definition videos.

[0007] For example, due to the very high pixel density of Micro-LED, very delicate image display effects can be achieved. This technology can present a more delicate and rich visual effect when watching high-definition movies, playing games, or processing images.

[0008] For example, compared with traditional LCD displays, Micro-LED displays have significant advantages in power consumption, which can achieve energy saving and environmental protection. This technology can effectively reduce energy consumption and reduce the impact on the environment during use.

[0009] For example, the service life of Micro-LED is very long, which can reach tens of thousands of hours. Due to its small device size and high reliability, it has very high durability. This technology can maintain stable performance during long-term use, reduce the frequency of maintenance and replacement, and reduce maintenance costs.

[0010] For example, Micro-LEDs can be prepared on a flexible substrate, realizing flexible display. This technology has broad application prospects in the fields of future wearable devices, smart homes, etc. By preparing Micro-LEDs on a flexible substrate, bendable and wearable display devices can be realized, bringing more convenience and creativity to people's life and work.

[0011] For example, Micro-LEDs can realize transparent display. By preparing Micro-LEDs on a transparent substrate, a display with high transparency can be realized while maintaining high-definition display effect. This technology has broad application prospects in the fields of commercial display, home decoration, and vehicle navigation, etc., and can bring people a more intuitive and realistic visual experience.

[0012] However, as the size of Micro-LEDs decreases, the external quantum efficiency under small current density decreases sharply, mainly due to the introduction of non-radiative recombination centers and leakage current by sidewall damage caused by plasma etching in the manufacturing process.

[0013] In the prior art, improvements are made in the following ways: for example, the sidewalls of the light-emitting structure are passivated to reduce the non-radiative recombination centers and leakage current introduced by sidewall damage. However, this way of improvement is far from meeting the needs, although it can produce some optimization effect, but when the device becomes smaller and smaller, the effect of side length becomes more and more obvious. For example, the electrode is set away from the position where the sidewall is located. However, the device space is limited, and there is current spreading, so the actual effect is not good after improvement. For example, isolation is achieved by ion implantation, but ion implantation itself will bring many defects, and defects will bring non-radiative recombination centers; at the same time, high temperature is needed to eliminate ion implantation, and high temperature brings great challenges to device integration.

[0014] The information disclosed in this BACKGROUND section is only intended to increase an understanding of the general context in which the present application can be practiced. It will be apparent that the information in this BACKGROUND section can not be prior art to the claimed application, and it should not be construed as suggesting that any of the approaches described in this BACKGROUND section are known prior art in the United States or any other jurisdiction. SUMMARY

[0015] The purpose of the present application is to provide a Micro-LED chip structure and a preparation method thereof, which can solve the problems in the prior art.

[0016] To achieve the above-mentioned purpose, a chip structure is provided in an embodiment of the present application, comprising:

[0017] An epitaxial structure, comprising a first doped type semiconductor layer, a second doped type semiconductor layer, and an active layer disposed between the first doped type semiconductor layer and the second doped type semiconductor layer, wherein a side of the second doped type semiconductor layer away from the active layer forms a mesa structure;

[0018] The epitaxial structure further comprises a confinement layer formed on the side of the mesa structure and in contact with the mesa structure, wherein the confinement layer has the second doped type or the first doped type or has no doped type;

[0019] The material of the confinement layer is a semiconductor material, which is composed of any one of group III elements Ga, In, Al and any one of group V elements N, As, P,

[0020] A space charge region is formed between the confinement layer and the second doped type semiconductor layer, which can control the current flow path to bypass the side of the mesa structure;

[0021] When the confinement layer has the second doped type, the doping concentration of the confinement layer is less than the doping concentration of the second doped type semiconductor layer in contact with the confinement layer; when the confinement layer contains Al, the content of Al is less than 0.5%.

[0022] In one or more embodiments of the present application, the second doped type semiconductor layer comprises a second doped type electron blocking layer formed on the surface of the active layer and a second doped type cap layer formed on the surface of the second doped type electron blocking layer, wherein the doping concentration of the second doped type electron blocking layer is 1E18-1E20, and the doping concentration of the second doped type cap layer is 1E19-1E21.

[0023] In one or more embodiments of the present application, the mesa structure is formed by partially etching the second doped type cap layer in the thickness direction; wherein when the confinement layer has the second doped type, the doping concentration of the confinement layer is less than the doping concentration of the second doped type cap layer.

[0024] In one or more embodiments of the present application, the height of the mesa structure is less than the thickness of the second doped type cap layer, and the height of the mesa structure is greater than half of the thickness of the second doped type cap layer.

[0025] In one or more embodiments of the present application, the mesa structure is formed by etching the second doped type cap layer in the thickness direction, and the height of the mesa structure is equal to the thickness of the second doped type cap layer; wherein when the confinement layer has the second doped type, the doping concentration of the confinement layer is less than the doping concentration of the second doped type cap layer and less than the doping concentration of the second doped type electron blocking layer.

[0026] In one or more embodiments of the present application, the confinement layer is formed in the etched region, and the thickness of the confinement layer is equal to the height of the mesa structure.

[0027] In one or more embodiments of the present application, when the confinement layer has a first doping type, the doping concentration of the confinement layer ranges from 1E17 to 5E19; when the confinement layer has a second doping type, the doping concentration of the confinement layer ranges from 1E17 to 1E20.

[0028] In one or more embodiments of the present application, the chip structure further comprises:

[0029] a first electrode electrically connected to the first-doping-type semiconductor layer;

[0030] a second electrode electrically connected to the second-doping-type semiconductor layer.

[0031] In one or more embodiments of the present application, the second electrode is formed on the surface of the mesa structure, and the second electrode is electrically isolated from the confinement layer by an insulating layer.

[0032] In one or more embodiments of the present application, the first electrode is formed on the surface of the first-doping-type semiconductor layer away from the active layer, and the orthographic projection of the first electrode in the thickness direction has an overlapping region with the orthographic projection of the mesa structure in the thickness direction; or,

[0033] the first electrode is formed on the side surface of the first-doping-type semiconductor layer.

[0034] One embodiment of the present application provides a preparation method of a chip structure, comprising:

[0035] providing a substrate, and sequentially forming a first-doping-type semiconductor layer, an active layer, and a second-doping-type semiconductor layer on the substrate;

[0036] etching the second-doping-type semiconductor layer in the thickness direction to form a mesa structure;

[0037] growing an epitaxial layer in the etched region, the confinement layer is in contact with the mesa structure, the confinement layer has a second doping type or a first doping type or has no doping type, when the confinement layer has a second doping type, the doping concentration of the confinement layer is less than the doping concentration of the second-doping-type semiconductor layer in contact with the confinement layer;

[0038] forming a first electrode electrically connected to the first-doping-type semiconductor layer and a second electrode electrically connected to the second-doping-type semiconductor layer.

[0039] Compared with the prior art, the chip structure and the preparation method thereof provided in the embodiments of the present application form a space charge region between the etched sidewall and the limiting layer with a different doping type or a different doping concentration from the second doped semiconductor layer, so as to control the current flow path to bypass the etched sidewall, reduce the non-radiative recombination center and the leakage current introduced by etching damage, and also not introduce other problems adverse to the device performance.

[0040] The chip structure and the preparation method thereof provided in the embodiments of the present application control the concentration difference between the limiting layer and the second doped semiconductor layer and the proportion of the limiting layer in the thickness of the second doped semiconductor layer, control the size of the space charge region formed between the limiting layer and the second doped semiconductor layer, and further improve the current limiting effect of the space charge region on the current, so as to avoid the non-radiative recombination center and the leakage current phenomenon of the etched sidewall. BRIEF DESCRIPTION OF DRAWINGS

[0041] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed to be used in the embodiments or the prior art description will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments described in the present application, and for those skilled in the art, other drawings can also be obtained without creative labor on the basis of these drawings.

[0042] FIG. 1 is a sectional view of a chip structure in the first, third, fifth, seventh and ninth embodiments of the present application;

[0043] FIG. 2 is a sectional view of a chip structure in the second, fourth, sixth, eighth and tenth embodiments of the present application;

[0044] FIG. 3 is a sectional view of a chip structure in the eleventh embodiment of the present application;

[0045] FIG. 4 is a process flow diagram of a preparation method of a chip structure in an embodiment of the present application. DETAILED DESCRIPTION

[0046] In order to enable those skilled in the art to better understand the technical solutions in the present application, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor should be within the scope of protection of the present application.

[0047] As described in the background, Micro-LED display technology is a new type of display technology, which has the advantages of high brightness, high contrast, high resolution, energy saving and environmental protection, long service life, and easy realization of flexible display and transparent display. However, with the reduction of the size of Micro-LED, the external quantum efficiency under small current density decreases sharply, which is mainly due to the introduction of non-radiative recombination centers and leakage current caused by sidewall damage in the manufacturing process.

[0048] In the prior art, improvement can be made in the following way: for example, the sidewall of the light-emitting structure is passivated to reduce the non-radiative recombination centers and leakage current introduced by sidewall damage. However, such improvement is far from meeting the needs, although it can produce some optimization effect, but when the device becomes smaller and smaller, the effect of the side length becomes more and more obvious. For example, the electrode is set away from the position where the sidewall is located. However, the device space is limited, and there is current spreading, so the actual effect is not good after improvement. For example, isolation is achieved by ion implantation, but ion implantation itself will bring many defects, and defects will bring non-radiative recombination centers; at the same time, high temperature is needed to eliminate ion implantation, and high temperature brings great challenges to device integration.

[0049] In order to solve the above technical problems, the chip structure and the preparation method thereof provided by the present application are suitable for Micro-LED.

[0050] The chip structure provided by the embodiments of the present application at least includes an epitaxial structure. The epitaxial structure at least includes a first doped type semiconductor layer, an active layer and a second doped type semiconductor layer arranged in sequence. The second doped type semiconductor layer is partially etched along the thickness direction to form a mesa structure.

[0051] The first doped type semiconductor layer can be formed by doping the first conductive type semiconductor layer with a first dopant. The material of the first conductive type semiconductor layer is Al x1 In y1 Ga (1-x1-y1) N(0≤x1≤1, 0≤y1≤1, 0≤x1+y1≤1), which can be formed by any one or more of GaN, GaNAs, InP, InAlGaN, AlGaAs, GaP, GaAs, GaAsP, AlGaInP, but is not limited thereto. The material of the first dopant includes N-type dopants such as Si, Ge, Sn, Se and Te.

[0052] The second doped type semiconductor layer can be formed by doping the second conductive type semiconductor layer with a second dopant. The material of the second conductive type semiconductor layer is Al X2 In y2 Ga 1-x2-y2The semiconductor material of N(0≤x2≤1, 0≤y2≤1, 0≤x2+y2≤1) can be formed by any one or more of GaN, GaNAs, InP, AlInN, AlGaAs, GaP, GaAs, GaAsP, AlGaInP, without limitation. The material of the second dopant includes P-type dopants such as Mg, Zn, Ca, Sr, Ba, and the like.

[0053] The mesa structure formed by partially etching the second doped semiconductor layer in the thickness direction has a width in the range of 1 μm to 30 μm. Specifically, the width can be, for example, 1.5 μm, 3 μm, 6 μm, 8 μm, 10 μm, 15 μm, 20 μm, or the like. The width can be in the range of 1 μm to 20 μm, 1 μm to 10 μm, 3 μm to 8 μm, or the like. The mesa structure having a narrow width has the function of increasing the current density in the semiconductor device and confining the current within the semiconductor device.

[0054] The epitaxial structure further includes a confinement layer formed on the side surface of the mesa structure and located entirely within the region of the second doped semiconductor layer that is etched. The confinement layer is in contact with the mesa structure and the second doped semiconductor layer. The confinement layer is provided with the second doping type or the first doping type or no doping type. When the confinement layer has the second doping type, the doping concentration of the confinement layer is less than the doping concentration of the second doped semiconductor layer in contact therewith.

[0055] The material of the confinement layer is a semiconductor material, and the lattice of the confinement layer is adapted to the lattice of the second doped semiconductor layer. The material of the confinement layer is composed of any one of the group III elements Ga, In, Al and any one of the group V elements N, As, P. Optionally, the material of the confinement layer includes GaN, GaAs, GaNAs, InGaN, AlGaN, AlInGaN, or the like. When the material of the confinement layer contains Al, the content of Al is less than 0.5%. The limitation of the content of Al is to adapt the lattice when growing the confinement layer and to improve the efficiency of doping. Based on this, a space charge region can be formed between the confinement layer and the second doped semiconductor layer. The electric field in the space charge region can prevent the diffusion of free electrons and holes to the side surface of the mesa structure, thereby preventing the flow of current. In this way, the current flow path is controlled so that the current bypasses the side surface (etched side wall) of the mesa structure, greatly reducing the non-radiative recombination centers and leakage current introduced by etching damage.

[0056] In an optional embodiment, the second-doped-type semiconductor layer includes a second-doped-type electron-blocking layer formed on the surface of the active layer and a second-doped-type cap layer formed on the surface of the second-doped-type electron-blocking layer. The second-doped-type electron-blocking layer has a doping concentration of 1E18-1E20 and a thickness of 10-100 nm. The second-doped-type cap layer has a doping concentration of 1E19-1E21 and a thickness of 10-500 nm.

[0057] The mesa structure is formed by partially etching the second-doped-type cap layer in the thickness direction. In this embodiment, the second-doped-type semiconductor layer in contact with the confinement layer is only the second-doped-type cap layer. Therefore, when the confinement layer has the second-doped-type, the doping concentration of the confinement layer is smaller than that of the second-doped-type cap layer.

[0058] The height of the mesa structure is smaller than the thickness of the second-doped-type cap layer, and the height of the mesa structure is greater than half of the thickness of the second-doped-type cap layer. That is, the thickness of the confinement layer grown in the region where the second-doped-type cap layer is etched needs to be greater than half of the thickness of the second-doped-type cap layer. Optionally, the thickness of the confinement layer is greater than 2 / 3 or 3 / 4 of the thickness of the second-doped-type cap layer. The remaining thickness of the second-doped-type cap layer after etching is as small as possible, and the difference between the doping concentration of the grown confinement layer and that of the second-doped-type cap layer is as large as possible, so that the space charge region formed therebetween is much larger than the remaining thickness of the second-doped-type cap layer after etching, thereby obtaining the maximum current-limiting effect and reducing the non-radiative recombination centers and leakage current introduced by etching damage to the maximum extent.

[0059] In yet another optional embodiment, the second-doped-type semiconductor layer includes a second-doped-type electron-blocking layer formed on the surface of the active layer and a second-doped-type cap layer formed on the surface of the second-doped-type electron-blocking layer. The second-doped-type electron-blocking layer has a doping concentration of 1E18-1E20 and a thickness of 10-100 nm. The second-doped-type cap layer has a doping concentration of 1E19-1E21 and a thickness of 10-500 nm.

[0060] The mesa structure is formed by etching the second-doped-type cap layer in the thickness direction. In this embodiment, the second-doped-type semiconductor layer in contact with the confinement layer is the second-doped-type cap layer and the second-doped-type electron-blocking layer. Therefore, when the confinement layer has the second-doped-type, the doping concentration of the confinement layer is smaller than that of the second-doped-type cap layer and that of the second-doped-type electron-blocking layer.

[0061] The height of the mesa structure is equal to the thickness of the second-doped-type cap layer. That is, the thickness of the grown confinement layer in the region where the second-doped-type cap layer is etched is equal to the thickness of the second-doped-type cap layer. Optionally, the difference between the doping concentration of the grown confinement layer and the doping concentration of the second-doped-type cap layer is as large as possible, so that a thick space charge region is formed between the two, to achieve the maximum current limiting effect, thereby minimizing the non-radiative recombination centers and leakage current introduced by etching damage.

[0062] It can be understood that the epitaxial structure in the present application is not limited to the structure described above, but can also include other layer structures, such as a substrate, a buffer layer, etc. The point of the present application is the second-doped-type semiconductor layer and the grown confinement layer, so the chip structure containing the second-doped-type semiconductor layer and the grown confinement layer and the limiting relationship between the two described in the present application should fall within the scope to be protected by the present application.

[0063] The chip structure of the present application further includes a first electrode and a second electrode.

[0064] The first electrode is electrically connected to the first-doped-type semiconductor layer. Optionally, the first electrode is formed on the surface of the first-doped-type semiconductor layer away from the active layer, and the orthogonal projection of the first electrode in the thickness direction has an overlapping region with the orthogonal projection of the mesa structure in the thickness direction. Alternatively, the first electrode is formed on the side surface of the first-doped-type semiconductor layer.

[0065] The second electrode is electrically connected to the second-doped-type semiconductor layer. Optionally, the second electrode is formed on the surface of the mesa structure, and the second electrode is electrically isolated from the confinement layer by an insulating layer.

[0066] The chip structure provided by the embodiments of the present application first forms a confinement layer of a different doping type or a different doping concentration than the second-doped-type semiconductor layer in the region where the second-doped-type semiconductor layer is etched, to form a space charge region between the etched side walls. The electric field in the space charge region prevents the further diffusion of free electrons and holes. Since the space charge region lacks free carriers (electrons and holes), it forms an insulating region that prevents the flow of current. In this way, the current flow path is controlled to bypass the etched side walls, greatly reducing the non-radiative recombination centers and leakage current introduced by etching damage, while also not introducing other problems that are detrimental to device performance. Second, by controlling the difference in concentration between the confinement layer and the second-doped-type semiconductor layer in contact with the confinement layer and controlling the proportion of the confinement layer in the thickness of the second-doped-type semiconductor layer, the size of the space charge region formed between the two is further adjusted, to further improve the current limiting effect of the space charge region on the current, thereby avoiding the non-radiative recombination centers and leakage current phenomenon of the etched side walls.

[0067] The chip structure of the present application is described in detail below with reference to several specific embodiments in conjunction with the accompanying drawings, so as to make the technical solution of the present application more clearly understood.

[0068] First embodiment:

[0069] As shown in FIG. 1, the chip structure in the first embodiment of the present application comprises, from bottom to top, a substrate 10, a buffer layer 20, an N-type layer 30, an active layer 40, a P-type EBL layer (electron blocking layer) 51 and a P-type cap layer 52. The P-type cap layer 52 is partially etched along the thickness direction to form a mesa structure. A confinement layer 60 is arranged on the side surface of the mesa structure (in the region where the P-type cap layer 52 is etched).

[0070] The material of the P-type EBL layer 51 is P-type AlGaN. The doping concentration of the P-type EBL layer 51 is 1E18. The thickness of the P-type EBL layer 51 is 50 nm.

[0071] The material of the P-type cap layer 52 is P-type GaN. The doping concentration of the P-type cap layer 52 is 1E19. The thickness of the P-type cap layer 52 is 50 nm. The height of the mesa structure is 30 nm, and the width is 3 μm.

[0072] The material of the confinement layer 60 is GaN. The doping type of the confinement layer 60 is P-type. The doping concentration of the confinement layer 60 is 1E18. The thickness of the confinement layer 60 is 30 nm.

[0073] The chip structure further comprises an insulating layer 70 formed on the side surface of the epitaxial structure composed of the buffer layer 20, the N-type layer 30, the active layer 40, the P-type EBL layer (electron blocking layer) 51 and the confinement layer 60, and the upper surface of the confinement layer 60 (the side surface facing away from the substrate 10). A first electrode 81 is arranged on the lower surface of the substrate 10 (the side surface facing away from the buffer layer 20), and overlaps with the part of the mesa structure in the thickness direction. A second electrode 82 is arranged on the upper surface of the P-type cap layer 52.

[0074] Second embodiment:

[0075] As shown in FIG. 2, the chip structure in the second embodiment of the present application comprises, from bottom to top, a substrate 10, a buffer layer 20, an N-type layer 30, an active layer 40, a P-type EBL layer (electron blocking layer) 51 and a P-type cap layer 52. The P-type cap layer 52 is completely etched along the thickness direction to form a mesa structure. A confinement layer 60 is arranged on the side surface of the mesa structure (in the region where the P-type cap layer 52 is etched).

[0076] The material of the P-type EBL layer 51 is P-type AlGaN. The doping concentration of the P-type EBL layer 51 is 1E18. The thickness of the P-type EBL layer 51 is 50 nm.

[0077] The material of the P-type cap layer 52 is P-type GaN. The doping concentration of the P-type cap layer 52 is 1E19. The thickness of the P-type cap layer 52 is 50 nm. The height of the mesa structure is 50 nm, and the width is 3 μm.

[0078] The material of the confinement layer 60 is GaN. The doping type of the confinement layer 60 is P-type. The doping concentration of the confinement layer 60 is 1E17. The thickness of the confinement layer 60 is 50 nm.

[0079] The chip structure further includes an insulating layer 70 formed on the side surface of the epitaxial structure composed of the buffer layer 20, the N-type layer 30, the active layer 40, the P-type EBL layer (electron blocking layer) 51, and the confinement layer 60, and the upper surface of the confinement layer 60 (the side surface facing away from the substrate 10). A first electrode 81 is provided on the lower surface of the substrate 10 (the side surface facing away from the buffer layer 20) and overlaps the orthographic projection of the mesa structure in the thickness direction. A second electrode 82 is provided on the upper surface of the P-type cap layer 52.

[0080] Third Embodiment:

[0081] As shown in FIG. 1, the chip structure in the third embodiment of the present application includes, from bottom to top, a substrate 10, a buffer layer 20, an N-type layer 30, an active layer 40, a P-type EBL layer (electron blocking layer) 51, and a P-type cap layer 52. The P-type cap layer 52 is partially etched in the thickness direction to form a mesa structure. The side surface of the mesa structure (in the region where the P-type cap layer 52 is etched) is provided with a confinement layer 60.

[0082] The material of the P-type EBL layer 51 is P-type AlGaN. The doping concentration of the P-type EBL layer 51 is 1E19. The thickness of the P-type EBL layer 51 is 50 nm.

[0083] The material of the P-type cap layer 52 is P-type GaN. The doping concentration of the P-type cap layer 52 is 3E19. The thickness of the P-type cap layer 52 is 100 nm. The height of the mesa structure is 80 nm, and the width is 8 μm.

[0084] The material of the confinement layer 60 is GaN. The doping type of the confinement layer 60 is P-type. The doping concentration of the confinement layer 60 is 1E19. The thickness of the confinement layer 60 is 80 nm.

[0085] The chip structure further includes an insulating layer 70 formed on the side surface of the epitaxial structure composed of the buffer layer 20, the N-type layer 30, the active layer 40, the P-type EBL layer (electron blocking layer) 51, and the confinement layer 60, and the upper surface of the confinement layer 60 (the side surface facing away from the substrate 10). A first electrode 81 is provided on the lower surface of the substrate 10 (the side surface facing away from the buffer layer 20) and overlaps the orthographic projection of the mesa structure in the thickness direction. A second electrode 82 is provided on the upper surface of the P-type cap layer 52.

[0086] A fourth embodiment:

[0087] As shown in FIG. 2, the chip structure in the fourth embodiment of the present application includes, from bottom to top, a substrate 10, a buffer layer 20, an N-type layer 30, an active layer 40, a P-type EBL layer (electron blocking layer) 51, and a P-type cap layer 52. The P-type cap layer 52 is etched along the thickness direction to form a mesa structure. A confinement layer 60 is provided on the side surface of the mesa structure (in the region where the P-type cap layer 52 is etched).

[0088] The material of the P-type EBL layer 51 is P-type AlGaN. The doping concentration of the P-type EBL layer 51 is 1E19. The thickness of the P-type EBL layer 51 is 50 nm.

[0089] The material of the P-type cap layer 52 is P-type GaN. The doping concentration of the P-type cap layer 52 is 3E19. The thickness of the P-type cap layer 52 is 100 nm. The height of the mesa structure is 100 nm, and the width is 8 μm.

[0090] The material of the confinement layer 60 is GaN. The doping type of the confinement layer 60 is P-type. The doping concentration of the confinement layer 60 is 1E18. The thickness of the confinement layer 60 is 100 nm.

[0091] The chip structure further includes an insulating layer 70 formed on the side surface of the epitaxial structure composed of the buffer layer 20, the N-type layer 30, the active layer 40, the P-type EBL layer (electron blocking layer) 51, and the confinement layer 60, and on the upper surface of the confinement layer 60 (the side surface facing away from the substrate 10). A first electrode 81 is provided on the lower surface of the substrate 10 (the side surface facing away from the buffer layer 20), and overlaps with the portion of the mesa structure in the thickness direction. A second electrode 82 is provided on the upper surface of the P-type cap layer 52.

[0092] A fifth embodiment:

[0093] As shown in FIG. 1, the chip structure in the fifth embodiment of the present application includes, from bottom to top, a substrate 10, a buffer layer 20, an N-type layer 30, an active layer 40, a P-type EBL layer (electron blocking layer) 51, and a P-type cap layer 52. The P-type cap layer 52 is partially etched along the thickness direction to form a mesa structure. A confinement layer 60 is provided on the side surface of the mesa structure (in the region where the P-type cap layer 52 is etched).

[0094] The material of the P-type EBL layer 51 is P-type AlGaN. The doping concentration of the P-type EBL layer 51 is 1E20. The thickness of the P-type EBL layer 51 is 50 nm.

[0095] The material of the P-type cap layer 52 is P-type GaN. The doping concentration of the P-type cap layer 52 is 6E19. The thickness of the P-type cap layer 52 is 200 nm. The height of the mesa structure is 170 nm, and the width is 15 μm.

[0096] The material of the confinement layer 60 is GaN. The doping type of the confinement layer 60 is P-type. The doping concentration of the confinement layer 60 is 1E19. The thickness of the confinement layer 60 is 170 nm.

[0097] The chip structure further includes an insulating layer 70 formed on the side surface of the epitaxial structure composed of the buffer layer 20, the N-type layer 30, the active layer 40, the P-type EBL layer (electron blocking layer) 51, and the confinement layer 60, and the upper surface of the confinement layer 60 (the side surface facing away from the substrate 10). A first electrode 81 is provided on the lower surface of the substrate 10 (the side surface facing away from the buffer layer 20) and overlaps the portion of the mesa structure in the thickness direction. A second electrode 82 is provided on the upper surface of the P-type cap layer 52.

[0098] Sixth Embodiment:

[0099] As shown in FIG. 2, the chip structure in the sixth embodiment of the present application includes, from bottom to top, a substrate 10, a buffer layer 20, an N-type layer 30, an active layer 40, a P-type EBL layer (electron blocking layer) 51, and a P-type cap layer 52. The P-type cap layer 52 is etched in the thickness direction to form a mesa structure. The side surface of the mesa structure (the region in which the P-type cap layer 52 is etched) is provided with a confinement layer 60.

[0100] The material of the P-type EBL layer 51 is P-type AlGaN. The doping concentration of the P-type EBL layer 51 is 1E20. The thickness of the P-type EBL layer 51 is 50 nm.

[0101] The material of the P-type cap layer 52 is P-type GaN. The doping concentration of the P-type cap layer 52 is 6E19. The thickness of the P-type cap layer 52 is 200 nm. The height of the mesa structure is 200 nm, and the width is 15 μm.

[0102] The material of the confinement layer 60 is GaN. The doping type of the confinement layer 60 is P-type. The doping concentration of the confinement layer 60 is 1E19. The thickness of the confinement layer 60 is 200 nm.

[0103] The chip structure further includes an insulating layer 70 formed on the side surface of the epitaxial structure composed of the buffer layer 20, the N-type layer 30, the active layer 40, the P-type EBL layer (electron blocking layer) 51, and the confinement layer 60, and the upper surface of the confinement layer 60 (the side surface facing away from the substrate 10). A first electrode 81 is provided on the lower surface of the substrate 10 (the side surface facing away from the buffer layer 20) and overlaps the portion of the mesa structure in the thickness direction. A second electrode 82 is provided on the upper surface of the P-type cap layer 52.

[0104] Seventh embodiment:

[0105] As shown in FIG. 1, the chip structure in the seventh embodiment of the present application includes, from bottom to top, a substrate 10, a buffer layer 20, an N-type layer 30, an active layer 40, a P-type EBL layer (electron blocking layer) 51, and a P-type cap layer 52. The P-type cap layer 52 is partially etched in the thickness direction to form a mesa structure. A confinement layer 60 is provided on the side surface of the mesa structure (in the region where the P-type cap layer 52 is etched).

[0106] The material of the P-type EBL layer 51 is P-type AlGaN. The doping concentration of the P-type EBL layer 51 is 1E20. The thickness of the P-type EBL layer 51 is 50 nm.

[0107] The material of the P-type cap layer 52 is P-type GaN. The doping concentration of the P-type cap layer 52 is 1E20. The thickness of the P-type cap layer 52 is 300 nm. The height of the mesa structure is 250 nm, and the width is 20 μm.

[0108] The material of the confinement layer 60 is GaN. The doping type of the confinement layer 60 is P-type. The doping concentration of the confinement layer 60 is 5E19. The thickness of the confinement layer 60 is 250 nm.

[0109] The chip structure further includes an insulating layer 70 formed on the side surface of the epitaxial structure composed of the buffer layer 20, the N-type layer 30, the active layer 40, the P-type EBL layer (electron blocking layer) 51, and the confinement layer 60, and on the upper surface of the confinement layer 60 (the side surface facing away from the substrate 10). A first electrode 81 is provided on the lower surface of the substrate 10 (the side surface facing away from the buffer layer 20), and overlaps with the portion of the mesa structure in the thickness direction. A second electrode 82 is provided on the upper surface of the P-type cap layer 52.

[0110] Eighth embodiment:

[0111] As shown in FIG. 2, the chip structure in the eighth embodiment of the present application includes, from bottom to top, a substrate 10, a buffer layer 20, an N-type layer 30, an active layer 40, a P-type EBL layer (electron blocking layer) 51, and a P-type cap layer 52. The P-type cap layer 52 is completely etched in the thickness direction to form a mesa structure. A confinement layer 60 is provided on the side surface of the mesa structure (in the region where the P-type cap layer 52 is etched).

[0112] The material of the P-type EBL layer 51 is P-type AlGaN. The doping concentration of the P-type EBL layer 51 is 1E20. The thickness of the P-type EBL layer 51 is 50 nm.

[0113] The material of the P-type cap layer 52 is P-type GaN. The doping concentration of the P-type cap layer 52 is 1E20. The thickness of the P-type cap layer 52 is 300 nm. The mesa structure has a height of 300 nm and a width of 20 μm.

[0114] The material of the confinement layer 60 is GaN. The doping type of the confinement layer 60 is P-type. The doping concentration of the confinement layer 60 is 5E19. The thickness of the confinement layer 60 is 300 nm.

[0115] The chip structure further includes an insulating layer 70 formed on the side surface of the epitaxial structure composed of the buffer layer 20, the N-type layer 30, the active layer 40, the P-type EBL layer (electron blocking layer) 51, and the confinement layer 60, and the upper surface of the confinement layer 60 (the side surface facing away from the substrate 10). A first electrode 81 is provided on the lower surface of the substrate 10 (the side surface facing away from the buffer layer 20) and overlaps the orthographic projection of the mesa structure in the thickness direction. A second electrode 82 is provided on the upper surface of the P-type cap layer 52.

[0116] Ninth Embodiment:

[0117] As shown in FIG. 1, the chip structure in the ninth embodiment of the present application includes, from bottom to top, a substrate 10, a buffer layer 20, an N-type layer 30, an active layer 40, a P-type EBL layer (electron blocking layer) 51, and a P-type cap layer 52. The P-type cap layer 52 is partially etched in the thickness direction to form a mesa structure. The side surface of the mesa structure (in the region where the P-type cap layer 52 is etched) is provided with a confinement layer 60.

[0118] The material of the P-type EBL layer 51 is P-type AlGaN. The doping concentration of the P-type EBL layer 51 is 1E18. The thickness of the P-type EBL layer 51 is 50 nm.

[0119] The material of the P-type cap layer 52 is P-type GaN. The doping concentration of the P-type cap layer 52 is 3E19. The thickness of the P-type cap layer 52 is 100 nm. The mesa structure has a height of 80 nm and a width of 8 μm.

[0120] The material of the confinement layer 60 is GaN. The doping type of the confinement layer 60 is N-type. The doping concentration of the confinement layer 60 is 5E19. The thickness of the confinement layer 60 is 80 nm.

[0121] The chip structure further includes an insulating layer 70 formed on the side surface of the epitaxial structure composed of the buffer layer 20, the N-type layer 30, the active layer 40, the P-type EBL layer (electron blocking layer) 51, and the confinement layer 60, and the upper surface of the confinement layer 60 (the side surface facing away from the substrate 10). A first electrode 81 is provided on the lower surface of the substrate 10 (the side surface facing away from the buffer layer 20) and overlaps the orthographic projection of the mesa structure in the thickness direction. A second electrode 82 is provided on the upper surface of the P-type cap layer 52.

[0122] Tenth embodiment:

[0123] As shown in FIG. 2, the chip structure in the tenth embodiment of the present application includes, from bottom to top, a substrate 10, a buffer layer 20, an N-type layer 30, an active layer 40, a P-type EBL layer (electron blocking layer) 51, and a P-type cap layer 52. The P-type cap layer 52 is etched along the thickness direction to form a mesa structure. A confinement layer 60 is provided on the side surface of the mesa structure (in the region where the P-type cap layer 52 is etched).

[0124] The material of the P-type EBL layer 51 is P-type AlGaN. The doping concentration of the P-type EBL layer 51 is 1E18. The thickness of the P-type EBL layer 51 is 50 nm.

[0125] The material of the P-type cap layer 52 is P-type GaN. The doping concentration of the P-type cap layer 52 is 6E19. The thickness of the P-type cap layer 52 is 100 nm. The height of the mesa structure is 100 nm, and the width is 8 μm.

[0126] The material of the confinement layer 60 is GaN. The confinement layer 60 is undoped. The thickness of the confinement layer 60 is 100 nm.

[0127] The chip structure further includes an insulating layer 70 formed on the side surface of the epitaxial structure composed of the buffer layer 20, the N-type layer 30, the active layer 40, the P-type EBL layer (electron blocking layer) 51, and the confinement layer 60, and on the upper surface of the confinement layer 60 (the side surface facing away from the substrate 10). A first electrode 81 is provided on the lower surface of the substrate 10 (the side surface facing away from the buffer layer 20), and overlaps with the portion of the mesa structure in the thickness direction. A second electrode 82 is provided on the upper surface of the P-type cap layer 52.

[0128] Eleventh embodiment:

[0129] As shown in FIG. 3, the chip structure in the eleventh embodiment of the present application includes, from bottom to top, a substrate 10, a buffer layer 20, an N-type layer 30, a quantum well layer 40, a P-type EBL layer (electron blocking layer) 51, and a P-type cap layer 52. The P-type cap layer 52 is etched along the thickness direction to form a mesa structure. A confinement layer 60 is provided on the side surface of the mesa structure (in the region where the P-type cap layer 52 is etched).

[0130] The material of the P-type EBL layer 51 is P-type AlGaN. The doping concentration of the P-type EBL layer 51 is 1E19. The thickness of the P-type EBL layer 51 is 50 nm.

[0131] The material of the P-type cap layer 52 is P-type GaN. The doping concentration of the P-type cap layer 52 is 3E19. The thickness of the P-type cap layer 52 is 100 nm. The height of the mesa structure is 100 nm, and the width is 8 μm.

[0132] The material of the confinement layer 60 is GaN. The doping type of the confinement layer 60 is P-type. The doping concentration of the confinement layer 60 is 1E18. The thickness of the confinement layer 60 is 100 nm.

[0133] The chip structure further includes an insulating layer 70 formed on the side surface of the epitaxial structure composed of the quantum well layer 40, the P-type EBL layer (electron blocking layer) 51 and the confinement layer 60, and the upper surface of the confinement layer 60 (the side surface away from the substrate 10). The first electrode 81 is formed on the upper surface of the substrate 10 (the side surface close to the buffer layer 20) and is arranged to conform to the side surface of the N-type layer 30 and the buffer layer 20. The second electrode 82 is arranged on the upper surface of the P-type cap layer 52.

[0134] Twelfth embodiment:

[0135] The chip structure in the first embodiment of the present application includes, from bottom to top, the substrate 10, the buffer layer 20, the N-type layer 30, the active layer 40, the P-type EBL layer (electron blocking layer) 51 and the P-type cap layer 52. The P-type cap layer 52 is partially etched in the thickness direction to form a mesa structure. The confinement layer 60 is arranged on the side surface of the mesa structure (in the region where the P-type cap layer 52 is etched).

[0136] The material of the P-type EBL layer 51 is P-type AlGaN. The doping concentration of the P-type EBL layer 51 is 1E18. The thickness of the P-type EBL layer 51 is 50 nm.

[0137] The material of the P-type cap layer 52 is P-type GaAs or GaNAs or InGaN or AlGaN. The doping concentration of the P-type cap layer 52 is 1E19. The thickness of the P-type cap layer 52 is 50 nm. The height of the mesa structure is 30 nm, and the width is 3 pm.

[0138] The material of the confinement layer 60 is GaAs or GaNAs or InGaN or AlGaN (Al content is 0.4%). The doping type of the confinement layer 60 is P-type. The doping concentration of the confinement layer 60 is 1E18. The thickness of the confinement layer 60 is 30 nm.

[0139] The chip structure further includes an insulating layer 70 formed on the side surface of the epitaxial structure composed of the buffer layer 20, the N-type layer 30, the active layer 40, the P-type EBL layer (electron blocking layer) 51 and the confinement layer 60, and the upper surface of the confinement layer 60 (the side surface away from the substrate 10). The first electrode 81 is arranged on the lower surface of the substrate 10 (the side surface away from the buffer layer 20) and overlaps with the part of the mesa structure in the thickness direction. The second electrode 82 is arranged on the upper surface of the P-type cap layer 52.

[0140] Referring to FIG. 4, the application also provides a preparation method of the chip structure, which comprises the following steps:

[0141] S1, providing a substrate, and sequentially forming a first doped type semiconductor layer, an active layer and a second doped type semiconductor layer on the substrate.

[0142] For example, a buffer layer, an N-type layer, an active layer, a P-type EBL layer and a P-type cap layer are sequentially epitaxially grown on the surface of the substrate. The material of the P-type EBL layer can be P-type AlGaN. The material of the P-type cap layer can be P-type GaN.

[0143] S2, etching the second doped type semiconductor layer in the thickness direction to form a mesa structure.

[0144] For example, a mask layer can be formed on the surface of the P-type cap layer by using a photolithography and development technology. The mask material can be SiN x , SiO2, etc. The P-type cap layer is etched by using the mask layer to form the mesa structure.

[0145] S3, growing a confinement layer in the etched region, the confinement layer being in contact with the mesa structure, the confinement layer having the second doped type or the first doped type or not having a doped type, and when the confinement layer has the second doped type, the doping concentration of the confinement layer is lower than the doping concentration of the second doped type semiconductor layer.

[0146] For example, the confinement layer is epitaxially grown to be low-p-doped or not doped or n-doped. The doping concentration of the low-p-doped confinement layer is as low as possible compared with the doping concentration of the P-type cap layer or the P-type EBL layer. When the confinement layer is directly in contact with the P-type cap layer and the P-type EBL layer, the doping concentration of the confinement layer is lower than that of the P-type cap layer and the P-type EBL layer with lower doping concentration. When the confinement layer is directly in contact with the P-type cap layer, the doping concentration of the confinement layer is lower than that of the P-type cap layer.

[0147] S4, forming a first electrode electrically connected to the first doped type semiconductor layer and a second electrode electrically connected to the second doped type semiconductor layer.

[0148] For example, the first electrode can be formed on the lower surface (the surface away from the buffer layer) of the substrate within the range of the orthogonal projection of the mesa structure in the thickness direction, and the second electrode can be formed on the upper surface of the P-type cap layer. The second electrode is electrically isolated from the entire epitaxial structure by an insulating layer.

[0149] For another example, the first electrode can be arranged on the upper surface (the surface close to the buffer layer) of the substrate and adhered to the side surface of the N-type layer and the buffer layer, and the second electrode can be formed on the upper surface of the P-type cap layer. The second electrode is electrically isolated from the entire epitaxial structure by an insulating layer.

[0150] Compared with the prior art, the chip structure and the preparation method thereof provided by the embodiments of the present application form a space charge region between the etched sidewall and the limiting layer with different doping type or different doping concentration from the second doping type semiconductor layer in the region of the second doping type semiconductor layer being etched, so as to control the current flow path to bypass the etched sidewall, reduce the non-radiative recombination center and leakage current introduced by etching damage, and also will not introduce other problems adverse to the device performance.

[0151] The chip structure and the preparation method thereof provided by the embodiments of the present application control the concentration difference between the limiting layer and the second doping type semiconductor layer and the proportion of the limiting layer in the thickness of the second doping type semiconductor layer, control the size of the space charge region formed between the two, and further improve the current limiting effect of the space charge region on the current, so as to avoid the non-radiative recombination center and leakage current phenomenon of the etched sidewall.

[0152] It is obvious for those skilled in the art that the present application is not limited to the details of the above exemplary embodiments, and the present application can be implemented in other specific forms without departing from the spirit or essential characteristics of the present application. Therefore, the embodiments should be regarded as exemplary and non-limiting, and the scope of the present application is defined by the appended claims rather than the above description, and all changes falling within the meaning and scope of the equivalent elements of the claims are intended to be included in the present application. Any reference signs in the claims should not be regarded as limiting the claims involved.

[0153] In addition, it should be understood that although the present specification is described in terms of embodiments, not every embodiment contains only one independent technical solution, and the description of the specification is only for the sake of clarity, and those skilled in the art should regard the specification as a whole, and the technical solutions in each embodiment can be properly combined to form other embodiments that those skilled in the art can understand.

Claims

1. A chip structure, comprising: an epitaxial structure, the epitaxial structure comprising a first doped type semiconductor layer, a second doped type semiconductor layer, and an active layer disposed between the first doped type semiconductor layer and the second doped type semiconductor layer, a mesa structure formed on a side of the second doped type semiconductor layer facing away from the active layer; the epitaxial structure further comprising a confinement layer formed on a side of the mesa structure and in contact with the mesa structure, the confinement layer having a second doped type or a first doped type or no doped type; the confinement layer being a semiconductor material composed of any one of Ga, In, Al of group III elements and any one of N, As, P of group V elements, a space charge region formed between the confinement layer and the second doped type semiconductor layer, the space charge region being capable of controlling a current flow path to bypass the side of the mesa structure; wherein, when the confinement layer has the second doped type, a doped concentration of the confinement layer is less than a doped concentration of the second doped type semiconductor layer in contact with the confinement layer; and when the confinement layer contains Al, an Al content is less than 0.5%. the second doped type semiconductor layer comprising a second doped type electron blocking layer formed on a surface of the active layer and a second doped type cap layer formed on a surface of the second doped type electron blocking layer, the second doped type electron blocking layer having a doped concentration of 1E18-1E20; and the second doped type cap layer having a doped concentration of 1E19-1E21. the mesa structure being formed by partially etching the second doped type cap layer in a thickness direction; wherein, when the confinement layer has the second doped type, a doped concentration of the confinement layer is less than a doped concentration of the second doped type cap layer. a height of the mesa structure is less than a thickness of the second doped type cap layer, and the height of the mesa structure is greater than half of the thickness of the second doped type cap layer. the mesa structure being formed by etching the second doped type cap layer in the thickness direction entirely, the height of the mesa structure being equal to the thickness of the second doped type cap layer; wherein, when the confinement layer has the second doped type, a doped concentration of the confinement layer is less than a doped concentration of the second doped type cap layer and less than a doped concentration of the second doped type electron blocking layer. the confinement layer being formed in an etched region, and a thickness of the confinement layer being equal to the height of the mesa structure. when the confinement layer has the first doped type, a doped concentration of the confinement layer ranges from 1E17 to 5E19; and when the confinement layer has the second doped type, a doped concentration of the confinement layer ranges from 1E17 to 1E20. further comprising: a first electrode electrically connected to the first doped type semiconductor layer; and a second electrode electrically connected to the second doped type semiconductor layer. the second electrode being formed on a surface of the mesa structure, the second electrode being electrically isolated from the confinement layer by an insulating layer. ​ ​ ​ ​ ​ 2. The chip structure of claim 1, wherein, ​ 3. The chip structure of claim 2, wherein, ​ ​ 4. The chip structure of claim 3, wherein, ​ 5. The chip structure of claim 2, wherein, ​ ​ 6. The chip structure according to any of claims 3-5, wherein, ​ 7. The chip structure of claim 1, wherein, ​ ​ 8. The chip structure of claim 1, wherein, ​ ​ ​ 9. The chip structure of claim 8, wherein, ​ 10. The chip structure of claim 8, wherein, The first electrode is formed on a surface of the first doped semiconductor layer away from the active layer, and a projection of the first electrode on a thickness direction has an overlapping area with a projection of the mesa structure on the thickness direction. Or, The first electrode is formed on a side surface of the first doped semiconductor layer.

11. A method for manufacturing the chip structure according to any one of claims 1-10, comprising: providing a substrate, and sequentially forming a first doped semiconductor layer, an active layer and a second doped semiconductor layer on the substrate; etching the second doped semiconductor layer in a thickness direction to form a mesa structure; growing a confinement layer in the etched area, the confinement layer being in contact with the mesa structure, the confinement layer being of a semiconductor material composed of any one of Ga, In and Al of the third group and any one of N, As and P of the fifth group, the confinement layer having the second doped type or the first doped type or no doped type, when the confinement layer has the second doped type, a doped concentration of the confinement layer is less than a doped concentration of the second doped semiconductor layer in contact with the confinement layer; forming a first electrode electrically connected to the first doped semiconductor layer and a second electrode electrically connected to the second doped semiconductor layer.

12. The chip structure according to claim 1, wherein the active layer is a single quantum well layer or a multiple quantum well layer.

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