CPU capable of quickly processing memory copy instruction, and method using same

Abstract

Disclosed in the present invention are a CPU capable of quickly processing a memory copy instruction, and a method using same. The CPU comprises: an instruction decoder, a general-purpose register, a memory copy controller, a bus interface, a buffer, an adder, and a comparator. The memory copy controller comprises a state machine, and the state machine comprises an idle state, a read state, and a write state, wherein in the idle state, the memory copy controller waits to receive a valid memory copy instruction; in the read state, the memory copy controller reads data of a source address by means of the bus interface, and temporarily stores the data in the buffer; and in the write state, the memory copy controller writes the data, which is temporarily stored in the buffer, to a destination address by means of the bus interface. The adder is used for updating an address. The comparator is used for determining the end of copying. The present invention can maximize the utilization of a memory bandwidth to greatly improve the memory copy efficiency, can support an arbitrary alignment mode and support interruption, can reduce the power consumption of instruction fetching, and has a simple structure.

Description

CPU and method capable of quickly processing memory copy instruction TECHNICAL FIELD

[0001] The present application belongs to the technical field of computers, and particularly relates to a CPU and method capable of quickly processing memory copy instruction. BACKGROUND

[0002] Memory copy (memcpy) is a simple and diverse operation, which is generally implemented in two ways, namely software method and hardware method.

[0003] Software method: there are many codes that can be implemented, but all of them need to run a loop program, repeatedly fetch instructions, and consume more power; meanwhile, the overall copy performance is affected by instruction bus latency; branch instruction prediction failure of the CPU will introduce bubbles in the pipeline, reducing execution efficiency; the minimum value of the source address alignment byte number, the target address alignment byte number and the CPU register width is selected as the maximum byte number (n) of single copy, and for memory copy of any address, the delay fluctuation is large; since the single copy is limited by the maximum width of the CPU register, the memory bandwidth cannot be maximally utilized, resulting in low memory copy efficiency.

[0004] Hardware method: relies on DMA implementation, but DMA generally does not support source / destination address alignment; in addition, software needs to wait for the completion of the last DMA before performing the next DMA operation, which cannot be suspended in the interrupt / thread switching scenario; in addition, DMA is a non-standard hardware resource, and the use of DMA by different design manufacturers is different, and application programs that need to ensure compatibility often use software method for memory copy, such as operating system, protocol stack, system library, etc. SUMMARY

[0005] The present application provides a CPU and method capable of quickly processing memory copy instruction to solve the problem of low memory copy efficiency in the prior art.

[0006] Technical scheme: a CPU capable of quickly processing memory copy instruction, comprising:

[0007] An instruction decoder, an input end of which inputs CPU instructions, and an output end of which is connected to a read port of a general register and a memory copy controller, used for decoding valid memory copy instructions, the valid memory copy instructions including a source address register index, a target address register index and a copy end information register index;

[0008] A general register, connected to the memory copy controller, used for storing the source address, the target address and the copy end information;

[0009] The memory copy controller comprises a state machine, the state machine comprises an idle state, a read state and a write state, in the idle state, an effective memory copy instruction is received; in the read state, the bus interface reads data of a source address and stores the data in a buffer; in the write state, the bus interface writes the data stored in the buffer to a target address;

[0010] The bus interface is connected with the memory copy controller and the buffer, and is externally connected with an external memory;

[0011] The buffer is connected with the memory copy controller;

[0012] The adder is connected with the read port of the general register and the memory copy controller at input ends, and is connected with the write port of the general register at an output end, and is used for updating the source address and the target address;

[0013] The comparator is connected with the read port of the general register at input ends, and is connected with the memory copy controller at an output end, and is used for judging whether the copy is completed according to the copy end information.

[0014] Further, the buffer space is M*2 N bytes, wherein M is a positive integer, 2 N is the bus interface width.

[0015] Further, the copy end information is one or more of an end address of the source address, an end address of the target address and a total length of the copy.

[0016] Further, the state machine, the adder and the bus interface are one; one write port of the general register is occupied, and is used for writing the updated source address or target address in time; two read ports of the general register are occupied, a first read port is used for reading the copy end information, and a second read port is used for reading the current source address and target address in time; a first selector is further included, two input ends of the first selector input a source address register mark and a target address register mark respectively, a control end is connected with the memory copy controller, and an output end is connected with the second read port and the write port of the general register; in the read state, the first selector outputs the source address register mark; in the write state, the first selector outputs the target address register mark.

[0017] Further, the state machine, the adder and the bus interface are two, including a read state machine, a read adder and a read bus interface used for reading operation, a write state machine, a write adder and a write bus interface used for writing operation, the read state machine comprises an idle state and a read state, and the write state machine comprises an idle state and a write state; two write ports of the general register are occupied, and are used for writing the updated source address and target address respectively; three read ports of the general register are occupied, and are used for reading the copy end information, the source address and the target address respectively.

[0018] A method for fast processing memory copy instruction using the CPU capable of fast processing memory copy instruction, comprising the following steps:

[0019] The state machine of the memory copy controller is initially in idle state;

[0020] When the instruction decoder receives a valid memory copy instruction, the source address register index, the target address register index, the copy end information register index are read from the valid memory copy instruction to the general register, and a start signal is sent to the memory copy controller, and the source address, the target address initial value and the copy end information are obtained and outputted by the general register through the source address register index, the target address register index and the copy end information register index;

[0021] When the memory copy controller receives the start signal, the state machine jumps to the read state, and the data is read from the source address to the buffer through the bus interface, and jumps to the write state after reading the data at least once; in the write state, the data in the buffer is written to the target address according to the first-in first-out principle through the bus interface, and the written data in the buffer is cleared, and jumps to the read state after writing the data at least once; the read state and the write state are switched constantly, the source address and the target address are updated by the adder, and the copy is determined to be completed by the comparator according to the copy end information, and returns to the idle state if the copy is completed.

[0022] Further, in the read state, 1-2 N byte data is read each time; in the write state, 1-2 N byte data is written each time, and the bus interface width is 2 N .

[0023] Further, in the read state, if the buffer empty space is less than 2 N byte, jump to the write state, otherwise remain in the read state; in the write state, if the buffer valid space is less than 2 N byte, jump to the read state, otherwise remain in the write state.

[0024] Further, the method for determining whether the copy is completed according to the copy end information is:

[0025] In the read state, the read operation is predicted to be completed soon by the comparator according to the source address and the copy end information, if the read operation is completed soon, the read state is followed by the empty state instead of the write state, otherwise the read operation is executed normally and jumps to the write operation;

[0026] In the empty state, the data in the buffer is written to the target address, and the written data is cleared until the buffer is empty, and the memory copy is completed.

[0027] Further, if the state machine is in the non-idle state, the memory copy controller receives the interrupt request signal or the debug signal of the instruction decoder, the state machine first jumps to the empty state, and after the state machine returns to the idle state, the processor normally responds to the interrupt or the debug request; if the state machine is in the idle state, the memory copy controller receives the interrupt request signal or the debug signal of the instruction decoder, the processor normally responds to the interrupt or the debug request; during the interrupt or the debug response process, the return program pointer is saved as the program pointer of the current memory copy instruction, and the general register is saved and restored according to the application program binary interface; after the interrupt or the debug exits, the program pointer is restored to the return program pointer, the processor re-executes the memory copy instruction, and continues to execute from the memory copy breakpoint, and completes the remaining copy.

[0028] A method for quickly processing a memory copy instruction using the CPU capable of quickly processing the memory copy instruction, comprising the following steps:

[0029] The read state machine and the write state machine of the memory copy controller are initially in the idle state;

[0030] When the instruction decoder receives a valid memory copy instruction, the source address register label, the target address register label, and the copy end information register label are read from the valid memory copy instruction to the general register, and a start signal is sent to the memory copy controller; the source address, the target address, and the copy end information are obtained and output by the general register through the source address register label, the target address register label, and the copy end information register label;

[0031] After the memory copy controller receives the start signal, the read state machine jumps to the read state, constantly reads data from the source address to the buffer through the read bus interface, and updates the source address by using the read adder until the read operation ends, and the read state machine jumps to the idle state;

[0032] At the same time, the write state machine of the memory copy controller jumps to the write state, sequentially writes the data in the buffer to the target address according to the first-in first-out principle through the write bus interface, and clears the written data in the buffer, and updates the target address by using the write adder until the write operation ends, and the write state machine jumps to the idle state.

[0033] Further, in the read state, 1-2 bytes of data are read each time; in the write state, 1-2 bytes of data are written each time. N N N The bus interface width is 2.

[0034] Further, the method for judging whether the read operation ends is that the comparator judges whether the read operation is completed according to the source address and the copy end information.​​

[0035] The method for determining the end of the write operation is: when the read state machine is idle, if the buffer is empty, the write operation is completed; if the buffer is not empty, the write operation continues until the buffer is empty; if the read state machine is not idle, the write state machine always remains in the write state.

[0036] Further, when the memory copy controller receives an interrupt request signal or a debugging signal of the instruction decoder, if at least one of the read state machine and the write state machine is in the non-idle state, the read state machine first jumps to the idle state, and after the write state machine also jumps to the idle state, the processor normally responds to the interrupt or the debugging request; if the read state machine and the write state machine are both in the idle state, when the memory copy controller receives an interrupt request signal or a debugging signal of the instruction decoder, the processor normally responds to the interrupt or the debugging request; during the interrupt or the debugging response process, the return program pointer is saved as the program pointer of the current memory copy instruction, and the general register is saved and restored according to the application program binary interface; after the interrupt or the debugging exits, the program pointer is restored to the return program pointer, the processor re-executes the memory copy instruction, and continues to execute from the memory copy breakpoint, and completes the remaining copy.

[0037] Compared with the prior art, the CPU and the method for quickly processing a memory copy instruction provided by the application have the following beneficial effects:

[0038] (1) The memory bandwidth is maximally utilized, and the memory copy efficiency is greatly improved;

[0039] (2) The source address alignment mode and the target address alignment mode are not required, and can be arbitrarily aligned;

[0040] (3) There is no branch instruction overhead;

[0041] (4) The interrupt interruption is supported, and after the interrupt processing, the memory copy that is not completed is continued to be returned;

[0042] (5) The repeated instruction fetching is avoided, the instruction fetching power consumption is reduced, and the influence of the instruction bus latency is avoided;

[0043] (6) The original logic units of the CPU can be fully reused, the new units are few, and the structure is simple. For example, the adder, the comparator and the bus interface can reuse the original functional units in the CPU, and are selected for the memory copy instruction or the original path by increasing the selector. BRIEF DESCRIPTION OF DRAWINGS

[0044] Fig. 1 is a structural schematic diagram of the CPU capable of quickly processing a memory copy instruction according to the embodiment one;

[0045] Fig. 2 is a diagram of the change of data in the buffer in the memory copy process;

[0046] Figure 3 is a schematic diagram of the structure of a CPU capable of quickly processing a memory copy instruction according to Embodiment 2. DETAILED DESCRIPTION

[0047] The application will be further explained in connection with the accompanying drawings and specific embodiments.

[0048] Embodiment 1

[0049] A CPU capable of quickly processing a memory copy instruction, as shown in Figure 1, comprises an instruction decoder (DEC), a memory copy controller, general purpose registers (GPR), a bus interface, a buffer, an adder and a comparator.

[0050] The instruction decoder: the input end inputs CPU instructions, and the output end is connected to the read port of the general purpose registers and the memory copy controller, and is used for decoding valid memory copy instructions, which include the source address register label, the target address register label and the copy end information register label; the source address, the target address and the copy end information storage position in the general purpose registers can be obtained through the source address register label, the target address register label and the copy end information register label.

[0051] The memory copy controller: contains a state machine, which comprises an idle state, a read state and a write state; in the idle state, it waits for receiving valid memory copy instructions; in the read state, it reads the data of the source address through the bus interface and temporarily stores the data in the buffer; in the write state, it writes the data temporarily stored in the buffer to the target address through the bus interface.

[0052] The general purpose registers: connected to the memory copy controller, used for storing the source address and the target address; in this embodiment, the general purpose registers comprise a write port 1 (write port 1 address, write port 1 data, write port 1 enable), two read ports, read port 0 (read port 0 address, read port 0 data) and read port 1 (read port 1 address, read port 1 data). The write port 1 address is used for writing the source address or the target address register label, the write port 1 data is used for writing the source address or the target address updated through the adder, and the write port 1 enable is connected to the memory copy controller and is used for controlling the write enable of the write port 1. The read port 1 address selects the read-in source address register label or the target address register label under the selection of the selector, and the read port 0 address is used for reading in the copy end information, which can be the total length of the copy or the end address (the end address includes the end address relative to the source address and the end address relative to the target address); for example, in this embodiment, the copy end information is the end address relative to the source address.

[0053] The general register is a register stack for storing temporary results in the CPU, in which the source address, target address and copy end information are pre-stored. The source address register index in the memory copy instruction points to a register in the GPR, and the value corresponding to the register is the initial value of the source address, which is the first read address; the target address register index points to a register in the GPR, and the value corresponding to the register is the initial value of the target address, which is the first write address; the copy end information register index points to a register in the GPR, and the value corresponding to the register is the end address of the source address. During the working process of the memory copy controller, the adder will update the source address / target address according to the number of bytes read / written each time (read / write increment). If the copy end information is the total length of the copy, the remaining copy length also needs to be updated each time read / write. The controller will write the latest read address into the register pointed to by the source address register index SA IDX in real time, write the latest write address into the register pointed to by the target address register index DA IDX, and write the latest copy end information into the register pointed to by the copy end information register index EA IDX. That is, the register pointed to by SA IDX reflects the latest read address at all times, the register pointed to by DA IDX reflects the latest write address at all times, and the register pointed to by EA IDX reflects the latest copy end information at all times. The read / write state machine uses the addresses to access the memory and generate an end signal, respectively.

[0054] Bus interface: connects the memory copy controller and the buffer, receives the read / write request of the memory copy controller, and feeds back the bus response, and the bus interface is externally connected with the external memory. The memory copy controller controls the bus interface to perform read / write operation on the external memory according to the current source address / target address.

[0055] Buffer: connected with the memory copy controller; the buffer space is M*2 N bytes, where M is a positive integer, 2 N the bus interface width is 4 bytes, the buffer space is 8 bytes, and M is 2.

[0056] Adder: one input end is connected with the read port 1 data (source address / destination address) of the general register, the other input end is connected with the memory copy controller, the memory copy controller provides address increment, which is used to update the source address and the destination address. For example, in the read state, the source address needs to be added by 4 bytes after reading 4 bytes of data, the increment is 4 bytes, the source address is updated to the offset address through the adder, and is written back to the general register through the output end of the adder, or is written back through the write back unit (WB). The updating process of the destination address is the same. The adder is time-multiplexed through the first selector, the two input ends of the first selector are connected with the register number of the source address and the register number of the destination address respectively, the control end is connected with the memory copy controller, and the output end is connected with the general register. In the read state, the first selector outputs the register number of the source address; in the write state, the first selector outputs the register number of the destination address. Therefore, one adder is needed to be matched with the selector in this embodiment.

[0057] Comparator: one input end is connected with the read port 1 data (source address / destination address) of the general register, in this scheme, the comparison is only performed when the source address is input, the other input end is connected with the read port 0 data (end address of the source address) of the general register, and the output end is connected with the memory copy controller, which is used to judge whether the copy is completed.

[0058] In this embodiment, the adder, the comparator and the bus interface are only one group, and occupy one write port of the general register, and further comprise the first selector. When it is needed to be used in the read state and the write state respectively, the first selector is used for time-multiplexing. In addition, the adder, the comparator and the bus interface can also be multiplexed to realize the original functional units in the CPU, and are selected by the selector to be used for the memory copy instruction or the original path, so that the structure is simpler, and the connection between each part in the CPU includes direct connection and indirect connection.

[0059] In this embodiment, the memory copy controller only contains one state machine, which at least comprises an idle state, a read state and a write state, and can further comprise a clear state, which is used when the copy is completed.

[0060] A method for quickly processing a memory copy instruction using the CPU capable of quickly processing the memory copy instruction, comprising the following steps:

[0061] The state machine of the memory copy controller is initially in the idle state;

[0062] When the instruction decoder receives a valid memory copy instruction, it reads the source address register label, the destination address register label, and the copy end information register label from the valid memory copy instruction into the general-purpose register. At the same time, it sends a start signal to the memory copy controller. The general-purpose register can obtain and output the initial values ​​of the source address and destination address and the copy end information through the source address register label, the destination address register label, and the copy end information register label.

[0063] When the memory copy controller receives a start signal, its state machine transitions to the read state, and it reads data from the source address via the bus interface and temporarily stores it in the buffer, reading 1 to 2 bytes at a time. N For each byte of data, after reading the data at least once, the system jumps to write mode. In write mode, the data in the buffer is written sequentially to the target address via the bus interface according to the first-in-first-out principle, and the previously written data in the buffer is cleared. Each write operation consists of 1 to 2 bytes. N The system processes byte data, and after writing the data at least once, it jumps to the read state. It continuously switches between the read and write states, uses an adder to update the source and destination addresses, and uses a comparator to determine whether the copy is complete based on the copy end information. If the copy is complete, it returns to the idle state.

[0064] To maximize memory copy efficiency, read operations typically have a higher priority than write operations; that is, in read mode, if the buffer has less than 2 empty slots... N If the buffer reads a byte, it jumps to write mode; otherwise, it remains in read mode. In write mode, if the number of valid bits in the buffer is less than 2... N If the byte is empty, the program jumps to the read state; otherwise, it remains in the write state. The number of empty bits plus the number of valid bits equals M * 2. N This ensures that there is no idle waiting time during read / write switching, maximizing memory copy efficiency.

[0065] The determination of whether the copy is complete can be performed in either read or write mode, with read mode being the preferred method. In this case, a fourth state, namely the clear state, needs to be set. The specific method is as follows:

[0066] In read mode, the comparator uses the source address and copy end information (end address of the source address) to predict whether the read operation is about to be completed. Prediction means that before the read operation starts, it is determined whether the source address after the read has reached or exceeded the end address. If the determination is yes, it is considered that the read operation will be completed after reading one piece of data. After the read operation, it enters the clear state instead of the write state. Otherwise, the read operation is executed normally and jumps to the write operation.

[0067] In the emptying state, the data in the buffer is written to the target address, and the written data is cleared until the buffer is emptied and the memory copy is completed. The difference between the emptying state and the writing state is that in the writing state, the state machine jumps to the reading state when the buffer space reaches or exceeds 2 N bytes, while in the emptying state, the data in the buffer is written completely until the buffer is emptied and the state machine jumps to the idle state.

[0068] The present embodiment supports interrupt interruption. When the state machine is in a non-idle state and the memory copy controller receives an interrupt request signal or a debug signal from the instruction decoder, the state machine first jumps to the emptying state, and after the state machine returns to the idle state, the processor normally responds to the interrupt or the debug request; when the state machine is in the idle state and the memory copy controller receives an interrupt request signal or a debug signal from the instruction decoder, the processor normally responds to the interrupt or the debug request; during the interrupt or debug response process, the return program pointer is saved as the program pointer of the current memory copy instruction, and the general registers are saved and restored according to the application binary interface; after the interrupt or debug exits, the program pointer is restored to the return program pointer, the processor re-executes the memory copy instruction, and continues to execute from the memory copy breakpoint, completing the remaining copy.

[0069] In addition to the method of setting the emptying state, the same effect can also be achieved by an end flag. When the end flag is valid, it is equivalent to entering the emptying state. Before each reading, a comparison is made. If the result of the comparison is that the reading operation will be completed soon, the end flag is marked as valid, otherwise the end flag is marked as invalid. After the reading state, the writing state is switched. When the end flag is valid, all data in the buffer is written and the buffer is emptied in the writing state, and the reading state will not be jumped to again; when the end flag is invalid, the writing state is a normal writing operation, and after the writing operation, the reading state will still be jumped to according to the buffer space.

[0070] As shown in FIG. 2, the figure shows the change of data in the buffer in an example of a memory copy. In this example, EA = 0x1009, SA = 0x1001, DA = 0x2003, and the total length of the copy is 8 bytes. IDLE is the idle state, LOAD is the reading state, STORE is the writing state, and CLEAN is the emptying state. In the reading state, 4 bytes of data are read each time, and the data can also be marked. In the writing state, the maximum alignment principle (maximum size principle) is used.

[0071] In the present embodiment, the number of bytes in a single reading operation can reach the bus interface width 2 N , and the writing operation can use the maximum alignment principle and is not limited, so the memory copy efficiency can be improved as much as possible.

[0072] Embodiment Two

[0073] Embodiment two is different from embodiment one in that in embodiment two, reading and writing can be carried out simultaneously. As shown in Fig. 3, in this case, the memory copy controller needs two state machines for controlling reading and writing respectively, including a reading state machine and a writing state machine, the reading state machine including an idle state and a reading state for reading operation; the writing state machine including an idle state and a writing state for writing operation. This embodiment can carry out reading and writing simultaneously, so the memory copy efficiency is higher.

[0074] In addition to the state machines, there are two sets of adders and bus interfaces, one set of reading adder and reading bus interface for reading operation, and one set of writing adder and writing bus interface for writing operation. Two writing ports and three reading ports of the general register need to be occupied. One input end of the reading adder is connected to the data of reading port 1 of the general register, the other input end is connected to the reading state machine of the memory copy controller (to obtain reading increment), and the output end is connected to the data of writing port 1. One input end of the writing adder is connected to the data of reading port 2 of the general register, the other input end is connected to the writing state machine of the memory copy controller (to obtain writing increment), and the output end is connected to the data of writing port 2. The address of reading port 1 of the general register and the address of writing port 1 are both connected to SA IDX, the address of reading port 2 and the address of writing port 2 are both connected to DA IDX, and the address of reading port 0 is connected to SA IDX. The writing enable of writing port 1 is connected to the reading state machine for controlling the writing enable of writing port 1, and the writing enable of writing port 2 is connected to the writing state machine for controlling the writing enable of writing port 2.

[0075] A method for quickly processing a memory copy instruction using the above CPU capable of quickly processing a memory copy instruction, comprising the following steps:

[0076] The reading state machine and the writing state machine of the memory copy controller are initially in an idle state;

[0077] When the instruction decoder receives a valid memory copy instruction, the source address register index, the target address register index, and the copy end information register index are read from the valid memory copy instruction to the general register, the initial values of the source address and the target address and the copy end information are obtained through the source address register index, the target address register index, and the copy end information register index, and a start signal is sent to the memory copy controller, and reading and writing are carried out simultaneously;

[0078] The reading state machine of the memory copy controller jumps to a reading state, continuously reads data from the source address to the buffer through the reading bus interface, and updates the source address by using the reading adder, until the reading operation ends, and the reading state machine jumps to an idle state;

[0079] Meanwhile, the write state machine of the memory copy controller jumps to a write state, writes the data in the buffer to the target address through the write bus interface, clears the written data in the buffer, and updates the target address by using a write adder until the write operation is completed, and the write state machine jumps to an idle state.

[0080] The method for determining the end of the read operation is that the comparator determines whether the read operation is completed according to the source address and the copy end information.

[0081] The method for determining the end of the write operation is that, when the read state machine is idle, if the buffer is empty, the write operation is completed; if the buffer is not empty, the write operation continues until the buffer is empty; when the read state machine is not idle, the write state machine is always in the write state.

[0082] The embodiment supports interrupt interruption. When at least one of the read state machine and the write state machine is in a non-idle state, the memory copy controller receives an interrupt request signal or a debugging signal of the instruction decoder, the read state machine jumps to the idle state first, and after the write state machine also jumps to the idle state, the processor normally responds to the interrupt or the debugging request; when the read state machine and the write state machine are both in the idle state, the memory copy controller receives the interrupt request signal or the debugging signal of the instruction decoder, and the processor normally responds to the interrupt or the debugging request; during the interrupt or debugging response process, a return program pointer is saved as a program pointer of a current memory copy instruction, and general registers are saved and restored according to an application binary interface; after the interrupt or the debugging exits, the program pointer is restored to the return program pointer, the processor re-executes the memory copy instruction, and continues to execute from a memory copy breakpoint, thereby completing the remaining copy.

Claims

1. A CPU capable of fast handling of memory copy instructions, characterized in that, The application relates to a memory copy control device, which comprises the following parts: an instruction decoder, which is connected with a read port of a general register and a memory copy controller, and is used for decoding a valid memory copy instruction, the valid memory copy instruction comprising a source address register mark, a target address register mark and a copy end information register mark; a general register, which is connected with the memory copy controller, and is used for storing the source address, the target address and the copy end information; a memory copy controller, which comprises a state machine, the state machine comprising an idle state, a read state and a write state, in the idle state, the state machine waits for receiving the valid memory copy instruction, in the read state, the state machine controls a bus interface to read data of the source address and temporarily stores the data in a buffer, and in the write state, the state machine controls the bus interface to write the data temporarily stored in the buffer to the target address; a bus interface, which is connected with the memory copy controller and the buffer, and is externally connected with an external memory; a buffer, which is connected with the memory copy controller; an adder, which is connected with the read port of the general register and the memory copy controller, and is connected with a write port of the general register, and is used for updating the source address and the target address; a comparator, which is connected with the read port of the general register, and is connected with the memory copy controller, and is used for judging whether the copy is completed according to the copy end information.

2. The CPU capable of quickly processing memory copy instructions of claim 1, wherein, Buffer space is M*2 N bytes, where M is a positive integer, 2 N is the bus interface width.

3. The CPU capable of quickly processing memory copy instructions of claim 1, wherein, The copy end information is one or more of an end address of the source address, an end address of the target address and a total length of the copy.

4. The CPU capable of quickly processing memory copy instructions according to any one of claims 1 to 3, wherein, The state machine, the adder and the bus interface are one; one write port of the general register is used for writing the updated source address or target address; two read ports of the general register are used for reading the copy end information, the current source address and the target address; a first selector is further included, two input ends of the first selector input the source address register mark and the target address register mark, a control end of the first selector is connected with the memory copy controller, and an output end of the first selector is connected with the second read port and the write port of the general register; in the read state, the first selector outputs the source address register mark; and in the write state, the first selector outputs the target address register mark.

5. The CPU capable of quickly processing memory copy instructions according to any one of claims 1 to 3, wherein, The state machine, the adder and the bus interface are two, comprising a read state machine, a read adder and a read bus interface used for reading operation, and a write state machine, a write adder and a write bus interface used for writing operation; the read state machine comprises the idle state and the read state; and the write state machine comprises the idle state and the write state. Two write ports of the general register are used for writing the updated source address and target address; and three read ports of the general register are used for reading the copy end information, the source address and the target address.

6. A method for fast processing a memory copy instruction using the CPU capable of fast processing a memory copy instruction according to any one of claims 1 to 4, characterized by, The application further discloses a memory copy method, which comprises the following steps: the state machine of the memory copy controller is initially in the idle state; When the instruction decoder receives the valid memory copy instruction, the source address register index, the target address register index, and the copy end information register index are read from the valid memory copy instruction to the general register, and a start signal is sent to the memory copy controller, and the source address, the target address, and the copy end information are obtained and output by the source address register index, the target address register index, and the copy end information register index; When the memory copy controller receives the start signal, the state machine jumps to the read state, and the data is temporarily stored in the buffer by reading from the source address through the bus interface, and jumps to the write state after reading the data at least once; In the write state, the data in the buffer is sequentially written into the target address according to the first-in first-out principle through the bus interface, and the written data in the buffer is cleared, and jumps to the read state after writing the data at least once; the read state and the write state are switched constantly, the source address and the target address are updated by the adder, and whether the copy is completed is judged by the comparator according to the copy end information, and if the copy is completed, the state machine returns to the idle state.

7. The method for fast processing memory copy instruction according to claim 6, wherein, In read state, 1-2 N bytes of data are read at a time; in write state, 1-2 N bytes of data are written at a time, 2 N is the bus interface width.

8. The method for fast processing memory copy instruction according to claim 7, wherein, In the read state, if the buffer space is less than 2 N bytes, then jump to the write state, otherwise remain in the read state; in the write state, if the buffer valid bits are less than 2 N bytes, then jump to the read state, otherwise remain in the write state.

9. The method for fast processing memory copy instructions according to any of claims 6 to 8, characterized in that, The method for judging whether the copy is completed according to the copy end information is: In the read state, whether the read operation is about to be completed is pre-judged by the comparator according to the source address and the copy end information, if the read operation is about to be completed, the read state is entered into the empty state instead of the write state after the read operation, otherwise the read operation is executed normally and jumps to the write operation; In the empty state, the data in the buffer is written into the target address, and the written data is cleared until the buffer is empty, and the memory copy is completed.

10. The method for fast processing memory copy instruction of claim 9, wherein, If the state machine is in the non-idle state, when the memory copy controller receives the interrupt request signal or the debugging signal of the instruction decoder, the state machine first jumps to the empty state, and after the state machine returns to the idle state, the processor normally responds to the interrupt or the debugging request; If the state machine is in the idle state, when the memory copy controller receives the interrupt request signal or the debugging signal of the instruction decoder, the processor normally responds to the interrupt or the debugging request; during the interrupt or the debugging response process, the return program pointer is saved as the program pointer of the current memory copy instruction, and the general register is saved and restored according to the application program binary interface; after the interrupt or the debugging exits, the program pointer is restored as the return program pointer, the processor re-executes the memory copy instruction, and continues to execute from the memory copy breakpoint, and completes the remaining copy.

11. A method for fast processing a memory copy instruction using the CPU capable of fast processing a memory copy instruction according to claim 5, wherein, The steps include: The read state machine and the write state machine of the memory copy controller are initially in the idle state; When the instruction decoder receives the valid memory copy instruction, the source address register index, the target address register index, and the copy end information register index are read from the valid memory copy instruction to the general register, and a start signal is sent to the memory copy controller; the source address, the target address, and the copy end information are obtained and output by the source address register index, the target address register index, and the copy end information register index; After the memory copy controller receives the start signal, the read state machine jumps to the read state, continuously reads data from the source address to the buffer through the read bus interface, and updates the source address by using the read adder until the read operation is completed, and the read state machine jumps to the idle state; At the same time, the write state machine of the memory copy controller jumps to the write state, and sequentially writes the data in the buffer to the target address according to the first-in first-out principle through the write bus interface, and clears the written data in the buffer, and updates the target address by using the write adder until the write operation is completed, and the write state machine jumps to the idle state.

12. The method for fast processing memory copy instruction of claim 11, wherein, In read state, 1-2 N bytes of data are read each time; in write state, 1-2 N bytes of data are written each time, 2 N is the bus interface width.

13. The method for fast processing memory copy instruction according to claim 11 or 12, wherein, The method for judging whether the read operation is completed is that the comparator judges whether the read operation is completed according to the source address and the copy end information; The method for judging whether the write operation is completed is that when the read state machine is idle, if the buffer is empty, the write operation is completed; if the buffer is not empty, the write operation continues until the buffer is empty; if the read state machine is not idle, the write state machine always remains in the write state.

14. The method for fast processing memory copy instruction of claim 13, wherein, If at least one of the read state machine and the write state machine is in the non-idle state, when the memory copy controller receives the interrupt request signal or the debugging signal of the instruction decoder, the read state machine jumps to the idle state first, and after the write state machine also jumps to the idle state, the processor normally responds to the interrupt or the debugging request; if the read state machine and the write state machine are both in the idle state, when the memory copy controller receives the interrupt request signal or the debugging signal of the instruction decoder, the processor normally responds to the interrupt or the debugging request; during the interrupt or the debugging response process, the return program pointer is saved as the program pointer of the current memory copy instruction, and the general register is saved and restored according to the application program binary interface; after the interrupt or the debugging exits, the program pointer is restored to the return program pointer, the processor re-executes the memory copy instruction, and continues to execute from the memory copy breakpoint, and completes the remaining copy.

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