Carry logic circuit, carry cascade circuit, and chip

Abstract

The present application discloses a carry logic circuit, a carry cascade circuit, and a chip. The carry logic circuit comprises Y stages of cascaded carry operation modules and a carry output module; each stage of carry operation module is used for receiving i pairs of arithmetic signals; a first-stage carry operation module is used for outputting a first-stage carry generation signal and outputting a first-stage carry propagation signal; an x th-stage carry operation module is further used for receiving a previous-stage carry generation signal and a previous-stage carry propagation signal, outputting an x th-stage carry generation signal, and outputting an x th-stage carry propagation signal; and the carry output module is used for receiving an initial carry signal, a Y th-stage carry generation signal, and a Y th-stage carry propagation signal, and outputting a first carry signal. The present application improves the carry operation performance of the carry logic circuit.

Description

Carry logic circuit, carry cascading circuit and chip

[0001] Cross-reference to Related Applications

[0002] This application claims priority to Chinese application No. 202411067839.7, filed on August 5, 2024, which is hereby incorporated by reference in its entirety for all purposes. TECHNICAL FIELD

[0003] The present application relates to the technical field of integrated circuits, in particular to a carry logic circuit, a carry cascading circuit and a chip. BACKGROUND

[0004] The carry circuit is a key component for integrated circuits to achieve high-performance computing. The principle is to use multiple carry generators to process logical operations based on input signals, and then to pass the carry signals to the next stage of carry generators with a small delay. However, after cascading multiple carry generators, as the bit width of the operation increases, the number of cascaded carry generators also increases, resulting in a long carry chain, which introduces a large carry delay when the carry circuit processes data, ultimately causing the data processing and operation of the carry circuit to be not real-time. SUMMARY

[0005] In view of the above problems, the present application provides a carry logic circuit, a carry cascading circuit and a chip to solve the above technical problems.

[0006] In a first aspect, the present application provides a carry logic circuit, comprising Y-stage carry operation modules and a carry output module connected in cascade, each stage of carry operation modules is used for receiving i pairs of arithmetic signals, Y>1, i≥1;

[0007] The first-stage carry operation module is used for outputting a first-stage carry generation signal according to a preset carry generation operation strategy, and outputting a first-stage carry propagation signal according to a preset carry propagation operation strategy;

[0008] The x-stage carry operation module is also used for receiving a previous-stage carry generation signal and a previous-stage carry propagation signal, outputting an x-stage carry generation signal according to the carry generation operation strategy, and outputting an x-stage carry propagation signal according to the carry propagation operation strategy, 2≤x≤Y;

[0009] The carry output module is used for receiving a preset initial carry signal, a Y-stage carry generation signal and a Y-stage carry propagation signal, and is used for outputting a first carry signal according to a preset carry operation strategy;

[0010] The first-level carry generation signal is a carry generation signal of the i-th pair of arithmetic signals received by the first-level carry operation module, and the first-level carry transmission signal is a carry transmission signal of the i-th pair of arithmetic signals received by the first-level carry operation module; the x-th-level carry generation signal is a carry generation signal of the i-th pair of arithmetic signals received by the x-th-level carry operation module, and the x-th-level carry transmission signal is a carry transmission signal of the i-th pair of arithmetic signals received by the x-th-level carry operation module.

[0011] In a second aspect, the present application further provides a carry cascade circuit, comprising:

[0012] Z carry logic circuits connected in cascade as described in the first aspect above, wherein the carry output module of each carry logic circuit is configured to receive a first carry signal output by a previous carry logic circuit, a Y-th-level carry generation signal and a Y-th-level carry transmission signal of the current carry logic circuit, and output a first carry signal of the current carry logic circuit according to the carry operation strategy.

[0013] In a third aspect, the present application further provides a chip comprising the carry logic circuit of the first aspect.

[0014] These and other aspects of the present application will become more apparent from the following description of some embodiments. BRIEF DESCRIPTION OF DRAWINGS

[0015] In order to more clearly illustrate the technical solutions of the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings can also be obtained without creative labor.

[0016] FIG. 1 shows a schematic diagram of a conventional carry logic circuit.

[0017] FIG. 2 shows a schematic diagram of a module of a carry logic circuit according to an embodiment of the present application.

[0018] FIG. 3 shows another schematic diagram of a module of a carry logic circuit according to an embodiment of the present application.

[0019] FIG. 4 shows a schematic diagram of a structure of a carry logic circuit according to an embodiment of the present application.

[0020] FIG. 5 shows another schematic diagram of a structure of a carry logic circuit according to an embodiment of the present application.

[0021] FIG. 6 shows another schematic diagram of a structure of a carry logic circuit according to an embodiment of the present application.

[0022] Fig. 7 shows another structure diagram of the carry logic circuit according to an embodiment of the present application.

[0023] Fig. 8 shows another structure diagram of the carry logic circuit according to an embodiment of the present application.

[0024] Fig. 9 shows another structure diagram of the carry logic circuit according to an embodiment of the present application.

[0025] Fig. 10 shows a diagram of the carry cascade circuit according to an embodiment of the present application. DETAILED DESCRIPTION

[0026] In order to make the persons skilled in the art better understand the scheme of the present application, the technical scheme in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all the other embodiments obtained by the persons skilled in the art without creative labor fall within the protection scope of the present application.

[0027] In the embodiments of the present application, it should be noted that, in this document, the relationship terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply that there is any such actual relationship or order between the entities or operations.

[0028] Moreover, the term “comprising” or “including” or any other variant thereof is intended to cover non-exclusive inclusion, so that the process, method, article or equipment including a series of elements not only includes those elements, but also includes other elements not explicitly listed, or further includes the elements inherent to such process, method, article or equipment. Without more limitation, the element defined by the sentence “including a…” does not exclude the presence of another identical element in the process, method, article or equipment including the element.

[0029] In addition, “a plurality of” in the embodiments of the present application means two or more, and therefore “a plurality of” in the embodiments of the present application can also be understood as “at least two”. “At least one” can be understood as one or more, for example, as one, two or more. For example, including at least one means including one, two or more, and does not limit which ones are included, for example, including at least one of A, B and C means including A, B, C, A and B, A and C, B and C, or A and B and C.

[0030] It should be noted that the "connection" in the embodiments of the present application can be understood as an electrical connection, and the connection between two electrical elements can be direct or indirect connection between the two electrical elements. For example, A and B are connected, which can be direct connection between A and B, or indirect connection between A and B through one or more other electrical elements.

[0031] Figure 1 shows a schematic diagram of a conventional carry logic circuit. As shown in Figure 1, the conventional carry logic circuit includes a plurality of lookup tables connected in cascade, two input terminals of each lookup table are used to receive a pair of arithmetic signals, an output terminal of each lookup table is used to output a logic operation result of the pair of arithmetic signals received by the lookup table, a carry input terminal of each lookup table is connected with a carry output terminal of a previous lookup table, and is used to receive a carry signal of the pair of arithmetic signals received by the previous lookup table, and the carry input terminal of the first lookup table is used to receive an initial carry signal. Obviously, in the conventional carry logic circuit, for n arithmetic signals [i:i+n-1] with a bit width of n, n lookup table units are needed to calculate the carry value of the n arithmetic signals, that is, the conventional carry logic circuit needs n stages of carry chain to calculate the carry value of the n arithmetic signals.

[0032] In view of this, the embodiments of the present application provide a carry logic circuit to solve the above technical problems.

[0033] The embodiments of the present application provide a carry logic circuit. Figure 2 shows a schematic diagram of a module of the carry logic circuit provided by the embodiments of the present application. As shown in Figure 2, the carry logic circuit includes Y stages of carry operation modules and a carry output module connected in cascade, each carry operation module is used to receive i pairs of arithmetic signals (for example, A and B are a pair of arithmetic signals as shown in Figure 2), Y>1, i≥1. Optionally, the i pairs of arithmetic signals received by each carry operation module are values on each bit width of two operands in a logic operation. For example, for two operands "1010" and "0011" in a logic operation, assuming i=2, the first pair of arithmetic signals received by the first carry operation module is "0" "1", the second pair of arithmetic signals is "1" "1", the first pair of arithmetic signals received by the second carry operation module is "0" "0", and the second pair of arithmetic signals is "1" "0".

[0034] The first-level carry operation module is configured to output a first-level carry generation signal according to a preset carry generation operation strategy and output a first-level carry propagation signal according to a preset carry propagation operation strategy, i≥1. The xth-level carry operation module is further configured to receive a previous-level carry generation signal and a previous-level carry propagation signal, output an xth-level carry generation signal according to the carry generation operation strategy, and output an xth-level carry propagation signal according to the carry propagation operation strategy, 2≤x≤Y. The first-level carry generation signal is a carry generation signal of the ith pair of arithmetic signals received by the first-level carry operation module, and the first-level carry propagation signal is a carry propagation signal of the ith pair of arithmetic signals received by the first-level carry operation module. The xth-level carry generation signal is a carry generation signal of the ith pair of arithmetic signals received by the xth-level carry operation module, and the xth-level carry propagation signal is a carry propagation signal of the ith pair of arithmetic signals received by the xth-level carry operation module.

[0035] The carry output module is configured to receive a preset initial carry signal, the Yth-level carry generation signal and the Yth-level carry propagation signal, and output a first carry signal according to a preset carry operation strategy.

[0036] The carry logic circuit provided in the embodiments of the present application inputs Y×i pairs of arithmetic signals in a logic operation into Y-level carry operation modules, so that each level of carry operation module calculates a carry propagation signal and a carry generation signal of the ith pair of arithmetic signals received by the carry operation module according to a preset carry generation operation strategy. Based on this, the carry propagation signal and the carry generation signal output by the Yth-level carry operation module are the carry propagation signal and the carry generation signal of the last pair of arithmetic signals in the Y×i pairs of arithmetic signals. The carry output module only needs to calculate a first carry output signal according to the initial carry signal, the carry propagation signal and the carry generation signal output by the Yth-level carry operation module, and the first carry output signal is the final carry signal obtained after the Y×i pairs of arithmetic signals are subjected to a logic operation. The carry logic circuit provided in the embodiments of the present application compresses the carry chain of a logic value of an arbitrary bit width to one level through the multiple levels of carry operation modules connected in cascade and the carry output module connected with the carry operation modules, reduces the carry delay in the logic operation process, and improves the carry operation performance of the carry logic circuit.

[0037] It can be understood that, for a programmable logic circuit, the logic operation that can be performed includes at least addition, subtraction, comparison of input values, logical AND, logical OR, logical exclusive OR and other operation rules.

[0038] Next, the carry generation operation strategy, the carry propagation operation strategy and the carry operation strategy provided in the embodiments of the present application are described.

[0039] Optionally, in the embodiments of the present application, the preset carry propagation strategy is implemented based on the following formula (1): propagate k = (A k ^ B k ) & propagate k-1 , k = [1: Y x i] (1).

[0040] wherein, propagate k is the carry propagation signal of the kth pair of arithmetic signals, propagate k-1 is the carry propagation signal of the (k-1)th pair of arithmetic signals, A k and B k are the kth pair of arithmetic signals, "^" is a logical exclusive OR operator, and "&" is a logical AND operator.

[0041] The preset carry generation strategy is implemented based on the following formula (2): generate k = (A k ^ B k )? generate k-1 : A k / B k , k = [1: Y x i] (2).

[0042] wherein, generate k is the carry generation signal of the kth pair of arithmetic signals, generate k-1 is the carry generation signal of the (k-1)th pair of arithmetic signals, A k and B k are the kth pair of arithmetic signals, "^" is a logical exclusive OR operator, A k / B k is one of A k and B k , "?:" is a ternary operator, indicating that if (A k ^ B k ) is true, generate k-1 is assigned to generate k , and if (A k ^ B k ) is false, A k / B k is assigned to generate k .

[0043] The preset carry operation strategy is implemented based on the following formula (3): Cout k = propagate k ? Cin: generate k, k = [1:Y x i] (3);

[0044] wherein, Cout k is a carry signal of the 1st to the kth pair of arithmetic signals, propagate k is a carry propagation signal of the kth pair of arithmetic signals, Cin is a preset initial carry signal, i.e., a carry signal set for the 1st pair of arithmetic signals in the carry operation, generate k is a carry generation signal of the kth pair of arithmetic signals, and "?" is a ternary operator symbol, indicating that if propagate k is true, Cin is assigned to Cout k , and if propagate k is false, generate k is assigned to Cout k .

[0045] Optionally, in the above formula (1), formula (2) and formula (3), when k = 1, i.e., for the 1st pair of arithmetic signals of the 1st level carry operation module, the carry propagation signal is implemented based on the following formula (4) or formula (5): propagate1 = (A1^B1) & 1 (5);

[0046] wherein, propagate1 is a carry propagation signal of the 1st pair of arithmetic signals, A1^B1 is an exclusive-OR operation result of the 1st pair of arithmetic signals A1 and B1, and "&" is a logical AND operator symbol.

[0047] The carry generation signal is implemented based on the following formula (6): generate1 = A1^B1? 1'b0 : B1 (6);

[0048] wherein, generate1 is a carry generation signal of the 1st pair of arithmetic signals, A1^B1 is an exclusive-OR operation result of the 1st pair of arithmetic signals A1 and B1, "1'b0" is a binary number 1 or a binary number 0, and "?" is a ternary operator symbol.

[0049] In some embodiments, FIG. 3 shows another module schematic diagram of the carry logic circuit provided by the embodiments of the present application, as shown in FIG. 3, in the carry logic circuit provided by the embodiments of the present application, the carry output module is further configured to receive j pairs of arithmetic signals, to perform a carry operation strategy on the received j pairs of arithmetic signals, the initial carry signal, the Yth level carry generation signal and the Yth level carry propagation signal, and to output a second carry signal.

[0050] The carry logic circuit provided by the embodiments of the present application can calculate the carry occurrence signal and the carry propagation signal of the last j pairs of arithmetic signals in turn through the carry output module, and calculate the second carry signal according to the carry occurrence signal, the carry propagation signal of the last pair of arithmetic signals and the initial carry signal, wherein the second carry signal is the carry value of the two operands with the multiple-bit width. For example, for the two operands with the bit width of Yx i+j, the embodiments of the present application obtain the carry occurrence signal and the carry propagation signal of the Yx i pairs of arithmetic signals through the Y-level carry operation module, and obtain the carry occurrence signal and the carry propagation signal of the Yx i+j pairs of arithmetic signals through the carry output module, and obtain the carry value of the two operands with the bit width of Yx i+j through the carry output module. Based on this, the embodiments of the present application can place the operation of the carry occurrence signal and the carry propagation signal of multiple pairs of arithmetic signals in the carry output module, thereby reducing the cascade order of the carry operation module, further reducing the carry operation timing and saving the circuit resources.

[0051] It can be understood that the first carry signal and the second carry signal have the same meaning in the embodiments of the present application, and both represent the final carry signal obtained by performing the carry operation on the arithmetic value with the multiple-bit width.

[0052] In some embodiments, FIG. 4 and FIG. 5 respectively show two structural diagrams of the carry logic circuit provided by the embodiments of the present application. As shown in FIG. 4 and FIG. 5, each carry operation module in the carry logic circuit provided by the embodiments of the present application includes a first lookup table unit, and each first lookup table unit includes at least 2i+1 signal input ends, one signal output end, one carry input end and one carry output end.

[0053] In the first-level carry operation module, the 2i signal input ends of the first lookup table unit are used to receive i pairs of arithmetic signals, the signal output end of the first lookup table unit is used to output the first-level carry propagation signal, and the carry output end of the first lookup table unit is used to output the first-level carry occurrence signal. In the x-level carry operation module, the 2i+1 signal input ends of the first lookup table unit are used to receive i pairs of arithmetic signals and the previous-level carry propagation signal, the carry input end of the first lookup table unit is used to receive the previous-level carry occurrence signal, the carry output end of the first lookup table unit is used to output the x-level carry occurrence signal, and the signal output end of the first lookup table unit is used to output the x-level carry propagation signal. Optionally, the first-level carry operation module does not need to receive the carry occurrence signal and the carry propagation signal.

[0054] Next, the carry occurrence operation strategy and the carry propagation operation strategy of the first lookup table unit are described with respect to the ports of FIG. 4 and FIG. 5.

[0055] Optionally, for the first lookup table unit, the preset carry propagation operation strategy is implemented based on the following formula (7): Z=(I0^I1)&(I2^I3)&I4 (7).

[0056] The preset carry generation operation strategy is implemented based on the following formula (8): COUT=I2∧I3?(I0∧I1?CIN:I1):I3 (8).

[0057] In the formulas (7) and (8), Z is the signal output terminal of the first lookup table unit, COUT is the carry output terminal of the first lookup table unit, I0, I1, I2, I3, and I4 are respectively four signal input terminals of the first lookup table unit, and CIN is the carry input terminal of the first lookup table unit. It should be noted that in the formulas (7) and (8), the name of a port is used to represent the value of the port. Specifically, if it is an input port, it represents input data, and if it is an output port, it represents output data.

[0058] Optionally, for the first stage carry operation module, in the formula (7), I4 can be configured as a binary number "1", or configured as an idle state, that is, I4 has no connection in the circuit. In the formula (8), CIN can be configured as a binary number "1" or a binary number "0", or CIN can be configured as an idle state, that is, CIN has no connection in the circuit.

[0059] It can be understood that the formulas (7) and (8) are essentially the same as the aforementioned formulas (1) and (2), and the difference is that the formulas (7) and (8) use the ports of the first lookup table unit to represent the carry propagation operation strategy and the carry generation operation strategy. The signals input by the ports are substituted into the formulas (7) and (8) to obtain the aforementioned formulas (1) and (2).

[0060] It can be understood that in the embodiments of the present application, the structure diagram of the carry logic circuit shown in FIGS. 4 and 5 only shows the implementation manner of the carry operation module provided by the embodiments of the present application when i=2 and the lookup table is LUT6 (six-input lookup table). However, in fact, the carry operation module provided by the embodiments of the present application is not limited to the number of input stages of the lookup table and the value of i, where the value of i is determined according to the operation capability of the lookup table. Specifically, two LUTs (2n) can calculate the carry generation signal and the carry propagation signal of n pairs of arithmetic signals.

[0061] In some embodiments, FIG. 6 and FIG. 7 respectively show two structural diagrams of the carry logic circuit provided by the embodiments of the present application. As shown in FIG. 6 and FIG. 7, each second lookup table unit and each third lookup table unit in the carry logic circuit provided by the embodiments of the present application comprises at least 2i signal input terminals, a carry input terminal and a carry output terminal.

[0062] In the first-stage carry operation module, the 2i signal input terminals of the second lookup table unit are configured to receive i pairs of arithmetic signals, and the carry output terminal of the second lookup table unit is configured to output a first-stage carry generation signal. The 2i signal input terminals of the third lookup table unit are configured to multiplex i pairs of arithmetic signals with the second lookup table unit, and the carry output terminal of the third lookup table unit is configured to output a first-stage carry propagation signal. In the xth-stage carry operation module, the 2i signal input terminals of the second lookup table unit are configured to receive i pairs of arithmetic signals, the carry input terminal of the second lookup table unit is configured to receive a carry generation signal of a previous stage, and the carry output terminal of the second lookup table unit is configured to output an xth-stage carry generation signal. The 2i signal input terminals of the third lookup table unit are configured to multiplex i pairs of arithmetic signals with the second lookup table unit, the carry input terminal of the third lookup table unit is configured to receive a carry propagation signal of the previous stage, and the carry output terminal of the third lookup table unit is configured to output an xth-stage carry propagation signal. Optionally, the first-stage carry operation module does not need to receive the carry generation signal and the carry propagation signal.

[0063] Next, the carry propagation operation strategy of the second lookup table unit and the carry generation operation strategy of the third lookup table unit are described with respect to the ports of FIG. 6 and FIG. 7.

[0064] Optionally, for the second lookup table unit, the preset carry propagation operation strategy is implemented based on the following formula (9) in the embodiments of the present application:

[0065] In the formula (9), COUT is the carry output terminal of the second lookup table unit, I0, I1, I2 and I3 are respectively four signal input terminals of the second lookup table unit, and CIN is the carry input terminal of the second lookup table unit.

[0066] Optionally, for the first-stage carry operation module, in the above formula (9), CIN can be configured as a binary number 1, or CIN can be configured as an idle state, i.e. CIN has no connection in the circuit.

[0067] For the third lookup table unit, the preset carry generation operation strategy is implemented based on the following formula (10) in the embodiments of the present application:

[0068] wherein, for formula (10), COUT is the carry output terminal of the third lookup table unit, I0, I1, I2, I3 are respectively four signal input terminals of the third lookup table unit, and CIN is the carry input terminal of the third lookup table unit. It should be noted that the value of the port is represented by the name of the port in formula (9) and formula (10). Alternatively, for the first level carry operation module, in the above formula (10), CIN can be configured as binary number "1" or binary number "0", or CIN can be configured as an idle state, that is, CIN has no connection in the circuit.

[0069] It can be understood that the above formula (9) and formula (10) are essentially the same as the aforementioned formula (1) and formula (2), the difference is that formula (9) and formula (10) respectively use the ports of the second lookup table unit and the third lookup table to represent the carry propagation operation strategy and the carry generation operation strategy, and the signals input by the ports are substituted into formula (9) and formula (10) to obtain the aforementioned formula (1) and formula (2).

[0070] It can be understood that in the embodiments of the present application, the structure diagram of the carry logic circuit as shown in FIG. 6 and FIG. 7 only shows the implementation of the carry operation module provided by the embodiments of the present application when i = 2 and the lookup table is LUT6, however, in fact, the carry operation module provided by the embodiments of the present application is not limited to the input level of the lookup table and the value of i, wherein the value of i is determined according to the operation capacity of the lookup table, specifically, two LUTs (2n) can calculate the carry generation signal and the carry propagation signal of n pairs of arithmetic signals.

[0071] It can be understood that in the embodiments of the present application, the carry logic circuit as shown in FIG. 6 and FIG. 7 outputs the carry propagation signal and the carry generation signal through the carry output port of the lookup table, and in actual application, it can also be set to output the carry propagation signal and the carry generation signal through the signal output port of the lookup table. For example, FIG. 8 shows another structure diagram of the carry logic circuit provided by the embodiments of the present application, taking two operand bit widths equal to 4 as an example, that is, there are four pairs of arithmetic signals, then in the carry logic circuit as shown in FIG. 8, the carry operation module is one level, the carry operation module outputs the carry generation signal and the carry propagation signal of the third pair of arithmetic signals through the signal output terminals of two LUT6s (six-input lookup table), the carry output module includes one LUT6, the carry output module receives the initial carry signal, the fourth pair of arithmetic signals, the carry generation signal and the carry propagation signal of the third pair of arithmetic signals output by the carry operation module through the carry input terminal and the four signal input terminals, and outputs the carry signal of the four pairs of arithmetic signals through the carry output port.

[0072] As shown in FIG. 8, in the carry operation module, the carry propagation operation strategy is expressed by ports as follows: Z = (I0 ^ I1) & (12 ^ 13) & (14 ^ 15) (11).

[0073] In formula (11), Z is a signal output terminal of the LUT6A, and I0, I1, I2, I3, I4 and I5 are six signal input terminals of the LUT6A.

[0074] As shown in FIG. 8, in the carry operation module, the carry propagation operation strategy is expressed by ports as follows: Z = (I0 ^ I1) & (12 ^ 13) & (14 ^ 15) (11).

[0075] In formula (11), Z is a signal output terminal of the LUT6A, and I0, I1, I2, I3, I4 and I5 are six signal input terminals of the LUT6A.

[0076] As shown in FIG. 8, in the carry operation module, the carry propagation operation strategy is expressed by ports as follows: Z = (I0 ^ I1) & (12 ^ 13) & (14 ^ 15) (11). i :(I0 ^ I1? I3 : I1) (13).

[0077] In formula (13), COUT is a carry output terminal of the LUT6C, and I0, I1, I2 and I3 are four signal input terminals of the LUT6C. It should be noted that in formulas (11), (12) and (13), the name of the port is used to represent the value of the port.

[0078] It can be understood that formulas (11) and (12) are essentially the same as formulas (1) and (2) described above, and the difference is that formulas (11) and (12) respectively use the ports of the lookup table LUT6A and the lookup table LUT6B to represent the carry propagation operation strategy and the carry generation operation strategy. By substituting the signal input into formulas (11) and (12), formulas (1) and (2) can be obtained.

[0079] Formula (13) is used to represent the carry operation strategy by the port of the lookup table LUT6C. By substituting the signal input into formulas (11) and (12), formula (3) can be obtained.

[0080] In some embodiments, FIG. 9 shows another structural schematic diagram of the carry logic circuit provided by the embodiments of the present application. As shown in FIG. 9, in the carry logic circuit provided by the embodiments of the present application, each carry operation module includes i first combination logic units and i second combination logic units.

[0081] Each first combination logic unit comprises a first exclusive-OR unit and a first selection unit, two inputs of the first exclusive-OR unit are used to receive a pair of arithmetic signals, and one of the inputs of the first exclusive-OR unit is also connected with one input of the first selection unit (used to receive one of the pair of arithmetic signals), and an output of the first exclusive-OR unit is connected with a selection end of the first selection unit; another input of the first selection unit is connected with an output of the first selection unit of the previous first combination logic unit. Optionally, the first combination logic unit is used to realize the carry generation operation strategy described in the above formula (2) through a logic circuit formed by an exclusive-OR gate and a selector.

[0082] In the first-level carry operation module, another input of the first selection unit of the first combination logic unit is used to receive a preset selection signal. Optionally, the preset selection signal (1'b0) is any one of binary number "1" or binary number "0", and the first combination logic unit of the first-level carry operation module is used to realize the carry generation operation strategy described in the above formula (6).

[0083] Each second combination logic unit comprises an AND unit and a second exclusive-OR unit, one input of the AND unit is connected with an output of the AND unit of the previous second combination logic unit, another input of the AND unit is connected with an output of the second exclusive-OR unit, and two inputs of the exclusive-OR unit are used to receive a pair of arithmetic signals. Optionally, the second combination logic unit is used to realize the carry propagation operation strategy described in the above formula (1) through a logic circuit formed by an exclusive-OR gate and an AND gate.

[0084] In the first-level carry operation module, the first second combination logic unit further comprises a third exclusive-OR unit, two inputs of the third exclusive-OR unit are used to receive a pair of arithmetic signals, and an output of the third exclusive-OR unit is connected with one input of the AND unit. Optionally, the third exclusive-OR unit of the first second combination logic unit of the first-level carry operation module is used to realize the carry propagation operation strategy described in the above formula (4).

[0085] It can be understood that, in the embodiments of the present application, the first exclusive-OR unit and the second exclusive-OR unit are used to indicate a logic circuit capable of performing exclusive-OR operation, that is, the first exclusive-OR unit and the second exclusive-OR unit can be the same logic circuit, or can be different in hardware but the same in function, and the first exclusive-OR unit and the second exclusive-OR unit are used here to distinguish the first combination logic unit and the second combination logic unit.

[0086] It can be understood that the embodiment of the present application constructs the carry logic circuit as shown in FIG. 9 through the logical gates, when the carry logic circuit as shown in FIG. 9 is applied to the programmable logic device chip, the comprehensive tool should also be used to map each logical gate to the logic circuit supported by the programmable logic device to run. Exemplarily, when the carry logic circuit as shown in FIG. 9 is applied to the FPGA chip, the FPGA comprehensive tool should be used to map each logical gate to the logic circuit supported by the FPGA, such as LUT (lookup table), specific CARRY (carry circuit), etc., that is, when the carry logic circuit as shown in FIG. 9 is applied to the programmable logic device chip, it will be mapped to the carry logic circuit as shown in FIG. 4 to FIG. 7.

[0087] In some embodiments, as shown in FIG. 4 and FIG. 6, the carry logic circuit provided by the embodiment of the present application comprises:

[0088] The fourth lookup table unit comprises at least two signal input ends, a carry input end and a carry output end, the two signal input ends of the fourth lookup table unit are respectively used for receiving the Yth stage carry generation signal and the Yth stage carry propagation signal, the carry input end of the fourth lookup table unit is used for receiving the initial carry signal, and the carry output end of the fourth lookup table unit is used for outputting the first carry signal.

[0089] Next, the carry operation strategy of the fourth lookup table unit is described with respect to the ports of FIG. 4 and FIG. 6.

[0090] Optionally, for the fourth lookup table unit, the preset carry operation strategy is implemented based on the following formula (14) in the embodiment of the present application:

[0091] In the formula (14), COUT is the signal output end of the fourth lookup table unit, I2 and I3 are respectively the two signal input ends of the fourth lookup table unit, and CIN is the carry input end of the fourth lookup table unit. It should be noted that in the formula (14), the name of the port is used to represent the value of the port.

[0092] It can be understood that the above formula (14) is essentially the same as the aforementioned formula (3), the difference is that the formula (13) uses the port of the fourth lookup table unit to represent the carry propagation operation strategy and the carry generation operation strategy, and the signal input by the port is substituted into the formula (14) to obtain the aforementioned formula (3).

[0093] In some embodiments, as shown in FIG. 5 and FIG. 7, the carry logic circuit provided by the embodiment of the present application comprises:

[0094] The fifth lookup table unit includes at least 2j+2 signal input ends, a carry input end and a carry output end. The 2j+2 signal input ends of the fifth lookup table unit are respectively used for receiving j pairs of arithmetic signals, the Yth-level carry generation signal and the Yth-level carry transmission signal. The carry input end of the fifth lookup table unit is used for receiving the initial carry signal. The carry output end of the fifth lookup table unit is used for outputting the second carry signal.

[0095] Optionally, for the fifth lookup table unit, the preset carry operation strategy is implemented based on the following formula (15): COUT=I0^I1&I2?Cin i :(I0^I1?I3:I1) (15).

[0096] For the formula (15), COUT is the signal output end of the fifth lookup table unit, I0, I1, I2 and I3 are respectively the four signal input ends of the fourth lookup table unit, and CIN is the carry input end of the fifth lookup table unit. It should be noted that in the formula (15), the value of the port is represented by the name of the port.

[0097] It can be understood that the above formula (15) is essentially the same as the aforementioned formula (3), wherein I0^I1&I2 is the carry transmission signal of the i-th pair of arithmetic signals received by the carry output module, and I0^I1?I3:I1 is the carry generation signal of the i-th pair of arithmetic signals received by the carry output module.

[0098] It can be understood that in the embodiments of the present application, the structure diagram of the carry logic circuit as shown in FIGS. 4 to 7 only shows the implementation mode of the carry output module provided by the embodiments of the present application when j=1 and the lookup table is LUT6. However, in fact, the carry output module provided by the embodiments of the present application is not limited to the input level of the lookup table and the value of j, wherein the value of j is determined according to the operation capacity of the lookup table. Specifically, two LUTs (2n) can calculate the carry generation signal and the carry transmission signal of n pairs of arithmetic signals.

[0099] In some embodiments, as shown in FIG. 9, the carry output module in the carry logic circuit provided by the embodiments of the present application includes:

[0100] The second selection unit is used for receiving the Yth-level carry transmission signal through the selection end. One input end of the second selection unit is used for receiving the Yth-level carry generation signal. The other input end of the second selection unit is used for receiving the initial carry signal. The output end of the second selection unit is used for outputting the first carry signal. Optionally, the second selection unit is used for implementing the carry operation strategy described in the above formula (3) through the selector.

[0101] It can be understood that, in the embodiments of the present application, the first selection unit and the second selection unit are used to indicate a logic circuit capable of performing selection logic, that is, the first selection unit and the second selection unit can be the same logic circuit, or can be logic circuits different in hardware but the same in function, and the first selection unit and the second selection unit are used here to distinguish the first combination logic unit and the carry output module.

[0102] The carry logic circuit provided in the embodiments of the present application inputs the Y×i pairs of arithmetic signals in the logic operation into the Y-stage carry operation module respectively, so that each stage carry operation module calculates the carry transfer signal and the carry generation signal of the ith pair of arithmetic signals among the i pairs of arithmetic signals received by the stage carry operation module according to the preset carry generation operation strategy, and based on this, the carry transfer signal and the carry generation signal output by the Yth stage carry operation module are the carry transfer signal and the carry generation signal of the last pair of arithmetic signals among the Y×i pairs of arithmetic signals. The carry output module only needs to calculate the first carry output signal according to the initial carry signal, the carry transfer signal and the carry generation signal output by the Yth stage carry operation module, and the first carry output signal is the final carry signal obtained after the Y×i pairs of arithmetic signals are subjected to the logic operation. The carry logic circuit provided in the embodiments of the present application compresses the carry chain of the logic values of any bit width to one stage through the multiple-stage carry operation module connected in cascade and the carry output module connected with the carry operation module, reduces the carry delay in the logic operation process, and improves the carry operation performance of the carry logic circuit.

[0103] Further, the embodiments of the present application can place the operation of the carry generation signals and the carry transfer signals of the multiple pairs of arithmetic signals in the carry output module, thereby reducing the cascade number of the carry operation module, further reducing the carry operation timing, and saving the circuit resources.

[0104] The embodiments of the present application also provide a carry cascade circuit. FIG. 10 shows a schematic diagram of the carry cascade circuit provided in the embodiments of the present application. As shown in FIG. 10, the carry cascade circuit includes Z carry logic circuits connected in cascade. The carry output module of each carry logic circuit is used to receive the first carry signal output by the previous stage carry logic circuit, the Yth stage carry generation signal and the Yth stage carry transfer signal of the current stage carry logic circuit, and output the first carry signal of the current stage carry logic circuit according to the carry operation strategy.

[0105] The carry cascade circuit provided in the embodiments of the present application can compress the carry chain of the logic operation of the two operands of multiple bit widths to 1 / Z according to the design requirement, reduces the timing of the carry operation, and improves the carry operation performance of the carry logic circuit.

[0106] The embodiment of the present application further provides a chip, which comprises the carry logic circuit.

[0107] The embodiment of the present application further provides a carry operation method applied to the carry logic circuit shown in FIG. 2, and the method comprises the following steps:

[0108] The first-stage carry operation module outputs a first-stage carry generation signal according to a preset carry generation operation strategy and outputs a first-stage carry propagation signal according to a preset carry propagation operation strategy.

[0109] The xth-stage carry operation module receives a previous-stage carry generation signal and a previous-stage carry propagation signal, outputs an xth-stage carry generation signal according to the carry generation operation strategy and outputs an xth-stage carry propagation signal according to the carry propagation operation strategy, and 2≤x≤Y.

[0110] The carry output module receives a preset initial carry signal, a Yth-stage carry generation signal and a Yth-stage carry propagation signal, and outputs a first carry signal according to a preset carry operation strategy.

[0111] The first-stage carry generation signal is a carry generation signal of the ith pair of arithmetic signals received by the first-stage carry operation module, and the first-stage carry propagation signal is a carry propagation signal of the ith pair of arithmetic signals received by the first-stage carry operation module; the xth-stage carry generation signal is a carry generation signal of the ith pair of arithmetic signals received by the xth-stage carry operation module, and the xth-stage carry propagation signal is a carry propagation signal of the ith pair of arithmetic signals received by the xth-stage carry operation module.

[0112] The carry operation method provided by the embodiment of the present application can compress a carry chain of a logic value with an arbitrary bit width to one stage through the multiple-stage carry operation modules connected in cascade and the carry output module connected with the carry operation modules, thereby reducing carry delay in a logic operation process and improving carry operation performance of the carry logic circuit.

[0113] In an optional embodiment, the carry logic circuit is shown in FIG. 3, and the method further comprises the following steps: the carry output module receives j pairs of arithmetic signals to execute the carry operation strategy on the received j pairs of arithmetic signals, the initial carry signal, the Yth-stage carry generation signal and the Yth-stage carry propagation signal and output a second carry signal, and j≥1.

[0114] In an alternative embodiment, the carry logic circuit is as shown in FIG. 4 and FIG. 5, each of the carry operation modules includes a first lookup table unit, each of the first lookup table units includes at least 2i+1 signal input terminals, one signal output terminal, one carry input terminal and one carry output terminal, and the method further comprises:

[0115] In the first stage carry operation module, the 2i signal input terminals of the first lookup table unit receive i pairs of arithmetic signals, the signal output terminal of the first lookup table unit outputs the first stage carry propagation signal, and the carry output terminal of the first lookup table unit outputs the first stage carry generation signal.

[0116] In the xth stage carry operation module, the 2i+1 signal input terminals of the first lookup table unit receive i pairs of arithmetic signals and the previous stage carry propagation signal, the carry input terminal of the first lookup table unit receives the previous stage carry generation signal, the carry output terminal of the first lookup table unit outputs the xth stage carry generation signal, and the signal output terminal of the first lookup table unit outputs the xth stage carry propagation signal.

[0117] In an alternative embodiment, the carry logic circuit is as shown in FIG. 6 and FIG. 7, each of the carry operation modules includes a second lookup table unit and a third lookup table unit, each of the second lookup table units and each of the third lookup table units includes at least 2i signal input terminals, one carry input terminal and one carry output terminal, and the method further comprises:

[0118] In the first stage carry operation module, the 2i signal input terminals of the second lookup table unit receive i pairs of arithmetic signals, the carry output terminal of the second lookup table unit outputs the first stage carry generation signal, the 2i signal input terminals of the third lookup table unit multiplex i pairs of arithmetic signals with the second lookup table unit, and the carry output terminal of the third lookup table unit outputs the first stage carry propagation signal.

[0119] In the xth stage carry operation module, the 2i signal input terminals of the second lookup table unit receive i pairs of arithmetic signals, the carry input terminal of the second lookup table unit receives the previous stage carry generation signal, the carry output terminal of the second lookup table unit outputs the xth stage carry generation signal, the 2i signal input terminals of the third lookup table unit multiplex i pairs of arithmetic signals with the second lookup table unit, the carry input terminal of the third lookup table unit receives the previous stage carry propagation signal, and the carry output terminal of the third lookup table unit outputs the xth stage carry propagation signal.

[0120] In an alternative embodiment, the carry logic circuit is as shown in FIG. 9, each of the carry operation modules includes i first combination logic units and i second combination logic units, each of the first combination logic units includes a first XOR unit and a first selection unit, one input of the first XOR unit is connected with one input of the first selection unit, the output of the first XOR unit is connected with the selection end of the first selection unit; the other input of the first selection unit is connected with the output of the first selection unit of the previous first combination logic unit; each of the second combination logic units includes an AND unit and a second XOR unit, one input of the AND unit is connected with the output of the AND unit of the previous second combination logic unit, the other input of the AND unit is connected with the output of the second XOR unit, the first second combination logic unit further includes a third XOR unit, the output of the third XOR unit is connected with one input of the AND unit, and the method further includes:

[0121] In the first carry operation module, two inputs of the first XOR unit receive a pair of arithmetic signals, the other input of the first selection unit of the first first combination logic unit receives a preset selection signal, two inputs of the XOR unit receive a pair of arithmetic signals, and two inputs of the third XOR unit receive a pair of arithmetic signals.

[0122] In an alternative embodiment, the carry logic circuit is as shown in FIG. 4 and FIG. 6, the carry output module includes a fourth lookup table unit, the fourth lookup table unit includes at least two signal input ends, a carry input end and a carry output end, and the method further includes: the two signal input ends of the fourth lookup table unit receive the Yth carry generation signal and the Yth carry propagation signal respectively, the carry input end of the fourth lookup table unit receives the initial carry signal, and the carry output end of the fourth lookup table unit outputs the first carry signal.

[0123] In an alternative embodiment, the carry logic circuit is as shown in FIG. 9, the carry output module includes a second selection unit, and the method further includes: the selection end of the second selection unit receives the Yth carry propagation signal, one input of the second selection unit receives the Yth carry generation signal, the other input of the second selection unit receives the initial carry signal, and the output of the second selection unit outputs the first carry signal.

[0124] In an alternative embodiment, the carry logic circuit is as shown in FIG. 5 and FIG. 7, the carry output module comprises a fifth lookup table unit, the fifth lookup table unit comprises at least 2j+2 signal input terminals, a carry input terminal and a carry output terminal, and the method further comprises: the 2j+2 signal input terminals of the fifth lookup table unit respectively receive j pairs of arithmetic signals, the Yth stage carry generation signal and the Yth stage carry transfer signal, the carry input terminal of the fifth lookup table unit receives the initial carry signal, and the carry output terminal of the fifth lookup table unit outputs the second carry signal.

[0125] The above is a further detailed description of the present application in combination with specific embodiments, and cannot be deemed to limit the specific implementation of the present application to these descriptions. For ordinary skilled persons in the technical field of the present application, several simple deductions or replacements can be made without departing from the concept of the present application, and all should be regarded as the protection scope of the present application.

Claims

1. A carry logic circuit, wherein, The Y-stage carry operation module and a carry output module are connected in cascade, each of the Y-stage carry operation modules is used for receiving i pairs of arithmetic signals, Y>1, i≥1; The first-stage carry operation module is used for outputting a first-stage carry generation signal according to a preset carry generation operation strategy and outputting a first-stage carry transfer signal according to a preset carry transfer operation strategy; The x-stage carry operation module is also used for receiving a previous-stage carry generation signal and a previous-stage carry transfer signal, outputting an x-stage carry generation signal according to the carry generation operation strategy and outputting an x-stage carry transfer signal according to the carry transfer operation strategy, 2≤x≤Y; The carry output module is used for receiving a preset initial carry signal, a Y-stage carry generation signal and a Y-stage carry transfer signal, and outputting a first carry signal according to a preset carry operation strategy. The first-stage carry generation signal is a carry generation signal of the i pairs of arithmetic signals received by the first-stage carry operation module, and the first-stage carry transfer signal is a carry transfer signal of the i pairs of arithmetic signals received by the first-stage carry operation module; the x-stage carry generation signal is a carry generation signal of the i pairs of arithmetic signals received by the x-stage carry operation module, and the x-stage carry transfer signal is a carry transfer signal of the i pairs of arithmetic signals received by the x-stage carry operation module.

2. The carry logic circuit of claim 1, wherein, The carry output module is also used for receiving j pairs of arithmetic signals, and is used for executing the carry operation strategy on the received j pairs of arithmetic signals, the initial carry signal, the Y-stage carry generation signal and the Y-stage carry transfer signal to output a second carry signal, j≥1.

3. The carry logic circuit of claim 1 or 2, wherein, Each of the carry operation modules comprises a first lookup table unit, and each of the first lookup table units comprises at least 2i+1 signal input ends, one signal output end, one carry input end and one carry output end; In the first-stage carry operation module, the 2i signal input ends of the first lookup table unit are used for receiving the i pairs of arithmetic signals, the signal output end of the first lookup table unit is used for outputting the first-stage carry transfer signal, and the carry output end of the first lookup table unit is used for outputting the first-stage carry generation signal; In the x-stage carry operation module, the 2i+1 signal input ends of the first lookup table unit are used for receiving the i pairs of arithmetic signals and the previous-stage carry transfer signal, the carry input end of the first lookup table unit is used for receiving the previous-stage carry generation signal, the carry output end of the first lookup table unit is used for outputting the x-stage carry generation signal, and the signal output end of the first lookup table unit is used for outputting the x-stage carry transfer signal.

4. The carry logic circuit of claim 1 or 2, wherein, Each of the carry operation modules comprises a second lookup table unit and a third lookup table unit, and each of the second lookup table units and each of the third lookup table units comprises at least 2i signal input ends, one carry input end and one carry output end; In the first-stage carry operation module, the 2i signal input ends of the second lookup table unit are used for receiving the i pairs of arithmetic signals, and the carry output end of the second lookup table unit is used for outputting the first-stage carry generation signal; The 2i signal input ends of the third lookup table unit multiplex i pairs of arithmetic signals with the second lookup table unit, and the carry output end of the third lookup table unit is used for outputting the first level carry transfer signal; In the xth level carry operation module, the 2i signal input ends of the second lookup table unit are used for receiving i pairs of arithmetic signals, the carry input end of the second lookup table unit is used for receiving the carry generation signal of the previous level, and the carry output end of the second lookup table unit is used for outputting the xth level carry generation signal; The 2i signal input ends of the third lookup table unit multiplex i pairs of arithmetic signals with the second lookup table unit, and the carry input end of the third lookup table unit is used for receiving the carry transfer signal of the previous level, and the carry output end of the third lookup table unit is used for outputting the xth level carry transfer signal.

5. The carry logic circuit of claim 1 or 2, wherein, Each of the carry operation modules comprises i first combination logic units and i second combination logic units; Each of the first combination logic units comprises a first exclusive OR unit and a first selection unit, two input ends of the first exclusive OR unit are used for receiving a pair of arithmetic signals, one of the input ends of the first exclusive OR unit is also connected with one input end of the first selection unit, and the output end of the first exclusive OR unit is connected with the selection end of the first selection unit; the other input end of the first selection unit is connected with the output end of the first selection unit of the previous first combination logic unit; In the first level carry operation module, the other input end of the first selection unit of the first first combination logic unit is used for receiving a preset selection signal. Each of the second combination logic units comprises an AND unit and a second exclusive OR unit, one input end of the AND unit is connected with the output end of the AND unit of the previous second combination logic unit, the other input end of the AND unit is connected with the output end of the second exclusive OR unit, and two input ends of the exclusive OR unit are used for receiving a pair of arithmetic signals; In the first level carry operation module, the first second combination logic unit further comprises a third exclusive OR unit, two input ends of the third exclusive OR unit are used for receiving a pair of arithmetic signals, and the output end of the third exclusive OR unit is connected with one input end of the AND unit.

6. The carry logic circuit of claim 1, wherein, The carry output module comprises: A fourth lookup table unit, the fourth lookup table unit comprises at least two signal input ends, a carry input end and a carry output end, the two signal input ends of the fourth lookup table unit are respectively used for receiving the Yth level carry generation signal and the Yth level carry transfer signal, the carry input end of the fourth lookup table unit is used for receiving the initial carry signal, and the carry output end of the fourth lookup table unit is used for outputting the first carry signal.

7. The carry logic circuit of claim 1, wherein, The carry output module comprises: A second selection unit, a selection end of the second selection unit is used for receiving the Yth level carry propagation signal, one input end of the second selection unit is used for receiving the Yth level carry generation signal, another input end of the second selection unit is used for receiving the initial carry signal, and an output end of the second selection unit is used for outputting the first carry signal.

8. The carry logic circuit of claim 2, wherein, The carry output module comprises: A fifth lookup table unit, the fifth lookup table unit comprises at least 2j+2 signal input ends, one carry input end and one carry output end, the 2j+2 signal input ends of the fifth lookup table unit are respectively used for receiving j pairs of arithmetic signals, the Yth level carry generation signal and the Yth level carry propagation signal, the carry input end of the fifth lookup table unit is used for receiving the initial carry signal, and the carry output end of the fifth lookup table unit is used for outputting the second carry signal.

9. A carry cascade circuit, wherein, Comprise: Z cascaded carry logic circuits as claimed in any one of claims 1 to 8, the carry output module of each carry logic circuit is used for receiving the first carry signal output by the previous stage carry logic circuit, the Yth level carry generation signal and the Yth level carry propagation signal of the current stage carry logic circuit, and outputting the first carry signal of the current stage carry logic circuit according to the carry operation strategy, and Z>1.

10. A chip, wherein, The carry logic circuit as claimed in any one of claims 1 to 8.

11. A carry operation method, wherein, The method as claimed in claim 1, the method comprises: The first stage carry operation module outputs the first stage carry generation signal according to a preset carry generation operation strategy, and outputs the first stage carry propagation signal according to a preset carry propagation operation strategy; The xth stage carry operation module receives the carry generation signal and the carry propagation signal of the previous stage, outputs the xth stage carry generation signal according to the carry generation operation strategy, and outputs the xth stage carry propagation signal according to the carry propagation operation strategy, and 2≤x≤Y; The carry output module receives the preset initial carry signal, the Yth level carry generation signal and the Yth level carry propagation signal, and outputs the first carry signal according to the preset carry operation strategy; The first stage carry generation signal is the carry generation signal of the ith pair of arithmetic signals received by the first stage carry operation module, and the first stage carry propagation signal is the carry propagation signal of the ith pair of arithmetic signals received by the first stage carry operation module; the xth stage carry generation signal is the carry generation signal of the ith pair of arithmetic signals received by the xth stage carry operation module, and the xth stage carry propagation signal is the carry propagation signal of the ith pair of arithmetic signals received by the xth stage carry operation module.

12. The carry operation method of claim 11, wherein, The method further comprises: The carry output module receives j pairs of arithmetic signals, and executes the carry operation strategy on the received j pairs of arithmetic signals, the initial carry signal, the Yth level carry generation signal and the Yth level carry propagation signal to output the second carry signal, and j≥1.

13. The carry operation method according to claim 11 or 12, wherein, Each of the carry operation modules comprises a first lookup table unit, each of the first lookup table units comprises at least 2i+1 signal input ends, one signal output end, one carry input end and one carry output end, and the method further comprises: In the first-level carry operation module, the 2i signal input ends of the first lookup table unit receive i pairs of arithmetic signals, the signal output end of the first lookup table unit outputs the first-level carry propagation signal, and the carry output end of the first lookup table unit outputs the first-level carry generation signal; In the xth-level carry operation module, the 2i+1 signal input ends of the first lookup table unit receive i pairs of arithmetic signals and the previous-level carry propagation signal, the carry input end of the first lookup table unit receives the previous-level carry generation signal, the carry output end of the first lookup table unit outputs the xth-level carry generation signal, and the signal output end of the first lookup table unit outputs the xth-level carry propagation signal.

14. The carry operation method according to claim 11 or 12, wherein, Each of the carry operation modules comprises a second lookup table unit and a third lookup table unit, each of the second lookup table units and each of the third lookup table units comprises at least 2i signal input ends, one carry input end and one carry output end, and the method further comprises: In the first-level carry operation module, the 2i signal input ends of the second lookup table unit receive i pairs of arithmetic signals, the carry output end of the second lookup table unit outputs the first-level carry generation signal, and the 2i signal input ends of the third lookup table unit multiplex i pairs of arithmetic signals with the second lookup table unit, and the carry output end of the third lookup table unit outputs the first-level carry propagation signal; In the xth-level carry operation module, the 2i signal input ends of the second lookup table unit receive i pairs of arithmetic signals, the carry input end of the second lookup table unit receives the previous-level carry generation signal, the carry output end of the second lookup table unit outputs the xth-level carry generation signal, the 2i signal input ends of the third lookup table unit multiplex i pairs of arithmetic signals with the second lookup table unit, the carry input end of the third lookup table unit receives the previous-level carry propagation signal, and the carry output end of the third lookup table unit outputs the xth-level carry propagation signal.

15. The carry operation method according to claim 11 or 12, wherein, Each of the carry operation modules comprises i first combination logic units and i second combination logic units, each of the first combination logic units comprises a first exclusive-OR unit and a first selection unit, one input terminal of the first exclusive-OR unit is connected with one input terminal of the first selection unit, the output terminal of the first exclusive-OR unit is connected with the selection terminal of the first selection unit; the other input terminal of the first selection unit is connected with the output terminal of the first selection unit of the previous first combination logic unit; each of the second combination logic units comprises an AND unit and a second exclusive-OR unit, one input terminal of the AND unit is connected with the output terminal of the AND unit of the previous second combination logic unit, the other input terminal of the AND unit is connected with the output terminal of the second exclusive-OR unit, the first second combination logic unit further comprises a third exclusive-OR unit, the output terminal of the third exclusive-OR unit is connected with one input terminal of the AND unit, and the method further comprises: In the first stage carry operation module, two input terminals of the first exclusive-OR unit receive a pair of arithmetic signals, the other input terminal of the first selection unit of the first first combination logic unit receives a preset selection signal, two input terminals of the exclusive-OR unit receive a pair of arithmetic signals, and two input terminals of the third exclusive-OR unit receive a pair of arithmetic signals.

16. The carry operation method of claim 11, wherein, The carry output module comprises a fourth lookup table unit, the fourth lookup table unit comprises at least two signal input terminals, a carry input terminal and a carry output terminal, and the method further comprises: Two signal input terminals of the fourth lookup table unit receive the Yth stage carry generation signal and the Yth stage carry transfer signal respectively, the carry input terminal of the fourth lookup table unit receives the initial carry signal, and the carry output terminal of the fourth lookup table unit outputs the first carry signal.

17. The carry operation method of claim 11, wherein, The carry output module comprises a second selection unit, and the method further comprises: The selection terminal of the second selection unit receives the Yth stage carry transfer signal, one input terminal of the second selection unit receives the Yth stage carry generation signal, the other input terminal of the second selection unit receives the initial carry signal, and the output terminal of the second selection unit outputs the first carry signal.

18. The carry operation method of claim 12, wherein, The carry output module comprises a fifth lookup table unit, the fifth lookup table unit comprises at least 2j+2 signal input terminals, a carry input terminal and a carry output terminal, and the method further comprises: 2j+2 signal input terminals of the fifth lookup table unit receive j pairs of arithmetic signals, the Yth stage carry generation signal and the Yth stage carry transfer signal respectively, the carry input terminal of the fifth lookup table unit receives the initial carry signal, and the carry output terminal of the fifth lookup table unit outputs the second carry signal.

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