Post-optical proximity correction mask layout correction for wafer back side overlay

Abstract

A method for mask pattern design includes obtaining information indicative of distortion on a second side of a wafer that is opposite to a first side of the wafer, wherein the information is obtained based on characteristics of the first side; obtaining mask patterns configured for a second layer design for the second side of the wafer, the mask patterns resulting from an optical proximity correction process; and correcting the mask patterns based on the obtained information.

Description

POST-OPTICAL PROXIMITY CORRECTION MASK LAYOUT CORRECTION FOR WAFER BACK SIDE OVERLAYCROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims priority of US application 63 / 681,715 which was filed on August 09, 2024 and which is incorporated herein in its entirety by reference.TECHNICAL FIELD

[0002] The embodiments provided herein relate to mask layout correction, and more particularly to post-optical proximity correction mask layout correction for wafer back side overlay.BACKGROUND

[0003] A lithographic apparatus can be used, for example, in the manufacturing of integrated circuits (ICs). In such a case, a mask or a reticle may contain or provide a circuit pattern corresponding to an individual layer of the IC (“design layout”), and this circuit pattern can be transferred onto a target portion (e.g., comprising one or more dies) on a substrate (e.g., silicon wafer).

[0004] Wafer bonding is a process in which two wafers are bonded together. One exemplary technique is fusion wafer bonding, in which a fully processed front side of a device wafer is coated with SiOz or SiCN and polished before being adhered to a carrier wafer, followed by back side wafer processing. The bonding process creates wafer stress that impacts the back side processing of the wafer. For example, the back side of the bonded wafer may not be perfectly flat (e.g., may have some waviness on the surface) which may impact a circuit pattern transferred onto the back side of the wafer.SUMMARY

[0005] Some embodiments provide a method for mask pattern design includes obtaining information indicative of distortion on a second side of a wafer that is opposite to a first side of the wafer, wherein the information is obtained based on characteristics of the first side; obtaining mask patterns configured for a second layer design for the second side of the wafer, the mask patterns resulting from an optical proximity correction process; and correcting the mask patterns based on the obtained information.

[0006] Some embodiments provide a method for mask layout correction for a second side of a bonded wafer that is opposite to a first side of the wafer. The method includes performing optical proximity correction on the mask layout for the second side of the wafer; performing cell flattening on the mask layout; determining mask polygon placement correction to the mask layout; and generating the corrected mask layout of the second side of the wafer based on the mask polygon placement correction. Determining the mask polygon placement correction includes obtaining topographyinformation of the first side prior to bonding; creating a pre-bonding topography map of the first side based on the obtained topography information; converting the pre-bonding topography map into an x- y distortion map; determining a mean x-y distortion from the x-y distortion map; and using the mean x-y distortion as an input to mask polygon placement correction for the mask layout of the second side of the wafer.

[0007] Some embodiments provide a non-transitory computer readable medium that stores a set of instructions that is executable by at least one processor of a computing device to cause the computing device to perform operations for mask pattern design. The operations include obtaining information indicative of distortion on a second side of a wafer that is opposite to a first side of the wafer, wherein the information is obtained based on characteristics of the first side; obtaining mask patterns configured for a second layer design for the second side of the wafer, the mask patterns resulting from an optical proximity correction process; and correcting the mask patterns based on the obtained information.

[0008] Some embodiments provide a non-transitory computer readable medium that stores a set of instructions that is executable by at least one processor of a computing device to cause the computing device to perform operations for mask layout correction for a second side of a bonded wafer that is opposite to a first side of the wafer. The operations include performing optical proximity correction on the mask layout for the second side of the wafer; performing cell flattening on the mask layout; determining mask polygon placement correction to the mask layout; and generating the corrected mask layout of the second side of the wafer based on the mask polygon placement correction. Determining the mask polygon placement correction includes obtaining topography information of the first side prior to bonding; creating a pre-bonding topography map of the first side based on the obtained topography information; converting the pre -bonding topography map into an x-y distortion map; determining a mean x-y distortion from the x-y distortion map; and using the mean x-y distortion as an input to mask polygon placement correction for the mask layout of the second side of the wafer.

[0009] Other advantages of the embodiments of the present disclosure will become apparent from the following description taken in conjunction with the accompanying drawings wherein are set forth, by way of illustration and example, certain embodiments of the present invention.BRIEF DESCRIPTION OF FIGURES

[0010] The above and other aspects of the present disclosure will become more apparent from the description of exemplary embodiments, taken in conjunction with the accompanying drawings.

[0011] Fig. 1 is a diagram of wafer bonding, consistent with some embodiments of the present disclosure.

[0012] Fig. 2 is a block diagram of various subsystems of a lithography system, consistent with some embodiments of the present disclosure.

[0013] Fig. 3 is an example flowchart of a method for simulating lithography in a lithographic projection apparatus, consistent with some embodiments of the present disclosure.

[0014] Fig. 4 is a flowchart of an example method of source or mask optimization of a patterning process, consistent with some embodiments of the present disclosure.

[0015] Fig. 5 is a block diagram of an exemplary server, consistent with some embodiments of the present disclosure.

[0016] Fig. 6 is a schematic diagram illustrating an example neural network, consistent with some embodiments of the present disclosure.

[0017] Fig. 7 is a flow diagram of a method for correcting a mask layout using wafer height information, consistent with some embodiments of the present disclosure.

[0018] Fig. 8 is a flow diagram of a model calibration flow, consistent with some embodiments of the present disclosure.

[0019] Fig. 9 is a flowchart of an example method for determining mask polygon placement correction to a mask layout for a back side of a bonded wafer, consistent with embodiments of the present disclosure.

[0020] Fig. 10 is a flowchart of another example method for determining mask polygon placement correction to a mask layout for a back side of a bonded wafer, consistent with embodiments of the present disclosure.DETAILED DESCRIPTION

[0021] Reference will now be made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings. The following description refers to the accompanying drawings in which the same numbers in different drawings represent the same or similar elements unless otherwise represented. The implementations set forth in the following description of exemplary embodiments do not represent all implementations. Instead, they are merely examples of apparatuses and methods consistent with aspects related to the disclosed embodiments as recited in the appended claims.

[0022] Relative dimensions of components in drawings may be exaggerated for clarity. Within the following description of drawings, the same or like reference numbers refer to the same or like components or entities, and only the differences with respect to the individual embodiments are described. As used herein, unless specifically stated otherwise, the term “or” encompasses all possible combinations, except where infeasible. For example, if it is stated that a component may include A or B, then, unless specifically stated otherwise or infeasible, the component may include A, or B, or A and B. As a second example, if it is stated that a component may include A, B, or C, then, unless specifically stated otherwise or infeasible, the component may include A, or B, or C, or A and B, or A and C, or B and C, or A and B and C.

[0023] Electronic devices are constructed of circuits formed on a piece of semiconductor material called a substrate. The semiconductor material may include, for example, silicon, gallium arsenide, indium phosphide, or silicon germanium, or the like. Many circuits may be formed together on the same piece of silicon and are called integrated circuits or ICs. The size of these circuits has decreased dramatically so that many more of them can be fit on the substrate. For example, an IC chip in a smartphone can be as small as a thumbnail and yet may include over 2 billion transistors, the size of each transistor being less than 1 / 1000th the size of a human hair.

[0024] Making these ICs with extremely small structures or components is a complex, timeconsuming, and expensive process, often involving hundreds of individual steps. Errors in even one step have the potential to result in defects in the finished IC, rendering it useless. Thus, one goal of the manufacturing process is to avoid such defects to maximize the number of functional ICs made in the process; that is, to improve the overall yield of the process.

[0025] A lithographic apparatus can be used, for example, in the manufacturing of ICs. In such a case, a mask or a reticle may contain or provide a circuit pattern corresponding to an individual layer of the IC (“design layout”), and this circuit pattern can be transferred onto a target portion (e.g., comprising one or more dies) on a substrate (e.g., silicon wafer) that has been coated with a layer of radiation-sensitive material (“resist”), by methods such as irradiating the target portion through the circuit pattern on the mask.

[0026] Although specific reference may be made in this text to the manufacture of ICs, it should be explicitly understood that the description herein has many other possible applications. For example, it may be employed in the manufacture of integrated optical systems, guidance and detection patterns for magnetic domain memories, liquid-crystal display panels, thin-film magnetic heads, etc. The skilled artisan will appreciate that, in the context of such applications, use of the terms “reticle,” “wafer,” or “die” in the present disclosure may be interchangeable with the more general terms “mask,” “substrate,” and “target portion,” respectively.

[0027] In wafer bonding, a wafer is patterned on a first side (e.g., the front side). The patterned front side of the wafer is polished, the wafer is bonded to a carrier wafer and flipped over. The back side of the wafer is ground and lithography is performed on the ground back side of the wafer.

[0028] Because the polishing process may not be perfect, the front surface of the wafer may have some waviness to it, or process-induced height variation. For example, some locations on the wafer surface may be a little higher than other locations (e.g., a few nanometers (nm)) and some locations on the wafer surface may be a little lower than other locations (e.g., a few nm). Based on the waviness of the surfaces, from contact or adhesion mechanics, there may be stress induced when the wafers are bonded together. The stress may also be induced by the mechanical chuck used to hold the wafer in position during the bonding process and may be referred to herein as “wafer chucking.” The induced stress may cause the elastic material (i.e., the wafer substrate) to deform locally, such as a positive deformation or a negative deformation. Fig. 1 is a diagram of wafer bonding, consistent with someembodiments of the present disclosure. As shown in Fig. 1, different induced stresses on the wafer may result in deformations. In some cases, the topography may be caused by a pre-bonding surface preparation process on the front surface, including deposition, chemical mechanical polishing, or surface treatment.

[0029] Wafer deformation will appear as an x-y displacement, or in-plane distortion, on the wafer. If the displacement is repetitive on every field, then there will be a similar degree of in-plane distortion on every field. However, in some instances, the in-plane distortion may be localized, or in high spatial frequency. For example, there may be a change in wafer in-plane distortion from +lnm to -5nm within a few micrometer range of each other. In such circumstances, the localized or high spatial frequency distortions may be difficult for a scanner system to actively correct depending on how scanner systems are configured.

[0030] According to embodiments of the present disclosure, to address this problem, the topography on the first (e.g., front) side of the wafer causing the distortions on the second (e.g., back) side may be simulated and incorporated in the mask design process for the second side application layer. In some embodiments, the front side topography can be converted into a predicted intrafield distortion. In some embodiments, a topographical map may be created and the expected degree of distortion from the topographical map may then be incorporated in the design process of the photolithography mask to reduce the impact of the distortion on the back side patterning. For example, if the degree of distortion is known (e.g., 5nm), the mask patterns may be adjusted accordingly to compensate for the distortion effect. Creating a model of the distortions in wafer bonding advantageously allows the distortions to be incorporated across the design.

[0031] In-die metrology is a time-consuming process. To reduce the amount of time, one approach is to obtain sparse overlay information by measuring selected parts of the wafer. Interpolation may then be performed based on the sparse overlay information to predict overlay in other parts of the wafer (i.e., the parts of the wafer that were not actually measured). The present disclosure adds a topography metrology step, which provides additional information that may be difficult to obtain in-device, thereby providing a higher resolution of information.

[0032] Embodiments of the present disclosure can provide methods for correcting a mask pattern design used for processing a back side of a wafer after bonding. In some embodiments, after a front side of the wafer is patterned, the topography of the front side of the wafer is measured with a metrology tool or is inferred using a topography model. The topography of the front side of the wafer is used to create a topography map of the front side of the wafer. In some embodiments, the topography map represents a post-processing and pre-bonding topography. The pre-bonding topography map can be converted into a spatial distortion map (e.g., an x-y distortion map). Mean spatial distortion values may be determined based on the spatial distortion map. For example, the z- axis distortion values from the topography map of the front side of the wafer may be converted into x- axis and y-axis distortion values of the back side of the wafer by using a model. Mask featureplacement correction (e.g., as in an OPC process) can be performed based on the mean x-y distortion values. In some embodiments, the mask features are represented using mask contour polygons, and the correction is performed on the mask polygons. For example, the mask polygon locations may be shifted on the mask layout based on its x, y coordinates on the mask layout. Based on the expected x-y distortion values, the mask polygons may be shifted to counteract the expected degree of distortion. After the mask polygon placement correction, a corrected mask layout of the back side of the wafer is generated and is sent out for mask production.

[0033] In the present disclosure, the terms “radiation” and “beam” may be used to encompass all types of electromagnetic radiation, including ultraviolet radiation (e.g., with a wavelength of 365, 248, 193, 157 or 126 nm) and EUV (extreme ultra-violet radiation, e.g., having a wavelength in the range 5-20 nm).

[0034] The term “optimizing” and “optimization” as used herein may indicate adjusting a lithographic projection apparatus such that results or processes of lithography have more desirable characteristics, such as higher accuracy of projection of design layouts on a substrate, larger process windows, etc.

[0035] The design layouts may be generated utilizing CAD (computer-aided design) programs, this process often being referred to as EDA (electronic design automation). Most CAD programs follow a set of predetermined design rules to create functional design layouts / patterning devices. These rules are set by processing and design limitations. For example, design rules define the space tolerance between circuit devices (such as gates, capacitors, etc.) or interconnect lines, to ensure that the circuit devices or lines do not interact with one another in an undesirable way. The design rule limitations are typically referred to as “critical dimensions” (CD). A critical dimension of a circuit can be defined as the smallest width of a line or hole or the smallest space between two lines or two holes. Thus, the CD determines the overall size and density of the designed circuit. One of the goals in integrated circuit fabrication is to faithfully reproduce the original circuit design on the substrate (via the patterning device).

[0036] The term “mask” or “patterning device” as used herein may be broadly interpreted as referring to a generic patterning device that may be used to endow an incoming radiation beam with a patterned cross-section, corresponding to a pattern that is to be created in a target portion of the substrate; the term “light valve” may also be used in this context. Besides the classic mask (transmissive or reflective, binary, phase-shifting, hybrid, etc.), examples of other such patterning devices include a programmable mirror array. An example of such a device is a matrix-addressable surface having a viscoelastic control layer and a reflective surface. The basic principle behind such an apparatus is that (for example) addressed areas of the reflective surface reflect incident radiation as diffracted radiation, whereas unaddressed areas reflect incident radiation as undiffracted radiation. Using an appropriate filter, the undiffracted radiation can be filtered out of the reflected beam, leaving only the diffracted radiation behind; in this manner, the beam becomes patterned according to theaddressing pattern of the matrix-addressable surface. The required matrix addressing may be performed using suitable electronic means. More information on such mirror arrays may be gleaned, for example, from U.S. Patent Nos. 5,296,891 and 5,523,193, which are incorporated herein by reference in their entirety.

[0037] Another example of such patterning devices includes a programmable LCD array. An example of such a construction is given in U.S. Patent No. 5,229,872, which is incorporated herein by reference in its entirety.

[0038] Fig. 2 illustrates an example lithographic projection apparatus 200, consistent with some embodiments of the present disclosure. Major components of the apparatus 200 are a radiation source 202, which may be a deep-ultraviolet excimer laser source or other type of source including an extreme ultra violet (EUV) source (the lithographic projection apparatus itself need not have the radiation source), illumination optics which define the partial coherence (denoted as sigma) and which may include optic components 204, 206a, and 206b that shape radiation from the source 202; a patterning device 208; and transmission optics 206c that project an image of the patterning device pattern onto a substrate plane 212. An adjustable filter or aperture 210 at the pupil plane of the projection optics may restrict the range of beam angles that impinge on the substrate plane 212, where the largest possible angle defines the numerical aperture of the projection optics NA = n sin(0max) where n is the index of reflection of the media between the last lens element to the substrate.

[0039] In an optimization process of a system, a figure of merit of the system may be represented as a cost function. The optimization process finds a set of parameters (design variables) of the system that minimizes the cost function. The cost function may have any suitable form depending on the goal of the optimization. For example, the cost function may be a weighted root mean square (RMS) of deviations of certain characteristics (evaluation points) of the system with respect to the intended values (e.g., ideal values) of these characteristics; the cost function may also be the maximum of these deviations (e.g., worst deviation). The term “evaluation points” herein should be interpreted broadly to include any characteristics of the system. The design variables of the system may be confined to finite ranges or be interdependent due to practicalities of implementations of the system. In case of a lithographic projection apparatus, the constraints are often associated with physical properties and characteristics of the hardware such as tunable ranges or patterning device manufacturability design rules, and the evaluation points may include physical points on a resist image on a substrate, as well as non-physical characteristics such as dose and focus.

[0040] In a lithographic projection apparatus, a source provides illumination (e.g., light); projection optics direct and shape the illumination via a patterning device and onto a substrate. The term “projection optics” is broadly defined to include any optical component that may alter the wavefront of the radiation beam. For example, projection optics may include at least some of the components 204, 206a, 206b, and 206c. An aerial image is the radiation intensity distribution at substrate level. A resist layer on the substrate is exposed and the aerial image is transferred to the resist layer as a latent“resist image” therein. The resist image may be defined as a spatial distribution of solubility of the resist in the resist layer. A resist model may be used to calculate the resist image from the aerial image, an example of which can be found in commonly assigned U.S. Patent No. 8,200,468, the disclosure of which is hereby incorporated by reference in its entirety. The resist model is related to properties of the resist layer (e.g., effects of chemical processes which occur during exposure, postexposure bake (PEB), and development). Optical properties of the lithographic projection apparatus (e.g., properties of the source, the patterning device, and the projection optics) dictate the aerial image. Since the patterning device used in the lithographic projection apparatus may be changed, it is desirable to separate the optical properties of the patterning device from the optical properties of the rest of the lithographic projection apparatus including at least the source and the projection optics.

[0041] Fig. 3 is an example flowchart of a method 300 for simulating lithography in a lithographic projection apparatus, consistent with some embodiments of the present disclosure. A source model 302 represents optical characteristics (including radiation intensity distribution or phase distribution) of the source. A projection optics model 304 represents optical characteristics (including changes to the radiation intensity distribution or the phase distribution caused by the projection optics) of the projection optics. A design layout model 306 represents optical characteristics (including changes to the radiation intensity distribution or the phase distribution caused by a given design layout) of a design layout, which is the representation of an arrangement of features on or formed by a patterning device. An aerial image 308 may be simulated from the source model 302, the projection optics model 304, and the design layout model 306. A resist image 312 may be simulated from the aerial image 308 using a resist model 310. Simulation of lithography can, for example, predict contours and CDs in the resist image.

[0042] More specifically, it is noted that the source model 302 may represent the optical characteristics of the source that include, but are not limited to, NA-sigma (o) settings as well as any particular illumination source shape (e.g., off-axis radiation sources such as annular, quadrupole, and dipole, etc.). The projection optics model 304 may represent the optical characteristics of the projection optics that include aberration, distortion, refractive indexes, physical sizes, physical dimensions, etc. The design layout model 306 may represent physical properties of a physical patterning device, as described, for example, in U.S. Patent No. 7,587,704, which is incorporated by reference in its entirety. The objective of the simulation is to accurately predict, for example, edge placements, aerial image intensity slopes, and critical dimensions (CDs), which can then be compared against an intended design. The intended design is generally defined as a pre-optical proximity correction (OPC, sometimes also referred to as “optical and process correction”) design layout which can be provided in a standardized digital file format. The layout file may be in a Graphic Database System (GDS) format, Graphic Database System II (GDS II) format, an Open Artwork System Interchange Standard (OASIS) format, a Caltech Intermediate Format (CIF), etc. The wafer design may include patterns or structures for inclusion on the wafer. The patterns or structures may be maskpatterns used to transfer features from the photolithography masks or reticles to a wafer. In some embodiments, a layout in GDS or OASIS format, among others, may include feature information stored in a binary file format representing planar geometric shapes, text, and other information related to the wafer design.

[0043] From this design layout, one or more portions may be identified, which are referred to as “clips.” In some embodiments, a set of clips is extracted, which represents the complicated patterns in the design layout (typically about 50 to 1000 clips, although any number of clips may be used). As will be appreciated by those skilled in the art, these patterns or clips represent small portions (e.g., circuits, cells, or patterns) of the design and especially the clips represent small portions for which particular attention or verification is needed. In other words, clips may be the portions of the design layout or may be similar or have a similar behavior of portions of the design layout where critical features are identified either by experience (including clips provided by a customer), by trial and error, or by running a full-chip simulation. Clips usually contain one or more test patterns or gauge patterns.

[0044] An initial larger set of clips may be provided a priori by a customer based on known critical feature areas in a design layout which require particular image optimization. Alternatively, in some embodiments, the initial larger set of clips may be extracted from the entire design layout by using some kind of automated (such as, machine vision) or manual algorithm that identifies the critical feature areas.

[0045] In some embodiments, an optimization process (e.g., source mask optimization (SMO)) relates to one or more of a patterning process that employs process models (e.g., an optics model, a mask model, a resist model, etc. of Fig. 3). The optimization process may involve execution of the one or more process models and computing a cost function which may be reduced by modifying one or more characteristics (e.g., source, mask pattern, etc.) of the patterning process. In some embodiments, the one or more characteristics may be described by design variables. Hence, an optimized characteristic may also be referred to as an optimized design variable, where a design variable is optimized based on a cost function (e.g., CF).

[0046] In some embodiments, modifying the one or more characteristics is based on a gradient of the cost function that guides how the characteristic should be modified to reduce the cost function. In some embodiments, a cost function is a function of a certain continuous metric such as an edge placement error (e.g., a difference between contours of printed pattern and a target pattern). Using a continuous metric or a cost function of a continuous nature allows use of gradient-based optimizing algorithms that have acceptable runtime performance of an optimization process.

[0047] In some embodiments, non-smooth or discontinuous cost functions (e.g., based on defect counts) are not employed, as such non-smooth cost functions necessitate using non-continuous optimizers which have a relatively high runtime compared to the continuous cost function based optimization. In addition, such optimizers may not provide the best solutions. In some embodiments,use of a non-smooth cost function such as related to defects may be desired so that optimization may be performed to reduce a particular defect or several defects that may potentially appear on a printed substrate.

[0048] The present disclosure provides methods that employ a non-smooth cost function, for example, to reduce the number of defects and thereby improve the yield of the patterning process. It can be understood by a person skilled in the art that concepts of a guide function (e.g., a pseudogradient) and discrete cost function (e.g., a first cost function discussed herein) may be applied to any aspect of the patterning process including an optimization process and not limited to a particular aspect of the patterning process. In some embodiments, the concepts are explained with respect to a source mask optimization process for better understandability.

[0049] Details of techniques and models used to transform a patterning device pattern into various lithographic images (e.g., an aerial image, a resist image, an etch image, etc.), apply OPC (e.g., using models) and evaluate performance (e.g., in terms of process window) are described in U.S. Patent Nos. 7,695,876; 7,707,538; 7,747,978; 7,882,480; 8,413,081; 8,438,508; and 9,360,766, the disclosure of each which is hereby incorporated by reference in its entirety.

[0050] Fig. 4 is a flowchart of an example method 400 of source or mask optimization of a patterning process, consistent with some embodiments of the present disclosure.

[0051] In a typical high-end design almost every feature edge requires some modification to achieve printed patterns that come sufficiently close to the target design. These modifications may include shifting or biasing of edge positions or line widths as well as application of “assist” features that are not intended to print themselves, but will affect the properties of an associated primary feature. Furthermore, optimization techniques applied to the source of illumination may have different effects on different edges and features. Optimization of illumination sources may include the use of pupils to restrict source illumination to a selected pattern of light. Embodiments of the present disclosure provide optimization methods that can be applied to both source and mask configurations.

[0052] In general, a method of performing source and mask optimization (SMO) enables full chip pattern coverage while lowering the computation cost by intelligently selecting a small set of critical design patterns from the full set of clips to be used in SMO. SMO is performed only on these selected patterns to obtain an optimized source. The optimized source is then used to optimize the mask (e.g., using OPC) for the full chip, and the results are compared.

[0053] One example SMO method according to embodiments of the invention will be explained in connection with the method 400.

[0054] A target design 401 (typically comprising a layout in a standard digital format such as OASIS, GDSII, etc.) for which a lithographic process is to be optimized includes memory, test patterns, and logic. From this design, a full set of clips 402 is extracted, which represents all the complicated patterns in the design 401 (typically about 50 to 1000 clips). As will be appreciated bythose skilled in the art, these clips represent small portions (i.e., circuits, cells, or patterns) of the design for which particular attention and / or verification is needed.

[0055] As generally shown in step 404, a small subset of clips 406 (e.g., 15 to 50 clips) is selected from the full set 402. As will be explained in more detail below, the selection of clips is preferably performed such that the process window of the selected patterns as closely as possible matches the process window for the full set of critical patterns. The effectiveness of the selection is also measured by the total turn run time (pattern selection and SMO) reduction.

[0056] In step 408, SMO is performed with the selected patterns (15 to 50 patterns) 406. More particularly, an illumination source is optimized for the selected patterns 406. This optimization may be performed using any of a wide variety of known methods, for example those described in U.S. Patent Application Publication No. 2004 / 0265707, the contents of which are incorporated herein by reference.

[0057] In step 410, manufacturability verification of the selected patterns 406 is performed with the source obtained in step 408. More particularly, verification includes performing an aerial image simulation of the selected patterns 406 and the optimized source and verifying that the patterns will print across a sufficiently wide process window. This verification may be performed using any of a wide variety of known methods, for example those described in U.S. Patent No. 7,342,646, the contents of which are incorporated herein by reference.

[0058] If the verification in step 410 is satisfactory, as determined in step 412, then processing advances to full chip optimization in step 414. Otherwise, processing returns to step 408, where SMO is performed again but with a different source or set of patterns. For example, the process performance as estimated by the verification tool can be compared against thresholds for certain process window parameters such as exposure latitude and depth of focus. These thresholds may be predetermined or set by a user.

[0059] In step 416, after the selected patterns meet lithography performance specification as determined in step 412, the optimized source 414 will be used for optimization of the full set of clips.

[0060] In step 418, model-based sub-resolution assist feature placement (MB-SRAF) and optical proximity correction (OPC) for all the patterns in the full set of clips 416 is performed. This process may be performed using any of a wide variety of known methods, for example those described in U.S. Patent Nos. 5,663,893; 5,821,014; 6,541,167; and 6,670,081, the contents of which are incorporated herein by reference.

[0061] In step 420, using processes similar to step 410, full pattern simulation based manufacturability verification is performed with the optimized source 414 and the full set of clips 416 as corrected in step 418.

[0062] In step 422, the performance (e.g., process window parameters such as exposure latitude and depth of focus) of the full set of clips 416 is compared against the subset of clips 406. In one example embodiment, the pattern selection is considered complete and / or the source is fully qualified for thefull chip when the similar (< 10%) lithography performances are obtained for both selected patterns (15 to 50) 406 and all critical patterns (50 to 1000) 416.

[0063] Otherwise, in step 424, hotspots are extracted, and in step 426 these hotspots are added to the subset 406, and the process starts over. For example, hotspots (i.e., features among the full set of clips 416 that limit process window performance) identified during verification step 420 are used for further source tuning or to re-run SMO. The source is considered fully converged when the process window of the full set of clips 416 are the same between the last run and the run before the last run of step 422.

[0064] OPC calibration may be performed by modeling or simulation. For example, for the desired yield, the total number of features, and their respective probabilities of failure, simulation may be performed to optimize OPC for a lowest yielding feature. OPC addresses the fact that, in addition to any demagnification by the lithographic projection apparatus, the final size and placement of an image of the patterning device pattern projected on the substrate will not be identical to, or simply depend only on the size and placement of, the corresponding patterning device pattern features on the patterning device.

[0065] In some embodiments, the measurement data (e.g., stochastic variations) related to the printed pattern may be employed in optimizing the patterning process or adjusting parameters of the patterning process. It is noted that the terms “mask,” “reticle,” and “patterning device” are utilized interchangeably herein. Also, person skilled in the art will recognize that, especially in the context of lithography simulation / optimization, the term “mask” / “patterning device” and “design layout” may be used interchangeably, as in lithography simulation / optimization, a physical patterning device is not necessarily used but a design layout can be used to represent a physical patterning device. For the small feature sizes and high feature densities present on some design layouts, the position of a particular edge of a given feature may be influenced to a certain extent by the presence or absence of other adjacent features. These proximity effects arise from minute amounts of radiation coupled from one feature to another or non-geometrical optical effects such as diffraction and interference.Similarly, proximity effects may arise from diffusion and other chemical effects during post-exposure bake (PEB), resist development, and etching that generally follow lithography.

[0066] To ensure that the projected image of the patterning device pattern is in accordance with requirements of a given target design, proximity effects should be predicted and compensated for, using sophisticated numerical models, corrections, or pre-distortions of the patterning device pattern. The article “Full-Chip Lithography Simulation and Design Analysis — How OPC Is Changing IC Design,” C. Spence, Proc. SPIE, Vol. 5751, pp 1-14 (2005) provides an overview of “model-based” optical proximity correction processes. In a typical high-end design, almost every feature of the patterning device pattern has some modification to achieve high fidelity of the projected image to the target design. These OPC modifications may include shifting or biasing of edge positions or line widths and / or application of “assist” features that are intended to assist projection of other features.

[0067] Application of model-based OPC to a target design involves good process models and considerable computational resources, given the many millions of features typically present in a device design. However, applying OPC is generally an empirical, iterative process that does not always compensate for all possible proximity effects. Therefore, the effect of OPC, e.g., patterning device patterns after application of OPC and any other resolution enhancement technique (RET), should be verified by design inspection, e.g., intensive full-chip simulation using calibrated numerical process models, to reduce or minimize the possibility of design flaws being built into the patterning device pattern. This is driven by the enormous cost of making high-end patterning devices, which run in the multi-million dollar range, as well as by the impact on turn-around time by reworking or repairing actual patterning devices once they have been manufactured. Both OPC and full-chip RET verification may be based on numerical modelling systems and methods as described, for example in, U.S. Pat. No. 7,003,758 and an article titled “Optimized Hardware and Software For Fast, Full Chip Simulation”, by Y. Cao et al., Proc. SPIE, Vol. 5754, 405 (2005), which are incorporated herein in their entireties by reference.

[0068] The illumination source can also be optimized, either jointly with patterning device optimization or separately, to improve the overall lithography fidelity. The terms “illumination source” and “source” are used interchangeably in this disclosure. As is known, off-axis illumination (such as annular, quadrupole, and dipole) is a proven way to resolve fine structures (e.g., target features) contained in the patterning device.

[0069] However, when compared to a traditional illumination source, an off-axis illumination source usually provides less radiation intensity for the aerial image. Thus, it becomes desirable to attempt to optimize the illumination source to achieve the optimal balance between finer resolution and reduced radiation intensity.

[0070] Numerous illumination source optimization approaches can be found, for example, in an article by Rosenbluth et al., titled “Optimum Mask and Source Patterns to Print A Given Shape,” Journal of Microlithography, Microfabrication, Microsystems 1(1), pp.13-20, (2002). The source is partitioned into several regions, each of which corresponds to a certain region of the pupil spectrum. Then, the source distribution is assumed to be uniform in each source region and the brightness of each region is optimized for process window. However, such an assumption that the source distribution is uniform in each source region is not always valid, and as a result the effectiveness of this approach suffers. In another example set forth in an article by Granik, titled “Source Optimization for Image Fidelity and Throughput,” Journal of Microlithography, Microfabrication, Microsystems 3(4), pp.509-522, (2004), several existing source optimization approaches are overviewed and a method based on illuminator pixels is proposed that converts the source optimization problem into a series of non-negative least square optimizations. Though these methods have demonstrated some successes, they typically require multiple complicated iterations to converge. In addition, it may be difficult to determine the appropriate / optimal values for some extra parameters, such as y in Granik’smethod, which dictates the trade-off between optimizing the source for substrate image fidelity and the smoothness requirement of the source.

[0071] For low ki photolithography, optimization of both the source and patterning device are useful to ensure a viable process window for projection of critical circuit patterns. Some algorithms (e.g., Socha et. Al. Proc. SPIE vol.5853, 2005, p.180) discretize illumination into independent source points and mask into diffraction orders in the spatial frequency domain, and separately formulate a cost function (which is defined as a function of selected design variables) based on process window metrics such as exposure latitude which could be predicted by optical imaging models from source point intensities and patterning device diffraction orders. The term “design variables” as used herein includes a set of parameters of a lithographic projection apparatus or a lithographic process. For example, parameters a user of the lithographic projection apparatus can adjust, or image characteristics a user can adjust by adjusting those parameters (e.g., source or mask design variables). It should be appreciated that any characteristics of a lithographic projection process, including those of the source, the patterning device, the projection optics, or resist characteristics may be among the design variables in the optimization. The cost function is often a non-linear function of the design variables. Then standard optimization techniques are used to minimize the cost function.

[0072] A source and patterning device (design layout) optimization method and system that allows for simultaneous optimization of the source and patterning device using a cost function without constraints and within a practicable amount of time is described in a commonly assigned International Patent Application No. PCT / US2009 / 065359, filed on November 20, 2009, and published as W02010 / 059954, titled “Fast Freeform Source and Mask Co-Optimization Method”, which is hereby incorporated by reference in its entirety.

[0073] Another source and mask optimization method and system that involves optimizing the source by adjusting pixels of the source is described in a commonly assigned U.S. Patent No. 8,786,824, which is hereby incorporated by reference in its entirety.

[0074] Fig. 5 is a block diagram of an example server 500, consistent with some embodiments of the disclosure. As shown in Fig. 5, server 500 can include processor 502. When processor 502 executes instructions described herein, server 500 can become a specialized machine. Processor 502 can be any type of circuitry capable of manipulating or processing information. For example, processor 502 can include any combination of any number of a central processing unit (“CPU”), a graphics processing unit (“GPU”), a neural processing unit (“NPU”), a microcontroller unit (“MCU”), an optical processor, a programmable logic controller, a microcontroller, a microprocessor, a digital signal processor, an intellectual property (IP) core, a Programmable Logic Array (PLA), a Programmable Array Logic (PAL), a Generic Array Logic (GAL), a Complex Programmable Logic Device (CPLD), a Field-Programmable Gate Array (FPGA), a System On Chip (SoC), an Application-Specific Integrated Circuit (ASIC), or the like. In some embodiments, processor 502 can also be a set ofprocessors grouped as a single logical component. For example, as shown in Fig. 5, processor 502 can include multiple processors, including processor 502a, processor 502b, and processor 502n.

[0075] Server 500 can also include memory 504 configured to store data (e.g., a set of instructions, computer codes, intermediate data, or the like). For example, as shown in Fig. 5, the stored data can include program instructions and data for processing. Processor 502 can access the program instructions and data for processing (e.g., via bus 510), and execute the program instructions to perform an operation or manipulation on the data for processing. Memory 504 can include a highspeed random-access storage device or a non-volatile storage device. In some embodiments, memory 504 can include any combination of any number of a random-access memory (RAM), a read-only memory (ROM), an optical disc, a magnetic disk, a hard drive, a solid-state drive, a flash drive, a security digital (SD) card, a memory stick, a compact flash (CF) card, or the like. Memory 504 can also be a group of memories (not shown in Fig. 5) grouped as a single logical component.

[0076] Bus 510 can be a communication device that transfers data between components inside server 500, such as an internal bus (e.g., a CPU-memory bus), an external bus (e.g., a universal serial bus port, a peripheral component interconnect express port), or the like.

[0077] For ease of explanation without causing ambiguity, processor 502 and other data processing circuits are collectively referred to as a “data processing circuit” in this disclosure. The data processing circuit can be implemented entirely as hardware, or as a combination of software, hardware, or firmware. In addition, the data processing circuit can be a single independent module or can be combined entirely or partially into any other component of server 500.

[0078] Server 500 can further include network interface 506 to provide wired or wireless communication with a network (e.g., the Internet, an intranet, a local area network, a mobile communications network, or the like). In some embodiments, network interface 506 can include any combination of any number of a network interface controller (NIC), a radio frequency (RF) module, a transponder, a transceiver, a modem, a router, a gateway, a wired network adapter, a wireless network adapter, a Bluetooth adapter, an infrared adapter, a near-field communication (“NFC”) adapter, a cellular network chip, or the like.

[0079] In some embodiments, optionally, server 500 can further include peripheral interface 508 to provide a connection to one or more peripheral devices. As shown in Fig. 5, the peripheral device can include, but is not limited to, a cursor control device (e.g., a mouse, a touchpad, or a touchscreen), a keyboard, a display (e.g., a cathode-ray tube display, a liquid crystal display, or a light-emitting diode display), a video input device (e.g., a camera or an input interface coupled to a video archive), or the like.

[0080] Consistent with some embodiments of this disclosure, the computer-implemented method of determining mask polygon placement correction to a mask layout for a back side of a bonded wafer may also include training a machine learning model using obtained training data. In some embodiments, the machine learning model may be trained by a computer hardware system. In someembodiments, as described elsewhere in this disclosure, the training data may include previously obtained images of the mask layout.

[0081] In some embodiments, machine learning may be employed in converting a pre -bonding topography map of the front side of the wafer into a x-y distortion map, in performing mask polygon placement correction for a design for the back side of the wafer using mean x-y distortion determined from the x-y distortion map, or in generating the topography model based on a product design and back end of line (BEOL) circuit density. For example, the machine learning model may take a prebonding topography map as an input and may generate an x-y distortion map of the back side of the wafer after bonding and thinning as an output. In some embodiments, machine learning may be employed in method 700 of FIG. 7, method 800 of FIG. 8, method 900 of FIG. 9, or method 1000 of FIG. 10. In some embodiments, a machine learning system may include a discriminative model. In some embodiments, a machine learning system may include a generative model. For example, learning can feature two types of mechanisms: discriminative learning that may be used to create classification and detection algorithms, and generative learning that may be used to create models that, in the extreme, can render images.

[0082] If the model(s) include one or more discriminative models, the discriminative model(s) may have any suitable architecture and / or configuration known in the art. Discriminative models, also called conditional models, are a class of models used in machine learning for modeling the dependence of an unobserved variable “y” on an observed variable “x.” Within a probabilistic framework, this may be done by modeling a conditional probability distribution P(ylx), which can be used for predicting y based on x. Application specific details ultimately dictate the suitability of selecting a discriminative versus generative model.

[0083] A generative model can be generally defined as a model that is probabilistic in nature. In other words, a “generative” model is not one that performs forward simulation or rule-based approaches and, as such, it may not be necessary to model the physics of the processes involved in generating an actual image or output (for which a simulated image or output is being generated).

[0084] The machine learning described herein may be further performed as described in “Introduction to Statistical Machine Eearning,” by Sugiyama, Morgan Kaufmann, 2016, 534 pages; “Discriminative, Generative, and Imitative Learning,” by Jebara, MIT Thesis, 2002, 212 pages; and “Principles of Data Mining (Adaptive Computation and Machine Learning)” by Hand et al., MIT Press, 2001, 578 pages; which are incorporated by reference as if fully set forth herein. The embodiments described herein may be further configured as described in these references.

[0085] In some embodiments, a machine learning system may comprise a neural network. For example, a model may be a deep neural network with a set of weights that model the world according to the data that it has been fed to train it.

[0086] Neural networks typically consist of multiple layers, and the signal path traverses from front to back. The goal of the neural network is to solve problems in the same way that the human brainwould, although several neural networks are much more abstract. Modern neural network projects typically work with a few thousand to a few million neural units and millions of connections. The neural network may have any suitable architecture and / or configuration known in the art.

[0087] A neural network, as used herein, may refer to a computing model for analyzing underlying relationships in a set of input data by way of mimicking human brains. Similar to a biological neural network, the neural network may include a set of connected units or nodes (referred to as “neurons”), structured as different layers, where each connection (also referred to as an “edge”) may obtain and send a signal between neurons of neighboring layers in a way similar to a synapse in a biological brain. The signal may be any type of data (e.g., a real number). Each neuron may obtain one or more signals as an input and output another signal by applying a non-linear function to the inputted signals. Neurons and edges may typically be weighted by corresponding weights to represent the knowledge the neural network has acquired. During a training process (similar to a learning process of a biological brain), the weights may be adjusted (e.g., by increasing or decreasing their values) to change the strengths of the signals between the neurons to improve the performance accuracy of the neural network. Neurons may apply a thresholding function (referred to as an “activation function”) to its output values of the non-linear function such that a signal is outputted only when an aggregated value (e.g., a weighted sum) of the output values of the non-linear function exceeds a threshold determined by the thresholding function. Different layers of neurons may transform their input signals in different manners (e.g., by applying different non-linear functions or activation functions). The output of the last layer (referred to as an “output layer”) may output the analysis result of the neural network, such as, for example, a categorization of the set of input data (e.g., as in image recognition cases), a numerical result, or any type of output data for obtaining an analytical result from the input data.

[0088] During the training of a neural network, a loss function (or referred to as a “cost function”) may be used to evaluate the output data. The loss function, as used herein, may map output data of a machine learning model (e.g., the neural network) onto a real number (referred to as a “loss” or a “cost”) that intuitively represents a loss or an error (e.g., representing a difference between the output data and target output data) associated with the output data. The training of the neural network may seek to maximize or minimize the loss function (e.g., by pushing the loss towards a local maximum or a local minimum in a loss curve). For example, one or more parameters of the neural network may be adjusted or updated purporting to maximize or minimize the loss function. After adjusting or updating the one or more parameters, the neural network may obtain new input data in a next iteration of its training. When the loss function is maximized or minimized, the training of the neural network may be terminated.

[0089] By way of example, Fig. 6 is a schematic diagram illustrating an example neural network 600, consistent with some embodiments of the present disclosure. As depicted in Fig. 6, neural network 600 may include an input layer 620 that receives inputs, including input 610-1, . . ., input 610-m (mbeing an integer). For example, an input of neural network 600 may include any structure or unstructured data (e.g., an image). In some embodiments, neural network 600 may obtain a plurality of inputs simultaneously. For example, in Fig. 6, neural network 600 may obtain m inputs simultaneously. In some embodiments, input layer 620 may obtain m inputs in succession such that input layer 620 receives input 610-1 in a first cycle (e.g., in a first inference) and pushes data from input 610-1 to a hidden layer (e.g., hidden layer 630-1), then receives a second input in a second cycle (e.g., in a second inference) and pushes data from input the second input to the hidden layer, and so on. Input layer 620 may obtain any number of inputs in the simultaneous manner, the successive manner, or any manner of grouping the inputs.

[0090] Input layer 620 may include one or more nodes, including node 620-1, node 620-2, . . ., node 620-a (a being an integer). A node (also referred to as a “machine perceptron” or a “neuron”) may model the functioning of a biological neuron. Each node may apply an activation function to received inputs (e.g., one or more of input 610-1, . . ., input 610-m). An activation function may include a Heaviside step function, a Gaussian function, a multiquadratic function, an inverse multiquadratic function, a sigmoidal function, a rectified linear unit (ReLU) function (e.g., a ReLU5 function or a Leaky ReLU function), a hyperbolic tangent (“tanh”) function, or any non-linear function. The output of the activation function may be weighted by a weight associated with the node. A weight may include a positive value between 0 and 1, or any numerical value that may scale outputs of some nodes in a layer more or less than outputs of other nodes in the same layer.

[0091] As further depicted in Fig. 6, neural network 600 includes multiple hidden layers, including hidden layer 630-1, . . ., hidden layer 630-n (n being an integer). When neural network 600 includes more than one hidden layer, it may be referred to as a “deep neural network” (DNN). Each hidden layer may include one or more nodes. For example, in Fig. 6, hidden layer 630-1 includes node 630-1- 1, node 630-1-2, node 630-1-3, . . ., node 630-1-b (b being an integer), and hidden layer 630-n includes node 630-n-l, node 630-n-2, node 630-n-3, . . ., node 630-n-c (c being an integer). Similar to nodes of input layer 620, nodes of the hidden layers may apply the same or different activation functions to outputs from connected nodes of a previous layer, and weight the outputs from the activation functions by weights associated with the nodes.

[0092] As further depicted in Fig. 6, neural network 600 may include an output layer 640 that finalizes outputs, including output 650-1, output 650-2, . . ., output 650-d (d being an integer). Output layer 640 may include one or more nodes, including node 640-1, node 640-2, . . ., node 640-d. Similar to nodes of input layer 620 and of the hidden layers, nodes of output layer 640 may apply activation functions to outputs from connected nodes of a previous layer and weight the outputs from the activation functions by weights associated with the nodes.

[0093] Although nodes of each hidden layer of neural network 600 are depicted in Fig. 6 to be connected to each node of its previous layer and next layer (referred to as “fully connected”), the layers of neural network 600 may use any connection scheme. For example, one or more layers (e.g.,input layer 620, hidden layer 630-1, . . ., hidden layer 630-n, or output layer 640) of neural network 600 may be connected using a convolutional scheme, a sparsely connected scheme, or any connection scheme that uses fewer connections between one layer and a previous layer than the fully connected scheme as depicted in Fig. 6.

[0094] Moreover, although the inputs and outputs of the layers of neural network 600 are depicted as propagating in a forward direction (e.g., being fed from input layer 620 to output layer 640, referred to as a “feedforward network”) in Fig. 6, neural network 600 may additionally or alternatively use backpropagation (e.g., feeding data from output layer 640 towards input layer 620) for other purposes. For example, the backpropagation may be implemented by using long short-term memory nodes (LSTM). Accordingly, although neural network 600 is depicted similar to a convolutional neural network (CNN), neural network 600 may include a recurrent neural network (RNN) or any other neural network.

[0095] Fig. 7 is a flow diagram of a method 700 for correcting a mask layout using wafer height information, consistent with some embodiments of the present disclosure. The method 700 is used for applications where patterning is to be performed on a back side of a wafer after bonding. As used herein, the “back side” of the wafer refers to the back side of the device wafer (and not the carrier wafer).

[0096] At step 702, OPC is performed for the target mask design of the back side of the wafer. To be able to correct the mask layout with the location dependent height information, the cells need to be flattened. For example, cell flattening may include converting information from a hierarchical cell structure into a single cell such that the single cell contains all the information in the cell hierarchy. As used herein, the term “cell” refers to a portion of the mask design.

[0097] At step 704, a pre-bonding topography map is created. For example, the topography map may be created using measurements from wafer shape tools, such as patterned wafer geometry, white light interferometry, or high-resolution profilometry. In some embodiments, other wafer shape tools may be used (for example, an optical tool or atomic force microscopy) with the goal being to obtain measurements of the height variations of the wafer, and the topography map may be generated from the measurements. In some embodiments, the pre-bonding topography map may be inferred from a topography model. For example, the topography model may be trained based on the mask design (e.g., density of the design) and polishing parameters (e.g., pad hardness, overpolishing).

[0098] At step 706, the pre-bonding topography map (e.g., a heightmap z(x, y) and / or a thickness map t(x, y)) is converted into an x, y distortion map. For example, the z-axis information in the topography map is converted into x-axis and y-axis information by a projection from the 3D coordinate space into a 2D coordinate space. The x, y distortion map may include differential values such as mean distortion values and may be provided as a mean distortion field (Ax, Ay). In some embodiments, this conversion may be performed by a trained machine learning model (such as a neural network model described elsewhere in this disclosure), a finite element method model, or asemi-rigorous model with mathematical formulas. For example, a data-driven model may be trained to recognize an after development image (ADI) overlay fingerprint from the pre -bonding topography map. For example, the machine learning model may use an encoder-decoder neural network to convert the z-axis information into x-axis information and y-axis information based on z(x, y) — Ax(x, y) and z(x, y) — Ay(x, y). For example, the finite element method model may include a spatially and temporally discretized model that embeds (including but not limited to) mechanical strain and stress calculations, surface adhesion calculations, thermal deformation calculations, and viscous air flow calculations, with topography information z(x, y) as an input, material mechanical and thermal properties as an input, and displacement fields as an output, both before and after the wafer backside is ground and polished. For example, the semi-rigorous model may include a mathematical model using analytical equations to relate the post-bonding in-plane distortion to the starting topography (z) information. The analytical calculations may include, but are not limited to, calculating the gradient of z(x, y), first and higher order derivatives, convolution and deconvolution with radial or custom Kernal equations of primary and non-primary functions, Fourier transforms, Laplace transforms, solution to differential equations, or combinations of all the above. The semi- rigorous model may also include tunable and calibratable parameters including scaling factors, length scale factors, and anisotropy factors that may link to the material’s mechanical and thermal properties.

[0099] An analytical model may be based on Hertzian contact theory, which assumes that the material is elastic and the surface waviness is not abrupt, meaning that there are no step function-like “hard” transitions or spikes in the height variation of the surface, but instead may be a slowly varying topography. The in-plane distortion locked in the bonding process originates from the non-flat prebonding wafer surface. When the surface is adhered to the carrier wafer, local stress and deformation is formed. In some embodiments, this post-bonding distortion may include distortion from the bonding process (e.g., post-bonding) and post- thinning. This deformation can be calculated using Hertzian theory of contact mechanics, by solving a matrix inversion problem. After grinding, the top wafer (device wafer) is planarized, leaving uneven thickness variations. The different amount of stress release may be included as an additional linear term that scales the local distortion.

[0100] As another example, a reduced mechanical finite element method model may be used. In some embodiments, a reduced model may be derived from the finite element method model, using data-driven methods or pre-calculated library.

[0101] At step 708, the output of the conversion process (performed in step 706) is a mean distortion field (Ax, Ay) that may be inserted into the mask correction flow.

[0102] At step 710, in some embodiments, the mask correction is performed on the mask polygons. Mask polygon placement correction for the back side of the wafer is performed using the information in the mean distortion field. The mask polygon locations are shifted on the mask layout and each feature depends on its x, y coordinates on the mask layout. Based on the expected Ax and Ay, the mask polygons are shifted to counteract the expected degree of distortion.

[0103] At step 712, the corrected mask layout for the back side of the wafer is generated, which may then be sent for the masks to be created.

[0104] Steps 702, 710, and 712 may be part of a basic flow that may be performed when correcting a mask layout based on root causes other than back side wafer distortion. Steps 704, 706, and 708 are implemented to correct the mask layout based on the back side wafer distortion.

[0105] Fig. 8 is a flow diagram of a model calibration flow 800, consistent with some embodiments of the present disclosure. The model calibration flow 800 may be used to calibrate the model used to convert the pre-bonding topography map into the x, y distortion map (e.g., as used in step 706 of the method 700).

[0106] At step 802, the product design (e.g., what will ultimately written to the mask) is tested and back end of line (BEOL) circuit density is determined.

[0107] At step 804, a device wafer processing design-of-experiment (DoE) technique is used to apply different wafer processing variables to determine how the processing variables may affect the final output.

[0108] At step 806, a topography model (Model 1) may be generated based on the product design and BEOL circuit density (from step 802) and the adjusted process variables (from step 804).

[0109] At step 808, a wafer pre-bonding topographical map is created. In some embodiments, the topographical map may be created in a similar manner as in step 704 of the method 700.

[0110] At step 810, wafer bonding is performed, followed by grinding and polishing of the back side of the wafer.

[0111] At step 812, the pre-bonding topography map is converted into the x, y distortion map, for example, by a model (Model 2). The model is calibrated using a topography DoE technique using test wafers and test vehicles. The topography may be modulated both by design (density steps) and polish process (overpolishing and pad hardness). The distortion model parameters may be calibrated to the test wafer stack (e.g., stack height, mechanical properties of the stack material, and backside polish residue thickness). In some embodiments, the model may be calibrated by measuring an overlay after a back side imaging or pattern transfer step is performed. In some embodiments, the overlay may be obtained by using a grid readout without exposing the second layer, to obtain a grid distortion of the device after bonding. For example, overlay = grid distortion - scanner actuation. To restore the grid distortion, actuated scanner parameters may be acquired (e.g., from a stored scanner log) and added to the measured overlay. In some embodiments, a wafer alignment sensor directly captures grid distortion information, but may not provide sufficiently dense information.

[0112] Fig. 9 is a flowchart of an example method 900 for determining mask polygon placement correction to a mask layout for a back side of a bonded wafer, consistent with embodiments of the present disclosure. In some embodiments, the method 900 may be performed by server 500 of Fig. 5.

[0113] At step 902, the topography of a front side of a wafer is measured. For example, the topography of the front side of the wafter may be measured using wafer shape tools, as described in connection with step 704 of Fig. 7.

[0114] At step 904, a pre-bonding topography map of the front side of the wafer is created. The topography map may be created based on the topography measurements obtained in step 902.

[0115] At step 906, the pre-bonding topography map is converted into an x-y distortion map. For example, the z-axis information in the topography map is converted into x-axis and y-axis information. In some embodiments, this conversion may be performed by a trained machine learning model (such as a neural network model described elsewhere in this disclosure), a finite element method model, or a semi-rigorous model with mathematical formulas, as described in connection with step 706 of Fig. 7. In some embodiments, steps 902, 904, and 906 may be collectively referred to as obtaining information indicative of distortion on a wafer.

[0116] At step 908, a mean x-y distortion is determined from the x-y distortion map. For example, a mean distortion field (Ax, Ay) may be determined from the x-y distortion map.

[0117] At step 910, mask polygon placement correction for the back side of the wafer is performed, using the in-plane distortion (e.g., the mean x-y distortion). The mask polygon locations are shifted on the mask layout and each feature depends on its x, y coordinate on the mask layout. Based on the expected Ax and Ay, the mask polygons are shifted to counteract the expected degree of in-plane distortion. For example, shifting the mask polygons may include changing the x, y coordinate for the mask polygon on the mask layout.

[0118] At step 912, a corrected mask layout for the back side of the wafer is generated based on the mask polygon placement correction. The corrected mask layout may then be sent for the masks to be created.

[0119] Fig. 10 is a flowchart of another example method 1000 for determining mask polygon placement correction to a mask layout for a back side of a bonded wafer, consistent with embodiments of the present disclosure. In some embodiments, the method 1000 may be performed by server 500 of Fig. 5.

[0120] At step 1002, a topography model may be used to infer the topography of a front side of a wafer. For example, the topography model may be trained with inputs based on the mask design (e.g., density of the design) and polishing parameters (e.g., pad hardness, overpolishing), as described in connection with step 704 of Fig. 7.

[0121] At step 1004, a pre -bonding topography map of the front side of the wafer is created. The topography map may be created based on the inferred topography from the topography model in step 1002.

[0122] At step 1006, the pre-bonding topography map is converted into an x-y distortion map. For example, the z-axis information in the topography map is converted into x-axis and y-axis information. In some embodiments, this conversion may be performed by a trained machine learningmodel (such as a neural network model described elsewhere in this disclosure), a finite element method model, or a semi-rigorous model with mathematical formulas, as described in connection with step 706 of Fig. 7.

[0123] At step 1008, a mean x-y distortion is determined from the x-y distortion map. For example, a mean distortion field (Ax, Ay) may be determined from the x-y distortion map.

[0124] At step 1010, mask polygon placement correction for the back side of the wafer is performed, using the mean x-y distortion. The mask polygon locations are shifted on the mask layout and each feature depends on its x, y coordinate on the mask. Based on the expected Ax and Ay, the mask polygons are shifted to counteract the expected degree of distortion.

[0125] At step 1012, a corrected mask layout for the back side of the wafer is generated based on the mask polygon placement correction. The corrected mask layout may then be sent for the masks to be created.

[0126] A non-transitory computer readable medium may be provided that stores instructions for a processor of a server (e.g., server 500 of FIG. 5) to carry out, among other things, operations of method 700 of FIG. 7, method 800 of FIG. 8, method 900 of FIG. 9, or method 1000 of FIG. 10.Common forms of non-transitory media include, for example, a floppy disk, a flexible disk, hard disk, solid state drive, magnetic tape, or any other magnetic data storage medium, a Compact Disc Read Only Memory (CD-ROM), any other optical data storage medium, any physical medium with patterns of holes, a Random Access Memory (RAM), a Programmable Read Only Memory (PROM), and Erasable Programmable Read Only Memory (EPROM), a FLASH-EPROM or any other flash memory, Non-Volatile Random Access Memory (NVRAM), a cache, a register, any other memory chip or cartridge, and networked versions of the same.

[0127] Embodiments of the present disclosure can be further described by the following clauses.1. A method for mask pattern design, comprising: obtaining information indicative of distortion on a second side of a wafer that is opposite to a first side of the wafer, wherein the information is obtained based on characteristics of the first side; obtaining mask patterns configured for a second layer design for the second side of the wafer, the mask patterns resulting from an optical proximity correction process; and correcting the mask patterns based on the obtained information.2. The method of clause 1, wherein: the first side is a front side of the wafer; and the second side is a back side of the wafer.3. The method of clause 1, wherein the characteristics of the first side of the wafer comprises topography of the first side.4. The method of clause 3, wherein the information is indicative of in-plane distortion of the second side.5. The method of clause 4, wherein the correcting comprises converting the topography of the first side to the in-plane distortion of the second side.6. The method of clause 2, further comprising: determining the information based on a correlation between topography of the front side of the wafer to post-bonding in-plane distortion on the back side of the wafer.7. The method of clause 6, wherein the topography is associated with process variation in processing the first side.8. The method of clause 7, wherein the process variation occurs during pre-bonding surface preparation process, including deposition, chemical mechanical polishing, and surface treatment.9. The method of clause 6, wherein the correlation is defined by a machine learning model, an analytical model, or a numerical analysis model.10. The method of clause 1, wherein the obtaining information includes measuring a topography of the first side of the wafer following processing thereof and prior to bonding.11. The method of clause 1, wherein the obtaining information includes using a topography model to infer a topography of the first side of the wafer prior to bonding.12. The method of clause 1, wherein the correcting comprises adjusting a mask pattern based on the in-plane distortion associated with the mask pattern.13. The method of clause 1, wherein correcting the mask patterns includes: creating a pre-bonding topography map of the first side of the wafer based on the obtained information; converting the pre -bonding topography map into a spatial distortion map; determining a mean spatial distortion from the spatial distortion map; using the mean spatial distortion as an input to mask polygon placement correction for the mask patterns, wherein the mask polygon placement correction includes shifting mask polygons on the mask layout; and generating the corrected mask patterns based on the mask polygon placement correction.14. The method of clause 13, wherein the spatial distortion map comprises an x-y distortion map.15. The method of clause 14, wherein: each feature in the mask layout depends on its x, y coordinate on the mask layout; and shifting the mask polygons includes changing the x, y coordinate for the mask polygon on the mask layout.16. The method of clause 15, wherein shifting the mask polygons counteracts an expected degree of spatial distortion.17. The method of clause 13, wherein the converting includes using a model to convert z- axis information in the pre-bonding topography map into x-axis information and y-axis information for the spatial distortion map.18. The method of clause 17, wherein the model includes a trained machine learning model, a finite element method model, or a semi-rigorous model with mathematical formulas.19. The method of clause 17, further comprising: calibrating the model by measuring an overlay after a second side imaging or patterning step.20. The method of clause 17, further comprising: calibrating the model by obtaining a grid distortion of the second side of the wafer after bonding.21. A method for mask layout correction for a second side of a bonded wafer that is opposite to a first side of the wafer, the method comprising: performing optical proximity correction on the mask layout for the second side of the wafer; performing cell flattening on the mask layout; determining mask polygon placement correction to the mask layout, comprising: obtaining topography information of the first side prior to bonding; creating a pre -bonding topography map of the first side based on the obtained topography information; converting the pre -bonding topography map into an x-y distortion map; determining a mean x-y distortion from the x-y distortion map; and using the mean x-y distortion as an input to mask polygon placement correction for the mask layout of the second side of the wafer; and generating the corrected mask layout of the second side of the wafer based on the mask polygon placement correction.22. The method of clause 21, wherein obtaining the topography information includes measuring the topography information of the first side of the wafer.23. The method of clause 21, wherein obtaining the topography information includes using a topography model to infer the topography of the first side of the wafer.24. The method of clause 21, wherein the converting includes using a model to convert z- axis information in the pre-bonding topography map into x-axis information and y-axis information for the x-y distortion map.25. The method of clause 21, wherein: the first side is a front side of the wafer; and the second side is a back side of the wafer.26. A non-transitory computer readable medium that stores a set of instructions that is executable by at least one processor of a computing device to cause the computing device to perform operations for mask pattern design, the operations comprising:obtaining information indicative of distortion on a second side of a wafer that is opposite to a first side of the wafer, wherein the information is obtained based on characteristics of the first side; obtaining mask patterns configured for a second layer design for the second side of the wafer, the mask patterns resulting from an optical proximity correction process; and correcting the mask patterns based on the obtained information.27. A non-transitory computer readable medium that stores a set of instructions that is executable by at least one processor of a computing device to cause the computing device to perform operations for mask layout correction for a second side of a bonded wafer that is opposite to a first side of the wafer, the operations comprising: performing optical proximity correction on the mask layout for the second side of the wafer; performing cell flattening on the mask layout; determining mask polygon placement correction to the mask layout, comprising: obtaining topography information of the first side prior to bonding; creating a pre -bonding topography map of the first side based on the obtained topography information; converting the pre -bonding topography map into an x-y distortion map; determining a mean x-y distortion from the x-y distortion map; and using the mean x-y distortion as an input to mask polygon placement correction for the mask layout of the second side of the wafer; and generating the corrected mask layout of the second side of the wafer based on the mask polygon placement correction.

[0128] Block diagrams in the figures may illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer hardware or software products according to various exemplary embodiments of the present disclosure. In some embodiments, a non- transitory computer-readable medium is provided and can include instructions to perform the functions described in connection with any one or more of Figs. 7-10. In this regard, each block in a schematic diagram may represent certain arithmetical or logical operation processing that may be implemented using hardware such as an electronic circuit. Blocks may also represent a module, segment, or portion of code that comprises one or more executable instructions for implementing the specified logical functions. It should be understood that in some alternative implementations, functions indicated in a block may occur out of the order noted in the figures. For example, two blocks shown in succession may be executed or implemented substantially concurrently, or two blocks may sometimes be executed in reverse order, depending upon the functionality involved. Some blocks may also be omitted. It should also be understood that each block of the block diagrams, and combination of the blocks, may be implemented by special purpose hardware-based systems that perform the specified functions or acts, or by combinations of special purpose hardware and computer instructions.

[0129] It will be appreciated that the embodiments of the present disclosure are not limited to the exact construction that has been described above and illustrated in the accompanying drawings, and that various modifications and changes may be made without departing from the scope thereof. The present disclosure has been described in connection with various embodiments, and other embodiments will be apparent to those skilled in the art from consideration of the specification and practice of the technology disclosed herein. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the invention being indicated by the following claims.

Claims

CLAIMS1. A method for mask pattern design, comprising: obtaining information indicative of distortion on a second side of a wafer that is opposite to a first side of the wafer, wherein the information is obtained based on characteristics of the first side; obtaining mask patterns configured for a second layer design for the second side of the wafer, the mask patterns resulting from an optical proximity correction process; and correcting the mask patterns based on the obtained information.

2. The method of claim 1, wherein: the first side is a front side of the wafer; and the second side is a back side of the wafer.

3. The method of claim 1, wherein the characteristics of the first side of the wafer comprises topography of the first side.

4. The method of claim 3, wherein the information is indicative of in-plane distortion of the second side, and wherein the correcting comprises converting the topography of the first side to the in-plane distortion of the second side.

5. The method of claim 2, further comprising: determining the information based on a correlation between topography of the front side of the wafer to post-bonding in-plane distortion on the back side of the wafer.

6. The method of claim 5, wherein the topography is associated with process variation in processing the first side, wherein the process variation occurs during pre-bonding surface preparation process, including deposition, chemical mechanical polishing, and surface treatment.

7. The method of claim 5, wherein the correlation is defined by a machine learning model, an analytical model, or a numerical analysis model.

8. The method of claim 1, wherein the obtaining information includes measuring a topography of the first side of the wafer following processing thereof and prior to bonding.

9. The method of claim 1, wherein the obtaining information includes using a topography model to infer a topography of the first side of the wafer prior to bonding.

10. The method of claim 1, wherein the correcting comprises adjusting a mask pattern based on the in-plane distortion associated with the mask pattern.

11. The method of claim 1 , wherein correcting the mask patterns includes: creating a pre-bonding topography map of the first side of the wafer based on the obtained information; converting the pre -bonding topography map into a spatial distortion map; determining a mean spatial distortion from the spatial distortion map; using the mean spatial distortion as an input to mask polygon placement correction for the mask patterns, wherein the mask polygon placement correction includes shifting mask polygons on the mask layout; and generating the corrected mask patterns based on the mask polygon placement correction.

12. The method of claim 11, wherein the spatial distortion map comprises an x-y distortion map, and wherein each feature in the mask layout depends on its x, y coordinate on the mask layout; and shifting the mask polygons includes changing the x, y coordinate for the mask polygon on the mask layout based on the spatial distortion map.

13. The method of claim 11, wherein the converting includes using a model to convert z- axis information in the pre-bonding topography map into x-axis information and y-axis information for the spatial distortion map.

14. The method of claim 13, wherein the model includes a trained machine learning model, a finite element method model, or a semi-rigorous model with mathematical formulas.

15. The method of claim 13, further comprising at least one of: calibrating the model by measuring an overlay after a second side imaging or patterning step; and calibrating the model by obtaining a grid distortion of the second side of the wafer after bonding.

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