Tracker circuit

Abstract

A power supply modulation circuit (12) comprises an input terminal (T211) that accepts a first voltage (V1), an input terminal (T212) that accepts a second voltage (V2) higher than the first voltage (V1), an output terminal (T213), an FET (M211), an FET (M212), an FET (M213), and a transformer (X211) that includes coils (X211a and X211b), wherein: the source terminal of the FET (M211) is connected to the input terminal (T211); the drain terminal of the FET (M211) is connected to the source terminal of the FET (M213) and one end of the coil (X211a); the drain terminal of the FET (M212) is connected to the input terminal (T212); the source terminal of the FET (M212) is connected to one end of the coil (X211b); and the drain terminal of the FET (M213) is connected to the other end of the coil (X211a), the other end of the coil (X211b), and the output terminal (T213).

Description

Tracker Circuit

[0001] The present invention relates to a tracker circuit.

[0002] In recent years, attempts have been made to improve power efficiency by modulating the power supply voltage supplied to a power amplifier. Patent Document 1 discloses a digital envelope tracking (D-ET) mode in which multiple discrete voltages are selectively supplied to a power amplifier based on an envelope signal. Patent Document 2 discloses a symbol power tracking (SPT) mode in which the level of the power supply voltage is modulated in units of one symbol based on the power of the symbol interval. In such D-ET and SPT modes, an output switching stage and a switch circuit (hereinafter referred to as a supply modulator circuit) are used to modulate the power supply voltage.

[0003] U.S. Patent No. 9,755,672 U.S. Patent No. 1,0686,407

[0004] However, in the above-described conventional technology, reverse conduction may occur in the switch in the power supply modulation circuit when it is in the OFF state.

[0005] Therefore, the present invention provides a tracker circuit that can suppress reverse conduction in a power supply modulation circuit.

[0006] A tracker circuit according to one aspect of the present invention comprises: a multilevel converter circuit configured to output two or more discrete voltages; and a first power supply modulation circuit configured to selectively output a plurality of discrete voltages including the two or more discrete voltages, wherein the first power supply modulation circuit comprises: a first input terminal for receiving a first voltage included in the two or more discrete voltages; a second input terminal for receiving a second voltage included in the two or more discrete voltages, the second voltage being higher than the first voltage; a first output terminal; a first FET, a second FET, a third FET; and a first transformer including a first coil and a second coil, wherein a source terminal of the first FET is connected to the first input terminal, a drain terminal of the first FET is connected to a source terminal of the third FET and one end of the first coil, a drain terminal of the second FET is connected to the second input terminal, a source terminal of the second FET is connected to one end of the second coil, and a drain terminal of the third FET is connected to the other end of the first coil, the other end of the second coil, and the first output terminal.

[0007] A tracker circuit according to one aspect of the present invention comprises: a multilevel converter circuit configured to output two or more discrete voltages; and a first power supply modulation circuit configured to selectively output a plurality of discrete voltages including the two or more discrete voltages, wherein the first power supply modulation circuit comprises: a first input terminal for receiving a first voltage included in the two or more discrete voltages; a second input terminal for receiving a second voltage included in the two or more discrete voltages, the second voltage being higher than the first voltage; a first output terminal; a first FET, a second FET, a third FET; and a first transformer including a first coil and a second coil, wherein a source terminal of the first FET is connected to the first input terminal, a drain terminal of the first FET is connected to one end of the first coil, a drain terminal of the second FET is connected to the second input terminal, a source terminal of the second FET is connected to the drain terminal of the third FET and one end of the second coil, and a source terminal of the third FET is connected to the other end of the first coil, the other end of the second coil, and the first output terminal.

[0008] According to the present invention, reverse conduction in the power supply modulation circuit can be suppressed.

[0009] FIG. 1A is a graph showing an example of a transition of a power supply voltage in APT (Average Power Tracking) mode. FIG. 1B is a graph showing an example of a transition of a power supply voltage in A-ET (Analog Envelope Tracking) mode. FIG. 1C is a graph showing an example of a transition of a power supply voltage in D-ET mode and SPT mode. FIG. 2A is a diagram showing frames, subframes, slots, and symbols. FIG. 2B is a diagram showing an example of a transition of a power supply voltage in SPT mode. FIG. 3 is a circuit configuration diagram of a communication device according to a first embodiment. FIG. 4 is a circuit configuration diagram of a multilevel converter circuit according to the first embodiment. FIG. 5 is a circuit configuration diagram of a power supply modulation circuit according to the first embodiment. FIG. 6 is a diagram for explaining a first mode of the power supply modulation circuit according to the first embodiment. FIG. 7 is a diagram for explaining a second mode of the power supply modulation circuit according to the first embodiment. FIG. 8 is a diagram for explaining a third mode of the power supply modulation circuit according to the first embodiment. FIG. 9 is a circuit configuration diagram of a power supply modulation circuit according to a comparative example. FIG. 10 is a circuit configuration diagram of a multilevel converter circuit according to a modification of the first embodiment. Fig. 11 is a circuit configuration diagram of a power supply modulation circuit according to a modification of embodiment 1. Fig. 12 is a circuit configuration diagram of a communication device according to embodiment 2. Fig. 13 is a circuit configuration diagram of a power supply modulation circuit according to embodiment 2. Fig. 14 is a circuit configuration diagram of a power supply modulation circuit according to a modification of embodiment 2. Fig. 15 is a circuit configuration diagram of a communication device according to embodiment 3. Fig. 16 is a circuit configuration diagram of a power supply modulation circuit according to embodiment 3. Fig. 17 is a circuit configuration diagram of a power supply modulation circuit according to a modification of embodiment 3.

[0010] As a technology for highly efficient amplification of high-frequency signals, a tracking mode is described below, in which a power supply voltage that is dynamically adjusted over time based on the high-frequency signal is supplied to a power amplifier. The tracking mode is a mode in which the power supply voltage applied to the power amplifier is dynamically adjusted. There are several types of tracking modes, but here, the average power tracking (APT) mode, analog envelope tracking (A-ET) mode, D-ET mode, and SPT mode are described.

[0011] First, the APT mode, A-ET mode, and D-ET mode will be explained with reference to Figures 1A, 1B, and 1C. In Figures 1A, 1B, and 1C, the horizontal axis represents time and the vertical axis represents voltage. The thick solid line represents the power supply voltage, and the thin solid line (waveform) represents the modulation signal.

[0012] 1A is a graph showing an example of the transition of the power supply voltage in the APT mode, which is a mode in which the power supply voltage is varied to a plurality of discrete voltage levels in units of one frame based on the average power.

[0013] A frame is a unit that constitutes a high-frequency signal (modulated signal). For example, in 5GNR (5th Generation New Radio) and LTE (Long Term Evolution), a frame includes 10 subframes, each subframe includes multiple slots, and each slot includes multiple symbols. The subframe length is 1 millisecond, and the frame length is 10 milliseconds.

[0014] In addition, the APT mode may include a mode in which the voltage level is varied in units larger than one frame based on the average power, and may also include a mode in which the voltage level is varied in units smaller than one frame (e.g., subframe or slot units) based on the average power.

[0015] 1B is a graph showing an example of the transition of the power supply voltage in the A-ET mode. The A-ET mode is a mode in which the power supply voltage is continuously varied based on the envelope signal. In the A-ET mode, the power supply voltage can track the envelope of the modulating signal.

[0016] The envelope signal is a signal that indicates the envelope of the modulated signal. The envelope value is, for example, (I ２ +Q ２) where (I, Q) represents a constellation point. A constellation point is a point that represents a digitally modulated signal on a constellation diagram. (I, Q) is determined, for example, by a Baseband Integrated Circuit (BBIC) based on the transmitted information.

[0017] 1C is a graph showing an example of the transition of the power supply voltage in the D-ET mode and the SPT mode. The D-ET mode is a mode in which the power supply voltage is varied to a plurality of discrete voltage levels within one frame based on an envelope signal. In the D-ET mode, the power supply voltage can track the envelope of the modulating signal, and the power supply voltage level varies at shorter time intervals than in the APT mode.

[0018] The SPT mode is a mode in which the level of the power supply voltage is modulated in units of one symbol based on the power of the symbol interval. In other words, in the SPT mode, the level of the power supply voltage can be changed in units of one symbol.

[0019] The SPT mode will now be further described with reference to Figures 2A and 2B. Figure 2A is a diagram showing frames, subframes, slots, and symbols. Figure 2B is a diagram showing changes in the power supply voltage level in the SPT mode. Note that Figures 2A and 2B show the relationship between frames, subframes, slots, and symbols in 5G NR and LTE.

[0020] As shown in Fig. 2A, a frame is a unit of a high-frequency signal having a length of 10 milliseconds and includes 10 subframes. A subframe is a unit of a high-frequency signal having a length of 1 millisecond and includes 2 slots. A slot is a unit of a high-frequency signal having a length of 0.5 milliseconds and includes 6 symbols. A symbol is a unit of a high-frequency signal having a length of 71 microseconds and includes a cyclic prefix (CP).

[0021] As shown in Figure 2B, in SPT mode, the level of the power supply voltage is modulated in units of one symbol. At this time, the voltage level is changed in the CP section. For example, in symbol "1", the voltage level is changed to a higher voltage level in the CP, and in symbol "2", the voltage level is changed to a lower voltage level in the CP. Note that the voltage level does not have to be changed, as in symbol "5". The level of the power supply voltage can be modulated based on the data signal in each symbol section.

[0022] Below, embodiments of a tracker circuit that can be used in D-ET mode and SPT mode will be described in detail with reference to the drawings. Note that the embodiments described below all represent comprehensive or specific examples. The numerical values, shapes, materials, components, component arrangements, and connection forms shown in the following embodiments are merely examples and are not intended to limit the present invention.

[0023] It should be noted that the drawings are schematic diagrams in which emphasis, omission, or adjustment of proportions has been appropriately made to illustrate the present invention, and are not necessarily strictly illustrated, and may differ from the actual shapes, positional relationships, and proportions. In the drawings, the same reference numerals are used to denote substantially the same components, and redundant explanations may be omitted or simplified.

[0024] In the following description, "connected" includes not only direct connection by a connection terminal and / or wiring conductor, but also electrical connection via other circuit elements. "C is connected between A and B" means that one end of C is connected to A and the other end of C is connected to B, and C is arranged in series on the path connecting A and B. "Path connecting A and B" means a path made up of a conductor electrically connecting A to B. "Directly connected" means direct connection by a connection terminal and / or wiring conductor without going through other circuit elements.

[0025] "A is switchably connected to B" means that the connection and disconnection between A and B can be switched, and that A is connected to B via a switch. Note that "A is connected to B" includes "A is switchably connected to B."

[0026] "Terminal" means a point at which a conductor within a circuit element terminates, and is to be construed as any point on or the entire conductor between circuit elements, not just a single point, provided the impedance of the conductor between circuit elements is sufficiently low.

[0027] "Node" means a point between circuit elements, and is understood to mean any point on a conductor between circuit elements or the entire conductor, not just a single point, if the impedance of the conductor between the circuit elements is sufficiently low.

[0028] Terms indicating the relationship between elements, such as "parallel" and "perpendicular," terms indicating the shape of elements, such as "straight line," and numerical ranges do not only express strict meanings, but also include substantially equivalent ranges, for example, including an error of about several percent.

[0029] (First embodiment) A communication device 6 according to a first embodiment will be described with reference to Fig. 3. Fig. 3 is a circuit configuration diagram of the communication device 6 according to this embodiment.

[0030] 3 is an exemplary circuit diagram, and communication device 6 may be implemented using any of a wide variety of circuit implementations and circuit technologies. Therefore, the descriptions of communication device 6, radio frequency circuit 3, and tracker circuit 1 provided below should not be construed as limiting.

[0031] [1.1. Communication Device 6] First, the communication device 6 will be described with reference to FIG. 3 . The communication device 6 according to this embodiment can be used to provide wireless connectivity. For example, the communication device 6 can be implemented in user equipment (UE) in a cellular network, such as a mobile phone, a smartphone, a tablet computer, or a wearable device. In another example, the communication device 6 can provide wireless connectivity to Internet of Things (IoT) sensor devices, medical / healthcare devices, cars, unmanned aerial vehicles (UAVs) (so-called drones), and automated guided vehicles (AGVs). In yet another example, the communication device 6 can provide wireless connectivity in a wireless access point or a wireless hotspot. Furthermore, the communication device 6 can be implemented in a base station (BS).

[0032] The communication device 6 includes a tracker circuit 1 , an antenna 2 , a high-frequency circuit 3 , an RFIC (Radio Frequency Integrated Circuit) 4 , and a BBIC 5 .

[0033] The tracker circuit 1 can supply a power supply voltage (Vcc) to the power amplifier 32. Details of the tracker circuit 1 will be described later.

[0034] The antenna 2 is connected to the high-frequency circuit 3. The antenna 2 can receive a high-frequency signal from the high-frequency circuit 3 and transmit it to the outside of the communication device 6. Furthermore, the antenna 2 may receive a high-frequency signal from the outside of the communication device 6 and supply it to the high-frequency circuit 3. The antenna 2 does not have to be included in the communication device 6. Furthermore, the communication device 6 may include one or more antennas in addition to the antenna 2.

[0035] The high-frequency circuit 3 is connected between the antenna 2 and the RFIC 4. The high-frequency circuit 3 can transmit high-frequency signals between the antenna 2 and the RFIC 4. Details of the high-frequency circuit 3 will be described later.

[0036] The RFIC 4 is an example of a signal processing circuit that processes high-frequency signals. Specifically, the RFIC 4 can perform signal processing on a transmission signal input from the BBIC 5 by up-conversion or the like, and output the high-frequency transmission signal generated by the signal processing to the high-frequency circuit 3. Furthermore, the RFIC 4 can perform signal processing on a high-frequency reception signal input via the reception path of the high-frequency circuit 3 by down-conversion or the like, and output the reception signal generated by the signal processing to the BBIC 5. The RFIC 4 can also have a control unit that controls switches, power amplifiers, and the like included in the high-frequency circuit 3. Note that some or all of the functions of the RFIC 4 as a control unit may be included outside the RFIC 4, and may be included in, for example, the BBIC 5 and / or the high-frequency circuit 3.

[0037] The BBIC 5 is a baseband signal processing circuit that processes signals using a frequency band lower than the high-frequency signals transmitted by the high-frequency circuit 3. The signals processed by the BBIC 5 include, for example, image signals for image display and / or audio signals for calls via a speaker. Note that part or all of the BBIC 5 may not be included in the communication device 6.

[0038] 3, the high-frequency circuit 3 will be described. The high-frequency circuit 3 includes a high-frequency input terminal 31, a power amplifier 32, a switch circuit 33, filters 34 and 35, a switch circuit 36, and an antenna connection terminal 37.

[0039] The radio frequency input terminal 31 is an external connection terminal of the radio frequency circuit 3. The radio frequency input terminal 31 is connected to the RFIC 4 outside the radio frequency circuit 3, and is connected to the input end of the power amplifier 32 inside the radio frequency circuit 3.

[0040] The power amplifier 32 is connected between the radio frequency input terminal 31 and the switch circuit 33, and is also connected to the tracker circuit 1. Specifically, the input terminal of the power amplifier 32 is connected to the radio frequency input terminal 31, and the output terminal of the power amplifier 32 is connected to the common terminal 330 of the switch circuit 33 and the tracker circuit 1.

[0041] The switch circuit 33 includes a common terminal 330 and selection terminals 331 and 332. The common terminal 330 is connected to the output terminal of the power amplifier 32. The selection terminals 331 and 332 are connected to the filters 34 and 35, respectively. In this connection configuration, the switch circuit 33 can selectively connect the common terminal 330 to the selection terminals 331 and 332 based on, for example, a control signal from the RFIC 4. The switch circuit 33 is configured, for example, as an SPDT (Single-Pole Double-Throw) type switch circuit.

[0042] The filter 34 is a band-pass filter having a pass band that includes the transmission band of band A. The filter 34 is connected between the switch circuits 33 and 36. Specifically, one end of the filter 34 is connected to a selection terminal 331 of the switch circuit 33, and the other end of the filter 34 is connected to a selection terminal 361 of the switch circuit 36.

[0043] The filter 35 is a band-pass filter having a pass band that includes the transmission band of band B. The filter 35 is connected between the switch circuits 33 and 36. Specifically, one end of the filter 35 is connected to the selection terminal 332 of the switch circuit 33, and the other end of the filter 35 is connected to the selection terminal 362 of the switch circuit 36.

[0044] Bands A and B are frequency bands for communication systems built using radio access technology (RAT), and are defined in advance by standardization organizations (e.g., 3GPP (registered trademark) (3rd Generation Partnership Project) and IEEE (Institute of Electrical and Electronics Engineers)). Examples of communication systems include 5GNR (5th Generation New Radio) systems, LTE (Long Term Evolution) systems, and WLAN (Wireless Local Area Network) systems.

[0045] The switch circuit 36 ​​includes a common terminal 360 and selection terminals 361 and 362. The common terminal 360 is connected to the antenna connection terminal 37. The selection terminals 361 and 362 are connected to the filters 34 and 35, respectively. In this connection configuration, the switch circuit 36 ​​can selectively connect the common terminal 360 to the selection terminals 361 and 362 based on, for example, a control signal from the RFIC 4. The switch circuit 36 ​​is configured as, for example, an SPDT type switch circuit.

[0046] The high frequency circuit 3 only needs to include at least the power amplifier 32, and does not necessarily have to include the switch circuits 33 and 36 and the filters 34 and 35.

[0047] 3 and 4, the tracker circuit 1 will be described. The tracker circuit 1 includes a multilevel converter circuit (MLC) 11, a power supply modulation circuit (SM) 12, and digital control circuits (DCTL) 13 and 14.

[0048] [1.3.1. Multilevel Converter Circuit 11] First, the multilevel converter circuit 11 will be described with reference to Fig. 4. Fig. 4 is a circuit configuration diagram of the multilevel converter circuit 11 according to this embodiment.

[0049] 4 is an exemplary circuit diagram, and the multilevel converter circuit 11 may be implemented using any of a wide variety of circuit implementations and circuit technologies. Therefore, the description of the multilevel converter circuit 11 provided below should not be construed as limiting.

[0050] The multilevel converter circuit 11 can simultaneously output two or more discrete voltages. Specifically, the multilevel converter circuit 11 can convert an input voltage (Vbat) supplied from a DC power supply (not shown) into a first voltage (V1) and a second voltage (V2) having different levels. Here, the second voltage (V2) is higher than the first voltage (V1) (V1<V2). As shown in FIG. 4 , the multilevel converter circuit 11 includes a buck-boost converter circuit 111 and a buck converter circuit 112.

[0051] [1.3.1.1. Buck-Boost Converter Circuit 111] The buck-boost converter circuit 111 will now be described with reference to FIG. 4. The buck-boost converter circuit 111 can convert the input voltage (Vbat) to a second voltage (V2) by stepping up and down the input voltage (Vbat). The buck-boost converter circuit 111 can adjust the level of the second voltage (V2) based on a control signal CS11 supplied from the digital control circuit 13. The second voltage (V2) is supplied to the power supply modulation circuit 12.

[0052] As shown in FIG. 4, the buck-boost converter circuit 111 includes an input terminal T111, an output terminal T112, switches S111, S112, S113, and S114, a power inductor L111, and capacitors C111 and C112.

[0053] The input terminal T111 is a terminal for receiving an input voltage (Vbat). The input terminal T111 is connected to a DC power supply (not shown) outside the multilevel converter circuit 11, and is connected to a switch S111 inside the multilevel converter circuit 11.

[0054] The output terminal T112 is a terminal for supplying a second voltage (V2) to the power supply modulation circuit 12. The output terminal T112 is connected to the power supply modulation circuit 12 outside the multilevel converter circuit 11, and is connected to the switch S113 inside the multilevel converter circuit 11.

[0055] The power inductor L111 is an inductor used to step up and step down the input voltage (Vbat). One end of the power inductor L111 is connected to the switches S111 and S112, and the other end of the power inductor L111 is connected to the switches S113 and S114.

[0056] The switch S111 is connected between the input terminal T111 and one end of the power inductor L111. In this connection configuration, the switch S111 can switch between connection and disconnection between the input terminal T111 and one end of the power inductor L111 by switching between opening and closing.

[0057] The switch S112 is connected between one end of the power inductor L111 and the ground. In this connection configuration, the switch S112 can switch between connecting and disconnecting the one end of the power inductor L111 and the ground by switching between opening and closing.

[0058] The switch S113 is connected between the other end of the power inductor L111 and the output terminal T112. In this connection configuration, the switch S113 can switch between connecting and disconnecting the other end of the power inductor L111 and the output terminal T112 by switching between opening and closing.

[0059] The switch S114 is connected between the other end of the power inductor L111 and the ground. In this connection configuration, the switch S114 can switch between connecting and disconnecting the other end of the power inductor L111 and the ground by switching between opening and closing.

[0060] The capacitor C111 is connected between the path between the input terminal T111 and the switch S111 and ground. Specifically, one of the two electrodes of the capacitor C111 is connected to the input terminal T111 and the switch S111, and the other of the two electrodes of the capacitor C111 is connected to ground.

[0061] The capacitor C112 is connected between the path between the switch S113 and the output terminal T112 and ground. Specifically, one of the two electrodes of the capacitor C112 is connected to the switch S113 and the output terminal T112, and the other of the two electrodes of the capacitor C112 is connected to ground.

[0062] 4 is an example and is not limiting. For example, some of the switches S111 to S114 may be replaced with diodes. Also, some or all of the buck-boost converter circuit 111 may not be included in the multilevel converter circuit 11. Note that the multilevel converter circuit 11 may include a buck converter circuit or a boost converter circuit instead of the buck-boost converter circuit 111.

[0063] [1.3.1.2. Buck Converter Circuit 112] Next, the buck converter circuit 112 will be described with reference to FIG. 4. The buck converter circuit 112 can convert the input voltage (Vbat) to a first voltage (V1) lower than a second voltage (V2) by stepping down the input voltage (Vbat). The buck converter circuit 112 can adjust the level of the first voltage (V1) based on a control signal CS11 supplied from the digital control circuit 13. The first voltage (V1) is supplied to the power supply modulation circuit 12.

[0064] As shown in FIG. 4, the buck converter circuit 112 includes an input terminal T121, an output terminal T122, switches S121 and S122, a power inductor L121, and capacitors C121 and C122.

[0065] The input terminal T121 is a terminal for receiving an input voltage (Vbat). The input terminal T121 is connected to a DC power supply (not shown) outside the multilevel converter circuit 11, and is connected to a switch S121 inside the multilevel converter circuit 11.

[0066] The output terminal T122 is a terminal for supplying a first voltage (V1) to the power supply modulation circuit 12. The output terminal T122 is connected to the power supply modulation circuit 12 outside the multilevel converter circuit 11, and is connected to the power inductor L121 inside the multilevel converter circuit 11.

[0067] The power inductor L121 is an inductor used to step down the input voltage (Vbat). One end of the power inductor L121 is connected to the switches S121 and S122, and the other end of the power inductor L121 is connected to the output terminal T122.

[0068] The switch S121 is connected between the input terminal T121 and one end of the power inductor L121. In this connection configuration, the switch S121 can switch between connection and disconnection between the input terminal T121 and one end of the power inductor L121 by switching between opening and closing.

[0069] The switch S122 is connected between one end of the power inductor L121 and the ground. In this connection configuration, the switch S122 can switch between connecting and disconnecting the one end of the power inductor L121 and the ground by switching between opening and closing.

[0070] The capacitor C121 is connected between the path between the input terminal T121 and the switch S121 and ground. Specifically, one of the two electrodes of the capacitor C121 is connected to the input terminal T121 and the switch S121, and the other of the two electrodes of the capacitor C121 is connected to ground.

[0071] The capacitor C122 is connected between the path between the power inductor L121 and the output terminal T122 and ground. Specifically, one of the two electrodes of the capacitor C122 is connected to the other end of the power inductor L121 and the output terminal T122, and the other of the two electrodes of the capacitor C122 is connected to ground.

[0072] 4 is merely an example and is not limiting. For example, some of the switches S121 and S122 may be replaced with diodes. Furthermore, some or all of the buck converter circuit 112 may not be included in the multilevel converter circuit 11. The multilevel converter circuit 11 may include a buck-boost converter circuit or a boost converter circuit instead of the buck converter circuit 112.

[0073] [1.3.2. Power supply modulation circuit 12] Next, the power supply modulation circuit 12 will be described with reference to Fig. 5. Fig. 5 is a circuit configuration diagram of the power supply modulation circuit 12 according to this embodiment.

[0074] 5 is an exemplary circuit diagram, and power supply modulation circuit 12 may be implemented using any of a wide variety of circuit implementations and circuit technologies, and therefore the description of power supply modulation circuit 12 provided below should not be construed as limiting.

[0075] The power supply modulation circuit 12 is an example of a first power supply modulation circuit, and can selectively output a plurality of discrete voltages (V1, V2, V3) including a first voltage (V1) and a second voltage (V2) supplied from the multilevel converter circuit 11. The power supply modulation circuit 12 can switch between the first voltage (V1), the second voltage (V2), and the third voltage (V3) based on a control signal CS12 supplied from the digital control circuit 14, and supply the voltage to the power amplifier 32 as a power supply voltage (Vcc). Here, the third voltage (V3) is higher than the first voltage (V1) and lower than the second voltage (V2) (V1<V3<V2).

[0076] As shown in FIG. 5, the power supply modulation circuit 12 includes input terminals T211 and T212, an output terminal T213, field effect transistors (FETs) M211, M212, and M213, and a transformer X211.

[0077] The input terminal T211 is an example of a first input terminal, and is a terminal for receiving a first voltage (V1) from the multilevel converter circuit 11. The input terminal T211 is connected to the output terminal T122 of the multilevel converter circuit 11 outside the power supply modulation circuit 12, and is connected to the FET M211 inside the power supply modulation circuit 12.

[0078] The input terminal T212 is an example of a second input terminal, and is a terminal for receiving a second voltage (V2) higher than the first voltage (V1) from the multilevel converter circuit 11. The input terminal T212 is connected to the output terminal T112 of the multilevel converter circuit 11 outside the power supply modulation circuit 12, and is connected to the FET M212 inside the power supply modulation circuit 12.

[0079] The output terminal T213 is an example of a first output terminal. The output terminal T213 is connected to the power amplifier 32 outside the power supply modulation circuit 12, and is connected to the FET M213 and the transformer X211 inside the power supply modulation circuit 12.

[0080] The FET M211 is an example of a first FET. The source terminal of the FET M211 is connected to the input terminal T211. The drain terminal of the FET M211 is connected to the source terminal of the FET M213 and one end of the coil X211a of the transformer X211.

[0081] The FET M212 is an example of a second FET. The drain terminal of the FET M212 is connected to the input terminal T212. The source terminal of the FET M212 is connected to one end of the coil X211b of the transformer X211.

[0082] The FET M213 is an example of a third FET. The drain terminal of the FET M213 is connected to the other end of the coil X211a, the other end of the coil X211b, and the output terminal T213. The source terminal of the FET M213 is connected to the drain terminal of the FET M211 and one end of the coil X211a.

[0083] The FETs M211, M212 and M213 are controlled in accordance with a control signal CS12 supplied from the digital control circuit 14.

[0084] In this embodiment, N-channel MOSFETs (Metal-Oxide-Semiconductor Field Effect Transistors) are used as the FETs M211, M212, and M213, but the FETs M211, M212, and M213 are not limited to N-channel MOSFETs. For example, some or all of the FETs M211, M212, and M213 may be P-channel MOSFETs.

[0085] The transformer X211 is an example of a first transformer and includes coils X211a and X211b. The coil X211a is an example of a first coil, and the coil X211b is an example of a second coil. The coil X211a can be magnetically coupled to the coil X211b. In this embodiment, the coupling coefficient between the coil X211a and the coil X211b is 1. Furthermore, the ratio of the number of turns of the coil X211a to the number of turns of the coil X211b is 1:1. Note that the coupling coefficient is not limited to 1, and the turn ratio is not limited to 1:1.

[0086] One end of the coil X211a is connected to the drain terminal of the FET M211 and the source terminal of the FET M213. The other end of the coil X211a is connected to the other end of the coil X211b, the drain terminal of the FET M213, and the output terminal T213.

[0087] One end of the coil X211b is connected to the source terminal of the FET M212. The other end of the coil X211b is connected to the other end of the coil X211a, the drain terminal of the FET M213, and the output terminal T213.

[0088] [1.3.3. Digital Control Circuits 13 and 14] The digital control circuit 13 processes a digital control signal based on a serial data transmission standard supplied from the RFIC 4, and can generate a control signal CS11 for controlling the multilevel converter circuit 11. In this embodiment, a source synchronous digital control signal (a clock signal (CLK) and a data signal (DATA)) is used as the digital control signal based on the serial data transmission standard. Note that a clock-embedded digital control signal may also be used as the digital control signal based on the serial data transmission standard.

[0089] In the D-ET mode or the SPT mode, the digital control circuit 14 processes a digital control signal based on a parallel data transmission standard supplied from the RFIC 4, and can generate a control signal CS12 for controlling the FETs M211, M212, and M213 included in the power supply modulation circuit 12. In this embodiment, a digital control level (DCL) signal is used as the digital control signal based on the parallel data transmission standard. As a result, the FETs M211, M212, and M213 are controlled based on the DCL signal.

[0090] The DCL signal is a bit signal generated based on the envelope signal or the power of a symbol interval of the high frequency signal amplified by the power amplifier 32. Each of the first voltage (V1), the second voltage (V2), and the third voltage (V3) is represented by a combination of two bit signals. For example, the first voltage (V1), the second voltage (V2), and the third voltage (V3) are represented as "01," "10," and "11," respectively. Note that a Gray code may be used to represent the voltage levels.

[0091] [1.4. Multiple Output Modes of Power Supply Modulation Circuit 12] Next, multiple output modes of the power supply modulation circuit 12 will be described.

[0092] [1.4.1. First Mode] First, the first mode included in the multiple output modes will be described with reference to Fig. 6. Fig. 6 is a diagram showing the first mode of the power supply modulation circuit 12 according to this embodiment. In the following figures, dashed arrows represent the supply path of the power supply voltage.

[0093] The first mode is a mode for outputting a first voltage (V1). In the first mode, FET M211 is turned on, FET M212 is turned off, and FET M213 is turned on.

[0094] As a result, the first voltage (V1) is output without passing through the transformer X211. Note that in the off-state FET M212, the drain potential (V2) is higher than the source potential (V1), so reverse conduction does not occur. Note that, when a MOSFET or the like is used as a switch, when the drain potential is lower than the source potential in the off-state switch, drain-source conduction occurs via the body diode.

[0095] [1.4.2. Second Mode] Next, the second mode included in the plurality of output modes will be described with reference to Fig. 7. Fig. 7 is a diagram showing the second mode of the power supply modulation circuit 12 according to this embodiment.

[0096] The second mode is a mode for outputting a second voltage (V2). In the second mode, FET M211 is turned off, FET M212 is turned on, and FET M213 is turned on.

[0097] As a result, the second voltage (V2) is output via the transformer X211. In this embodiment, the coupling coefficient of the transformer X211 is 1 and the turns ratio is 1:1, so the current flowing through the coil X211a is equal to the current flowing through the coil X211b, and the voltage across the coil X211b is equal to the voltage across the coil X211a. When the FET M213 is turned on, the voltages across both the coils X211a and X211b become 0 V. Therefore, the output voltage of the power supply modulation circuit 12 becomes equal to the second voltage (V2).

[0098] In the OFF state of FET M211, the drain potential (V2) is higher than the source potential (V1), so reverse conduction does not occur.

[0099] [1.4.3. Third Mode] Next, the third mode included in the plurality of output modes will be described with reference to Fig. 8. Fig. 8 is a diagram showing the third mode of the power supply modulation circuit 12 according to this embodiment.

[0100] The third mode is a mode for outputting a third voltage (V3) that is higher than the first voltage (V1) and lower than the second voltage (V2). In the third mode, FET M211 is turned on, FET M212 is turned on, and FET M213 is turned off.

[0101] As a result, a third voltage (V3) is output via the transformer X211. In this embodiment, the coupling coefficient of the transformer X211 is 1 and the turns ratio is 1:1, so the current flowing through the coil X211a is equal to the current flowing through the coil X211b, and the voltage across the coil X211b is equal to the voltage across the coil X211a. Therefore, the third voltage (V3) is higher than the first voltage (V1) and lower than the second voltage (V2), and is equal to (V1 + V2) / 2.

[0102] In the OFF state of FET M213, the drain potential (V3) is higher than the source potential (V1), so reverse conduction does not occur.

[0103] The output voltages and FET states in the first, second and third modes are summarized in Table 1 below.

[0104]

[0105] For example, if the first voltage (V1) is 20V and the second voltage (V2) is 40V, the output voltage (Vcc) is 20V, 40V, and 30V in the first, second, and third modes, respectively.

[0106] [1.5. Number of FETs] Next, the number of FETs included in the power supply modulation circuit 12 according to the present embodiment will be described while comparing it with the number of FETs included in a power supply modulation circuit 12X according to a comparative example. Fig. 9 is a circuit configuration diagram of the power supply modulation circuit 12X according to the comparative example.

[0107] The power supply modulation circuit 12X includes FETs M211X, M212X, M213X, and M214X. The FET M211X is connected between an input terminal T211X and an output terminal T214X. The FET M212X is connected between an input terminal T212X and an output terminal T214X. The FETs M213X and M214X are connected between the input terminal T213X and the output terminal T214X.

[0108] When the first voltage (V1) is output, FET M211X is turned on, and FETs M212X and M214X are turned off. At this time, in FET M212X, the drain potential (V2) is higher than the source potential (V1), so reverse conduction does not occur. In FET M214X, the drain potential (V3) is higher than the source potential (V1), so reverse conduction does not occur. Conversely, even if FET M213X is turned off, the source potential (V3) becomes higher than the drain potential (V1), so reverse conduction occurs in FET M213X.

[0109] When the second voltage (V2) is output, FET M212X is turned on, and FETs M211X and M213X are turned off. At this time, in FET M211X, the drain potential (V2) is higher than the source potential (V1), so reverse conduction does not occur. In FET M213X, the drain potential (V2) is higher than the source potential (V3), so reverse conduction does not occur. Conversely, even if FET M214X is turned off, the source potential (V3) becomes higher than the drain potential (V2), so reverse conduction occurs in FET M214X.

[0110] When the third voltage (V3) is output, FETs M213X and M214X are turned on, and FETs M211X and M212X are turned off. At this time, in FET M211X, the drain potential (V3) is higher than the source potential (V1), so reverse conduction does not occur. In FET M212X, the drain potential (V2) is higher than the source potential (V3), so reverse conduction does not occur.

[0111] In this way, in the power supply modulation circuit 12X according to the comparative example, the relationship between the potential levels of the input terminal T213X and the output terminal T214X is reversed when the first voltage (V1) is output and when the second voltage (V2) is output, so two FETs M213X and M214X are required to prevent reverse conduction, and therefore the number of FETs included in the power supply modulation circuit 12X is four.

[0112] On the other hand, in the power supply modulation circuit 12 according to the present embodiment, as described above, reverse conduction can be suppressed by the three FETs M211, M212, and M213. Therefore, the number of FETs included in the power supply modulation circuit 12 according to the present embodiment can be reduced compared to the power supply modulation circuit 12X according to the comparative example. When a high withstand voltage is required for the FETs, the size of the FETs becomes larger than the size of the transformer, which is effective in reducing the size of the power supply modulation circuit 12. For example, when the maximum output voltage of the power supply modulation circuit 12 is 5 V or higher, the power supply modulation circuit 12 can be made smaller than the power supply modulation circuit 12X. In particular, when the maximum output voltage of the power supply modulation circuit 12 is 50 V or higher, the effect of reducing the size of the power supply modulation circuit 12 is significant, and when the maximum output voltage of the power supply modulation circuit 12 is 100 V or higher, the effect of reducing the size of the power supply modulation circuit 12 is significant.

[0113] [1.6. Summary] As described above, the tracker circuit 1 according to this embodiment includes the multilevel converter circuit 11 configured to output two or more discrete voltages, and the power supply modulation circuit 12 configured to selectively output a plurality of discrete voltages including the two or more discrete voltages, and the power supply modulation circuit 12 includes an input terminal T211 that receives a first voltage (V1) included in the two or more discrete voltages, an input terminal T212 that receives a second voltage (V2) included in the two or more discrete voltages and that is higher than the first voltage (V1), an output terminal T213, an FET M211, and an FET M212. The transformer X211 includes a FET M212, a FET M213, and a transformer X211 including coils X211 a and X211 b, the source terminal of the FET M211 is connected to the input terminal T211, the drain terminal of the FET M211 is connected to the source terminal of the FET M213 and one end of the coil X211 a, the drain terminal of the FET M212 is connected to the input terminal T212, the source terminal of the FET M212 is connected to one end of the coil X211 b, and the drain terminal of the FET M213 is connected to the other end of the coil X211 a, the other end of the coil X211 b, and the output terminal T213.

[0114] This allows the drain potential of an FET in the off-state in the power supply modulation circuit 12 to be higher than the source potential of the FET, regardless of which of the three discrete voltages (V1, V2, V3) is output, thereby suppressing reverse conduction of the FET. Furthermore, the power supply modulation circuit 12 can output three discrete voltages (V1, V2, V3) in response to two discrete voltages (V1, V2). This reduces the number of output voltages required for the multilevel converter circuit 11, contributing to a more compact multilevel converter circuit 11. Furthermore, since there is no need to increase the number of FETs to suppress reverse conduction, the number of FETs can be reduced. When a high withstand voltage is required for the FETs, the size of the FETs becomes larger than the size of the transformer, contributing to a more compact power supply modulation circuit 12.

[0115] Furthermore, for example, in the tracker circuit 1 according to this embodiment, the FETs M211, M212, and M213 may be controlled based on the DCL signal.

[0116] This allows high-speed control of the FETs M211, M212 and M213, and is suitable for the D-ET mode and SPT mode.

[0117] For example, in the tracker circuit 1 according to this embodiment, in a first mode for outputting a first voltage (V1), FET M211 may be turned on, FET M212 may be turned off, and FET M213 may be turned on; in a second mode for outputting a second voltage (V2), FET M211 may be turned off, FET M212 may be turned on, and FET M213 may be turned on; and in a third mode for outputting a third voltage (V3) that is higher than the first voltage (V1) and lower than the second voltage (V2), FET M211 may be turned on, FET M212 may be turned on, and FET M213 may be turned off.

[0118] This allows the drain potential of an FET in the off state in the power supply modulation circuit 12 to be made higher than the source potential of the FET in any mode that outputs any of the three discrete voltages (V1, V2, V3), thereby suppressing reverse conduction of the FET.

[0119] (Variation of First Embodiment) Next, a variation of the first embodiment will be described. In this variation, the main differences from the first embodiment are the configuration of the multilevel converter circuit and the configuration of the power supply modulation circuit. Below, the tracker circuit according to this variation will be described with reference to the drawings, focusing on the differences from the first embodiment.

[0120] The tracker circuit 1 according to this modification includes a multilevel converter circuit 11A and a power supply modulation circuit 12A instead of the multilevel converter circuit 11 and the power supply modulation circuit 12. The multilevel converter circuit 11A and the power supply modulation circuit 12A according to this modification will be described below in order.

[0121] [1.7. Multilevel Converter Circuit 11A] First, the multilevel converter circuit 11A according to this modification will be described with reference to Fig. 10. Fig. 10 is a circuit configuration diagram of the multilevel converter circuit 11A according to this modification.

[0122] 10 is an exemplary circuit diagram, and the multilevel converter circuit 11A may be implemented using any of a wide variety of circuit implementations and circuit technologies, and therefore the description of the multilevel converter circuit 11A provided below should not be construed as limiting.

[0123] The multilevel converter circuit 11A can simultaneously output a plurality of discrete voltages based on a control signal CS11A supplied from the digital control circuit 13. Specifically, the multilevel converter circuit 11A can convert an input voltage (Vbat) supplied from a DC power supply (not shown) into a first voltage (V1) and a second voltage (V2) having different levels. Here, the second voltage (V2) is higher than the first voltage (V1).

[0124] 10, the multilevel converter circuit 11A includes a buck-boost converter circuit 111 and a switched capacitor circuit 113. Note that the buck-boost converter circuit 111 is the same as that in the first embodiment, so its description will be omitted and the switched capacitor circuit 113 will be described below.

[0125] The switched capacitor circuit 113 can generate a first voltage (V1) and a second voltage (V2) based on the voltage supplied from the buck-boost converter circuit 111. The switched capacitor circuit 113 is controlled in accordance with a control signal CS11A supplied from the digital control circuit 13.

[0126] The switched capacitor circuit 113 includes flying capacitors C130 and C131, smoothing capacitors C132 and C133, switches S130 to S137, an input terminal T130, and output terminals T131 and T132. Energy and charge are input from the buck-boost converter circuit 111 to a node N1 via the input terminal T130, and are extracted from the nodes N1 and N2 to the power supply modulation circuit 12A via the output terminals T131 and T132.

[0127] The input terminal T130 is a terminal that receives a regulated voltage from the buck-boost converter circuit 111. The input terminal T130 is connected to the output terminal T112 of the buck-boost converter circuit 111 outside the switched capacitor circuit 113, and is connected to a node N1 inside the switched capacitor circuit 113. Note that the node to which the input terminal T130 is connected is not limited to the node N1. The input terminal T130 may also be connected to a node N2.

[0128] The output terminals T131 and T132 are terminals that supply a first voltage (V1) and a second voltage (V2), respectively, to the power supply modulation circuit 12A. The output terminals T131 and T132 are connected to the power supply modulation circuit 12A outside the switched capacitor circuit 113, and are connected to nodes N1 and N2 inside the switched capacitor circuit 113, respectively.

[0129] Flying capacitors C130 and C131, sometimes referred to as transfer capacitors, are used to boost and / or lower the regulated voltage supplied from the buck-boost converter circuit 111. More specifically, flying capacitors C130 and C131 transfer charge between nodes N1 and N2 and ground so that V1 and V2 at two nodes N1 and N2 are maintained such that (V2-V1):(V1-VG)=1:1 and V2>V1>VG. Here, VG represents ground potential. Note that (V2-V1):(V1-VG) is not limited to 1:1 and can be designed to have any ratio (e.g., 1:2 or 2:1).

[0130] One of the two electrodes of the flying capacitor C130 is connected to one end of the switch S130 and one end of the switch S131. The other of the two electrodes of the flying capacitor C130 is connected to one end of the switch S134 and one end of the switch S135.

[0131] One of the two electrodes of the flying capacitor C131 is connected to one end of the switch S132 and one end of the switch S133. The other of the two electrodes of the flying capacitor C131 is connected to one end of the switch S136 and one end of the switch S137.

[0132] Smoothing capacitors C132 and C133 are used to hold and smooth the first voltage (V1) and second voltage (V2) at nodes N1 and N2.

[0133] The smoothing capacitor C132 is connected between the node N1 and the ground. Specifically, one of the two electrodes of the smoothing capacitor C132 is connected to the node N1. Meanwhile, the other of the two electrodes of the smoothing capacitor C132 is connected to the ground.

[0134] The smoothing capacitor C133 is connected between the nodes N1 and N2. Specifically, one of the two electrodes of the smoothing capacitor C133 is connected to the node N2. Meanwhile, the other of the two electrodes of the smoothing capacitor C133 is connected to the node N1.

[0135] The switch S130 is connected between the flying capacitor C130 and ground. Specifically, one end of the switch S130 is connected to one of the two electrodes of the flying capacitor C130. Meanwhile, the other end of the switch S130 is connected to ground.

[0136] The switch S131 is connected between the flying capacitor C130 and the node N1. Specifically, one end of the switch S131 is connected to one of the two electrodes of the flying capacitor C130. On the other hand, the other end of the switch S131 is connected to the node N1.

[0137] The switch S132 is connected between the flying capacitor C131 and ground. Specifically, one end of the switch S132 is connected to one of the two electrodes of the flying capacitor C131. On the other hand, the other end of the switch S132 is connected to ground.

[0138] The switch S133 is connected between the flying capacitor C131 and the node N1. Specifically, one end of the switch S133 is connected to one of the two electrodes of the flying capacitor C131. On the other hand, the other end of the switch S133 is connected to the node N1.

[0139] The switch S134 is connected between the flying capacitor C130 and the node N1. Specifically, one end of the switch S134 is connected to the other of the two electrodes of the flying capacitor C130. Meanwhile, the other end of the switch S134 is connected to the node N1.

[0140] The switch S135 is connected between the flying capacitor C130 and the node N2. Specifically, one end of the switch S135 is connected to the other of the two electrodes of the flying capacitor C130. Meanwhile, the other end of the switch S135 is connected to the node N2.

[0141] The switch S136 is connected between the flying capacitor C131 and the node N1. Specifically, one end of the switch S136 is connected to the other of the two electrodes of the flying capacitor C131. Meanwhile, the other end of the switch S136 is connected to the node N1.

[0142] The switch S137 is connected between the flying capacitor C131 and a node N2. Specifically, one end of the switch S137 is connected to the other of the two electrodes of the flying capacitor C131. On the other hand, the other end of the switch S137 is connected to the node N2.

[0143] A first set of switches including switches S130, S133, S134 and S137 and a second set of switches including switches S131, S132, S135 and S136 are switched between open and closed states inversely to each other based on a control signal CS11A from the digital control circuit 13.

[0144] Specifically, in the first phase, a first set of switches is closed and a second set of switches is opened, so that one of the two electrodes of flying capacitor C130 is connected to ground. The other of the two electrodes of flying capacitor C130 and one of the two electrodes of flying capacitor C131 are connected to node N1. The other of the two electrodes of flying capacitor C131 is connected to node N2.

[0145] Conversely, in the second phase, the first set of switches are opened and the second set of switches are closed, thereby connecting one of the two electrodes of flying capacitor C131 to ground. One of the two electrodes of flying capacitor C130 and the other of the two electrodes of flying capacitor C131 are connected to node N1. The other of the two electrodes of flying capacitor C130 is connected to node N2.

[0146] By repeating the first and second phases, the flying capacitors C130 and C131 can be charged and discharged in a complementary manner. For example, during one of the first and second phases, the flying capacitor C130 charges the smoothing capacitors C132 and C133, and during the other of the first and second phases, the flying capacitor C131 charges the smoothing capacitors C132 and C133. In other words, the smoothing capacitors C132 and C133 are always charged by either the flying capacitors C130 or C131. Therefore, even if a current flows from either the node N1 or N2 to the power supply modulation circuit 12A at high speed, charge is quickly replenished to either the node N1 or N2, thereby suppressing fluctuations in the potential of the nodes N1 and N2.

[0147] By operating in this manner, the switched capacitor circuit 113 can maintain approximately equal voltages across the smoothing capacitors C132 and C133. Specifically, at two nodes N1 and N2 labeled V1 and V2, V1 and V2 are maintained such that (V2-V1):(V1-VG)=1:1 and V2>V1>VG. For example, if the regulated voltage supplied from the buck-boost converter circuit 111 is 20V, the switched capacitor circuit 113 can generate (V1, V2) of (20V, 40V).

[0148] [1.8. Power supply modulation circuit 12A] Next, the power supply modulation circuit 12A according to this modification will be described with reference to Fig. 11. Fig. 11 is a circuit configuration diagram of the power supply modulation circuit 12A according to this modification.

[0149] 11 is an example circuit diagram, and power supply modulation circuit 12A may be implemented using any of a wide variety of circuit implementations and circuit technologies, and therefore the description of power supply modulation circuit 12A provided below should not be construed as limiting.

[0150] The power supply modulation circuit 12A is an example of a first power supply modulation circuit, and can selectively output a plurality of discrete voltages (V1, V2, V3) including a first voltage (V1) and a second voltage (V2) supplied from the multilevel converter circuit 11A. The power supply modulation circuit 12A can switch between the plurality of discrete voltages (V1, V2, V3) and supply them to the power amplifier 32 as a power supply voltage (Vcc) based on a control signal CS12A supplied from the digital control circuit 14.

[0151] As shown in FIG. 11, the power supply modulation circuit 12A includes input terminals T211 and T212, an output terminal T213, FETs M211, M212, and M213A, and a transformer X211.

[0152] The FET M213A is an example of a third FET. The drain terminal of the FET M213A is connected to the source terminal of the FET M212 and one end of the coil X211b. The source terminal of the FET M213A is connected to the other end of the coil X211a, the other end of the coil X211b, and the output terminal T213.

[0153] The FETs M211, M212, and M213A are controlled in accordance with a control signal CS12A supplied from the digital control circuit 14. In other words, the FETs M211, M212, and M213A are controlled based on the DCL signal.

[0154] In this modification, N-channel MOSFETs are used as the FETs M211, M212, and M213A, but the FETs M211, M212, and M213A are not limited to N-channel MOSFETs. For example, some or all of the FETs M211, M212, and M213A may be P-channel MOSFETs.

[0155] [1.9. Multiple Output Modes of Power Supply Modulation Circuit 12A] Next, multiple output modes of the power supply modulation circuit 12A according to this modification will be described. Similar to the power supply modulation circuit 12 according to the first embodiment, the multiple output modes of the power supply modulation circuit 12A include a first mode, a second mode, and a third mode. The output voltages and FET states in the first mode, the second mode, and the third mode are summarized in Table 2 below.

[0156]

[0157] [1.10. Summary] As described above, the tracker circuit 1 according to this modification includes a multilevel converter circuit 11A configured to output two or more discrete voltages, and a power supply modulation circuit 12A configured to selectively output a plurality of discrete voltages including two or more discrete voltages, and the power supply modulation circuit 12A includes an input terminal T211 that receives a first voltage (V1) included in the two or more discrete voltages, an input terminal T212 that receives a second voltage (V2) included in the two or more discrete voltages and that is higher than the first voltage (V1), an output terminal T213, an FET M211, and an FET The transformer X211 includes a FET M212, a FET M213A, and a transformer X211 including coils X211a and X211b, the source terminal of the FET M211 is connected to the input terminal T211, the drain terminal of the FET M211 is connected to one end of the coil X211a, the drain terminal of the FET M212 is connected to the input terminal T212, the source terminal of the FET M212 is connected to the drain terminal of the FET M213A and one end of the coil X211b, and the source terminal of the FET M213A is connected to the other end of the coil X211a, the other end of the coil X211b, and the output terminal T213.

[0158] This allows the drain potential of the FET in the off-state in the power supply modulation circuit 12A to be higher than the source potential of the FET, regardless of which of the three discrete voltages (V1, V2, V3) is output, thereby suppressing reverse conduction of the FET. Furthermore, the power supply modulation circuit 12A can output three discrete voltages (V1, V2, V3) in response to two discrete voltages (V1, V2) as input. This reduces the number of output voltages required for the multilevel converter circuit 11A, contributing to a smaller size of the multilevel converter circuit 11A. Furthermore, since there is no need to increase the number of FETs to suppress reverse conduction, the number of FETs can also be reduced. When a high withstand voltage is required for the FETs, the size of the FETs becomes larger than the size of the transformer, contributing to a smaller size of the power supply modulation circuit 12A.

[0159] Furthermore, for example, in the tracker circuit 1 according to this modification, the FETs M211, M212, and M213A may be controlled based on the DCL signal.

[0160] This allows high-speed control of FETs M211, M212 and M213A, and is suitable for the D-ET mode and SPT mode.

[0161] Also, for example, in the tracker circuit 1 according to this modified example, in a first mode for outputting a first voltage (V1), FET M211 may be turned on, FET M212 may be turned off, and FET M213A may be turned on; in a second mode for outputting a second voltage (V2), FET M211 may be turned off, FET M212 may be turned on, and FET M213A may be turned on; and in a third mode for outputting a third voltage (V3) that is higher than the first voltage (V1) and lower than the second voltage (V2), FET M211 may be turned on, FET M212 may be turned on, and FET M213A may be turned off.

[0162] This allows the drain potential of an FET in the off state in the power supply modulation circuit 12A to be made higher than the source potential of the FET in question, regardless of the mode in which any of the three discrete voltages (V1, V2, V3) is output, thereby suppressing reverse conduction of the FET.

[0163] (Embodiment 2) Next, embodiment 2 will be described. In this embodiment, the main difference is that two power supply modulation circuits are included in the tracker circuit. The following describes this embodiment with reference to the drawings, focusing on the differences from embodiment 1.

[0164] The communication device 6A is similar to the communication device 6 except that it includes a tracker circuit 1A instead of the tracker circuit 1, so the tracker circuit 1A will be described below with reference to Figures 12 and 13. Figure 12 is a circuit configuration diagram of the communication device 6A according to this embodiment. Figure 13 is a circuit configuration diagram of the power supply modulation circuits 12 and 12B according to this embodiment.

[0165] 12 and 13 are exemplary circuit diagrams, and tracker circuit 1A may be implemented using any of a wide variety of circuit implementations and circuit technologies, and therefore the description of tracker circuit 1A provided below should not be construed as limiting.

[0166] [2.1. Tracker Circuit 1A] The tracker circuit 1A includes a multilevel converter circuit (MLC) 11B, power supply modulation circuits (SM) 12 and 12B, and digital control circuits (DCTL) 13 and 14. The multilevel converter circuit 11B can output three discrete voltages (V1, V2, V4) based on a control signal CS11B supplied from the digital control circuit 13. The first voltage (V1) is higher than the fourth voltage (V4) and lower than the second voltage (V2) (V4<V1<V2). For example, the multilevel converter circuit 11B may include a new buck converter circuit or a buck-boost converter circuit in addition to the buck-boost converter circuit 111 and the buck converter circuit 112. Alternatively, the multilevel converter circuit 11B may include a switched capacitor circuit having more stages than the switched capacitor circuit 113, instead of the switched capacitor circuit 113.

[0167] The power supply modulation circuit 12B is an example of a second power supply modulation circuit, and can selectively output a plurality of discrete voltages (V1, V2, V3, V4, V5, V6, V7) based on the first voltage (V1), the second voltage (V2), and the third voltage (V3) supplied from the power supply modulation circuit 12 and the fourth voltage (V4) supplied from the multilevel converter circuit 11B. The power supply modulation circuit 12B can switch between the plurality of discrete voltages (V1, V2, V3, V4, V5, V6, V7) and supply them to the power amplifier 32 as a power supply voltage (Vcc) in accordance with a control signal CS12B supplied from the digital control circuit 14.

[0168] As shown in FIG. 13, the power supply modulation circuit 12B includes input terminals T214 and T215, an output terminal T216, FETs M214, M215 and M216, and a transformer X212.

[0169] The input terminal T214 is an example of a third input terminal, and is a terminal for receiving a fourth voltage (V4) lower than the first voltage (V1) from the multilevel converter circuit 11B. The input terminal T214 is connected to the multilevel converter circuit 11B outside the power supply modulation circuit 12B, and is connected to the FET M214 inside the power supply modulation circuit 12B.

[0170] The input terminal T215 is an example of a fourth input terminal, and is a terminal for receiving a voltage from the power supply modulation circuit 12. The input terminal T215 is connected to the output terminal T213 of the power supply modulation circuit 12B outside the power supply modulation circuit 12B, and is connected to the FET M215 inside the power supply modulation circuit 12B.

[0171] The output terminal T216 is an example of a second output terminal. The output terminal T216 is connected to the power amplifier 32 outside the power supply modulation circuit 12B, and is connected to the FET M216 and the transformer X212 inside the power supply modulation circuit 12B.

[0172] The FET M214 is an example of a fourth FET. The source terminal of the FET M214 is connected to the input terminal T214. The drain terminal of the FET M214 is connected to the source terminal of the FET M216 and one end of the coil X212a of the transformer X212.

[0173] The FET M215 is an example of a fifth FET. The drain terminal of the FET M215 is connected to the input terminal T215. The source terminal of the FET M215 is connected to one end of the coil X212b of the transformer X212.

[0174] The FET M216 is an example of a sixth FET. The drain terminal of the FET M216 is connected to the other end of the coil X212a, the other end of the coil X212b, and the output terminal T216. The source terminal of the FET M216 is connected to the drain terminal of the FET M214 and one end of the coil X212a.

[0175] The FETs M214, M215, and M216 are controlled in accordance with a control signal CS12B supplied from the digital control circuit 14. In other words, the FETs M214, M215, and M216 are controlled based on the DCL signal.

[0176] In this embodiment, N-channel MOSFETs are used as the FETs M214, M215, and M216, but the FETs M214, M215, and M216 are not limited to N-channel MOSFETs. For example, some or all of the FETs M214, M215, and M216 may be P-channel MOSFETs.

[0177] The transformer X212 is an example of a second transformer and includes coils X212a and X212b. The coil X212a is an example of a third coil, and the coil X212b is an example of a fourth coil. The coil X212a can be magnetically coupled to the coil X212b. In this embodiment, the coupling coefficient between the coil X212a and the coil X212b is 1. Furthermore, the ratio of the number of turns of the coil X212a to the number of turns of the coil X212b is 1:1. Note that the coupling coefficient is not limited to 1, and the turn ratio is not limited to 1:1.

[0178] One end of the coil X212a is connected to the drain terminal of the FET M214 and the source terminal of the FET M216. The other end of the coil X212a is connected to the other end of the coil X212b, the drain terminal of the FET M216, and the output terminal T216.

[0179] One end of the coil X212b is connected to the source terminal of the FET M215. The other end of the coil X212b is connected to the other end of the coil X212a, the drain terminal of the FET M216, and the output terminal T216.

[0180] [2.2. Multiple Output Modes of Power Supply Modulation Circuits 12 and 12B] Next, a description will be given of multiple output modes of the power supply modulation circuits 12 and 12B according to this modification. The multiple output modes of the power supply modulation circuits 12 and 12B include a first mode, a second mode, a third mode, a fourth mode, a fifth mode, a sixth mode, and a seventh mode.

[0181] The first mode is a mode for outputting a first voltage (V1). The second mode is a mode for outputting a second voltage (V2). The third mode is a mode for outputting a third voltage (V3) that is higher than the first voltage (V1) and lower than the second voltage (V2). The fourth mode is a mode for outputting a fourth voltage (V4). The fifth mode is a mode for outputting a fifth voltage (V5) that is higher than the fourth voltage (V4) and lower than the first voltage (V1). The sixth mode is a mode for outputting a sixth voltage (V6) that is higher than the fourth voltage (V4) and lower than the second voltage (V2). The seventh mode is a mode for outputting a seventh voltage (V7) that is higher than the fourth voltage (V4) and lower than the third voltage (V3).

[0182] The output voltages and FET states in the first to seventh modes are summarized in Table 3 below.

[0183]

[0184] For example, if the first voltage (V1) is 30 V, the second voltage (V2) is 40 V, and the fourth voltage (V4) is 10 V, the output voltage (Vcc) will be 30 V, 40 V, 35 V, 10 V, 20 V, 25 V, and 22.5 V in the first to seventh modes, respectively.

[0185] [2.3. Summary] As described above, the tracker circuit 1A according to this embodiment may further include a power supply modulation circuit 12B. The power supply modulation circuit 12B includes an input terminal T214 that receives a fourth voltage (V4) that is included in two or more discrete voltages and is lower than the first voltage (V1), an input terminal T215 that is connected to the output terminal T213 of the power supply modulation circuit 12, an output terminal T216, FETs M214, M215, and M216, and a transformer X211 that includes coils X212a and X212b. 2, the source terminal of FET M214 may be connected to input terminal T214, the drain terminal of FET M214 may be connected to the source terminal of FET M216 and one end of coil X212a, the drain terminal of FET M215 may be connected to input terminal T215, the source terminal of FET M215 may be connected to one end of coil X212b, and the drain terminal of FET M216 may be connected to the other end of coil X212a, the other end of coil X212b, and output terminal T216.

[0186] This allows the drain potential of the FET in the off-state in the power supply modulation circuits 12 and 12B to be higher than the source potential of the FET, regardless of which of the seven discrete voltages (V1, V2, V3, V4, V5, V6, and V7) is output, thereby suppressing reverse conduction of the FET. Furthermore, by connecting two power supply modulation circuits 12 and 12B in series, seven discrete voltages (V1, V2, V3, V4, V5, V6, and V7) can be output in response to an input of three discrete voltages (V1, V2, and V4). This reduces the number of output voltages required for the multilevel converter circuit 11B, contributing to a smaller size of the multilevel converter circuit 11B. Furthermore, since there is no need to increase the number of FETs to suppress reverse conduction, the number of FETs can be reduced. When a high withstand voltage is required for the FETs, the size of the FETs becomes larger than the size of the transformer, contributing to a smaller size of the power supply modulation circuits 12 and 12B.

[0187] Furthermore, for example, in the tracker circuit 1A according to this embodiment, the FETs M211, M212, M213, M214, M215, and M216 may be controlled based on the DCL signal.

[0188] This allows high speed control of FETs M211, M212, M213, M214, M215 and M216, and is suitable for the D-ET mode and SPT mode.

[0189] Also, for example, in the tracker circuit 1A according to the present embodiment, in a first mode for outputting a first voltage (V1), FETM211 may be turned on, FETM212 may be turned off, FETM213 may be turned on, FETM214 may be turned off, FETM215 may be turned on, and FETM216 may be turned on, and in a second mode for outputting a second voltage (V2), FETM211 may be turned off, FETM212 may be turned on, FETM213 may be turned on, and FETM214 may be turned off, and FETM215 may be turned on. In a third mode for outputting a third voltage (V3) higher than the first voltage (V1) and lower than the second voltage (V2), FET M211 is turned on, FET M212 is turned on, FET M213 is turned off, FET M214 is turned off, FET M215 is turned on, and FET M216 may be turned on; in a fourth mode for outputting a fourth voltage (V4), FET M214 is turned on, and FET M215 is turned off. FET M211 may be turned on, FET M212 may be turned off, FET M213 may be turned on, FET M214 may be turned on, FET M215 may be turned on, and FET M216 may be turned off in a fifth mode for outputting a fifth voltage (V5) that is higher than the fourth voltage (V4) and lower than the first voltage (V1). In a sixth mode for outputting a sixth voltage (V6) that is higher than the fourth voltage (V4) and lower than the second voltage (V2), FET M211 may be turned on, FET M212 may be turned off, FET M213 may be turned on, FET M214 may be turned on, FET M215 may be turned on, and FET M216 may be turned off. In a seventh mode for outputting a seventh voltage (V7) that is higher than the fourth voltage (V4) and lower than the third voltage (V3), FET M211 may be turned on, FET M212 may be turned on, FET M213 may be turned off, FET M214 may be turned on, FET M215 may be turned on, and FET M216 may be turned off.

[0190] According to this, in any mode that outputs any of the seven discrete voltages (V1, V2, V3, V4, V5, V6, V7), the drain potential of the FET in the off state in the power supply modulation circuits 12 and 12B can be made higher than the source potential of the FET, thereby suppressing reverse conduction of the FET.

[0191] (Variation of Embodiment 2) Next, a variation of embodiment 2 will be described. In this variation, the main difference from embodiment 2 is the configuration of the power supply modulation circuit. Below, the tracker circuit according to this variation will be described with reference to the drawings, focusing on the differences from embodiment 2.

[0192] The tracker circuit 1A according to this modification includes power supply modulation circuits 12A and 12C instead of the power supply modulation circuits 12 and 12B. The power supply modulation circuit 12C according to this modification will be described below.

[0193] [2.4. Power Supply Modulation Circuit 12C] FIG. 14 is a circuit configuration diagram of the power supply modulation circuits 12A and 12C according to this modification.

[0194] 14 is an exemplary circuit diagram, and power supply modulation circuit 12C may be implemented using any of a wide variety of circuit implementations and circuit technologies, and therefore the description of power supply modulation circuit 12C provided below should not be construed as limiting.

[0195] The power supply modulation circuit 12C is an example of a second power supply modulation circuit, and can selectively output a plurality of discrete voltages (V1, V2, V3, V4, V5, V6, V7) based on the first voltage (V1), the second voltage (V2), and the third voltage (V3) supplied from the power supply modulation circuit 12A and the fourth voltage (V4) supplied from the multilevel converter circuit 11B. The power supply modulation circuit 12C can switch among the plurality of discrete voltages (V1, V2, V3, V4, V5, V6, V7) and supply them to the power amplifier 32 as a power supply voltage (Vcc) in accordance with a control signal CS12C supplied from the digital control circuit 14.

[0196] As shown in FIG. 14, the power supply modulation circuit 12C includes input terminals T214 and T215, an output terminal T216, FETs M214, M215 and M216A, and a transformer X212.

[0197] The input terminal T214 is an example of a third input terminal, and is a terminal for receiving a fourth voltage (V4) lower than the first voltage (V1) from the multilevel converter circuit 11B. The input terminal T214 is connected to the multilevel converter circuit 11B outside the power supply modulation circuit 12C, and is connected to the FET M214 inside the power supply modulation circuit 12C.

[0198] The input terminal T215 is an example of a fourth input terminal, and is a terminal for receiving a voltage from the power supply modulation circuit 12 A. The input terminal T215 is connected to the output terminal T213 of the power supply modulation circuit 12 A outside the power supply modulation circuit 12 C, and is connected to the FET M215 inside the power supply modulation circuit 12 C.

[0199] The output terminal T216 is an example of a second output terminal. The output terminal T216 is connected to the power amplifier 32 outside the power supply modulation circuit 12C, and is connected to the FET M216A and the transformer X212 inside the power supply modulation circuit 12C.

[0200] The FET M214 is an example of a fourth FET. The source terminal of the FET M214 is connected to the input terminal T214. The drain terminal of the FET M214 is connected to one end of the coil X212a of the transformer X212.

[0201] The FET M215 is an example of a fifth FET. The drain terminal of the FET M215 is connected to the input terminal T215. The source terminal of the FET M215 is connected to the drain terminal of the FET M216A and one end of the coil X212b of the transformer X212.

[0202] The FET M216A is an example of a sixth FET. The source terminal of the FET M216A is connected to the other end of the coil X212a, the other end of the coil X212b, and the output terminal T216. The drain terminal of the FET M216A is connected to the source terminal of the FET M215 and one end of the coil X212b.

[0203] The FETs M214, M215, and M216A are controlled in accordance with a control signal CS12C supplied from the digital control circuit 14. In other words, the FETs M214, M215, and M216A are controlled based on the DCL signal.

[0204] In this modification, N-channel MOSFETs are used as the FETs M214, M215, and M216A, but the FETs M214, M215, and M216A are not limited to N-channel MOSFETs. For example, some or all of the FETs M214, M215, and M216A may be P-channel MOSFETs.

[0205] The transformer X212 is an example of a second transformer and includes coils X212a and X212b. The coil X212a is an example of a third coil, and the coil X212b is an example of a fourth coil. The coil X212a can be magnetically coupled to the coil X212b. In this modification, the coupling coefficient between the coil X212a and the coil X212b is 1. Furthermore, the ratio of the number of turns of the coil X212a to the number of turns of the coil X212b is 1:1. Note that the coupling coefficient is not limited to 1, and the turn ratio is not limited to 1:1.

[0206] One end of the coil X212a is connected to the drain terminal of the FET M214. The other end of the coil X212a is connected to the other end of the coil X212b, the source terminal of the FET M216A, and the output terminal T216.

[0207] One end of the coil X212b is connected to the source of the FET M215 and the drain of the FET M216A, and the other end of the coil X212b is connected to the other end of the coil X212a, the source of the FET M216A, and the output terminal T216.

[0208] [2.5. Multiple Output Modes of Power Supply Modulation Circuits 12A and 12C] Next, the multiple output modes of the power supply modulation circuits 12A and 12C according to this modification will be described. The multiple output modes of the power supply modulation circuits 12A and 12C include a first mode, a second mode, a third mode, a fourth mode, a fifth mode, a sixth mode, and a seventh mode, similar to the power supply modulation circuits 12 and 12B according to the second embodiment. The output voltages and the states of the FETs in the first to seventh modes are summarized in Table 4 below.

[0209]

[0210] [2.6. Summary] As described above, the tracker circuit 1A according to this modification may further include a power supply modulation circuit 12C, which includes an input terminal T214 that receives a fourth voltage (V4) that is included in two or more discrete voltages and is lower than the first voltage, an input terminal T215 that is connected to the output terminal T213 of the power supply modulation circuit 12A, an output terminal T216, FETs M214, FETs M215, FETs M216A, a transformer X212 that includes coils X212a and X212b, The source terminal of FET M214 may be connected to input terminal T214, the drain terminal of FET M214 may be connected to one end of coil X212a, the drain terminal of FET M215 may be connected to input terminal T215, the source terminal of FET M215 may be connected to the drain terminal of FET M216A and one end of coil X212b, and the source terminal of FET M216A may be connected to the other end of coil X212a, the other end of coil X212b, and output terminal T216.

[0211] This allows the drain potential of the FET in the off-state in the power supply modulation circuits 12A and 12C to be higher than the source potential of the FET, regardless of which of the seven discrete voltages (V1, V2, V3, V4, V5, V6, and V7) is output, thereby suppressing reverse conduction of the FET. Furthermore, by connecting the two power supply modulation circuits 12A and 12C in series, seven discrete voltages (V1, V2, V3, V4, V5, V6, and V7) can be output in response to an input of three discrete voltages (V1, V2, and V4). This reduces the number of output voltages required for the multilevel converter circuit 11B, contributing to a smaller size of the multilevel converter circuit 11B. Furthermore, since it is not necessary to increase the number of FETs to suppress reverse conduction, the number of FETs can be reduced. When a high withstand voltage is required for the FETs, the size of the FETs becomes larger than the size of the transformer, contributing to a smaller size of the power supply modulation circuits 12A and 12C.

[0212] Furthermore, for example, in the tracker circuit 1A according to this modification, the FETs M211, M212, M213A, M214, M215, and M216A may be controlled based on the DCL signal.

[0213] This allows high speed control of FETs M211, M212, M213A, M214, M215 and M216A, and is suitable for the D-ET mode and SPT mode.

[0214] Also, for example, in the tracker circuit 1A according to this modification, in a first mode for outputting a first voltage (V1), FET M211 may be turned on, FET M212 may be turned off, FET M213A may be turned on, FET M214 may be turned off, FET M215 may be turned on, and FET M216A may be turned on; in a second mode for outputting a second voltage (V2), FET M211 may be turned off, FET M212 may be turned on, FET M213A may be turned on, FET M214 may be turned off, and FET M216A may be turned on. In a third mode for outputting a third voltage (V3) higher than the first voltage (V1) and lower than the second voltage (V2), FET M211 is turned on, FET M212 is turned on, FET M213A is turned off, FET M214 is turned off, FET M215 is turned on, and FET M216A may be turned on; in a fourth mode for outputting a fourth voltage (V4), FET M214 is turned on, FET M215 is turned off, and FET M216A may be turned on. FET M211 may be turned on, FET M212 may be turned off, FET M213A may be turned on, FET M214 may be turned on, FET M215 may be turned on, and FET M216A may be turned off in a fifth mode to output a fifth voltage (V5) that is higher than the fourth voltage (V4) and lower than the first voltage (V1). In a sixth mode to output a sixth voltage (V6) that is higher than the fourth voltage (V4) and lower than the second voltage (V2), FET M211 may be turned on, FET M212 may be turned off, FET M213A may be turned on, FET M214 may be turned on, FET M215 may be turned on, and FET M216A may be turned off. In a seventh mode for outputting a seventh voltage (V7) that is higher than the fourth voltage (V4) and lower than the third voltage (V3), FET M211 may be turned on, FET M212 may be turned on, FET M213A may be turned on, FET M214 may be turned on, FET M215 may be turned on, and FET M216A may be turned off.

[0215] According to this, in any mode that outputs any of the seven discrete voltages (V1, V2, V3, V4, V5, V6, V7), the drain potential of the FET in the off state in the power supply modulation circuits 12A and 12C can be made higher than the source potential of the FET, thereby suppressing reverse conduction of the FET.

[0216] (Embodiment 3) Next, embodiment 3 will be described. In this embodiment, the configuration and connection form of the two power supply modulation circuits are mainly different from embodiment 2. The tracker circuit according to this embodiment will be described below with reference to the drawings, focusing on the differences from embodiment 2.

[0217] Note that communication device 6B is similar to communication device 6A except that it includes tracker circuit 1B instead of tracker circuit 1A, so tracker circuit 1B will be described below with reference to Figures 15 and 16. Figure 15 is a circuit configuration diagram of communication device 6B according to this embodiment. Figure 16 is a circuit configuration diagram of power supply modulation circuits 12D and 12E according to this embodiment.

[0218] 15 and 16 are exemplary circuit diagrams, and tracker circuit 1B may be implemented using any of a wide variety of circuit implementations and circuit technologies, and therefore the description of tracker circuit 1B provided below should not be construed as limiting.

[0219] [3.1. Tracker Circuit 1B] The tracker circuit 1B includes a multilevel converter circuit (MLC) 11C, power supply modulation circuits (SM) 12D and 12E, and digital control circuits (DCTL) 13 and 14.

[0220] [3.1.1. Multilevel Converter Circuit 11C] The multilevel converter circuit 11C can output four discrete voltages (V1, V2, V4, V5). The first voltage (V1) is lower than the second voltage (V2), the second voltage (V2) is lower than the fourth voltage (V4), and the fourth voltage (V4) is lower than the fifth voltage (V5) (V1<V2<V4<V5). For example, the multilevel converter circuit 11C may include two additional buck converter circuits or buck-boost converter circuits in addition to the buck-boost converter circuit 111 and the buck converter circuit 112. Alternatively, for example, the multilevel converter circuit 11C may include a switched capacitor circuit having more stages than the switched capacitor circuit 113, instead of the switched capacitor circuit 113.

[0221] [3.1.2. Power Supply Modulation Circuit 12D] The power supply modulation circuit 12D is an example of a first power supply modulation circuit, and can selectively output a plurality of discrete voltages (V1, V2, V3) including a first voltage (V1) and a second voltage (V2) supplied from the multilevel converter circuit 11C. The power supply modulation circuit 12D can switch between the plurality of discrete voltages (V1, V2, V3) and supply them to the power amplifier 32 as a power supply voltage (Vcc) in accordance with a control signal CS12D supplied from the digital control circuit 14.

[0222] As shown in FIG. 16, the power supply modulation circuit 12D includes input terminals T211 and T212, an output terminal T213, FETs M211, M212, M213 and M214, and a transformer X211.

[0223] The input terminal T211 is an example of a first input terminal, and is a terminal for receiving a first voltage (V1) from the multilevel converter circuit 11 C. The input terminal T211 is connected to the multilevel converter circuit 11 C outside the power supply modulation circuit 12 D, and is connected to the FET M211 inside the power supply modulation circuit 12 D.

[0224] The input terminal T212 is an example of a second input terminal, and is a terminal for receiving a second voltage (V2) higher than the first voltage (V1) from the multilevel converter circuit 11C. The input terminal T212 is connected to the multilevel converter circuit 11C outside the power supply modulation circuit 12D, and is connected to the FET M212 inside the power supply modulation circuit 12D.

[0225] The output terminal T213 is an example of a first output terminal. The output terminal T213 is connected to the power amplifier 32 outside the power supply modulation circuit 12D, and is connected to the FET M214 inside the power supply modulation circuit 12D.

[0226] The FET M211 is an example of a first FET. The source terminal of the FET M211 is connected to the input terminal T211. The drain terminal of the FET M211 is connected to the source terminal of the FET M213 and one end of the coil X211a of the transformer X211.

[0227] The FET M212 is an example of a second FET. The drain terminal of the FET M212 is connected to the input terminal T212. The source terminal of the FET M212 is connected to one end of the coil X211b of the transformer X211.

[0228] The FET M213 is an example of a third FET. The drain terminal of the FET M213 is connected to the other end of the coil X211a, the other end of the coil X211b, and the source terminal of the FET M214. The source terminal of the FET M213 is connected to the drain terminal of the FET M211 and one end of the coil X211a.

[0229] The FET M214 is an example of a fourth FET. The drain terminal of the FET M214 is connected to the output terminal T213. The source terminal of the FET M214 is connected to the other end of the coil X211a, the other end of the coil X211b, and the drain terminal of the FET M213.

[0230] The FETs M211, M212, M213, and M214 are controlled in accordance with a control signal CS12D supplied from the digital control circuit 14. That is, the FETs M211, M212, M213, and M214 are controlled based on the DCL signal.

[0231] In this embodiment, N-channel MOSFETs are used as the FETs M211, M212, M213, and M214, but the FETs M211, M212, M213, and M214 are not limited to N-channel MOSFETs. For example, some or all of the FETs M211, M212, M213, and M214 may be P-channel MOSFETs.

[0232] The transformer X211 is an example of a first transformer and includes coils X211a and X211b. The coil X211a is an example of a first coil, and the coil X211b is an example of a second coil. The coil X211a can be magnetically coupled to the coil X211b. In this embodiment, the coupling coefficient between the coil X211a and the coil X211b is 1. Furthermore, the ratio of the number of turns of the coil X211a to the number of turns of the coil X211b is 1:1. Note that the coupling coefficient is not limited to 1, and the turn ratio is not limited to 1:1.

[0233] One end of the coil X211a is connected to the drain of the FET M211 and the source of the FET M213. The other end of the coil X211a is connected to the other end of the coil X211b, the drain of the FET M213, and the source of the FET M214.

[0234] One end of the coil X211b is connected to the source terminal of the FET M212. The other end of the coil X211b is connected to the other end of the coil X211a, the drain terminal of the FET M213, and the source terminal of the FET M214.

[0235] [3.1.3. Power Supply Modulation Circuit 12E] The power supply modulation circuit 12E is an example of a second power supply modulation circuit, and can selectively output a plurality of discrete voltages (V4, V5, V6) based on the fourth voltage (V4) and the fifth voltage (V5) supplied from the multilevel converter circuit 11C. The power supply modulation circuit 12E can switch between the plurality of discrete voltages (V4, V5, V6) and supply them to the power amplifier 32 as the power supply voltage (Vcc) in accordance with a control signal CS12E supplied from the digital control circuit 14.

[0236] As shown in FIG. 16, the power supply modulation circuit 12E includes input terminals T214 and T215, an output terminal T216, FETs M215, M216, M217 and M218, and a transformer X212.

[0237] The input terminal T214 is an example of a third input terminal, and is a terminal for receiving a fourth voltage (V4) higher than the second voltage (V2) from the multilevel converter circuit 11C. The input terminal T214 is connected to the multilevel converter circuit 11C outside the power supply modulation circuit 12E, and is connected to the FET M215 inside the power supply modulation circuit 12E.

[0238] The input terminal T215 is an example of a fourth input terminal, and is a terminal for receiving a fifth voltage (V5) higher than the fourth voltage (V4) from the multilevel converter circuit 11C. The input terminal T215 is connected to the multilevel converter circuit 11C outside the power supply modulation circuit 12E, and is connected to the FET M216 inside the power supply modulation circuit 12E.

[0239] The output terminal T216 is an example of a second output terminal. The output terminal T216 is connected to the power amplifier 32 outside the power supply modulation circuit 12E, and is connected to the FET M218 inside the power supply modulation circuit 12E.

[0240] The FET M215 is an example of a fifth FET. The source terminal of the FET M215 is connected to the input terminal T214. The drain terminal of the FET M215 is connected to the source terminal of the FET M217 and one end of the coil X212a of the transformer X212.

[0241] The FET M216 is an example of a sixth FET. The drain terminal of the FET M216 is connected to the input terminal T215. The source terminal of the FET M216 is connected to one end of the coil X212b of the transformer X212.

[0242] The FET M217 is an example of a seventh FET. The drain terminal of the FET M217 is connected to the other end of the coil X212a, the other end of the coil X212b, and the drain terminal of the FET M218. The source terminal of the FET M217 is connected to the drain terminal of the FET M215 and one end of the coil X212a.

[0243] The FET M218 is an example of an eighth FET. The source terminal of the FET M218 is connected to the output terminal T216. The drain terminal of the FET M218 is connected to the other end of the coil X212a, the other end of the coil X212b, and the drain terminal of the FET M217.

[0244] The FETs M215, M216, M217, and M218 are controlled in accordance with a control signal CS12E supplied from the digital control circuit 14. In other words, the FETs M215, M216, M217, and M218 are controlled based on the DCL signal.

[0245] In this embodiment, N-channel MOSFETs are used as the FETs M215, M216, M217, and M218, but the FETs M215, M216, M217, and M218 are not limited to N-channel MOSFETs. For example, some or all of the FETs M215, M216, M217, and M218 may be P-channel MOSFETs.

[0246] The transformer X212 is an example of a second transformer and includes coils X212a and X212b. The coil X212a is an example of a third coil, and the coil X212b is an example of a fourth coil. The coil X212a can be magnetically coupled to the coil X212b. In this embodiment, the coupling coefficient between the coil X212a and the coil X212b is 1. Furthermore, the ratio of the number of turns of the coil X212a to the number of turns of the coil X212b is 1:1. Note that the coupling coefficient is not limited to 1, and the turn ratio is not limited to 1:1.

[0247] One end of the coil X212a is connected to the drain of the FET M215 and the source of the FET M217. The other end of the coil X212a is connected to the other end of the coil X212b, the drain of the FET M217, and the drain of the FET M218.

[0248] One end of the coil X212b is connected to the source terminal of the FET M216. The other end of the coil X212b is connected to the other end of the coil X212a, the drain terminal of the FET M217, and the drain terminal of the FET M218.

[0249] [3.2. Multiple Output Modes of Power Supply Modulation Circuits 12D and 12E] Next, multiple output modes of the power supply modulation circuits 12D and 12E according to this modification will be described. The multiple output modes of the power supply modulation circuits 12D and 12E include a first mode, a second mode, a third mode, a fourth mode, a fifth mode, and a sixth mode.

[0250] The first mode is a mode for outputting a first voltage (V1). The second mode is a mode for outputting a second voltage (V2). The third mode is a mode for outputting a third voltage (V3) that is higher than the first voltage (V1) and lower than the second voltage (V2). The fourth mode is a mode for outputting a fourth voltage (V4). The fifth mode is a mode for outputting a fifth voltage (V5). The sixth mode is a mode for outputting a sixth voltage (V6) that is higher than the fourth voltage (V4) and lower than the fifth voltage (V5).

[0251] The output voltages and FET states in the first to sixth modes are summarized in Table 5 below.

[0252]

[0253] For example, if the first voltage (V1) is 10 V, the second voltage (V2) is 30 V, the fourth voltage (V4) is 40 V, and the fifth voltage (V5) is 60 V, the output voltage (Vcc) will be 10 V, 30 V, 20 V, 40 V, 60 V, and 50 V in the first to sixth modes, respectively.

[0254] [3.3. Summary] As described above, in the tracker circuit 1B according to this embodiment, the power supply modulation circuit 12D may further include an FET M214, the source terminal of which may be connected to the other end of the coil X211a, the other end of the coil X211b, and the drain terminal of the FET M213, and the drain terminal of the FET M214 may be connected to the output terminal T213. The tracker circuit 1B may further include a power supply modulation circuit 12E, the power supply modulation circuit 12E including an input terminal T214 that receives a fourth voltage (V4) included in two or more discrete voltages and that is higher than the second voltage (V2), an input terminal T215 that receives a fifth voltage (V5) included in the two or more discrete voltages and that is higher than the fourth voltage (V4), and an output terminal T216 that receives a fifth voltage (V5) included in the two or more discrete voltages and that is higher than the fourth voltage (V4). The power supply may include a transformer X212 including a transistor T16, a FET M215, a FET M216, a FET M217, a FET M218, and coils X212a and X212b. The source terminal of the FET M215 may be connected to the input terminal T214, the drain terminal of the FET M215 may be connected to the source terminal of the FET M217 and one end of the coil X212a, the drain terminal of the FET M216 may be connected to the input terminal T215, the source terminal of the FET M216 may be connected to one end of the coil X212b, the drain terminal of the FET M217 may be connected to the other end of the coil X212a, the other end of the coil X212b, and the drain terminal of the FET M218, and the source terminal of the FET M218 may be connected to the output terminal T216.

[0255] This allows the drain potential of the FET in the off-state in the power supply modulation circuits 12D and 12E to be higher than the source potential of the FET when outputting any of the six discrete voltages (V1, V2, V3, V4, V5, and V6), thereby suppressing reverse conduction of the FET. Furthermore, by connecting two power supply modulation circuits 12D and 12E in parallel, six discrete voltages (V1, V2, V3, V4, V5, and V6) can be output in response to four discrete voltages (V1, V2, V4, and V5). This reduces the number of output voltages required for the multilevel converter circuit 11C, contributing to a smaller size of the multilevel converter circuit 11C. Furthermore, since it is not necessary to increase the number of FETs to suppress reverse conduction, the number of FETs can be reduced. When a high withstand voltage is required for the FETs, the size of the FETs becomes larger than the size of the transformer, contributing to a smaller size of the power supply modulation circuits 12D and 12E.

[0256] Furthermore, for example, in the tracker circuit 1B according to this embodiment, the FETs M211, M212, M213, M214, M215, M216, M217, and M218 may be controlled based on the DCL signal.

[0257] This allows high speed control of FETs M211, M212, M213, M214, M215, M216, M217 and M218, and is suitable for the D-ET mode and SPT mode.

[0258] Also, for example, in the tracker circuit 1B according to the present embodiment, in a first mode for outputting a first voltage (V1), FET M211 may be turned on, FET M212 may be turned off, FET M213 may be turned on, FET M214 may be turned on, and FET M218 may be turned off; in a second mode for outputting a second voltage (V2), FET M211 may be turned off, FET M212 may be turned on, FET M213 may be turned on, FET M214 may be turned on, and FET M218 may be turned off; and in a third mode for outputting a third voltage (V3) that is higher than the first voltage (V1) and lower than the second voltage (V2), FET M211 may be turned on, FET M212 may be turned on, FET M213 may be turned off, FET M214 may be turned on, and FET M218 may be turned off. In a fourth mode for outputting a fourth voltage (V4), FET M214 may be turned off, FET M215 may be turned on, FET M216 may be turned off, FET M217 may be turned on, and FET M218 may be turned on; in a fifth mode for outputting a fifth voltage (V5), FET M214 may be turned off, FET M215 may be turned off, FET M216 may be turned on, FET M217 may be turned on, and FET M218 may be turned on; and in a sixth mode for outputting a sixth voltage (V6) that is higher than the fourth voltage (V4) and lower than the fifth voltage (V5), FET M214 may be turned off, FET M215 may be turned on, FET M216 may be turned on, FET M217 may be turned off, and FET M218 may be turned on.

[0259] According to this, in any mode that outputs any of the six discrete voltages (V1, V2, V3, V4, V5, V6), the drain potential of the FET in the off state in the power supply modulation circuits 12D and 12E can be made higher than the source potential of the FET, thereby suppressing reverse conduction of the FET.

[0260] (Variation of Embodiment 3) Next, a variation of embodiment 3 will be described. In this variation, the main difference from embodiment 3 is the configuration of the power supply modulation circuit. Below, the tracker circuit according to this variation will be described with reference to the drawings, focusing on the differences from embodiment 3.

[0261] The tracker circuit 1B according to this modification includes power supply modulation circuits 12F and 12G instead of the power supply modulation circuits 12D and 12E. The power supply modulation circuits 12F and 12G according to this modification will be described below with reference to FIG.

[0262] 17 is a circuit diagram of power supply modulation circuits 12F and 12G according to this modification. Note that FIG. 17 is an exemplary circuit diagram, and power supply modulation circuits 12F and 12G can be implemented using any of a wide variety of circuit implementations and circuit technologies. Therefore, the description of power supply modulation circuits 12F and 12G provided below should not be construed as limiting.

[0263] [3.4. Power Supply Modulation Circuit 12F] The power supply modulation circuit 12F is an example of a first power supply modulation circuit, and can selectively output a plurality of discrete voltages (V1, V2, V3) including a first voltage (V1) and a second voltage (V2) supplied from the multilevel converter circuit 11C. The power supply modulation circuit 12F can switch between the plurality of discrete voltages (V1, V2, V3) and supply them to the power amplifier 32 as a power supply voltage (Vcc) in accordance with a control signal CS12F supplied from the digital control circuit 14.

[0264] As shown in FIG. 17, the power supply modulation circuit 12F includes input terminals T211 and T212, an output terminal T213, FETs M211, M212, M213A and M214, and a transformer X211.

[0265] The input terminal T211 is an example of a first input terminal, and is a terminal for receiving a first voltage (V1) from the multilevel converter circuit 11 C. The input terminal T211 is connected to the multilevel converter circuit 11 C outside the power supply modulation circuit 12 F, and is connected to the FET M211 inside the power supply modulation circuit 12 F.

[0266] The input terminal T212 is an example of a second input terminal, and is a terminal for receiving a second voltage (V2) higher than the first voltage (V1) from the multilevel converter circuit 11C. The input terminal T212 is connected to the multilevel converter circuit 11C outside the power supply modulation circuit 12F, and is connected to the FET M212 inside the power supply modulation circuit 12F.

[0267] The output terminal T213 is an example of a first output terminal. The output terminal T213 is connected to the power amplifier 32 outside the power supply modulation circuit 12F, and is connected to the FET M214 inside the power supply modulation circuit 12F.

[0268] The FET M211 is an example of a first FET. The source terminal of the FET M211 is connected to the input terminal T211. The drain terminal of the FET M211 is connected to one end of the coil X211a of the transformer X211.

[0269] The FET M212 is an example of a second FET. The drain terminal of the FET M212 is connected to the input terminal T212. The source terminal of the FET M212 is connected to the drain terminal of the FET M213A and one end of the coil X211b of the transformer X211.

[0270] The FET M213A is an example of a third FET. The source terminal of the FET M213A is connected to the other end of the coil X211a, the other end of the coil X211b, and the source terminal of the FET M214. The drain terminal of the FET M213A is connected to the source terminal of the FET M212 and one end of the coil X211b.

[0271] The FET M214 is an example of a fourth FET. The drain terminal of the FET M214 is connected to the output terminal T213. The source terminal of the FET M214 is connected to the other end of the coil X211a, the other end of the coil X211b, and the source terminal of the FET M213A.

[0272] The FETs M211, M212, M213A, and M214 are controlled in accordance with a control signal CS12F supplied from the digital control circuit 14. In other words, the FETs M211, M212, M213A, and M214 are controlled based on the DCL signal.

[0273] In this modification, N-channel MOSFETs are used as the FETs M211, M212, M213A, and M214, but the FETs M211, M212, M213A, and M214 are not limited to N-channel MOSFETs. For example, some or all of the FETs M211, M212, M213A, and M214 may be P-channel MOSFETs.

[0274] The transformer X211 is an example of a first transformer and includes coils X211a and X211b. The coil X211a is an example of a first coil, and the coil X211b is an example of a second coil. The coil X211a can be magnetically coupled to the coil X211b. In this modification, the coupling coefficient between the coil X211a and the coil X211b is 1. Furthermore, the ratio of the number of turns of the coil X211a to the number of turns of the coil X211b is 1:1. Note that the coupling coefficient is not limited to 1, and the turn ratio is not limited to 1:1.

[0275] One end of the coil X211a is connected to the drain terminal of the FET M211. The other end of the coil X211a is connected to the other end of the coil X211b, the source terminal of the FET M213A, and the source terminal of the FET M214.

[0276] One end of the coil X211b is connected to the source of the FET M212 and the drain of the FET M213A, and the other end of the coil X211b is connected to the other end of the coil X211a, the source of the FET M213A, and the source of the FET M214.

[0277] [3.5. Power Supply Modulation Circuit 12G] The power supply modulation circuit 12G is an example of a second power supply modulation circuit, and can selectively output a plurality of discrete voltages (V4, V5, V6) including a fourth voltage (V4) and a fifth voltage (V5) supplied from the multilevel converter circuit 11C. The power supply modulation circuit 12G can switch between the plurality of discrete voltages (V4, V5, V6) and supply them to the power amplifier 32 as a power supply voltage (Vcc) in accordance with a control signal CS12G supplied from the digital control circuit 14.

[0278] As shown in FIG. 17, the power supply modulation circuit 12G includes input terminals T214 and T215, an output terminal T216, FETs M215, M216, M217A and M218, and a transformer X212.

[0279] The input terminal T214 is an example of a third input terminal, and is a terminal for receiving a fourth voltage (V4) higher than the second voltage (V2) from the multilevel converter circuit 11C. The input terminal T214 is connected to the multilevel converter circuit 11C outside the power supply modulation circuit 12G, and is connected to the FET M215 inside the power supply modulation circuit 12G.

[0280] The input terminal T215 is an example of a fourth input terminal, and is a terminal for receiving a fifth voltage (V5) higher than the fourth voltage (V4) from the multilevel converter circuit 11C. The input terminal T215 is connected to the multilevel converter circuit 11C outside the power supply modulation circuit 12G, and is connected to the FET M216 inside the power supply modulation circuit 12G.

[0281] The output terminal T216 is an example of a second output terminal. The output terminal T216 is connected to the power amplifier 32 outside the power supply modulation circuit 12G, and is connected to the FET M218 inside the power supply modulation circuit 12G.

[0282] The FET M215 is an example of a fifth FET. The source terminal of the FET M215 is connected to the input terminal T214. The drain terminal of the FET M215 is connected to one end of the coil X212a of the transformer X212.

[0283] The FET M216 is an example of a sixth FET. The drain terminal of the FET M216 is connected to the input terminal T215. The source terminal of the FET M216 is connected to the drain terminal of the FET M217A and one end of the coil X212b of the transformer X212.

[0284] The FET M217A is an example of a seventh FET. The source terminal of the FET M217A is connected to the other end of the coil X212a, the other end of the coil X212b, and the drain terminal of the FET M218. The drain terminal of the FET M217A is connected to the source terminal of the FET M216 and one end of the coil X212b.

[0285] The FET M218 is an example of an eighth FET. The source terminal of the FET M218 is connected to the output terminal T216. The drain terminal of the FET M218 is connected to the other end of the coil X212a, the other end of the coil X212b, and the source terminal of the FET M217A.

[0286] The FETs M215, M216, M217A, and M218 are controlled in accordance with a control signal CS12G supplied from the digital control circuit 14. In other words, the FETs M215, M216, M217A, and M218 are controlled based on the DCL signal.

[0287] In this modification, N-channel MOSFETs are used as the FETs M215, M216, M217A, and M218, but the FETs M215, M216, M217A, and M218 are not limited to N-channel MOSFETs. For example, some or all of the FETs M215, M216, M217A, and M218 may be P-channel MOSFETs.

[0288] The transformer X212 is an example of a second transformer and includes coils X212a and X212b. The coil X212a is an example of a third coil, and the coil X212b is an example of a fourth coil. The coil X212a can be magnetically coupled to the coil X212b. In this modification, the coupling coefficient between the coil X212a and the coil X212b is 1. Furthermore, the ratio of the number of turns of the coil X212a to the number of turns of the coil X212b is 1:1. Note that the coupling coefficient is not limited to 1, and the turn ratio is not limited to 1:1.

[0289] One end of the coil X212a is connected to the drain terminal of the FET M215. The other end of the coil X212a is connected to the other end of the coil X212b, the source terminal of the FET M217A, and the drain terminal of the FET M218.

[0290] One end of the coil X212b is connected to the source of the FET M216 and the drain of the FET M217A, and the other end of the coil X212b is connected to the other end of the coil X212a, the source of the FET M217A, and the drain of the FET M218.

[0291] [3.6. Multiple Output Modes of Power Supply Modulation Circuits 12F and 12G] Next, the multiple output modes of the power supply modulation circuits 12F and 12G according to this modification will be described. The multiple output modes of the power supply modulation circuits 12F and 12G include a first mode, a second mode, a third mode, a fourth mode, a fifth mode, and a sixth mode, similar to the power supply modulation circuits 12D and 12E according to the third embodiment. The output voltages and FET states in the first to sixth modes are summarized in Table 6 below.

[0292]

[0293] [3.7. Summary] As described above, in the tracker circuit 1B according to this modification, the power supply modulation circuit 12F may further include a FET M214, the source terminal of which may be connected to the other end of the coil X211a, the other end of the coil X211b, and the source terminal of the FET M213A, and the drain terminal of the FET M214 may be connected to the output terminal T213. The tracker circuit 1B may further include a power supply modulation circuit 12G, the power supply modulation circuit 12G having an input terminal T214 that receives a fourth voltage (V4) included in two or more discrete voltages and that is higher than the second voltage (V2), an input terminal T215 that receives a fifth voltage (V5) included in the two or more discrete voltages and that is higher than the fourth voltage (V4), and an output terminal T216. , FET M215, FET M216, FET M217A, FET M218, and a transformer X212 including coils X212a and X212b, the source terminal of FET M215 may be connected to input terminal T214, the drain terminal of FET M215 may be connected to one end of coil X212a, the drain terminal of FET M216 may be connected to input terminal T215, the source terminal of FET M216 may be connected to the drain terminal of FET M217A and one end of coil X212b, the source terminal of FET M217A may be connected to the other end of coil X212a, the other end of coil X212b, and the drain terminal of FET M218, and the source terminal of FET M218 may be connected to output terminal T216.

[0294] According to this configuration, regardless of which of the six discrete voltages (V1, V2, V3, V4, V5, and V6) is output, the drain potential of the FET in the off-state in the power supply modulation circuits 12F and 12G can be made higher than the source potential of the FET, thereby suppressing reverse conduction of the FET. Furthermore, by connecting two power supply modulation circuits 12F and 12G in parallel, six discrete voltages (V1, V2, V3, V4, V5, and V6) can be output in response to four discrete voltages (V1, V2, V4, and V5). This reduces the number of output voltages required for the multilevel converter circuit 11C, contributing to a smaller size of the multilevel converter circuit 11C. Furthermore, since it is not necessary to increase the number of FETs to suppress reverse conduction, the number of FETs can be reduced. When a high withstand voltage is required for the FETs, the size of the FETs becomes larger than the size of the transformers, contributing to a smaller size of the power supply modulation circuits 12F and 12G.

[0295] Also, for example, in the tracker circuit 1B according to this modification, the FETs M211, M212, M213A, M214, M215, M216, M217A, and M218 may be controlled based on the DCL signal.

[0296] This allows high speed control of FETs M211, M212, M213A, M214, M215, M216, M217A and M218, and is suitable for the D-ET mode and SPT mode.

[0297] Also, for example, in the tracker circuit 1B according to this modification, in a first mode for outputting a first voltage (V1), FET M211 may be turned on, FET M212 may be turned off, FET M213A may be turned on, FET M214 may be turned on, and FET M218 may be turned off; in a second mode for outputting a second voltage (V2), FET M211 may be turned off, FET M212 may be turned on, FET M213A may be turned on, FET M214 may be turned on, and FET M218 may be turned off; and in a third mode for outputting a third voltage (V3) that is higher than the first voltage (V1) and lower than the second voltage (V2), FET M211 may be turned on, FET M212 may be turned on, FET M213A may be turned off, FET M214 may be turned on, and FET M218 may be turned off. In a fourth mode for outputting a fourth voltage (V4), FET M214 may be turned off, FET M215 may be turned on, FET M216 may be turned off, FET M217A may be turned on, and FET M218 may be turned on; in a fifth mode for outputting a fifth voltage (V5), FET M214 may be turned off, FET M215 may be turned off, FET M216 may be turned on, FET M217A may be turned on, and FET M218 may be turned on; and in a sixth mode for outputting a sixth voltage (V6) that is higher than the fourth voltage (V4) and lower than the fifth voltage (V5), FET M214 may be turned off, FET M215 may be turned on, FET M216 may be turned on, FET M217A may be turned off, and FET M218 may be turned on.

[0298] According to this, in any mode that outputs any of the six discrete voltages (V1, V2, V3, V4, V5, V6), the drain potential of the FET in the off state in the power supply modulation circuits 12F and 12G can be made higher than the source potential of the FET, thereby suppressing reverse conduction of the FET.

[0299] Other Embodiments The tracker circuit according to the present invention has been described above based on the embodiments, but the tracker circuit according to the present invention is not limited to the above embodiments. The present invention also includes other embodiments realized by combining any of the components in the above embodiments, modifications obtained by applying various modifications to the above embodiments that would occur to those skilled in the art without departing from the spirit of the present invention, and various devices incorporating the above high-frequency circuit.

[0300] For example, in the circuit configuration of the tracker circuit according to each of the above embodiments, other circuit elements and wiring may be inserted between the paths connecting the circuit elements and signal paths disclosed in the drawings. For example, a filter circuit may be inserted between the power supply modulation circuit and the power amplifier. Also, for example, a switch circuit may be inserted between the power supply modulation circuit and the power amplifier. In this case, the tracker circuit may supply a power supply voltage to another power amplifier via the switch circuit.

[0301] It should be noted that the first embodiment and its modifications may be combined. In the first embodiment and its modifications, the multilevel converter circuits 11 and 11A are interchangeable, and the power supply modulation circuits 12 and 12A are also interchangeable. For example, in the tracker circuit 1 according to the first embodiment, the power supply modulation circuit 12 may be replaced with the power supply modulation circuit 12A. Also, for example, in the tracker circuit 1 according to the first embodiment, the multilevel converter circuit 11 may be replaced with the multilevel converter circuit 11A.

[0302] Note that the second embodiment and its modified examples may be combined. In the second embodiment and its modified examples, the power supply modulation circuit 12 and the power supply modulation circuit 12A are interchangeable, and the power supply modulation circuits 12B and 12C are interchangeable. For example, in the tracker circuit 1A according to the second embodiment, the power supply modulation circuit 12 may be replaced with the power supply modulation circuit 12A. Also, for example, in the tracker circuit 1A according to the second embodiment, the power supply modulation circuit 12B may be replaced with the power supply modulation circuit 12C.

[0303] Note that the third embodiment and its modifications may be combined. In the third embodiment and its modifications, the power supply modulation circuit 12D and the power supply modulation circuit 12F are interchangeable, and the power supply modulation circuits 12E and 12G are interchangeable. For example, in the tracker circuit 1B according to the third embodiment, the power supply modulation circuit 12D may be replaced with the power supply modulation circuit 12F. Also, for example, in the tracker circuit 1B according to the third embodiment, the power supply modulation circuit 12E may be replaced with the power supply modulation circuit 12G.

[0304] In the second and third embodiments, two power supply modulation circuits are combined, but more power supply modulation circuits may be combined.

[0305] The features of the tracker circuits described based on the above embodiments will be described below.

[0306] a first input terminal for receiving a first voltage included in the two or more discrete voltages; a second input terminal for receiving a second voltage included in the two or more discrete voltages, the second voltage being higher than the first voltage; a first output terminal; a first FET; a second FET; a third FET; and a first transformer including a first coil and a second coil, wherein a source terminal of the first FET is connected to the first input terminal, a drain terminal of the first FET is connected to a source terminal of the third FET and one end of the first coil, a drain terminal of the second FET is connected to the second input terminal, a source terminal of the second FET is connected to one end of the second coil, and a drain terminal of the third FET is connected to the other end of the first coil, the other end of the second coil, and the first output terminal.

[0307] <2> A tracker circuit comprising: a multilevel converter circuit configured to output two or more discrete voltages; and a first power supply modulation circuit configured to selectively output a plurality of discrete voltages including the two or more discrete voltages, wherein the first power supply modulation circuit comprises: a first input terminal that receives a first voltage included in the two or more discrete voltages; a second input terminal that receives a second voltage that is included in the two or more discrete voltages and is higher than the first voltage; a first output terminal; a first FET; a second FET; a third FET; and a first transformer including a first coil and a second coil, wherein a source terminal of the first FET is connected to the first input terminal; a drain terminal of the first FET is connected to one end of the first coil; a drain terminal of the second FET is connected to the second input terminal; a source terminal of the second FET is connected to a drain terminal of the third FET and one end of the second coil; and a source terminal of the third FET is connected to the other end of the first coil, the other end of the second coil, and the first output terminal.

[0308] <3> The tracker circuit according to <1> or <2>, wherein the first FET, the second FET, and the third FET are controlled based on a digital control level (DCL) signal.

[0309] <4> The tracker circuit according to any one of <1> to <3>, wherein in a first mode for outputting the first voltage, the first FET is turned on, the second FET is turned off, and the third FET is turned on; in a second mode for outputting the second voltage, the first FET is turned off, the second FET is turned on, and the third FET is turned on; and in a third mode for outputting a third voltage that is higher than the first voltage and lower than the second voltage, the first FET is turned on, the second FET is turned on, and the third FET is turned off.

[0310] <5> The tracker circuit according to <1> or <2>, further comprising a second power supply modulation circuit, wherein the second power supply modulation circuit comprises: a third input terminal receiving a fourth voltage included in the two or more discrete voltages, the fourth voltage being lower than the first voltage; a fourth input terminal connected to the first output terminal of the first power supply modulation circuit; a second output terminal; a fourth FET, a fifth FET, a sixth FET; and a second transformer including a third coil and a fourth coil, wherein a source terminal of the fourth FET is connected to the third input terminal; a drain terminal of the fourth FET is connected to a source terminal of the sixth FET and one end of the third coil; a drain terminal of the fifth FET is connected to the fourth input terminal; a source terminal of the fifth FET is connected to one end of the fourth coil; and a drain terminal of the sixth FET is connected to the other end of the third coil, the other end of the fourth coil, and the second output terminal.

[0311] <6> The tracker circuit according to <1> or <2>, further comprising a second power supply modulation circuit, wherein the second power supply modulation circuit comprises: a third input terminal receiving a fourth voltage included in the two or more discrete voltages, the fourth voltage being lower than the first voltage; a fourth input terminal connected to the first output terminal of the first power supply modulation circuit; a second output terminal; a fourth FET, a fifth FET, a sixth FET; and a second transformer including a third coil and a fourth coil, wherein a source terminal of the fourth FET is connected to the third input terminal; a drain terminal of the fourth FET is connected to one end of the third coil; a drain terminal of the fifth FET is connected to the fourth input terminal; a source terminal of the fifth FET is connected to a drain terminal of the sixth FET and one end of the fourth coil; and a source terminal of the sixth FET is connected to the other end of the third coil, the other end of the fourth coil, and the second output terminal.

[0312] <7> The tracker circuit according to <5> or <6>, wherein the first FET, the second FET, the third FET, the fourth FET, the fifth FET, and the sixth FET are controlled based on a DCL signal.

[0313] <8> In a first mode for outputting the first voltage, the first FET is turned on, the second FET is turned off, the third FET is turned on, the fourth FET is turned off, the fifth FET is turned on, and the sixth FET is turned on; in a second mode for outputting the second voltage, the first FET is turned off, the second FET is turned on, the third FET is turned on, the fourth FET is turned off, the fifth FET is turned on, and the sixth FET is turned on; in a third mode for outputting a third voltage higher than the first voltage and lower than the second voltage, the first FET is turned on, the second FET is turned on, the third FET is turned off, the fourth FET is turned off, the fifth FET is turned on, and the sixth FET is turned on; and in a fourth mode for outputting the fourth voltage, the fourth FET is turned on, the fifth FET is turned off, and the sixth FET is turned on. <5> to <7>. The tracker circuit according to any one of <5> to <7>, wherein in a fifth mode for outputting a fifth voltage higher than the fourth voltage and lower than the first voltage, the first FET is turned on, the second FET is turned off, the third FET is turned on, the fourth FET is turned on, the fifth FET is turned on, and the sixth FET is turned off; in a sixth mode for outputting a sixth voltage higher than the fourth voltage and lower than the second voltage, the first FET is turned off, the second FET is turned on, the third FET is turned on, the fourth FET is turned on, the fifth FET is turned on, and the sixth FET is turned off; and in a seventh mode for outputting a seventh voltage higher than the fourth voltage and lower than the third voltage, the first FET is turned on, the second FET is turned on, the third FET is turned off, the fourth FET is turned on, the fifth FET is turned on, and the sixth FET is off.

[0314] <9> The first power supply modulation circuit further includes a fourth FET, a source terminal of which is connected to the other end of the first coil, the other end of the second coil, and a drain terminal of the third FET, and the drain terminal of the fourth FET is connected to the first output terminal, and the tracker circuit further includes a second power supply modulation circuit, the second power supply modulation circuit including: a third input terminal for receiving a fourth voltage included in the two or more discrete voltages and which is higher than the second voltage, a fourth input terminal for receiving a fifth voltage included in the two or more discrete voltages and which is higher than the fourth voltage, a second output terminal, a fifth FET, a sixth FET, a seventh FET, an eighth FET, and a second transformer including a third coil and a fourth coil, and the source terminal of the fifth FET is connected to the third input terminal, a drain terminal of the fifth FET is connected to the source terminal of the seventh FET and one end of the third coil, and the drain terminal of the sixth FET is connected to the fourth input terminal, The tracker circuit according to <1> or <2>, wherein a source terminal of the sixth FET is connected to one end of the fourth coil, a drain terminal of the seventh FET is connected to the other end of the third coil, the other end of the fourth coil, and a drain terminal of the eighth FET, and a source terminal of the eighth FET is connected to the second output terminal.

[0315] <10> The first power supply modulation circuit further includes a fourth FET, a source terminal of which is connected to the other end of the first coil, the other end of the second coil, and a source terminal of the third FET, and a drain terminal of the fourth FET is connected to the first output terminal, and the tracker circuit further includes a second power supply modulation circuit, the second power supply modulation circuit including: a third input terminal for receiving a fourth voltage included in the two or more discrete voltages and which is higher than the second voltage, a fourth input terminal for receiving a fifth voltage included in the two or more discrete voltages and which is higher than the fourth voltage, a second output terminal, a fifth FET, a sixth FET, a seventh FET, an eighth FET, and a second transformer including a third coil and a fourth coil, and the source terminal of the fifth FET is connected to the third input terminal, a drain terminal of the fifth FET is connected to one end of the third coil, and a drain terminal of the sixth FET is connected to the fourth input terminal, The tracker circuit according to <1> or <2>, wherein a source terminal of the sixth FET is connected to a drain terminal of the seventh FET and one end of the fourth coil, a source terminal of the seventh FET is connected to the other end of the third coil, the other end of the fourth coil and a drain terminal of the eighth FET, and a source terminal of the eighth FET is connected to the second output terminal.

[0316] <11> The tracker circuit according to <9> or <10>, wherein the first FET, the second FET, the third FET, the fourth FET, the fifth FET, the sixth FET, the seventh FET, and the eighth FET are controlled based on a DCL signal.

[0317] <12> In a first mode for outputting the first voltage, the first FET is turned on, the second FET is turned off, the third FET is turned on, the fourth FET is turned on, and the eighth FET is turned off; in a second mode for outputting the second voltage, the first FET is turned off, the second FET is turned on, the third FET is turned on, the fourth FET is turned on, and the eighth FET is turned off; in a third mode for outputting a third voltage higher than the first voltage and lower than the second voltage, the first FET is turned on, the second FET is turned on, the third FET is turned off, the fourth FET is turned on, and the eighth FET is turned off; in a fourth mode for outputting the fourth voltage, the fourth FET is turned off, the fifth FET is turned on, the sixth FET is turned off, the seventh FET is turned on, and the eighth FET is turned on; and in a fifth mode for outputting the fifth voltage, the fourth FET is turned off, the fifth FET is turned off, the sixth FET is turned on, the seventh FET is turned on, and the eighth FET is turned on. <9> to <11>. The tracker circuit according to any one of <9> to <11>, wherein in a sixth mode for outputting a sixth voltage higher than the fourth voltage and lower than the fifth voltage, the fourth FET is turned off, the fifth FET is turned on, the sixth FET is turned on, the seventh FET is turned off, and the eighth FET is turned on.

[0318] The present invention can be widely used in communication devices such as mobile phones as a tracker circuit that supplies a power supply voltage to a power amplifier arranged in a front end section.

[0319] 1, 1A, 1B Tracker circuit 2 Antenna 3 High frequency circuit 4 RFIC 5 BBIC 6, 6A, 6B Communication device 11, 11A, 11B, 11C Multilevel converter circuit 12, 12A, 12B, 12C, 12D, 12E, 12F, 12G, 12X Power supply modulation circuit 13, 14 Digital control circuit 31 High frequency input terminal 32 Power amplifier 33, 36 Switch circuit 34, 35 Filter 37 Antenna connection terminal 111 Buck-boost converter circuit 112 Buck converter circuit 113 Switched capacitor circuit 330, 360 Common terminal 331, 332, 361, 362 Selection terminal CS11, CS11A, CS11B, CS12, CS12A, CS12B, CS12C, CS12D, CS12E, CS12F, CS12G Control signals C111, C112, C121, C122 Capacitors C130, C131 Flying capacitors C132, C133 Smoothing capacitors L111, L121 Power inductors M211, M211X, M212, M212X, M213, M213A, M213X, M214, M214X, M215, M216, M216A, M217, M217A, M218 FET N1, N2 Node S111, S112, S113, S114, S121, S122, S130, S131, S132, S133, S134, S135, S136, S137 Switches T111, T121, T130, T211, T211X, T212, T212X, T213X, T214, T215 Input terminals T112, T122, T131, T132, T213, T214X, T216 Output terminals X211, X212 Transformer X211a, X211b, X212a, X212b Coil

Claims

1. A tracker circuit comprising: a multilevel converter circuit configured to output two or more discrete voltages; and a first power supply modulation circuit configured to selectively output a plurality of discrete voltages including the two or more discrete voltages, wherein the first power supply modulation circuit comprises: a first input terminal for receiving a first voltage included in the two or more discrete voltages; a second input terminal for receiving a second voltage included in the two or more discrete voltages, the second voltage being higher than the first voltage; a first output terminal; a first FET, a second FET, a third FET; and a first transformer including a first coil and a second coil, wherein a source terminal of the first FET is connected to the first input terminal; a drain terminal of the first FET is connected to a source terminal of the third FET and one end of the first coil; a drain terminal of the second FET is connected to the second input terminal; a source terminal of the second FET is connected to one end of the second coil; and a drain terminal of the third FET is connected to the other end of the first coil, the other end of the second coil, and the first output terminal.

2. A tracker circuit comprising: a multilevel converter circuit configured to output two or more discrete voltages; and a first power supply modulation circuit configured to selectively output a plurality of discrete voltages including the two or more discrete voltages, wherein the first power supply modulation circuit comprises: a first input terminal for receiving a first voltage included in the two or more discrete voltages; a second input terminal for receiving a second voltage included in the two or more discrete voltages, the second voltage being higher than the first voltage; a first output terminal; a first FET, a second FET, a third FET; and a first transformer including a first coil and a second coil, wherein a source terminal of the first FET is connected to the first input terminal; a drain terminal of the first FET is connected to one end of the first coil; a drain terminal of the second FET is connected to the second input terminal; a source terminal of the second FET is connected to the drain terminal of the third FET and one end of the second coil; and a source terminal of the third FET is connected to the other end of the first coil, the other end of the second coil, and the first output terminal.

3. The tracker circuit of claim 1 or 2, wherein the first FET, the second FET, and the third FET are controlled based on a Digital Control Level (DCL) signal.

4. The tracker circuit of any one of claims 1 to 3, wherein in a first mode for outputting the first voltage, the first FET is turned on, the second FET is turned off, and the third FET is turned on; in a second mode for outputting the second voltage, the first FET is turned off, the second FET is turned on, and the third FET is turned on; and in a third mode for outputting a third voltage higher than the first voltage and lower than the second voltage, the first FET is turned on, the second FET is turned on, and the third FET is turned off.

5. The tracker circuit according to claim 1 or 2, further comprising a second power supply modulation circuit, the second power supply modulation circuit comprising: a third input terminal configured to receive a fourth voltage included in the two or more discrete voltages, the fourth voltage being lower than the first voltage; a fourth input terminal connected to the first output terminal of the first power supply modulation circuit; a second output terminal; a fourth FET, a fifth FET, a sixth FET; and a second transformer including a third coil and a fourth coil, wherein a source terminal of the fourth FET is connected to the third input terminal; a drain terminal of the fourth FET is connected to a source terminal of the sixth FET and one end of the third coil; a drain terminal of the fifth FET is connected to the fourth input terminal; a source terminal of the fifth FET is connected to one end of the fourth coil; and a drain terminal of the sixth FET is connected to the other end of the third coil, the other end of the fourth coil, and the second output terminal.

6. The tracker circuit according to claim 1 or 2, further comprising a second power supply modulation circuit, the second power supply modulation circuit comprising: a third input terminal configured to receive a fourth voltage included in the two or more discrete voltages, the fourth voltage being lower than the first voltage; a fourth input terminal connected to the first output terminal of the first power supply modulation circuit; a second output terminal; a fourth FET, a fifth FET, a sixth FET; and a second transformer including a third coil and a fourth coil, wherein a source terminal of the fourth FET is connected to the third input terminal, a drain terminal of the fourth FET is connected to one end of the third coil, a drain terminal of the fifth FET is connected to the fourth input terminal, a source terminal of the fifth FET is connected to the drain terminal of the sixth FET and one end of the fourth coil, and a source terminal of the sixth FET is connected to the other end of the third coil, the other end of the fourth coil, and the second output terminal.

7. The tracker circuit according to claim 5 or 6, wherein the first FET, the second FET, the third FET, the fourth FET, the fifth FET, and the sixth FET are controlled based on a DCL signal.

8. In a first mode for outputting the first voltage, the first FET is turned on, the second FET is turned off, the third FET is turned on, the fourth FET is turned off, the fifth FET is turned on, and the sixth FET is turned on; in a second mode for outputting the second voltage, the first FET is turned off, the second FET is turned on, the third FET is turned on, the fourth FET is turned off, the fifth FET is turned on, and the sixth FET is turned on; in a third mode for outputting a third voltage higher than the first voltage and lower than the second voltage, the first FET is turned on, the second FET is turned on, the third FET is turned off, the fourth FET is turned off, the fifth FET is turned on, and the sixth FET is turned on; in a fourth mode for outputting the fourth voltage, the fourth FET is turned on, the fifth FET is turned off, and the sixth FET is turned on; 8. The tracker circuit of claim 5, wherein in a fifth mode for outputting a fifth voltage higher than the fourth voltage and lower than the first voltage, the first FET is turned on, the second FET is turned off, the third FET is turned on, the fourth FET is turned on, the fifth FET is turned on, and the sixth FET is turned off; in a sixth mode for outputting a sixth voltage higher than the fourth voltage and lower than the second voltage, the first FET is turned off, the second FET is turned on, the third FET is turned on, the fourth FET is turned on, the fifth FET is turned on, and the sixth FET is turned off; and in a seventh mode for outputting a seventh voltage higher than the fourth voltage and lower than the third voltage, the first FET is turned on, the second FET is turned on, the third FET is turned off, the fourth FET is turned on, the fifth FET is turned on, and the sixth FET is off.

9. The first power supply modulation circuit further includes a fourth FET, the source terminal of which is connected to the other end of the first coil, the other end of the second coil, and the drain terminal of the third FET, and the drain terminal of the fourth FET is connected to the first output terminal; the tracker circuit further includes a second power supply modulation circuit, the second power supply modulation circuit including: a third input terminal for receiving a fourth voltage included in the two or more discrete voltages, the fourth voltage being higher than the second voltage; a fourth input terminal for receiving a fifth voltage included in the two or more discrete voltages, the fifth voltage being higher than the fourth voltage; a second output terminal; a fifth FET; a sixth FET; a seventh FET; an eighth FET; and a second transformer including a third coil and a fourth coil, the source terminal of the fifth FET being connected to the third input terminal; the drain terminal of the fifth FET being connected to the source terminal of the seventh FET and one end of the third coil; and the drain terminal of the sixth FET being connected to the fourth input terminal; 3. The tracker circuit according to claim 1, wherein a source terminal of the sixth FET is connected to one end of the fourth coil; a drain terminal of the seventh FET is connected to the other end of the third coil, the other end of the fourth coil, and a drain terminal of the eighth FET; and a source terminal of the eighth FET is connected to the second output terminal.

10. The first power supply modulation circuit further comprises a fourth FET, the source terminal of which is connected to the other end of the first coil, the other end of the second coil, and the source terminal of the third FET, and the drain terminal of the fourth FET is connected to the first output terminal; the tracker circuit further comprises a second power supply modulation circuit, the second power supply modulation circuit comprising: a third input terminal for receiving a fourth voltage included in the two or more discrete voltages and higher than the second voltage; a fourth input terminal for receiving a fifth voltage included in the two or more discrete voltages and higher than the fourth voltage; a second output terminal; a fifth FET; a sixth FET; a seventh FET; an eighth FET; and a second transformer including a third coil and a fourth coil, the source terminal of the fifth FET being connected to the third input terminal; a drain terminal of the fifth FET being connected to one end of the third coil; and a drain terminal of the sixth FET being connected to the fourth input terminal; 3. The tracker circuit according to claim 1, wherein a source terminal of the sixth FET is connected to a drain terminal of the seventh FET and one end of the fourth coil, a source terminal of the seventh FET is connected to the other end of the third coil, the other end of the fourth coil and a drain terminal of the eighth FET, and a source terminal of the eighth FET is connected to the second output terminal.

11. The tracker circuit of claim 9 or 10, wherein the first FET, the second FET, the third FET, the fourth FET, the fifth FET, the sixth FET, the seventh FET, and the eighth FET are controlled based on a DCL signal.

12. In a first mode for outputting the first voltage, the first FET is turned on, the second FET is turned off, the third FET is turned on, the fourth FET is turned on, and the eighth FET is turned off; in a second mode for outputting the second voltage, the first FET is turned off, the second FET is turned on, the third FET is turned on, the fourth FET is turned on, and the eighth FET is turned off; in a third mode for outputting a third voltage higher than the first voltage and lower than the second voltage, the first FET is turned on, the second FET is turned on, the third FET is turned off, the fourth FET is turned on, and the eighth FET is turned off; in a fourth mode for outputting the fourth voltage, the fourth FET is turned off, the fifth FET is turned on, the sixth FET is turned off, the seventh FET is turned on, and the eighth FET is turned on; and in a fifth mode for outputting the fifth voltage, the fourth FET is turned off, the fifth FET is turned off, the sixth FET is turned on, the seventh FET is turned on, and the eighth FET is turned on.

12. The tracker circuit of claim 9, wherein in a sixth mode for outputting a sixth voltage higher than the fourth voltage and lower than the fifth voltage, the fourth FET is turned off, the fifth FET is turned on, the sixth FET is turned on, the seventh FET is turned off, and the eighth FET is turned on.

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