Optical proximity correction-based test pattern generation

Abstract

Systems and methods are presented for optical proximity correction (OPC)-based generation of test patterns. A method may include accessing an input test pattern and generating an intermediate OPC test pattern set for the input test pattern, which may include performing an OPC process on the input test pattern. The OPC process may include multiple iterations, the generated intermediate OPC test pattern set may include multiple intermediate OPC test patterns, and each given intermediate OPC test pattern in the intermediate OPC test pattern set may be an output of performance of a given iteration of the OPC process. The method may also include determining one or more selected intermediate OPC test patterns from the intermediate OPC test pattern set to include in a test mask to fabricate a test circuit and obtain measurement values through which to calibrate an OPC resist model.

Description

202414051OPTICAL PROXIMITY CORRECTION-BASED TEST PATTERN GENERATIONBACKGROUND

[0001] Electronic circuits, such as integrated circuits, are used in nearly every facet of modern society, from automobiles to microwaves to personal computers. Design of circuits may involve many steps, known as a "design flow." The particular steps of a design flow are often dependent upon the type of circuit being designed, its complexity, the design team, and the circuit fabricator or foundry that will manufacture the circuit. Electronic design automation (EDA) applications support the design and verification of circuits prior to fabrication. EDA applications may implement various EDA procedures, e.g., functions, tools, or features to analyze, test, or verify a circuit design at various stages of the design flow.BRIEF DESCRIPTIO OF THE DRAWINGS

[0002] Certain examples are described in the following detailed description and in reference to the drawings.

[0003] Figure 1 shows an example of a computing system that supports optical proximity correction (OPC)-based test pattern generation according to the present disclosure.

[0004] Figure 2 shows an example determination of selected intermediate OPC test patterns to include in a test mask.

[0005] Figure 3 shows an example of logic that a system may implement to support OPC-based test pattern generation according to the present disclosure.

[0006] Figure 4 shows an example of a computing system that supports OPC-based test pattern generation according to the present disclosure.202414051DETAILED DESCRIPTION

[0007] Electronic circuits, such as integrated circuits (ICs), are used in nearly every facet of modern society, from automobiles to microwaves to personal computers. The design, verification, and physical manufacture of circuit devices often involve several steps, sometimes referred to as a "design flow." The particular steps of a design flow are dependent upon various factors, such as the type of integrated circuit being designed, its complexity, the design team, and the integrated circuit fabricator (e.g., foundry) that will manufacture the physical circuit. Typically, software and hardware tools can verify the circuit designs at various stages of the design flow, for example through complex rule checks, software-based simulations, hardware-based emulation, and various other techniques supported by modern EDA technology. These steps of a design flow aid in the discovery of errors in circuit designs, and allow design teams and engineers to correct or otherwise improve the designs prior to, during, or after physical manufacture.

[0008] Several steps are common to most design flows of IC design. Initially, the specification for a new circuit can be transformed into or otherwise generated as a logical design. Logical designs are sometimes referred to as a register transfer level (RTL) description of a circuit. With logical designs, a circuit can be described in terms of both the exchange of signals between hardware registers and the logical operations that are performed on those signals. The logical design typically employs a Hardware Design Language (HDL), such as the Very high-speed integrated circuit Hardware Design Language (VHDL). The logic of the circuit is then analyzed to confirm that the design will accurately perform the functions desired for the circuit. This analysis is sometimes referred to as "functional verification."

[0009] After the accuracy of the logical design is confirmed through functional verification, a logical design can be converted into a device design by synthesis software. The device design, which is typically in the form of a schematic or netlist, can describe the specific electronic devices (e.g., transistors, resistors, and capacitors) that form the circuit design, along with the interconnections between these electronic devices. This device design generally corresponds to the level of representation displayed in conventional circuit diagrams. The relationships between the electronic devices are then analyzed to confirm that the circuit described by the device design will correctly perform the desired functions. This analysis is sometimes202414051 referred to as "formal verification." Additionally, preliminary timing estimates for portions of the circuit are often made at this stage, using an assumed characteristic speed for each device, and incorporated into the verification process.

[0010] Once the electronic devices components and their interconnections are established, the design can again be transformed in a design flow. In particular, the next transformation may be to a physical design that describes specific geometric elements that form the circuit design. This type of physical version of a circuit design is often referred to as a "layout" design or “physical layout” (and may simply be referred to as a “layout”). The geometric elements, which typically are polygons, define the shapes that will be created in various layers of material to physically manufacture the circuit. Automated place and route tools can be used to define or generate the physical layouts, especially for wires that will be used to interconnect the circuit devices in the physical representation of the circuit design. Each layer of a circuit can have a corresponding layer representation in the layout design, and the geometric shapes described in a layer representation will define the relative locations of the circuit elements that will make up the circuit device (e.g., of transistors, resistors, capacitors, etc.). For example, shapes in the layer representation of a metal layer will define the locations of the metal wires used to connect the circuit devices.

[0011] Integrated circuit layout descriptions can be provided in many different formats. The Graphic Data System II (GDSII) format is a popular format for transferring and archiving two-dimensional graphical IC layout data. Among other features, GDSII contains a hierarchy of structures, each structure containing layout elements (e.g., polygons, paths or poly-lines, circles and textboxes). Other layout formats include an open-source format named Open Access, Milkyway by Synopsys, Inc., EDDM by Siemens EDA (formerly Mentor Graphics Corporation), and the Open Artwork System Interchange Standard (OASIS) format proposed by Semiconductor Equipment and Materials International (SEMI). These various industry formats are used to define the geometrical information in IC layout designs that are employed to manufacture integrated circuits. Once the circuit design is finalized, the layout portion of the design can be used by fabrication tools to manufacture the device using a photolithographic process.

[0012] Typically, a designer will perform a number of verification processes on the layout design. For example, the layout design may be analyzed to confirm that it202414051 accurately represents the circuit devices and their relationships described in the device design. In this process, a layout-versus-schematic (LVS) tool can extract a netlistfrom the layout design and compare it with the netlist taken from the circuit schematic. LVS can be augmented by formal equivalence checking, which checks whether two circuits perform exactly the same function without demanding isomorphism.

[0013] The layout design also may be analyzed to confirm that it complies with various design requirements, such as minimum spacings between geometric elements and minimum linewidths of geometric elements. Such checks may be part of a design rule checking (DRC) process performed on layout design. DRC tools can take, as an input, a physical layout (e.g., in the GDSII or OASIS standard format) as well as a rule deck which specifies the specific rule checks to perform on the layout design. As checks in a DRC process can be specific to a particular circuit fabrication process, rule decks are typically provided by a foundry or circuit manufacturer specifying the particular rules that circuit designs must adhere to for circuit fabrication via the foundry (e.g., at a specified technology node or specific fabrication process parameters). Put another way, foundry-provided rule decks can include a list of rules specific to the semiconductor fabrication process employed by the foundry or otherwise selected for use in circuit manufacture. As such, a set of rules for a particular fabrication process can be referred to as a run-set, rule deck, or just a deck. An example format used for implementation of rule decks is the Standard Verification Rule Format (SVRF) by Siemens EDA (formerly Mentor Graphics Corporation).

[0014] There are many different fabrication processes for manufacturing a circuit, but most processes include a series of steps that deposit layers of different photoresist materials on a substrate, expose specific portions of each layer to radiation, and then etch the exposed (or non-exposed) portions of the layer away. For example, a simple semiconductor device component could be manufactured by the following steps. First, a positive-type epitaxial layer is grown on a silicon substrate through chemical vapor deposition. Next, a nitride layer is deposited over the epitaxial layer. Then specific areas of the nitride layer are exposed to radiation, and the exposed areas are etched away, leaving behind exposed areas on the epitaxial layer, (i.e., areas no longer covered by the nitride layer). The exposed areas then are subjected to a diffusion or ion implantation process, causing dopants, for example phosphorus, to enter the exposed epitaxial layer and form charged wells. This process of depositing layers of202414051 photoresist material on the substrate or subsequent material layers, and then exposing specific patterns to radiation, etching, and dopants or other diffusion materials, is repeated a number of times, allowing the different physical layers of the circuit to be manufactured.

[0015] Each time that a layer of material is exposed to radiation, a photomask (mask) must be created to expose only the desired areas to the radiation, and to protect the other areas from exposure. The mask can be created from circuit layout data. That is, the geometric elements described in a physical layout may define the relative locations or areas of the circuit wafer that will be exposed to radiation through the mask. A mask or reticle writing tool may be used to create masks based upon circuit design layouts, after which the mask can be used in a photolithographic process for fabrication of physical circuits. One or more resolution enhancement techniques (RETs) are often employed to improve the resolution of the image that the mask forms on the substrate during the photolithographic process. One of these techniques is optical proximity correction (OPC).

[0016] OPC has played an important role in the design and validation of circuit designs and semiconductor manufacturing processes. In many design flows, OPC is a major and necessary step in the data preparation and the generation of mask data for wafer targets. OPC can involve generation of mask data from a physical layout of a circuit design, and simulations of radiation through the mask data unto a wafer. As such, OPC processes may allow for modeling of optical effects in lithographical fabrication processes as well as chemical properties of photoresist materials to identify differences between target layout geometry and physical wafer structures manufactured through the lithographical fabrication process. OPC can be rule-based, model-based, or both. In rule-based OPC, the proximity effects are characterized, and specific solutions are devised for specific geometric configurations. Target points on the wafer are measured to determine the accuracy by which the mask data transfers to the wafer. Displacements between a target point and simulations results can indicate errors in the patterning process, and such displacement values are sometimes referred to as edge placement error (EPE). Through multiple iterations of simulation and mask data adjustments, OPC processes can seek to reduce EPE and converge at a mask data solution that more accurately transfers the desired physical contours to wafer. In support of such techniques, OPC processes can compare target images202414051 with predicted latent images on the photoresist printed through a photolithographic process. EPE and other quantifiable indicators can be measured in various OPC iterations.

[0017] In some OPC methods, the incremental move of each fragment is determined only by the EPE or the signal value of the resist surface at the single target point that is uniquely associated to this undergoing fragment. However, this association is nonphysical, and any movement of a single fragment on the mask impacts more than one target points on the wafer. As such, over time, OPC has evolved from rule-based to model-based correction operations. In model-based OPC processes, the change of EPE at a target point on the wafer is a consequence of the position updates of multiple fragments. Put another way, multiple different fragment movements surrounding a target location may impact the movement of an edge fragment at the target location, and thus impacts the EPE of the target location. Therefore, model-based OPC processes can consider the impact of the move of each fragment on some or all target points on the wafer. Model-based OPC can be implemented within the traditional OPC framework as a supplemental or helper function, e.g., as a matrix-based function.

[0018] The accuracy and stability of OPC processes (e.g., accuracy of latent image generation from aerial image inputs) can depend on the calibration of various OPC models used in OPC process. Continually increasing complexities in chip design can result in OPC analyses and processes performed on billions of features of a chip, oftentimes more. As such, modern OPC processes are often split into multiple different parameter spaces and models to particularly address or characterize various aspects of the lithographical fabrication process. An example split of OPC process aspects is optical models and resist models. Optical parameters or models of OPC processes may describe, simulate, parameterize, characterize, or otherwise represent optical effects in photolithography processes used to fabricate circuits. Resist parameters or models of OPC processes may describe, simulate, parameterize, characterize, or otherwise represent physical or chemical effects of photoresist materials used for circuit fabrications. Etch parameters or models of OPC processes may describe, simulate, parameterize, characterize, or otherwise represent physical or chemical effects of etching processes used for circuit fabrications. In some implementations, OPC processes may be performed through separate optical, resist, and etch models, e.g., as separate elements or parts of an overall OPC model or as202414051 distinct steps in an OPC process. As such, optical and photoresist behavior and characteristics may be modeled by an OPC model for an OPC process through separate sets of optical parameters and resist parameters. As used herein, the terms “model” and “parameters” may be used interchangeably to reference modeling of optical, resist, and etch effects for OPC processes.

[0019] In some OPC implementations, various predictive capabilities and parameters of OPC models can be calibrated through measured values of physically-printed circuits. In support of such measurement-based calibrations, a test mask can be generated that includes various test patterns from which measurements of test circuits can be extracted for the various test patterns. These measured values (e.g., critical dimensions, extracted contours, geometric features, wafer characteristics, and the like) can be used to calibrate various parameters of the OPC model, such as resist parameters (or resist models), optical parameters (or optical models), etch parameter (or etch models), or combinations thereof. Representative test pattern selection may improve OPC model performance by capturing physical values fabricated from different target layout structures included in a circuit design. Various techniques exist to determine selected test patterns to include for circuit fabrication and wafer measurements of fabricated circuits.

[0020] Example test patterns that have been generated, selected, or used include design-specific patterns (e.g., derived or representatively selected from actual circuit layouts) as well as test patterns that vary in dimension and mass (thus allowing for systematic measurement of the impact of mass changes in design layouts). One limitation of conventional techniques is that selected test patterns often fail to account for non-linearities that exist between changes in layout structures. For example, incrementally expanding the size or mass of a simple 1 -dimensional (1 D) layout structure can allow for systematic physical measurements for that 1 D structure based on the incremental changes. However, such changes to the 1 D structure can impact the fabrication and wafer characteristics of nearby structures as well, which are often not included in a test pattern. Some layout structures are particularly susceptible to such non-linear effects, and OPC models can attempt to address non-linear impacts through a mask error enhancement function (MEEF). Conventional pattern selection processes often fail to account for such MEEF effects in pattern selections.202414051

[0021] Conventional pattern selection techniques that fail to account for non-linearity effects in layout structures can negatively impact the accuracy and stability of OPC models. Fabrication test circuits will fail to include wafer structures manufactured through a test mask that includes representative test patterns specifically designed to address cross MEEF effects of layout structures. This is particularly relevant as OPC processes will often adjust circuit designs with small-precise changes (e.g., through movements of edge fragments or vertex locations for curvilinear OPC). Such edge fragment or curvilinear vertex movements during OPC processes can impact nearby layout locations, and OPC model calibrations that fail to account for such movements and effects during OPC iterations will be inaccurate or incomplete. The accuracy of OPC processes may thus be hindered, which can cause extraneous OPC iterations, inaccurate OPC modeling and RET adjustments, and could result in defects, malfunctioning circuits, and lower circuit yield.

[0022] The disclosure herein may provide systems, methods, devices, and logic for OPC-based test pattern generation. The various technical features described herein may be referred to as OPC-based test pattern generation technology, which may include the determination of intermediate OPC test patterns for inclusion in test masks used to fabricate test circuits. Intermediate OPC test patterns may be captured as layout structures output from iterations of an OPC process (e.g., prior to convergence), and may thus capture the impact of edge, fragment, or curvilinear vertex movements for layout structures via the OPC process. Selected intermediate OPC test patterns may be included in test masks for fabrication of test circuits. Measurement values (e.g., critical dimensions) obtained from circuits fabricated via intermediate OPC test patterns can allow for characterization and measurement of systematic changes to layout structures during an OPC process, e.g., across various OPC iterations of the OPC process. Such characterizations may be incorporated into OPC model calibrations with the measured values. Thus, the measured values from fabricated test circuits that utilized intermediate OPC test patterns of the present disclosure may support OPC model calibrations with increased accuracy and support OPC models with increased precision and stability.

[0023] These and other technical features and technical benefits of the OPC-based test pattern generation technology are presented herein.202414051

[0024] Figure 1 shows an example of a computing system that supports OPC-based test pattern generation according to the present disclosure. The computing system 100 may take the form of a single or multiple computing devices such as application servers, compute nodes, desktop or laptop computers, smart phones or other mobile devices, tablet devices, embedded controllers, and more. In some implementations, the computing system 100 hosts, instantiates, executes, supports, or implements an EDA application or EDA system that supports circuit design and analysis, and may accordingly provide or implement any of the OPC-based test pattern generation technology described herein.

[0025] As an example implementation to support any combination of the OPC-based test pattern generation technology described herein, the computing system 100 shown in Figure 1 includes an OPC-based test pattern generation engine 110. The computing system 100 may implement the OPC-based test pattern generation engine 110 (including components thereof) in various ways, for example as hardware and programming. The programming for the OPC-based test pattern generation engine 110 may take the form of processor-executable instructions stored on a non-transitory machine-readable storage medium and the hardware for the OPC-based test pattern generation engine 110 may include a processor to execute those instructions. A processor may take the form of single processor or multi-processor systems, and in some examples, the computing system 100 implements multiple engines using the same computing system features or hardware components (e.g., a common processor or a common storage medium).

[0026] In operation, the OPC-based test pattern generation engine 110 may access an input test pattern, and the input test pattern may specify a target geometry in a semiconductor fabrication process. In operation, the OPC-based test pattern generation engine 110 may also generate an intermediate OPC test pattern set for the input test pattern, including by performing an OPC process on the input test pattern that includes multiple iterations. The intermediate OPC test pattern set generated by the OPC-based test pattern generation engine 110 may include multiple intermediate OPC test patterns, and a given intermediate OPC test pattern in the intermediate OPC test pattern set may be the output of performance of a given iteration of the OPC process. In operation, the OPC-based test pattern generation engine 110 may further determine a selected intermediate OPC test pattern from the intermediate OPC test202414051 pattern set to include in a test mask to fabricate a test circuit and obtain measurement values through which to calibrate an OPC resist model, e.g., in any of the ways described herein.

[0027] These and other technical features and technical benefits of the OPC-based test pattern generation technology are described in greater detail next Many of the examples presented herein are within the context of OPC processes for layout structures fragmented into edges (also referred to has fragments), e.g., for Manhattan shape representations of test masks. The OPC-based test pattern generation technology presented herein may be consistently applied for curvilinear OPC and curvilinear masks, as well as any other mask, test pattern, or layout representation.

[0028] Figure 2 shows an example determination of selected intermediate OPC test patterns to include in a test mask. In the example of Figure 2, the OPC-based test pattern generation engine 110 accesses an input design pattern 210. The input design pattern 210 may take the form of any layout structure and may be generated through any suitable test pattern generation process. As examples, the input test pattern 210 may be selected as a representative pattern of a circuit design sampled from the various structures in the circuit design, as a synthetically generated test structure, as part of a test pattern suite created for a specific circuit design, or in any other manner. Any conventional form or technique for test pattern selection or generation is contemplated herein for the input test pattern 210, which the OPC-based test pattern generation engine 110 may implement, perform, or otherwise support. In some implementations, the input test pattern 210 may represent a target structure for a circuit design, e.g., a target shape in a fabricated circuit. The OPC-based test pattern generation engine 110 may access the input test pattern 210 in various ways, for example by loading the input test pattern 210 from a memory, receiving the input test pattern 210 over a communication network, or through specification or identification of the input test pattern 210 via user input.

[0029] An illustrative example of layout structure is shown in Figure 2 for the input test pattern 210. The shape of the input test pattern 210 in Figure 2 is that of an open “H” shape, which may be particularly susceptible or impacted by non-linearity factors from internal or nearby mass adjustments, e.g., fragment movements during OPC impacting fabrication accuracy of other nearby fragments. Thus, conventional pattern selection techniques may be incomplete or unable to account for the specific fragment202414051 impacts of OPC processes, and thus model calibrations through conventionally- selected test patterns can result in OPC models or parameters with diminished accuracy and stability. The OPC-based test pattern generation technology of the present disclosure may support model calibrations that inform OPC models of OPC movement and shapes throughout the OPC process.

[0030] In particular, the OPC-based test pattern generation engine 110 may perform an OPC process on the input test pattern 210 that includes multiple iterations. After each OPC iteration, the OPC-based test pattern generation engine 110 may take a snapshot of the OPC iteration output, which may then serve as an intermediate OPC test pattern that the OPC-based test pattern generation engine 110 can include as a test pattern for a test mask. As OPC processes can run for five (5) iterations, ten (10) iterations, twenty (20) iterations, and any other number more, the intermediate OPC test patterns generated by the OPC-based test pattern generation engine 110 may allow for test pattern selections that more adequately or thoroughly cover OPC edge movements, which can in turn improve model calibrations to allow OPC models to understand and account for cross MEEF-effects and produce more accurate OPC results.

[0031] To illustrate through Figure 2, the OPC-based pattern generation engine 110 may generate an intermediate OPC test pattern set 220 for the input test pattern 210. The OPC-based test pattern generation engine 110 may do so by performing an OPC process on the input test pattern 210. In some examples, the OPC-based test pattern generation engine 110 performs an OPC process that comprises some, but not all, parameters or models of an OPC process. For instance, the OPC-based test pattern generation engine 110 may perform the OPC process on the input test pattern 210 via an optical model (or optical parameters). OPC processes may employ optical models that computationally simulate optical properties of a lithographical fabrication process, e.g., without calibration through measured values from fabricated test circuits. Through an optical model, the OPC-based test pattern generation engine 110 may perform an OPC process on an input test pattern 210 and use generated intermediate OPC test patterns, a test mask, and measured values from a fabricated test circuit to tune other aspects off the OPC process, an OPC resist model (e.g., OPC resist parameters). In this example, the OPC-based test pattern generation engine 110 may perform the OPC process on the input test pattern 210 via optical parameters or an202414051OPC optical model that characterizes, simulates, or otherwise models optical properties of a photolithography circuit fabrication process.

[0032] The OPC process performed by the OPC-based test pattern generation engine 110 on the input test pattern 210 may be iterative. Each OPC iteration may take an input aerial image (e.g., starting with the input test pattern 210), generate a latent image of the aerial image, measure EPE between target locations and predicted locations in latent image, and perform fragment movements or other mass adjustments to reduce EPE. Accordingly, each OPC iteration may output a different intermediate pattern shape, continuing until the OPC process converges (e.g., a minimum total EPE is reached) or another ending criterion is reached. After performance of each OPC iteration, the OPC-based test pattern generation engine 110 may capture an output from the OPC iteration, saving the output layout shape as an intermediate OPC test pattern in the intermediate OPC test pattern set 220.

[0033] Thus, in Figure 2, the OPC-based test pattern generation engine 110 may perform a first iteration of the OPC process (e.g., via an OPC optical model), shown as OPC iterationi in Figure 2. In Figure 2, the output of OPC iterationi is shown as intermediate OPC test patterni, which the OPC-based test pattern generation engine 110 may include in the intermediate OPC test pattern set 220. The OPC-based test pattern generation engine 110 may then perform a second iteration of the OPC process, doing so on the intermediate OPC test patterni as an input to obtain a second intermediate OPC test pattern as an output, shown as intermediate OPC test pattern in Figure 2. In a similar manner, the OPC-based test pattern generation engine 110 may perform successive iterations of the OPC process and continue to obtain intermediate OPC test patterns until the OPC process ceases, such as intermediate OPC test patterns, intermediate OPC test pattern^ and so forth. For an OPC process performed on the input test pattern 210 that ends (e.g., converges) after ‘n’ number of iterations, the OPC-based test pattern generation engine 110 may obtain up to ‘n’ number of intermediate OPC test patterns, e.g., as the output of each of the ‘n’ number of OPC iterations. These intermediate OPC test patterns generated through the iterations of the OPC process may form the intermediate OPC test pattern set 220 for the input test pattern 210.

[0034] The OPC-based test pattern generation engine 110 may select some or all of the intermediate OPC test patterns of the intermediate OPC test pattern set 220 to202414051 include in a test mask. Intermediate OPC test patterns selected for inclusion in a test mask may be referred to as selected intermediate OPC test patterns. In the example of Figure 2, the OPC-based test pattern generation engine 110 determines the selected intermediate OPC test patterns 230 from the intermediate OPC test pattern set 220. As described herein, The OPC-based test pattern generation engine 110 may determine (e.g., identify or select) multiple selected intermediate OPC test patterns from the intermediate OPC test pattern set 220 to include in a test mask. As an illustrative example through Figure 2, the OPC-based test pattern generation engine 110 may select intermediate OPC test patterni (output from a first OPC iteration) and intermediate OPC test pattern (output from a second OPC iteration), but determine not to select intermediate OPC test patterns (output from a third OPC iteration) as one of the selected intermediate OPC test patterns 230 for inclusion in the test mask. Any suitable criteria for selection of intermediate OPC test patterns is contemplated herein.

[0035] Thus, in this example of Figure 2, the OPC-based test pattern generation engine 110 may determine multiple selected intermediate OPC test patterns by selecting both a first intermediate OPC test pattern output from a first OPC iteration and a second OPC test pattern output from a second OPC iteration to include in the test mask. In this example, the OPC-based test pattern generation engine 110 may further determine the multiple selected intermediate OPC test patterns by determining not to select a third intermediate OPC test pattern output from a third iteration of the OPC process as a selected intermediate OPC test pattern.

[0036] In determining selected intermediate OPC test patterns, the OPC-based test pattern generation engine 110 may apply any suitable selection, sampling, or determination technique. In some examples or for some input test patterns, the OPC- based test pattern generation engine 110 may select all of the intermediate OPC test patterns in the intermediate OPC test pattern set 220 for inclusion in the test mask. Doing so may support provision of increasingly comprehensive, extensive, exhaustive or complete data measurements for OPC fragment movement sequences to account for optical effects. Model calibrations through physically measured values from a test circuit fabricated through such a test mask may thus incorporate such measurements for sequential mass changes or iterative layout adjustments performed during OPC.202414051

[0037] As other examples, the OPC-based test pattern generation engine 110 may perform a sampling process to select some, but not all, of the intermediate OPC test patterns in the OPC test pattern set 220 for inclusion in the test mask. Doing so may allow the OPC-based test pattern generation engine 110 to balance between OPC optical effect coverage and resource consumption, efficiency, and die space requirements for test masks. In some implementations, the OPC-based test pattern generation engine 110 may determine the selected intermediate OPC test patterns 230 by performing a sampling process on the intermediate OPC test pattern set 220 to filter out at least some of the multiple intermediate OPC test patterns that do not differ from one another by greater than a difference threshold.

[0038] Difference thresholds may be measured or quantified by the OPC-based test pattern generation engine 110 in any suitable manner, e.g., based on features of a given intermediate OPC test pattern. To illustrate, the OPC-based test pattern generation engine 110 may determine differences between the multiple intermediate OPC test patterns of an intermediate OPC test pattern set based on a difference in measured feature values for each of the multiple intermediate OPC test patterns of the intermediate OPC test pattern set. Any suitable features of a layout pattern or structure may be employed, including within an OPC context. Example feature values include computed convolution kernel-based measurements, measured layout density (e.g., mass) values, geometry structure characterizations, optical intensity data, geometric measurements, and more. Applied kernels may include, as examples, optical kernels or density kernels, which the OPC-based test pattern generation engine 110 may convolve over a given intermediate OPC test pattern to compute a corresponding kernel-based measurement as a computed feature value.

[0039] Through any such features and measured values thereof, the OPC-based test pattern generation engine 110 may characterize a specific intermediate OPC test pattern. Difference measurements may be performed based on differences between feature values (e.g., as arranged in feature vectors) between various intermediate OPC test patterns of an intermediate OPC test pattern set generated for an input test pattern. Differences may be measured based on vector distances (e.g., Euclidean distance in a vector space of the feature vectors), absolute value differences, percentage differences, or according to any other suitable difference metric, any of which the OPC-based test pattern generation engine 110 may implement or support.202414051The difference threshold(s) by which the OPC-based test pattern generation engine 110 characterizes intermediate OPC test patterns as sufficiently distinct may be user- specified or configurable.

[0040] For any intermediate OPC test patterns that do not differ from one another by at least the difference threshold (e.g., greater 1.0% difference, less than a threshold distance between feature vectors, or any other threshold), the OPC-based test pattern generation engine 110 may filter out at least some of such non-differing intermediate OPC test patterns from inclusion in the test mask. Two intermediate OPC test patterns that are not meaningfully different (e.g., as measured through a specified difference threshold) may not provide relevantly different insights into OPC optical effects and relevantly different measurement values for model calibrations. As such, the OPC- based test pattern generation engine 110 may select a representative sample from non-differing intermediate OPC test patterns in the intermediate OPC test pattern set 220, thus conserving die space on a test mask and reducing overall resource consumption while balancing accuracy of capturing OPC optical effects in test pattern selections.

[0041] In some implementations, the OPC-based test pattern generation engine 110 may determine the selected intermediate OPC test patterns 230 through a clustering process. A given cluster of intermediate OPC test patterns may include those with similar feature values (e.g., that do not differ by a difference threshold), and the clustering process may thus partition the intermediate OPC test pattern set 220 into groupings of non-differing intermediate OPC test patterns, from which a representative intermediate OPC pattern can be sampled from each cluster. Any suitable clustering and down-sampling techniques are contemplated herein, which can be employed, performed, and implemented by the OPC-based test pattern generation 110.

[0042] Through any of the ways described herein, the OPC-based test pattern generation engine 110 may determine the selected intermediate OPC test patterns 230 for inclusion in a test mask. The OPC-based test pattern generation engine 110 may provide the selected intermediate OPC test patterns 230 as layout structures to include a test mask. In some implementations, the OPC-based test pattern generation engine 110 may itself add the selected intermediate OPC test patterns 230 to a mask structure for a test mask. The test mask may then be used to physically fabricate a test circuit, which the OPC-based test pattern generation engine 110 may support,202414051 control, or itself perform (e.g., as part of a semiconductor fabrication system). From the physically fabricated test circuit, values of the physical circuit may be measured, including wafer characteristics of the physically manufactured test circuit at circuit locations constructed through the selected intermediate OPC test patterns of the test mask. An example of a measured value includes a critical dimension (CD) of wafer locations, e.g., measured through scanning electron microscope (SEM) imaging techniques. The OPC-based test pattern generation engine 110 may obtain such measurement values (e.g., via any suitable data input or reception technique). The OPC-based test pattern generation engine 110 may then calibrate an OPC model, e.g., OPC resist model (e.g., resist parameters), through the measurement values obtained from the fabricated test circuit.

[0043] Through any combination of the features herein, the OPC-based test pattern generation technology of the present disclosure may provide technical improvements to EDA computing systems and processes. Selected intermediate OPC test patterns may extend coverage of test masks and measured physical values to support OPC model calibrations with increased accuracy, efficiency, and stability. As compared to conventional methods that may fail to account for layout structures in intermediate OPC iterations, the intermediate OPC test patterns captured by the OPC-based test pattern generation technology presented herein may capture subtle mass shifts and layout changes resultant from intermediate iterations of OPC processes. Thus, model calibrations through the measured values from test circuits fabrication through a test mask that includes selected intermediate OPC test patterns may capture subtle variations in layout (and thus mask) shapes during OPC processes, improving the quality of OPC model calibrations and accounting for non-linear mass change impacts with increased accuracy. Through OPC models tuned with measured values obtained via intermediate OPC test patterns, accuracy of OPC simulations can be improved, including on a per-iteration basis. Thus, OPC models may operate with increased efficiency, reducing computational latencies, improving RET techniques, and supporting circuit design and fabrication with increased efficiency and effectiveness.

[0044] While many examples are presented herein in the context of fragment-based OPC processes, the OPC-based test pattern generation technology of the present disclosure is not so limited. Any suitable mask representation and layout structures can be supported by the OPC-based test pattern generation technology disclosed202414051 herein, including curvilinear masks and curvilinear OPC processes. In a consistent manner, the OPC-based test pattern generation engine 110 may capture intermediate OPC test patterns output from iterations of curvilinear OPC processes, and determined select intermediate OPC test patterns for including on a test mask and fabrication of a test circuit. In any of the various ways described herein, the OPC-based test pattern generation technology of the present disclosure may provide various technical benefits and improve EDA computing systems.

[0045] Figure 3 shows an example of logic 300 that a system may implement to support OPC-based test pattern generation according to the present disclosure. For example, the computing system 100 may implement the logic 300 as hardware, executable instructions stored on a machine-readable medium, or as a combination of both. The computing system 100 may implement the logic 300 via the OPC-based test pattern generation engine 110, through which the computing system 100 may perform or execute the logic 300 as a method to support OPC-based test pattern generation. The following description of the logic 300 is provided using the OPC- based test pattern generation engine 110 as an example implementation. However, other implementation options by computing systems are possible.

[0046] In implementing the logic 300, the OPC-based test pattern generation engine 110 may access an input test pattern (302) and generate an intermediate OPC test pattern set for the input test pattern (304). In doing so, the OPC-based test pattern generation engine 110 may perform an OPC process on the input test pattern, e.g., via an optical model of the OPC process. The OPC process may include multiple iterations and the intermediate OPC test pattern set generated by the OPC-based test pattern generation engine 110 may include multiple intermediate OPC test patterns, and wherein a given intermediate OPC test pattern in the intermediate OPC test pattern set is an output of performance of a given iteration of the OPC process. In implementing the logic 300, the OPC-based test pattern generation engine 110 may also determine a selected intermediate OPC test pattern from the intermediate OPC test pattern set to include in a test mask to fabricate a test circuit and obtain measurement values through which to calibrate an OPC resist model (306), doing so in any of the ways described herein.

[0047] The logic 300 shown in Figure 3 provides an illustrative example by which a computing system 100 may support or implement various features of the OPC-based202414051 test pattern generation technology described herein. Additional or alternative steps in the logic 300 are contemplated herein, including according to any of the various features described herein for the OPC-based test pattern generation engine 110.

[0048] Figure 4 shows an example of a computing system 400 that supports OPC- based test pattern generation according to the present disclosure. The computing system 400 may include a processor 410, which may take the form of a single or multiple processors. The processor(s) 410 may include a central processing unit (CPU), microprocessor, or any hardware device suitable for executing instructions stored on a machine-readable medium. The computing system 400 may include a machine-readable medium 420. The machine-readable medium 420 may take the form of any non-transitory electronic, magnetic, optical, or other physical storage device that stores executable instructions, such as the OPC-based test pattern generation instructions 422 shown in Figure 4. As such, the machine-readable medium 420 may be, for example, Random Access Memory (RAM) such as a dynamic RAM (DRAM), flash memory, spin-transfer torque memory, an Electrically-Erasable Programmable Read-Only Memory (EEPROM), a storage drive, an optical disk, and the like.

[0049] The computing system 400 may execute instructions stored on the machine- readable medium 420 through the processor 410. Executing the instructions (e.g., the OPC-based test pattern generation instructions 422) may cause the computing system 400 to perform or implement any of the OPC-based test pattern generation technology described herein, including according to any aspect of the OPC-based test pattern generation engine 110.

[0050] For example, execution of the OPC-based test pattern generation instructions 422 by the processor 410 may cause the computing system 400 to access an input test pattern, generate an intermediate OPC test pattern set for the input test pattern, including by performing an OPC process on the input test pattern, and determine a selected intermediate OPC test pattern from the intermediate OPC test pattern set to include in a test mask to fabricate a test circuit and obtain measurement values through which to calibrate an OPC resist model, doing so in any of the ways described herein. Any combination of the OPC-based test pattern generation technology as described herein may be implemented via the OPC-based test pattern generation instructions 422.202414051

[0051] The systems, methods, devices, and logic described above, including the OPC-based test pattern generation engine 110, may be implemented in many different ways in many different combinations of hardware, logic, circuitry, and executable instructions stored on a machine-readable medium. For example, the OPC-based test pattern generation engine 110, may include circuitry in a controller, a microprocessor, or an application specific integrated circuit (ASIC), or may be implemented with discrete logic or components, or a combination of other types of analog or digital circuitry, combined on a single integrated circuit or distributed among multiple integrated circuits. A product, such as a computer program product, may include a storage medium and machine-readable instructions stored on the medium, which when executed in an endpoint, computer system, or other device, cause the device to perform operations according to any of the description above, including according to any features of the OPC-based test pattern generation engine 110.

[0052] The processing capability of the systems, devices, and engines described herein, including the OPC-based test pattern generation engine 110, may be distributed among multiple system components, such as among multiple processors and memories, optionally including multiple distributed processing systems or cloud / network elements. Parameters, databases, and other data structures may be separately stored and managed, may be incorporated into a single memory or database, may be logically and physically organized in many different ways, and may be implemented in many ways, including data structures such as linked lists, hash tables, or implicit storage mechanisms. Programs may be parts (e.g., subroutines) of a single program, separate programs, distributed across several memories and processors, or implemented in many different ways, such as in a library (e.g., a shared library).

[0053] While various examples and features have been described above, many more implementations are possible.

Claims

202414051CLAIMS1 . A method comprising: by a computing system: accessing an input test pattern, wherein the input test pattern specifies a target geometry in a semiconductor fabrication process; generating an intermediate OPC test pattern set for the input test pattern, including by performing an optical proximity correction (OPC) process on the input test pattern, wherein the OPC process includes multiple iterations, wherein the intermediate OPC test pattern set comprises multiple intermediate OPC test patterns, and wherein a given intermediate OPC test pattern in the intermediate OPC test pattern set is an output of performance of a given iteration of the OPC process; and determining a selected intermediate OPC test pattern from the intermediate OPC test pattern set to include in a test mask to fabricate a test circuit and obtain measurement values through which to calibrate an OPC resist model.

2. The method of claim 1 , comprising determining multiple selected intermediate OPC test patterns from the intermediate OPC test pattern set to include in the test mask.

3. The method of claim 2, wherein performing the OPC process comprises: performing a first iteration of the OPC process on the input test pattern to obtain a first intermediate OPC test pattern; and performing a second iteration of the OPC process on the first intermediate OPC test pattern to obtain a second intermediate OPC test pattern; and wherein determining the multiple selected intermediate OPC test patterns comprises selecting both the first intermediate OPC test pattern and the second OPC test pattern to include in the test mask.

4. The method of claim 3, wherein performing the OPC process further comprises performing a third iteration of the OPC process on the second intermediate OPC test pattern to obtain a third intermediate OPC test pattern; and202414051 wherein determining the multiple selected intermediate OPC test patterns comprises determining not to include the third intermediate OPC test pattern in the test mask.

5. The method of any of claims 1-4, wherein determining the selected intermediate OPC test pattern comprises performing a sampling process on the intermediate OPC test pattern set to filter out at least some of the multiple intermediate OPC test patterns that do not differ from one another by greater than a difference threshold, including by: determining differences between the multiple intermediate OPC test patterns based on a difference in measured feature values for each of the multiple intermediate OPC test patterns of the intermediate OPC test pattern set.

6. The method of any of claims 1-4, comprising determining all intermediate OPC test patterns of the intermediate OPC test pattern set as selected intermediate OPC test patterns to include in the test mask.

7. The method of any of claims 1-6, further comprising calibrating the OPC resist model through the measurement values obtained from the fabricated test circuit.

8. A system comprising: a processor; and a non-transitory machine-readable medium comprising instructions that, when executed by the processor, cause a computing system to: access an input test pattern, wherein the input test pattern specifies a target geometry in a semiconductor fabrication process; generate an intermediate OPC test pattern set for the input test pattern, including by performing an optical proximity correction (OPC) process on the input test pattern, wherein the OPC process includes multiple iterations, wherein the intermediate OPC test pattern set comprises multiple intermediate OPC test patterns, and wherein a given intermediate OPC test pattern in the intermediate OPC test pattern set is an output of performance of a given iteration of the OPC process; and202414051 determine a selected intermediate OPC test pattern from the intermediate OPC test pattern set to include in a test mask to fabricate a test circuit and obtain measurement values through which to calibrate an OPC resist model.

9. The system of claim 8, wherein the instructions, when executed, cause the computing system to determine multiple selected intermediate OPC test patterns from the intermediate OPC test pattern set to include in the test mask.

10. The system of claim 9, wherein the instructions, when executed, cause the computing system to perform the OPC process by: performing a first iteration of the OPC process on the input test pattern to obtain a first intermediate OPC test pattern; and performing a second iteration of the OPC process on the first intermediate OPC test pattern to obtain a second intermediate OPC test pattern; and wherein the instructions, when executed, cause the computing system to determine the multiple selected intermediate OPC test patterns by selecting both the first intermediate OPC test pattern and the second OPC test pattern to include in the test mask.11 . The system of claim 10, wherein the instructions, when executed, cause the computing system to perform the OPC process further by performing a third iteration of the OPC process on the second intermediate OPC test pattern to obtain a third intermediate OPC test pattern; and wherein the instructions, when executed, cause the computing system to determine the multiple selected intermediate OPC test patterns by determining not to include the third intermediate OPC test pattern in the test mask.

12. The system of any of claims 8-11 , wherein the instructions, when executed, cause the computing system to determine the selected intermediate OPC test pattern by performing a sampling process on the intermediate OPC test pattern set202414051 to filter out at least some of the multiple intermediate OPC test patterns that do not differ from one another by greater than a difference threshold, including by: determining differences between the multiple intermediate OPC test patterns based on a difference in measured feature values for each of the multiple intermediate OPC test patterns of the intermediate OPC test pattern set.

13. The system of any of claims 8-11 , wherein the instructions, when executed, cause the computing system to determine all intermediate OPC test patterns of the intermediate OPC test pattern set as selected intermediate OPC test patterns to include in the test mask.

14. The system of any of claims 8-13, wherein the instructions, when executed, further cause the computing system to calibrate the OPC resist model through the measurement values obtained from the fabricated test circuit.

15. A non-transitory machine-readable medium comprising instructions that, when executed by a processor, cause a computing system to perform a method according to any of claims 1-7.

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