Array substrate and display panel

Abstract

The present application discloses an array substrate and a display panel. The array substrate comprises a base substrate, a first electrode disposed on a side of the base substrate, an active portion disposed on a surface of a side of the first electrode facing away from the base substrate, a second electrode disposed on a surface of a side of the active portion facing away from the base substrate, and a gate disposed on a side of the second electrode facing away from the base substrate. The gate and the active portion are at least partially overlapped, and the first electrode, the active portion, the second electrode, and the gate are of a closed-loop structure.

Description

Array substrate and display panel TECHNICAL FIELD

[0001] The present application relates to the display field, in particular to an array substrate and a display panel. BACKGROUND

[0002] The material of the active layer in the common thin film transistor generally includes amorphous silicon, low-temperature polysilicon and oxide. The oxide TFT is widely applied to the TFT device in the display industry due to its low leakage current and high mobility.

[0003] With the decrease of the size of the thin film transistor, the channel thereof is also correspondingly smaller, thereby making the stability of the thin film transistor worse and the leakage current thereof increased. The channel length of the current ultra-short channel thin film transistor is about 2-3 microns, and the channel size of the thin film transistor is mainly limited by the precision of the exposure machine, which leads to the channel of the thin film transistor unable to be further reduced, thereby failing to meet the demand of the existing high mobility device. SUMMARY

[0004] The present application provides an array substrate and a display panel to solve the problem that the channel size of the existing thin film transistor cannot be reduced.

[0005] To solve the above-mentioned solution, the technical solution provided by the present application is as follows:

[0006] The present application provides an array substrate, which comprises:

[0007] a substrate;

[0008] a first electrode arranged on one side of the substrate;

[0009] an active part arranged on the surface of the first electrode away from the substrate;

[0010] a second electrode arranged on the surface of the active part away from the substrate;

[0011] a gate electrode arranged on the side of the second electrode away from the substrate, and the gate electrode and the active part are arranged at least partially overlapped;

[0012] wherein the first electrode, the active part, the second electrode and the gate electrode are in a closed loop structure.

[0013] The present application also provides a display panel, which comprises an array substrate and a light emitting member arranged on one side of the array substrate, and the array substrate and the light emitting member are combined into one body; wherein the array substrate comprises:

[0014] a substrate;

[0015] a first electrode arranged on one side of the substrate;

[0016] an active portion disposed on a surface of the first electrode away from the substrate;

[0017] a second electrode disposed on a surface of the active portion away from the substrate;

[0018] a gate disposed on a surface of the second electrode away from the substrate, and the gate at least partially overlaps with the active portion;

[0019] wherein the first electrode, the active portion, the second electrode and the gate are in a closed loop structure. BRIEF DESCRIPTION OF DRAWINGS

[0020] Fig. 1A is a structure of a first electrode in an array substrate according to the present application;

[0021] Fig. 1B is a structure of an active portion in an array substrate according to the present application;

[0022] Fig. 1C is a structure of a second electrode in an array substrate according to the present application;

[0023] Fig. 1D is a superimposed view of the first electrode, the active portion and the second electrode in an array substrate according to the present application;

[0024] Fig. 1E is a structure of a gate in an array substrate according to the present application;

[0025] Fig. 1F is a superimposed view of the gate and the active portion in an array substrate according to the present application;

[0026] Fig. 1G is a superimposed view of the first electrode, the active portion, the second electrode and the gate in an array substrate according to the present application;

[0027] Fig. 1H is a superimposed view of the first electrode and the gate in an array substrate according to the present application;

[0028] Fig. 2 is a sectional view of section MM in Fig. 1G;

[0029] Fig. 3 is a flow chart of a manufacturing method of an array substrate according to the present application;

[0030] Figs. 4A to 4I are flow charts of manufacturing processes of an array substrate according to the present application. Embodiments of the present application

[0031] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work fall within the scope of protection of the present application. In addition, it should be understood that the specific embodiments described herein are only used to illustrate and explain the present application, and are not used to limit the present application.

[0032] In the description of the present application, it needs to be understood that the terms "length", "width", "thickness", "upper", "lower", "front", "back", "left", "right", "top", "bottom", "inner", "outer" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, which is only for the convenience of describing the present application and simplifying the description, and does not indicate or imply that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present application.

[0033] In addition, the terms "first", "second" are only for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined with "first", "second" can explicitly or implicitly include one or more features. In the description of the present application, the meaning of "multiple" is two or more, at least one of which can be one, two or more, unless otherwise explicitly specified.

[0034] The existing array substrate usually adopts a double-gate structure or a double-active layer structure to improve the mobility of the oxide TFT. The double-gate structure usually improves the mobility of the oxide TFT by only 1.4 times of the single-gate structure, and in the double-active layer structure, the two layers of active layers are stacked, and the thickness of each layer of active layer is difficult to control, and the device uniformity is poor. Therefore, the present application provides an array substrate to solve the above technical problems.

[0035] Please refer to FIG. 1A to FIG. 1G and FIG. 2, FIG. 2 is a sectional view of section MM in FIG. 1G. The present application provides an array substrate 100, which includes a substrate 110, a first electrode 121 disposed on one side of the substrate 110, an active part 131 disposed on the surface of the first electrode 121 away from the substrate 110, a second electrode 151 disposed on the surface of the active part 131 away from the substrate 110, and a gate 171 disposed on the second electrode 151 away from the substrate 110, and the gate 171 and the active part 131 are at least partially overlapped.

[0036] In the present embodiment, the first electrode 121, the active part 131, the second electrode 151 and the gate 171 are closed loop structures.

[0037] The present application sets the first electrode 121, the active part 131, the second electrode 151 and the gate 171 as closed loop structures, and the first electrode 121, the active part 131 and the second electrode 151 are stacked, with the thickness of the active part 131 as the channel length of the transistor, reducing the channel length of the transistor, and at the same time, the channel width of the transistor is changed to the sum of the length of the inner ring AA and the outer ring BB of the active part, increasing the channel width of the transistor, and improving the device effect of the transistor.

[0038] In the embodiment, the closed loop structure can be a circular ring structure, an elliptical ring structure, or a ring structure in a quadrilateral or triangular shape.

[0039] Referring to FIG. 2 and FIG. 1A to FIG. 1G, the array substrate 100 can include a substrate 110 and a driving circuit layer disposed on the substrate 110, and the driving circuit layer can include a plurality of thin film transistors.

[0040] In the embodiment, the material of the substrate 110 can be glass, quartz, polyimide, or the like.

[0041] In the embodiment, referring to FIG. 2, the array substrate 100 can include a first electrode layer 120, and the material of the first electrode layer 120 can include Cr, W, Ti, Ta, Mo, Al, Cu, or the like, or a single-layer or multi-layer metal structure composed of at least two of the above-mentioned metals; for example, the material of the first electrode layer 120 can be Mo, Mo / Al, Mo / Cu, MoTi / Cu, MoTi / Cu / MoTi, Ti / Al / Ti, Ti / Cu / Ti, Mo / Cu / IZO, IZO / Cu / IZO, Mo / Cu / ITO, or the like.

[0042] In the embodiment, referring to FIG. 2, the array substrate 100 can further include an active layer 130 disposed on a side of the first electrode layer 120 away from the substrate 110, and the active layer 130 includes an active portion 131, and the material of the active layer 130 can be a metal oxide, such as IGZO, IGTO, Ln-IZO, ITZO, ITGZO, HIZO, IZO (InZnO), ZnO:F, In2O3:Sn, In2O3:Mo, Cd2SnO4, ZnO:Al, TiO2:Nb, Cd-Sn-O, or other metal oxides, and the following embodiments of the present application take IGZO as an example for illustration.

[0043] In the embodiment, referring to FIG. 2, the array substrate 100 can further include a buffer layer 140 disposed on the substrate 110, and the material of the buffer layer 140 can include a compound composed of nitrogen, silicon, and oxygen, such as a single-layer silicon oxide film layer, or a laminated structure of silicon oxide, silicon nitride, aluminum oxide, or the like.

[0044] In the embodiment, referring to FIG. 2, the array substrate 100 can further include a second electrode layer 150 disposed on the side of the buffer layer 140 away from the substrate 110. The material of the second electrode layer 150 can include Cr, W, Ti, Ta, Mo, Al, Cu or other metal or a single-layer or multi-layer metal structure composed of at least two of the above-mentioned metals. For example, the material of the second electrode layer 150 can be Mo, Mo / Al, Mo / Cu, MoTi / Cu, MoTi / Cu / MoTi, Ti / Al / Ti, Ti / Cu / Ti, Mo / Cu / IZO, IZO / Cu / IZO, Mo / Cu / ITO, etc.

[0045] In the embodiment, referring to FIG. 2, the buffer layer 140 is provided with an opening 141, and the second electrode 151 is disposed on the surface of the side of the buffer layer 140 away from the substrate 110 and extends into the opening 141, and the second electrode 151 contacts the surface of the side of the active part 131 in the opening 141 away from the substrate 110.

[0046] In the embodiment, referring to FIG. 2, the array substrate 100 can further include a gate insulating layer 160 disposed on the side of the second electrode layer 150 away from the substrate 110. The material of the gate insulating layer 160 can include a compound composed of nitrogen element, silicon element and oxygen element, such as a single-layer silicon oxide, silicon nitride or silicon oxynitride or a multi-layer inorganic film layer.

[0047] In the embodiment, referring to FIG. 2, the array substrate 100 can further include a gate layer 170 disposed on the side of the gate insulating layer 160 away from the substrate 110. The material of the gate layer 170 can include Cr, W, Ti, Ta, Mo, Al, Cu or an alloy composed of at least two of the above-mentioned metals. For example, the material of the gate layer 170 can be Mo, Mo / Al, Mo / Cu, MoTi / Cu, MoTi / Cu / MoTi, Ti / Al / Ti, Ti / Cu / Ti, Mo / Cu / IZO, IZO / Cu / IZO, Mo / Cu / ITO, etc.

[0048] In the embodiment, referring to FIG. 2, the gate insulating layer 160 covers the sidewall and bottom of the opening 141, and the gate 171 is disposed on the side of the gate insulating layer 160 away from the substrate 110. A part of the gate 171 overlaps the second electrode 151, and another part of the gate 171 extends to the sidewall and bottom of the opening 141.

[0049] In the embodiment, referring to FIG. 2, the array substrate 100 can further include a passivation layer 180 disposed on the side of the gate layer 170 away from the substrate 110. The material of the passivation layer 180 can include a compound composed of nitrogen element, silicon element and oxygen element, such as a single-layer silicon oxide, silicon nitride or silicon oxynitride or a multi-layer inorganic film layer.

[0050] In the embodiment, referring to FIG. 2, the array substrate 100 can further include a pixel electrode 190 disposed on the side of the passivation layer 180 away from the substrate 110, and the material of the pixel electrode 190 can include ITO, IZO, ITO / Ag / ITO, IZO / Ag / IZO, Mo / Cu, MoTi / Cu / MoTi.

[0051] Referring to FIG. 2 and FIG. 1A, the first electrode layer 120 includes a first electrode 121, and the first electrode 121 can be a circular ring structure having an outer circle and an inner circle.

[0052] Referring to FIG. 2 and FIG. 1B, the active layer 130 includes an active part 131, and the active part 131 is in direct contact with the first electrode 121. The active part 131 can be a ring structure having an inner side ring AA and an outer side ring BB, for example, the ring structure can be a circular ring structure, and the orthographic projection of the active part 131 on the first electrode layer 120 is located in the first electrode 121.

[0053] Referring to FIG. 2 and FIG. 1C, the second electrode layer 150 includes a second electrode 151, and the second electrode 151 can be a circular ring structure having an outer circle and an inner circle. The orthographic projection of the second electrode 151 on the active layer 130 is located in the active part 131. Meanwhile, the second electrode 151 is in direct contact with the part of the surface of the active part 131 away from the substrate 110, for example, the second electrode 151 is in contact with the end of the active part 131 close to the inner circle, or / and the second electrode 151 is in contact with the end of the active part 131 close to the outer circle.

[0054] In the embodiment, the first electrode 121, the active part 131 and the first electrode 121 are stacked, and the thickness of the active part 131 is used as the channel length of the active part 131, so as to further reduce the channel length of the transistor.

[0055] It should be noted that the first electrode 121 and the second electrode 151 of the present application can be one of the source and the drain of the thin film transistor.

[0056] It should be noted that when the process of the second electrode 151 is performed, the edges of the first electrode 121, the active part 131 and the first electrode 121 can be patterned by using a self-aligned process, so that the edges of the stacked first electrode 121, the active part 131 and the first electrode 121 are located on the same inclined plane, for example, the acute angle between the inclined plane and the substrate 110 can be 30 degrees to 60 degrees.

[0057] Since the first electrode 121 and the second electrode 151 are arranged in a stack, there is a parasitic capacitance between the first electrode 121 and the second electrode 151, and therefore, in order to reduce the parasitic capacitance between the first electrode 121 and the second electrode 151, the first electrode 121 and the second electrode 151 can be provided with a hollow pattern.

[0058] Referring to FIGS. 1A-1D, FIG. 1D is a schematic view of the array substrate of the present application, the first electrode 121 is provided with a plurality of first hollow patterns 121A, and the second electrode 151 is provided with a plurality of second hollow patterns 151A, and the plurality of second hollow patterns 151A are not overlapped with the plurality of first hollow patterns 121A in the orthographic projection of the film layer where the first electrode 121 is located.

[0059] Referring to FIGS. 1A-1D, the plurality of first hollow patterns 121A are arranged at intervals on the first electrode 121, and the plurality of second hollow patterns 151A are arranged at intervals on the second electrode 151, and the plurality of second hollow patterns 151A are arranged at intervals with the plurality of first hollow patterns 121A in the orthographic projection of the film layer where the first electrode 121 is located.

[0060] In the present embodiment, the arrangement of the first hollow pattern 121A and the second hollow pattern 151A reduces the overlapping area of the first electrode 121 and the second electrode 151, and further reduces the parasitic capacitance between the first electrode 121 and the second electrode 151.

[0061] It should be noted that the active part 131 can also be provided with a hollow pattern corresponding to the first hollow pattern 121A or / and the second hollow pattern 151A.

[0062] In the present embodiment, the shape of the first hollow pattern 121A and the second hollow pattern 151A can be oval, circular or quadrilateral, and oval is exemplified in FIGS. 1A-1D.

[0063] In the present embodiment, the area of the first hollow pattern 121A and the area of the second hollow pattern 151A can not be equal, for example, the area of the first hollow pattern 121A is greater than the area of the second hollow pattern 151A, or the area of the first hollow pattern 121A is less than the area of the second hollow pattern 151A.

[0064] In the present embodiment, the area of the first hollow pattern 121A and the area of the second hollow pattern 151A can be equal.

[0065] Referring to FIG. 2, FIG. 1E and FIG. 1F, FIG. 1E is a structure of a gate in an array substrate of the present application, and FIG. 1F is a structure of a gate and an active region in an array substrate of the present application, the gate layer 170 can include a gate 171, the gate 171 includes an inner ring segment 171B located inside the gate 171, an outer ring segment 171A located outside the gate 171, and a connecting segment 171C connecting the inner ring segment 171B and the outer ring segment 171A, the inner ring segment 171B and the outer ring segment are both circular ring structures, and the inner diameter of the inner ring segment 171B is smaller than the inner diameter of the outer ring segment 171A.

[0066] In the embodiment, the width of the inner ring segment 171B and the outer ring segment 171A can be equal.

[0067] In the embodiment, the gate 171 is composed of two circular rings which are spaced apart and connected, and the inner ring segment 171B overlaps with the end of the active region 131 close to the inner side, and the outer ring segment 171A overlaps with the end of the active region 131 close to the outer side, that is, each circular ring overlaps with a part of the active region 131.

[0068] Secondly, in the structure of FIG. 2, the distance between the end of the gate 171 close to the substrate 110 and the substrate 110 is less than or equal to the distance between the active region 131 and the substrate 110, that is, the two ends of the gate 171 need to extend to the side of the substrate 110, and then the orthographic projection of the gate 171 on the side of the active region 131 at least covers the whole side; at the same time, since the gate 171 of the present application has the inner ring segment 171B and the outer ring segment 171A, the end of the active region 131 corresponding to the inner ring segment 171B is an inner ring channel, and the end of the active region 131 corresponding to the outer ring segment 171A is an outer ring channel, that is, the channel length of the active region 131 of the present application is the sum of the circumference of the inner ring channel and the circumference of the outer ring channel, and in the case of reducing the channel length of the active region 131, the channel width of the active region 131 is increased, which further improves the mobility of the thin film transistor in the array substrate 100 of the present application.

[0069] Secondly, since the gate 171 overlaps with the first electrode 121 and the second electrode 151, and there is a parasitic capacitance between the gate 171 and the first electrode 121 and the second electrode 151, in order to reduce the parasitic capacitance between the gate 171 and the first electrode 121 and the second electrode 151, the gate 171 of the present application is provided with two connected circular ring structures.

[0070] Referring to FIG. 1G, which is a cross-sectional view of the array substrate of the present application, the first electrode, the active part, the second electrode and the gate, the first hollow pattern 121A is not overlapped with the inner ring segment 171B and the outer ring segment 171A in the orthographic projection of the gate 171 on the film layer, and the second hollow pattern 151A is not overlapped with the inner ring segment 171B and the outer ring segment 171A in the orthographic projection of the gate 171 on the film layer, that is, the first hollow pattern 121A and the second hollow pattern 151A are both located between the inner ring segment 171B and the outer ring segment 171A.

[0071] Meanwhile, referring to FIG. 1G, the connecting segment 171C is not overlapped with the second hollow pattern 151A in the orthographic projection of the second electrode 151 on the film layer. Referring to FIG. 1G, since the connecting segment 171C is electrically connected with the inner ring segment 171B and the outer ring segment 171A, and the second electrode 151 is provided with a plurality of second hollow patterns 151A, the second hollow pattern 151A exposes the active part 131, if the connecting segment 171C is overlapped with the second hollow part, the voltage on the gate will affect the moving direction of the carriers, and further affect the mobility of the transistor, therefore, the present application makes the connecting segment 171C not overlapped with the second hollow pattern 151A in the orthographic projection of the second electrode 151 on the film layer, which can further improve the stability of the device.

[0072] Referring to FIG. 1G and FIG. 1H, which is a cross-sectional view of the array substrate of the present application, the first electrode and the gate, in order to ensure that the gate 171 fully covers the part of the active part 131 close to the edge, the inner diameter of the inner ring segment 171B of the present application is smaller than the inner diameter of the inner ring of the first electrode 121, and the outer diameter of the outer ring segment 171A is larger than the outer diameter of the outer ring of the first electrode 121.

[0073] In the present embodiment, the difference between the inner diameter of the inner ring of the first electrode 121 and the inner diameter of the inner ring segment 171B ranges from 1 micrometer to 2 micrometers, and the difference between the outer diameter of the outer ring segment 171A and the outer diameter of the outer ring of the first electrode 121 ranges from 1 micrometer to 2 micrometers.

[0074] In the present embodiment, since the first electrode 121, the active part 131 and the second electrode 151 are stacked, the channel length of the active part 131 is the thickness of the active part 131; meanwhile, the inner ring segment 171B and the outer ring segment 171A in the gate 171 make the end part of the active part 131 corresponding to the inner ring segment 171B as the inner ring channel, and the end part of the active part 131 corresponding to the outer ring segment 171A as the outer ring channel, therefore, the channel width of the active part 131 of the present application is the sum of the length of the inner ring segment 171B and the length of the outer ring segment 171A, which increases the channel width of the transistor, and further improves the mobility of the thin film transistor in the array substrate 100 of the present application.

[0075] In the present embodiment, the channel length ranges from 0.05 micrometer to 0.6 micrometer.

[0076] Referring to FIG. 2, the first electrode layer 120 further includes a first conductive block 122 electrically connected with the first electrode 121, the second electrode layer 150 further includes a second conductive block 152 insulated from the second electrode 151, the gate electrode layer 170 further includes a third conductive block 172 insulated from the gate electrode 171, the second conductive block 152 is electrically connected with the first conductive block 122 through a via hole on the passivation layer 180, the third conductive block 172 is electrically connected with the second conductive block 152 through a via hole on the gate insulating layer 160, and the pixel electrode 190 is electrically connected with the third conductive block 172 through a via hole on the passivation layer 180.

[0077] The application further provides a display panel, which comprises the array substrate 100 and a light-emitting component arranged on one side of the array substrate 100, and the array substrate 100 and the light-emitting component are combined into one body.

[0078] For example, when the display panel is a liquid crystal display panel, the structure of the array substrate 100 can serve as an array layer of the liquid crystal display panel; when the display panel is a self-luminous display panel, the structure of the array substrate 100 can serve as an array layer of the self-luminous display panel, and the light-emitting device can be a MiniLED or a MicroLED.

[0079] Referring to FIG. 3, the application provides a manufacturing method of the array substrate 100, which comprises the following steps:

[0080] S10, providing a substrate 110, and forming a first electrode layer 120 comprising a first electrode 121 and a first conductive block 122 on the substrate 110, the first electrode 121 being electrically connected with the first conductive block 122;

[0081] Referring to FIG. 4A, the material of the substrate 110 can be glass, quartz or polyimide, etc.

[0082] In the embodiment, the material of the first electrode layer 120 can comprise Cr, W, Ti, Ta, Mo, Al, Cu or a single-layer or multi-layer metal structure composed of at least two of the above-mentioned metals; for example, the material of the first electrode layer 120 can be Mo, Mo / Al, Mo / Cu, MoTi / Cu, MoTi / Cu / MoTi, Ti / Al / Ti, Ti / Cu / Ti, Mo / Cu / IZO, IZO / Cu / IZO, Mo / Cu / ITO, etc.

[0083] Referring to FIG. 4A and FIG. 1A, the first electrode 121 can be a circular ring structure with an outer circle and an inner circle. A plurality of first hollow patterns 121A are formed on the first electrode 121, and the shape of the first hollow pattern 121A can be an ellipse, a circle or a quadrilateral, which is exemplified by an ellipse in FIG. 1A.

[0084] S20, forming an active layer 130 including an active part 131 on the first electrode layer 120;

[0085] Referring to FIG. 4B and FIG. 1B, the active part 131 is in direct contact with the first electrode 121, and the active part 131 can have a circular ring structure with an outer circle and an inner circle, and a normal projection of the active part 131 on the first electrode layer 120 is located in the first electrode 121.

[0086] In the embodiment, the material of the active layer 130 can be a metal oxide, such as IGZO, IGTO, Ln-IZO, ITZO, ITGZO, HIZO, IZO (InZnO), ZnO:F, In2O3:Sn, In2O3:Mo, Cd2SnO4, ZnO:Al, TiO2:Nb, Cd-Sn-O or other metal oxides, and the following embodiments of the present application take IGZO as an example for illustration.

[0087] S30, forming a buffer layer 140 on the active layer 130;

[0088] Referring to FIG. 4C, the buffer layer 140 is provided with an opening 141 and a first via 142, the opening 141 exposes part of the first electrode 121 and the active part 131 arranged in a stack, and the first via 142 exposes part of the first conductive block 122.

[0089] In the embodiment, the material of the buffer layer 140 can include a compound composed of nitrogen element, silicon element and oxygen element, for example, the material of the buffer layer 140 can include a single-layer silicon oxide film layer, or a stack structure of silicon oxide, silicon nitride, aluminum oxide, etc.

[0090] S40, forming a second electrode layer 150 including a second electrode 151 and a second conductive block 152 on the buffer layer 140;

[0091] Referring to FIG. 4D, the second electrode 151 is overlapped on a surface of the buffer layer 140 away from the substrate 110 and extends into the opening 141, and the second electrode 151 is in contact with a surface of the active part 131 in the opening 141 away from the substrate 110.

[0092] Referring to FIG. 4D and FIG. 1C, the second electrode 151 can have a circular ring structure with an outer circle and an inner circle, and a normal projection of the second electrode 151 on the active layer 130 is located in the active part 131. At the same time, the second electrode 151 is in direct contact with part of the surface of the active part 131 away from the substrate 110; for example, the second electrode 151 is in contact with an end of the active part 131 close to the inner circle, or / and the second electrode 151 is in contact with an end of the active part 131 close to the outer circle; at the same time, the second conductive block 152 is electrically connected with the first conductive block 122 through the first via 142.

[0093] In the present embodiment, the edge of the first electrode 121 and the active portion 131 exceeds the edge of the second electrode 151.

[0094] In the present embodiment, the material of the second electrode layer 150 can be the same as that of the first electrode layer 120.

[0095] S50, the first electrode 121, the second electrode 151 and the active portion 131 arranged in the stack are patterned by using a self-alignment process;

[0096] Referring to FIG. 4E, the first electrode 121, the active portion 131 and the edge of the first electrode 121 are patterned by using a self-alignment process, so that the first electrode 121, the active portion 131 and the edge of the first electrode 121 arranged in the stack are located on the same inclined surface, for example, the acute angle between the inclined surface and the substrate 110 can be 30 to 60 degrees.

[0097] S60, the gate insulating layer 160 is formed on the second electrode layer 150;

[0098] Referring to FIG. 4F, the gate insulating layer 160 covers the sidewall and the bottom of the opening 141, and the second via hole 161 is formed on the gate insulating layer 160, and the material of the gate insulating layer 160 can include a compound composed of nitrogen element, silicon element and oxygen element, for example, single-layer silicon oxide, silicon nitride or silicon oxynitride, or multi-layer inorganic film layers.

[0099] S70, the gate layer 170 including the gate 171 and the third conductive block 172 is formed on the gate insulating layer 160;

[0100] Referring to FIG. 4G, the gate 171 is arranged on the side of the gate insulating layer 160 away from the substrate 110, a part of the gate 171 overlaps the second electrode 151, and another part of the gate 171 extends to the sidewall and the bottom of the opening 141.

[0101] Referring to FIG. 4G and FIG. 1E, the gate 171 includes an inner ring segment 171B located on the inner side of the gate 171, an outer ring segment 171A located on the outer side of the gate 171, and a connecting segment 171C connecting the inner ring segment 171B and the outer ring segment 171A, both the inner ring segment 171B and the outer ring segment 171A are circular ring structures, the inner diameter of the inner ring segment 171B is smaller than that of the outer ring segment 171A, the inner ring segment 171B overlaps the end of the active portion 131 close to the inner side, and the outer ring segment 171A overlaps the end of the active portion 131 close to the outer side; at the same time, the third conductive block 172 is electrically connected with the second conductive block 152 through the second via hole 161.

[0102] Referring to FIG. 1G and FIG. 1H, in order to ensure that the gate 171 fully covers the edge-adjacent part of the active part 131, the inner diameter of the inner ring segment 171B of the gate 171 is smaller than the inner diameter of the inner ring of the first electrode 121, and the outer diameter of the outer ring segment 171A of the gate 171 is larger than the outer diameter of the outer ring of the first electrode 121.

[0103] In the embodiment, the material of the gate layer 170 can include a metal such as Cr, W, Ti, Ta, Mo, Al, Cu, or an alloy composed of at least two of the above-mentioned metals; for example, the material of the gate layer 170 can be Mo, Mo / Al, Mo / Cu, MoTi / Cu, MoTi / Cu / MoTi, Ti / Al / Ti, Ti / Cu / Ti, Mo / Cu / IZO, IZO / Cu / IZO, Mo / Cu / ITO, etc.

[0104] S80, a passivation layer 180 is formed on the gate layer 170, and a third via hole 181 is formed on the passivation layer 180;

[0105] Referring to FIG. 4H, the material of the passivation layer 180 can include a compound composed of nitrogen, silicon, and oxygen, such as a single-layer silicon oxide, silicon nitride, or silicon oxynitride, or a multi-layer inorganic film layer.

[0106] S90, a pixel electrode 190 is formed on the passivation layer 180, and the pixel electrode 190 is electrically connected to the third conductive block 172 through the third via hole 182;

[0107] Referring to FIG. 4I, the material of the pixel electrode 190 can include ITO, IZO, ITO / Ag / ITO, IZO / Ag / IZO, Mo / Cu, MoTi / Cu / MoTi.

[0108] It should be noted that the circular ring structure of the first electrode 121, the active part 131, the second electrode 151, and the gate 171 in the present application is only one embodiment of the present application, and the first electrode 121, the active part 131, the second electrode 151, and the gate 171 can be a closed loop structure, such as a circular ring structure, an elliptical ring structure, or a ring structure in the shape of a quadrilateral or a triangle.

[0109] The present application also provides a mobile terminal, which includes a terminal body and the above-mentioned display panel, and the terminal body and the display panel are combined into one. The terminal body can be a circuit board and other devices bound to the display panel, and a cover plate and the like arranged on the display panel. The mobile terminal can include a mobile phone, a television, a notebook computer, and other electronic devices.

[0110] In the above-mentioned embodiments, the description of each embodiment has its own focus, and the parts not described in detail in a certain embodiment can be referred to the related description of other embodiments.

[0111] The above describes the technical solutions provided by the embodiments of the present application in detail, and the principles and implementation manners of the present application are described by applying specific examples. The above descriptions of the embodiments are only used to help understand the technical solutions of the present application and the core ideas thereof. Those skilled in the art should understand that the technical solutions recorded in the foregoing embodiments can be modified, or some technical features thereof can be replaced equivalently, and the modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. An array substrate, comprising: a substrate; a first electrode disposed on one side of the substrate; an active part disposed on a surface of the first electrode away from the substrate; a second electrode disposed on a surface of the active part away from the substrate; a gate electrode disposed on a side of the second electrode away from the substrate, and the gate electrode at least partially overlaps with the active part; wherein the first electrode, the active part, the second electrode and the gate electrode are in a closed loop structure; the closed loop structure is a circular ring structure or an elliptical ring structure; a plurality of first hollow patterns are formed on the first electrode, and a plurality of second hollow patterns are formed on the second electrode; wherein a normal projection of the plurality of second hollow patterns on a film layer where the first electrode is located is non-overlapped with the plurality of first hollow patterns; the plurality of first hollow patterns are arranged at intervals on the first electrode, and the plurality of second hollow patterns are arranged at intervals on the second electrode; wherein a normal projection of the plurality of second hollow patterns on the film layer where the first electrode is located is arranged at intervals with the plurality of first hollow patterns; the first hollow pattern and the second hollow pattern are in an elliptical shape, a circular shape or a quadrilateral shape; a channel length of the active part is equal to a thickness of the active part, and a channel width of the active part is a sum of a length of an inner ring in the active part and a length of an outer ring in the active part; the channel length ranges from 0.05 microns to 0.6 microns; an end of the gate electrode close to the substrate is spaced apart from the substrate by a distance less than or equal to a distance between the active part and the substrate; the gate electrode comprises an inner ring segment, an outer ring segment and a connecting segment, the inner ring segment is located inside the outer ring segment, the connecting segment connects the inner ring segment and the outer ring segment, and an inner diameter of the inner ring segment is less than an inner diameter of the outer ring segment; a normal projection of the first hollow pattern on a film layer where the gate electrode is located is non-overlapped with the inner ring segment and the outer ring segment, and a normal projection of the second hollow pattern on the film layer where the gate electrode is located is non-overlapped with the inner ring segment and the outer ring segment; the normal projection of the first hollow pattern and the normal projection of the second hollow pattern on the gate electrode layer are both located between the inner ring segment and the outer ring segment; a normal projection of the connecting segment on a film layer where the second electrode is located is non-overlapped with the second hollow pattern; the inner diameter of the inner ring segment is less than an inner diameter of an inner ring of the first electrode, and an outer diameter of the outer ring segment is greater than an outer diameter of an outer ring of the first electrode; a difference between the inner diameter of the inner ring of the first electrode and the inner diameter of the inner ring segment ranges from 1 micron to 2 microns, and a difference between the outer diameter of the outer ring segment and the outer diameter of the outer ring of the first electrode ranges from 1 micron to 2 microns; the inner ring segment and the outer ring segment are equal in width; and the array substrate further comprises a buffer layer disposed on a side of the active part away from the substrate, and the buffer layer is provided with an opening; wherein the second electrode overlaps a surface of the buffer layer away from the substrate and extends into the opening, and the second electrode is in contact with a surface of the active part away from the substrate in the opening. ​ ​ ​ ​ ​ ​ 2. The array substrate according to claim 1, wherein, ​ 3. The array substrate according to claim 2, wherein, ​ ​ 4. The array substrate according to claim 3, wherein, ​ ​ 5. The array substrate according to claim 4, wherein, ​ 6. The array substrate of claim 2, wherein, ​ 7. The array substrate according to claim 2, wherein, ​ 8. The array substrate of claim 2, wherein, ​ 9. The array substrate according to any one of claims 2 to 8, wherein, ​ 10. The array substrate of claim 9, wherein, ​ 11. The array substrate of claim 10, wherein, ​ 12. The array substrate of claim 9, wherein, ​ 13. The array substrate of claim 9, wherein, ​ 14. The array substrate of claim 13, wherein, ​ 15. The array substrate of claim 9, wherein, ​ 16. The array substrate according to any one of claims 2 to 8, wherein, ​ ​ 17. The array substrate of claim 16, wherein, The array substrate further comprises a gate insulating layer disposed on the side of the buffer layer away from the substrate, the gate insulating layer covering the sidewall and the bottom of the opening, the gate disposed on the side of the gate insulating layer away from the substrate, a part of the gate overlapping the second electrode, and another part of the gate extending to the sidewall and the bottom of the opening.

18. A display panel comprising an array substrate and a light-emitting member located on one side of the array substrate, the array substrate and the light-emitting member being combined into one body; wherein, The array substrate comprises: a substrate; a first electrode disposed on one side of the substrate; an active part disposed on the surface of the first electrode away from the substrate; a second electrode disposed on the surface of the active part away from the substrate; a gate disposed on the side of the second electrode away from the substrate, and the gate at least partially overlapping the active part; wherein the first electrode, the active part, the second electrode and the gate are in a closed loop structure.

19. The display panel of claim 18, wherein, The closed loop structure is a circular ring structure or an elliptical ring structure.

20. The display panel of claim 19, wherein, A plurality of first hollow patterns are formed on the first electrode, and a plurality of second hollow patterns are formed on the second electrode; wherein the orthographic projection of the plurality of second hollow patterns on the film layer where the first electrode is located is non-overlapping with the plurality of first hollow patterns.

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