Array substrate, display panel, and display apparatus

Abstract

Disclosed in the present invention are an array substrate, a display panel, and a display apparatus. The array substrate comprises: a plurality of data lines, a plurality of gate lines and a plurality of pixel electrodes, wherein the plurality of pixel electrodes comprise: a plurality of first-type pixel electrodes and a plurality of second-type pixel electrodes; between an Nth group of gate lines and an (N+1)th group of gate lines, the first-type pixel electrodes are electrically connected to second gate lines in the Nth group of gate lines by means of a transistor, and the second-type pixel electrodes are electrically connected to first gate lines in the (N+1)th group of gate lines by means of the transistor; there is a first overlapping region between orthographic projections of the first-type pixel electrodes on a base and an orthographic projection of a common trace on the base; there is a second overlapping region between orthographic projections of the second-type pixel electrodes on the base and the orthographic projection of the common trace on the base; and the area of the first overlapping region is larger than that of the second overlapping region.

Description

Array substrate, display panel and display device

[0001] Cross-reference to related applications

[0002] The present application claims priority to the Chinese patent application No. 202411120504.7, filed on August 15, 2024, and entitled "Array substrate, display panel and display device", the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0003] The present disclosure relates to the technical field of display, and in particular, to an array substrate, a display panel and a display device. BACKGROUND

[0004] There are various commonly used display modes for thin film transistor-liquid crystal display (TFT-LCD), such as twisted nematic (TN) display mode, vertically alignment (VA) display mode, fringe field switching (FFS) display mode, and in-plane switching (IPS) display mode. Among them, the VA mode has better dark state performance and better contrast ratio than other display modes. SUMMARY

[0005] The present disclosure provides an array substrate, a display panel and a display device. The array substrate comprises:

[0006] a substrate;

[0007] a plurality of data lines, and a plurality of transistors;

[0008] a plurality of gate lines located on one side of the substrate, the plurality of gate lines comprising: a plurality of gate line groups extending along a first direction, each gate line group comprising: a first gate line and a second gate line extending along the first direction, and in an Nth gate line group, the first gate line is located on a side of the second gate line away from an N+1th gate line group;

[0009] a plurality of pixel electrodes, the plurality of pixel electrodes comprising: a plurality of first type pixel electrodes, and a plurality of second type pixel electrodes; between the Nth gate line group and the N+1th gate line group, the first type pixel electrodes are electrically connected to the second gate line in the Nth gate line group through the transistors, and the second type pixel electrodes are electrically connected to the first gate line of the N+1th gate line group through the transistors;

[0010] a plurality of common lines;

[0011] The first type of pixel electrode has a first projection on the substrate, and the first projection of the first type of pixel electrode has a first overlapping area with a projection of the common line on the substrate. The second type of pixel electrode has a second projection on the substrate, and the second projection of the second type of pixel electrode has a second overlapping area with the projection of the common line on the substrate. The first overlapping area has a larger area than the second overlapping area.

[0012] In a possible implementation, the plurality of common lines includes a first common compensation line extending along the first direction, and the first common compensation line has a projection on the substrate, and the projection of the first common compensation line on the substrate overlaps with an edge area of the projection of the first type of pixel electrode on the substrate.

[0013] In a possible implementation, the plurality of common lines includes a first common line extending along the second direction, and the first common line has a projection on the substrate, and the projection of the first common line on the substrate overlaps with a gap between the first type of pixel electrode and the second type of pixel electrode on the substrate.

[0014] The first common line has a projection on the substrate, and an overlapping area of the projection of the first common line on the substrate with the projection of the second type of pixel electrode on the substrate is smaller than an overlapping area of the projection of the first common line on the substrate with the projection of the first type of pixel electrode on the substrate.

[0015] In a possible implementation, the first type of pixel electrode has a first pixel outer edge on a side facing the first common line, and the second type of pixel electrode has a second pixel outer edge on a side facing the first common line.

[0016] The first common line has a first outer edge extending along the second direction, and a second outer edge. The first outer edge has a projection on the substrate, and the projection of the first outer edge on the substrate overlaps with the projection of the first type of pixel electrode on the substrate. The second outer edge has a projection on the substrate, and the projection of the second outer edge on the substrate overlaps with the projection of the second type of pixel electrode on the substrate.

[0017] The second outer edge has a projection on the substrate, and a distance between the projection of the second outer edge on the substrate and the projection of the second pixel outer edge on the substrate is smaller than a distance between the projection of the first outer edge on the substrate and the projection of the first pixel outer edge on the substrate.

[0018] In a possible implementation, the plurality of common lines comprises: a second common line extending along the second direction; the second common line comprises: a first sub-common line extending along the second direction, and a second sub-common line extending along the second direction; the first sub-common line and the second sub-common line in the same second common line are located on two sides of the data line in the orthographic projection of the substrate;

[0019] The first sub-common line has a first sub-outer edge away from a side of the data line, and the second sub-common line has a second sub-outer edge away from a side of the data line; the minimum distance between the first sub-outer edge in the orthographic projection of the substrate and the data line in the orthographic projection of the substrate is less than the minimum distance between the second sub-outer edge in the orthographic projection of the substrate and the data line in the orthographic projection of the substrate.

[0020] In a possible implementation, the width of the first sub-common line in the first direction is less than the width of the second sub-common line in the first direction.

[0021] In a possible implementation, the minimum distance between the orthographic projection of the first type of pixel electrode on the substrate and the orthographic projection of the second gate line electrically connected on the substrate is greater than the minimum distance between the orthographic projection of the second type of pixel electrode on the substrate and the orthographic projection of the first gate line electrically connected on the substrate.

[0022] In a possible implementation, between the Nth gate line group and the N+1th gate line group, the first type of pixel electrode has a third pixel outer edge facing the second gate line in the Nth gate line group; the second type of pixel electrode has a fourth pixel outer edge facing the first gate line in the N+1th gate line group.

[0023] The third outer edge extension line in the orthographic projection of the substrate overlaps with the orthographic projection of the second type of pixel electrode on the substrate; and the fourth outer edge extension line in the orthographic projection of the substrate does not overlap with the orthographic projection of the first type of pixel electrode on the substrate.

[0024] In a possible implementation, the second gate line in the Nth gate line group has a first notch in a region opposite to the first type of pixel electrode; and the first gate line in the N+1th gate line group has a first protrusion in a region opposite to the second type of pixel electrode.

[0025] In a possible implementation, the length of the first notch in the first direction is greater than or equal to the length of the first type of pixel electrode in the first direction; and the length of the first notch in the second direction is less than the width of the second gate line in the second direction.

[0026] The length of the first protrusion in the first direction is less than or equal to the length of the second pixel electrode in the first direction.

[0027] In a possible implementation, the transistor includes a plurality of first transistors and a plurality of second transistors; the first pixel electrode is electrically connected to the gate line and the data line through the first transistor, and the second pixel electrode is electrically connected to the gate line and the data line through the second transistor.

[0028] The transistor includes a first electrode electrically connected to the pixel electrode; the first electrode includes a first part extending in the first direction; in the first transistor, the projection of the gate line on the substrate that is electrically connected to the first transistor has a first spacing with the projection of the first part on the substrate; in the second transistor, the projection of the gate line on the substrate that is electrically connected to the second transistor has a second spacing with the projection of the first part on the substrate; the first spacing is greater than the second spacing.

[0029] In a possible implementation, the plurality of pixel electrodes further include a third pixel electrode; between the Nth gate line group and the N+1th gate line group, part of the third pixel electrode is electrically connected to the second gate line in the Nth gate line group through the transistor, and part of the third pixel electrode is electrically connected to the first gate line in the N+1th gate line group through the transistor.

[0030] The light-emitting wavelength range of the region where the first pixel electrode is located is greater than the light-emitting wavelength range of the region where the second pixel electrode is located; the light-emitting wavelength range of the region where the second pixel electrode is located is greater than the light-emitting wavelength range of the region where the third pixel electrode is located.

[0031] In a possible implementation, the array substrate includes a plurality of periodically arranged pixel electrode units; the pixel electrode unit includes a first pixel electrode, a second pixel electrode, a third pixel electrode, a fourth pixel electrode, a fifth pixel electrode, a sixth pixel electrode, a seventh pixel electrode, an eighth pixel electrode, a ninth pixel electrode, a tenth pixel electrode, an eleventh pixel electrode, and a twelfth pixel electrode.

[0032] The first pixel electrode is located in the nth row and the mth column and is electrically connected to the second gate line of the Nth gate line group and the M+1th data line.

[0033] The second pixel electrode is located in the nth row and the m+1th column and is electrically connected to the first gate line of the N+1th gate line group and the M+1th data line.

[0034] The third pixel electrode is located at the n-th row and the m+2-th column, and is electrically connected to the second gate line of the N-th gate line group and the M+2-th data line;

[0035] The fourth pixel electrode is located at the n-th row and the m+3-th column, and is electrically connected to the first gate line of the N+1-th gate line group and the M+2-th data line;

[0036] The fifth pixel electrode is located at the n-th row and the m+4-th column, and is electrically connected to the first gate line of the N+1-th gate line group and the M+3-th data line;

[0037] The sixth pixel electrode is located at the n-th row and the m+5-th column, and is electrically connected to the second gate line of the N-th gate line group and the M+3-th data line;

[0038] The seventh pixel electrode is located at the n+1-th row and the m-th column, and is electrically connected to the second gate line of the N+1-th gate line group and the M-th data line;

[0039] The eighth pixel electrode is located at the n+1-th row and the m+1-th column, and is electrically connected to the first gate line of the N+2-th gate line group and the M-th data line;

[0040] The ninth pixel electrode is located at the n+1-th row and the m+2-th column, and is electrically connected to the second gate line of the N+1-th gate line group and the M+1-th data line;

[0041] The tenth pixel electrode is located at the n+1-th row and the m+3-th column, and is electrically connected to the first gate line of the N+2-th gate line group and the M+1-th data line;

[0042] The eleventh pixel electrode is located at the n+1-th row and the m+4-th column, and is electrically connected to the first gate line of the N+2-th gate line group and the M+2-th data line;

[0043] The twelfth pixel electrode is located at the n+1-th row and the m+5-th column, and is electrically connected to the second gate line of the N+1-th gate line group and the M+2-th data line;

[0044] The first type of pixel electrode includes the fourth pixel electrode, the sixth pixel electrode, the ninth pixel electrode and the twelfth pixel electrode; the second type of pixel electrode includes the second pixel electrode, the fifth pixel electrode, the eighth pixel electrode and the eleventh pixel electrode; and the third type of pixel electrode includes the first pixel electrode, the fourth pixel electrode, the seventh pixel electrode and the tenth pixel electrode.

[0045] The display panel provided by the embodiments of the present disclosure includes the array substrate provided by the embodiments of the present disclosure, and further includes an opposite substrate arranged opposite to the array substrate, wherein the opposite substrate includes a common electrode layer.

[0046] The display device provided by the embodiments of the present disclosure includes the display panel provided by the embodiments of the present disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0047] FIG. 1 is a schematic diagram of a pixel architecture provided by the embodiments of the present disclosure;

[0048] FIG. 2A is a schematic diagram of an R pixel affected by a feed though voltage;

[0049] FIG. 2B is a schematic diagram of a G pixel affected by a feed though voltage;

[0050] FIG. 2C is a schematic diagram of a B pixel affected by a feed though voltage;

[0051] FIG. 3A is a schematic diagram of an array substrate provided by the embodiments of the present disclosure;

[0052] FIG. 3B is an enlarged schematic diagram of a dashed line with a width of S1 in FIG. 3A;

[0053] FIG. 3C is an enlarged schematic diagram of a dashed line with a width of S2 in FIG. 3A;

[0054] FIG. 3D is a schematic diagram of a single film layer of a layer where a gate line is located in FIG. 3A;

[0055] FIG. 3E is a schematic diagram of a single film layer of a layer where a data line is located in FIG. 3A;

[0056] FIG. 3F is a schematic diagram of a single film layer of a layer where a pixel electrode is located in FIG. 3A;

[0057] FIG. 3G is a schematic diagram of a pixel architecture corresponding to FIG. 3A;

[0058] FIG. 4A is a schematic diagram of an array substrate provided by the embodiments of the present disclosure;

[0059] FIG. 4B is a schematic diagram of a single film layer of a layer where a pixel electrode is located in FIG. 4A;

[0060] FIG. 5A is a schematic diagram of an array substrate provided by the embodiments of the present disclosure;

[0061] FIG. 5B is a schematic diagram of a single film layer of a layer where a gate line is located in FIG. 5A;

[0062] FIG. 6 is a schematic diagram of an array substrate provided by the embodiments of the present disclosure. DETAILED DESCRIPTION

[0063] In order to make the objectives, technical solutions and advantages of the embodiments of the present disclosure clearer, the following will clearly and completely describe the technical solutions of the embodiments of the present disclosure with reference to the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are some but not all of the embodiments of the present disclosure. Based on the described embodiments of the present disclosure, all other embodiments obtained by a person of ordinary skill in the art without creative effort belong to the scope of the present disclosure.

[0064] Unless otherwise defined, technical terms or scientific terms used in the present disclosure shall have the ordinary meanings as understood by a person of ordinary skill in the art to which the present disclosure pertains. The terms "first", "second" and similar terms used in the present disclosure do not denote any order, quantity or importance, but are used to distinguish different components. The terms "include", "comprise" and similar terms mean that the elements or objects before the terms encompass the elements or objects listed after the terms and their equivalents, and do not exclude other elements or objects. The terms "connect" or "connected" or similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms "upper", "lower", "left", "right" and the like are used only to represent relative positional relationships, and when the absolute positions of the described objects are changed, the relative positional relationships can also be changed accordingly.

[0065] As used herein, "about" or "approximately" includes the recited value and means within an acceptable range of deviation for a particular value as determined by one of ordinary skill in the art to be considered equivalent in the context of measuring the value and the error associated with measuring the particular quantity (i.e., limitations of the measurement system). For example, "about" can mean a difference within one or more standard deviations, or within ± 30%, 20%, 10%, 5% of the recited value.

[0066] In the drawings, the thicknesses of layers, films, panels, regions, etc., can be exaggerated for clarity. Descriptive terminology such as "above", "below", "left", "right", "upper", "lower", "up", "down", "top" and "bottom" are used for clarity in describing the illustrative embodiments. Such terminology can not necessarily be a reflection of actual relative or absolute positioning. Accordingly, the embodiments described herein should not be construed as limited to the particular form illustrated.

[0067] In order to keep the following description of the embodiments of the present disclosure clear and brief, the present disclosure omits the detailed description of known functions and known components.

[0068] In the design of dual gate, due to its special pixel architecture, as shown in Figure 1, part of the pixels (for example, red pixels R in Figure 1) are all connected by odd-numbered row gate lines, part (for example, green pixels G) are all connected by even-numbered row gate lines, and the other part of the pixels (for example, blue pixels B) are connected by both odd-numbered and even-numbered row gate lines; when working normally, due to the coupling effect of the capacitor, after the R pixel is charged, when the gate line of the next row is opened, due to the close distance between the gate line of the next row and the pixel of the current row, the pixel voltage will be reduced due to the capacitive coupling, for example, as shown in Figure 1, when the gate line of the Nth row is opened, the R pixel connected with the gate line of the Nth row in the n row pixel electrode is charged, after the charging is completed, the gate line of the N+1th row is opened, due to the close distance between the gate line of the N+1th row and the n row pixel electrode, the pixel voltage will be reduced due to the capacitive coupling, as shown in Figure 2A, wherein G(N) represents the voltage of the gate line of the Nth row, G(N+1) represents the voltage of the gate line of the N+1th row, Data represents the voltage loaded by the data line, and the broken line Z represents the voltage loaded on the liquid crystal; after the G pixel is charged, because it is far away from the gate line of the next row (there is a gate line between them), when the gate line of the next row is opened, the coupling effect is very small, for example, as shown in Figure 1, when the gate line of the N+1th row is opened, the G pixel connected with the gate line of the N+1th row in the n row pixel electrode is charged, after the charging is completed, the gate line of the N+2th row is opened, due to the far distance between the gate line of the N+2th row and the n row pixel electrode (there is a gate line between them), the capacitive coupling effect is very small, as shown in Figure 2B; after the B pixel is charged, half of the pixels are connected with the odd-numbered row gate lines, and the other half of the pixels are connected with the even-numbered row gate lines, when the charging is completed, when the gate line of the next row is scanned, half of the pixels are affected by the gate line coupling capacitor, and the pixel voltage will change, as shown in Figure 2C, that is, due to the different feed through voltages of the R, G and B pixels (R>B>G), the optimal common voltage (VCOM) required by the R, G and B pixels is inconsistent, an additional electric field is formed, which leads to the occurrence of residual image.

[0069] Therefore, in combination with Figures 3A-3G, wherein Figure 3B is an enlarged schematic view of the dashed line width S1 in Figure 3A, Figure 3C is an enlarged schematic view of the dashed line width S2 in Figure 3A, Figure 3D is a single film layer schematic view of the layer where the gate line is located, Figure 3E is a single film layer schematic view of the layer where the data line is located, Figure 3F is a single film layer schematic view of the layer where the pixel electrode is located, and Figure 3G is a schematic view of the pixel architecture corresponding to Figure 3A, the embodiment of the present application provides an array substrate, which comprises:

[0070] a substrate 1;

[0071] a plurality of data lines 2, and a plurality of transistors T;

[0072] a plurality of gate lines 30 located on one side of the substrate 1, the plurality of gate lines 30 comprising a plurality of gate line groups 3 extending along the first direction X, the gate line groups 3 comprising a first gate line 31 and a second gate line 32 extending along the first direction X, and in the Nth gate line group 3, the first gate line 31 is located on the side of the second gate line 32 away from the N+1th gate line group 3; that is, in the scanning sequence direction of the gate lines 30, the scanning signal is first loaded on the first gate line 31 and then loaded on the second gate line 32;

[0073] a plurality of pixel electrodes 4, the plurality of pixel electrodes 4 comprising a plurality of first-type pixel electrodes 41 and a plurality of second-type pixel electrodes 42; between the Nth gate line group 3 and the N+1th gate line group 3, the first-type pixel electrodes 41 are electrically connected to the second gate line 32 in the Nth gate line group 3 through a transistor T, and the second-type pixel electrodes 42 are electrically connected to the first gate line 31 of the N+1th gate line group 3 through a transistor T;

[0074] a plurality of common lines 5;

[0075] wherein the orthogonal projection of the first-type pixel electrodes 41 on the substrate 1 has a first overlapping area with the orthogonal projection of the common lines 5 on the substrate 1, and the orthogonal projection of the second-type pixel electrodes 42 on the substrate 1 has a second overlapping area with the orthogonal projection of the common lines 5 on the substrate 1; the area of the first overlapping area is greater than the area of the second overlapping area.

[0076] In the embodiments of the present disclosure, the orthogonal projection of the first-type pixel electrodes 41 on the substrate 1 has a first overlapping area with the orthogonal projection of the common lines 5 on the substrate 1, and the orthogonal projection of the second-type pixel electrodes 42 on the substrate 1 has a second overlapping area with the orthogonal projection of the common lines 5 on the substrate 1; the area of the first overlapping area is greater than the area of the second overlapping area, so as to compensate for the difference in the Feed though voltage wherein Clc is the liquid crystal capacitance of the pixel, Cst is the storage capacitance of the pixel, Cgsself is the capacitance between the pixel electrode and the connected gate line, Cgs other is the capacitance between the pixel electrode and the adjacent next gate line, the storage capacitance Cst of the first-type pixel electrodes 41 is increased by compensation design, and the storage capacitance Cst of the second-type pixel electrodes 42 is reduced by design, the storage capacitances of different pixel electrodes are designed differently, the difference in the Feed though voltage of different pixel electrodes is reduced, and then the residual image problem caused by the difference in the Feed though voltage is improved.

[0077] In a possible implementation, in combination with FIG. 3A, the plurality of pixel electrodes 4 further comprises: a third pixel electrode 43; between the Nth gate line group 3 and the N+1th gate line group 3, part of the third pixel electrode 43 is electrically connected to the second gate line 32 in the Nth gate line group 3 through the transistor T, and part of the third pixel electrode 43 is electrically connected to the first gate line 31 of the N+1th gate line group 3 through the transistor T3; the light-emitting wavelength range of the region where the first type of pixel electrode 41 is located is greater than the light-emitting wavelength range of the region where the second type of pixel electrode 42 is located; the light-emitting wavelength range of the region where the second type of pixel electrode 42 is located is greater than the light-emitting wavelength range of the region where the third pixel electrode 43 is located. The first type of pixel electrode 41 can be a pixel electrode of a red pixel, the second type of pixel electrode 42 can be a pixel electrode of a green pixel, and the third type of pixel electrode 43 can be a pixel electrode of a blue pixel. In the embodiment of the present disclosure, since the first type of pixel electrode 41 is subjected to the maximum Feed though voltage, the second type of pixel electrode 42 is subjected to the minimum Feed though voltage, and the third type of pixel electrode 43 is subjected to the medium Feed though voltage, therefore, by reducing the influence of the Feed though voltage on the first type of pixel electrode 41 and increasing the influence of the Feed though voltage on the second type of pixel electrode 42, the influence of the Feed though voltage on the three can be made roughly the same, thereby improving the problem of display residual image.

[0078] Optionally, every two pixel electrodes 4 can be located in a region formed by the intersection of a gate line group 3 and a data line 2, the two pixel electrodes 4 can be connected to the same data line 2 but different gate lines 30, one of the pixel electrodes 4 can be located on the side away from the data line 2 to which the other pixel electrode 4 is electrically connected, as a long pixel, and the other as a short pixel.

[0079] In specific implementation, since the common wire 5 can have multiple lines, the first type of pixel electrode 41 in the orthographic projection on the substrate 1 forms a first overlapping area with the orthographic projection of the common wire 5 on the substrate 1, which can be a combination of multiple overlapping areas, for example, as shown in FIG. 3A, the multiple common wires 5 include the third common wire 53 extending along the first direction X, and also include the first common wire 51 and the second common wire 52 extending along the second direction Y, and the first overlapping area can include: the overlapping area of the first type of pixel electrode 41 and the third common wire 53, the overlapping area of the first type of pixel electrode 41 and the first common wire 51, and the overlapping area of the first type of pixel electrode 41 and the third common wire 53; similarly, the second type of pixel electrode 42 in the orthographic projection on the substrate 1 forms a second overlapping area with the orthographic projection of the common wire 5 on the substrate 1, which can also be a combination of multiple overlapping areas.

[0080] In a possible implementation, as shown in FIG. 3A, the plurality of common lines 5 includes: a first common compensation line 50 extending along the first direction X; and a projection of the first common compensation line 50 on the substrate 1 overlaps with an edge region of the first type of pixel electrode 41 in a projection of the substrate 1. In the embodiment of the present disclosure, by arranging the first common compensation line 50, the overlapping area between the first type of pixel electrode 41 and the common line 5 can be increased, and thus the storage capacitance Cst of the first type of pixel electrode 41 can be increased, and the Feed though voltage difference between different pixel electrodes can be reduced. Moreover, the first common compensation line 50 is located at the edge region of the first type of pixel electrode 41 in the projection of the substrate 1, and thus the influence of the first common compensation line 50 on normal display can be reduced. For example, if the first common compensation line 50 is metal, if the first common compensation line 50 is arranged in the middle region of the pixel, the normal display of the pixel will be affected or the pixel opening area will be reduced.

[0081] In a possible implementation, as shown in FIG. 3A, the first common compensation line 50 arranged in the region of the first type of pixel electrode 41 can be located on a side of the third common line 53 away from the second gate line 32 to which the first type of pixel electrode 41 is electrically connected.

[0082] In a possible implementation, as shown in FIG. 3A, the transistor T further includes a first pole (which can be a drain pole), the first pole including: a first part TA1 extending along the first direction X, a second part TA2 extending along the second direction Y, and a third part TA3 connected to an end of the second part TA2; and the first common compensation line 50 arranged in the region of the first type of pixel electrode 41 can be located on a side of the first part TA1 in the projection of the substrate 1 away from the second gate line 32 to which the first type of pixel electrode 41 is electrically connected.

[0083] Optionally, as shown in FIG. 3A, in the region of the first type of pixel electrode 41, the region of the second type of pixel electrode 42, and the region of the third type of pixel electrode 43, only the region of the first type of pixel electrode 41 can be provided with the first common compensation line 50, that is, the region of the second type of pixel electrode 42 and the region of the third type of pixel electrode 43 can not be provided with the first common compensation line 50.

[0084] In a possible implementation, as shown in FIG. 3A, a projection of the first common line 51 on the substrate 1 overlaps with a gap between the first type of pixel electrode 41 and the second type of pixel electrode 42 in a projection of the substrate 1; and an overlapping area of the first common line 51 on the substrate 1 with the second type of pixel electrode 42 in the projection of the substrate 1 is less than an overlapping area of the first common line 51 on the substrate with the first type of pixel electrode 41 in the projection of the substrate 1.

[0085] In a possible implementation, as shown in FIG. 3B, the first type of pixel electrode 41 has a first pixel outer edge w1 on a side facing the first common line 51; the second type of pixel electrode 42 has a second pixel outer edge w2 on a side facing the first common line 51; the first common line 51 has a first outer edge v1 extending along the second direction Y and a second outer edge v2; the first outer edge v1 in the orthographic projection of the substrate 1 overlaps the first type of pixel electrode 41 in the orthographic projection of the substrate 1, and the second outer edge v2 in the orthographic projection of the substrate 1 overlaps the second type of pixel electrode 42 in the orthographic projection of the substrate 1; the spacing a1 between the second outer edge v2 in the orthographic projection of the substrate 1 and the second pixel outer edge w2 in the orthographic projection of the substrate 1 is smaller than the spacing a2 between the first outer edge v1 in the orthographic projection of the substrate 1 and the first pixel outer edge w1 in the orthographic projection of the substrate 1. In the embodiment of the present disclosure, the first common line 51 can be inwardly recessed toward the side of the second type of pixel electrode 42, thereby reducing the overlapping area of the first common line 51 and the second type of pixel electrode 42, and further reducing the overlapping area of the common line 5 and the second type of pixel electrode 42.

[0086] In a possible implementation, as shown in FIGS. 3A and 3C, the plurality of common lines 5 includes a second common line 52 extending along the second direction Y; the second common line 52 includes a first sub-common line 521 extending along the second direction Y and a second sub-common line 522; the first sub-common line 521 and the second sub-common line 522 in the same second common line 52 are located on both sides of the data line 2 in the orthographic projection of the substrate 1; the first sub-common line 521 has a first sub-outer edge f1 away from the data line 2 on one side, and the second sub-common line 522 has a second sub-outer edge f2 away from the data line 2 on one side; the minimum spacing a3 between the first sub-outer edge f1 in the orthographic projection of the substrate 1 and the data line 2 in the orthographic projection of the substrate 1 is smaller than the minimum spacing a4 between the second sub-outer edge f2 in the orthographic projection of the substrate 1 and the data line 2 in the orthographic projection of the substrate 1. In the embodiment of the present disclosure, the first sub-common line 521 can be inwardly recessed toward the side of the second type of pixel electrode 42, thereby reducing the overlapping area of the second common line 51 and the second type of pixel electrode 42, and further reducing the overlapping area of the common line 5 and the second type of pixel electrode 42.

[0087] In a possible implementation, as shown in FIGS. 3A and 3C, the width b1 of the first sub-common line 521 in the first direction X is smaller than the width b2 of the second sub-common line 522 in the first direction X.

[0088] In the embodiments of the present disclosure, as shown in FIGS. 3A-3C, by increasing the first common compensation line 50, thereby increasing the overlapping area of the first type of pixel electrode 41 and the common wire 5, and inwardly shrinking the common wire 5 overlapping with the second type of pixel electrode 42, thereby reducing the overlapping area of the common wire 5 and the second type of pixel electrode 42, and further reducing the Feed though voltage difference between the first type of pixel electrode 41 and the second type of pixel electrode 42.

[0089] In the embodiments of the present disclosure, as shown in FIGS. 3A-3C, by improving the pattern of the layer where the common wire 5 is located, the overlapping area of the first type of pixel electrode 41 and the common wire 5 can be increased, and the overlapping area of the common wire 5 and the second type of pixel electrode 42 can be reduced. In specific implementation, the pattern of the layer where the pixel electrode 4 is located can also be improved to increase the overlapping area of the first type of pixel electrode 41 and the common wire 5, and reduce the overlapping area of the common wire 5 and the second type of pixel electrode 42. For example, the edge of the second type of pixel electrode 42 towards the first common wire 51 can be inwardly shrunk, and the edge of the second type of pixel electrode 42 towards the first sub-common wire 521 can be inwardly shrunk, thereby also reducing the overlapping area of the common wire 5 and the second type of pixel electrode 42.

[0090] In a possible implementation, as shown in FIGS. 3A-3F, the plurality of common wires 5 can be of the same layer and material as the gate lines 30.

[0091] In a possible implementation, as shown in FIGS. 4A and 4B, FIG. 4B is a single film layer schematic diagram of the layer where the pixel electrode is located in FIG. 4A. The minimum distance c1 between the orthogonal projection of the first type of pixel electrode 41 on the substrate 1 and the orthogonal projection of the electrically connected second gate line 32 on the substrate 1 is greater than the minimum distance c2 between the orthogonal projection of the second type of pixel electrode 42 on the substrate 1 and the orthogonal projection of the electrically connected first gate line 31 on the substrate 1. Because the Feed though voltage difference between the first type of pixel electrode 41 and the second type of pixel electrode 42 is caused by the Feed though voltage difference between the first gate line 31 and the second gate line 32, the minimum distance c1 between the orthogonal projection of the first type of pixel electrode 41 on the substrate 1 and the orthogonal projection of the electrically connected second gate line 32 on the substrate 1 is greater than the minimum distance c2 between the orthogonal projection of the second type of pixel electrode 42 on the substrate 1 and the orthogonal projection of the electrically connected first gate line 31 on the substrate 1, thereby reducing the Feed though voltage difference between the first type of pixel electrode 41 and the second type of pixel electrode 42. In the embodiments of the present disclosure, by making the minimum distance c1 between the orthogonal projection of the first type of pixel electrode 41 on the substrate 1 and the orthogonal projection of the electrically connected second gate line 32 on the substrate 1 greater than the minimum distance c2 between the orthogonal projection of the second type of pixel electrode 42 on the substrate 1 and the orthogonal projection of the electrically connected first gate line 31 on the substrate 1, that is, by making the distance between the first type of pixel electrode 41 and the electrically connected second gate line 32 far away, and making the distance between the second type of pixel electrode 42 and the electrically connected first gate line 31 close, the Cgs of the first type of pixel electrode 41 can be increased, and the Cgs of the second type of pixel electrode 42 can be reduced, thereby reducing the Feed though voltage difference between different pixel electrodes, and further improving the residual image problem caused by the Feed though voltage difference.

[0092] In a possible implementation, as shown in FIG. 4A and FIG. 4B, between the Nth group of gate lines 3 and the (N+1)th group of gate lines 3, the first type of pixel electrode 41 has a third pixel outer edge w3 facing the second gate line 32 in the Nth group of gate lines; the second type of pixel electrode 42 has a fourth pixel outer edge w4 facing the first gate line 31 in the (N+1)th group of gate lines; the extended line of the third outer edge w3 in the orthographic projection of the substrate 1 overlaps the orthographic projection of the second type of pixel electrode 42 on the substrate 1; the extended line of the fourth outer edge w4 in the orthographic projection of the substrate 1 does not overlap the orthographic projection of the first type of pixel electrode 41 on the substrate 1. In the embodiments of the present disclosure, the pattern of the layer on which the pixel electrode 4 is located can be improved to achieve that the minimum distance c1 between the orthographic projection of the first type of pixel electrode 41 on the substrate 1 and the orthographic projection of the second gate line 32 electrically connected on the substrate 1 is greater than the minimum distance c2 between the orthographic projection of the second type of pixel electrode 42 on the substrate 1 and the orthographic projection of the first gate line 31 electrically connected on the substrate 1, thereby reducing the Feed though voltage difference of different pixel electrodes.

[0093] In a possible implementation, as shown in FIG. 5A and FIG. 5B, FIG. 5B can be a single film layer schematic diagram of the layer on which the gate lines are located, the second gate line 32 in the Nth group of gate lines 3 has a first notch Q in the area opposite to the first type of pixel electrode 41; the first gate line 31 in the (N+1)th group of gate lines 3 has a first protrusion P in the area opposite to the second type of pixel electrode 42. In the embodiments of the present disclosure, the pattern of the layer on which the gate lines 30 are located can be improved to achieve that the minimum distance c1 between the orthographic projection of the first type of pixel electrode 41 on the substrate 1 and the orthographic projection of the second gate line 32 electrically connected on the substrate 1 is greater than the minimum distance c2 between the orthographic projection of the second type of pixel electrode 42 on the substrate 1 and the orthographic projection of the first gate line 31 electrically connected on the substrate 1, thereby reducing the Feed though voltage difference of different pixel electrodes.

[0094] In a possible implementation, as shown in FIG. 5A and FIG. 5B, the length d1 of the first notch Q in the first direction X is greater than or equal to the length d2 of the first type of pixel electrode 41 in the first direction X; the length d3 of the first notch Q in the second direction Y is less than the width d4 of the second gate line 32 in the second direction Y; the length d5 of the first protrusion P in the first direction X is less than or equal to the length d6 of the second type of pixel electrode 42 in the first direction X.

[0095] In a possible implementation, as shown in FIG. 5A and FIG. 5B, the length d1 of the first notch Q in the first direction X can be less than the sum d7 of the lengths of the first type of pixel electrode 41 and the second type of pixel electrode 42 in the first direction X. In a possible implementation, the length d1 of the first notch Q in the first direction X can also be less than the length d2 of the first type of pixel electrode 41 in the first direction X.

[0096] In a possible implementation, referring to FIG. 6, the transistor T includes a plurality of first transistors T1 and a plurality of second transistors T2; the first type of pixel electrode 41 is electrically connected to the gate line 30 and the data line 2 through the first transistor T1, and the second type of pixel electrode 42 is electrically connected to the gate line 30 and the data line 2 through the second transistor T2; the transistor T includes a first pole TA electrically connected to the pixel electrode 4; the first pole TA includes a first part TA1 extending along the first direction X; in the first transistor T1, the normal projection of the gate line 30 electrically connected to the first transistor T1 on the substrate 1 has a first spacing e1 from the normal projection of the first part TA1 on the substrate 1; in the second transistor T2, the normal projection of the gate line 30 electrically connected to the second transistor T2 on the substrate 1 has a second spacing e2 from the normal projection of the first part TA1 on the substrate 1; the first spacing e1 is greater than the second spacing e2. In the embodiment of the present disclosure, since the first pole TA of the transistor T is electrically connected to the pixel electrode 4, that is, the first pole TA of the transistor T and the pixel electrode 4 can be an integrated structure electrically connected, and then the pattern of the layer where the data line 2 is located can be improved to reduce the Feed though voltage difference of different pixel electrodes.

[0097] In a possible implementation, referring to FIGS. 3A, 3D-3F, the transistor T can further include a second pole TB (which can be a source pole) and a control pole (which can be a multiplexing gate line) and an active pattern TC; the first pole TA can be electrically connected to the pixel electrode 4 through a first via K1, and the second pole TB can be electrically connected to the data line 2.

[0098] In a possible implementation, referring to FIGS. 3A, 3D-3F, the array substrate can further include a common switching part 54 connected to the third common line 53; the third part TA3 of the first pole TA has a normal projection on the substrate 1, which coincides with the normal projection of the common switching part 54 on the substrate 1, and the two can be electrically connected through the first via K1.

[0099] In a possible implementation, referring to FIGS. 3A, 3D-3F, the layer where the pixel electrode 4 is located can further include a switching electrode 44; the common lines 5 (for example, the first common line 51) on different sides of the gate line group 3 can be electrically connected through the switching electrode 44 through a second via K2, so as to realize that the plurality of common lines 5 form a mesh structure.

[0100] In a possible implementation, referring to FIG. 3G, the array substrate includes a plurality of pixel electrode units P0 arranged periodically; the pixel electrode unit P0 includes a first pixel electrode P1, a second pixel electrode P2, a third pixel electrode P3, a fourth pixel electrode P4, a fifth pixel electrode P5, a sixth pixel electrode P6, a seventh pixel electrode P7, an eighth pixel electrode P8, a ninth pixel electrode P9, a tenth pixel electrode P10, an eleventh pixel electrode P10, and a twelfth pixel electrode P12;

[0101] The first pixel electrode P1 is located at the nth row and the mth column, and is electrically connected to the second gate line 32 of the Nth gate line group 3 and the M+1th data line 2;

[0102] The second pixel electrode P2 is located at the nth row and the m+1th column, and is electrically connected to the first gate line 31 of the N+1th gate line group 3 and the M+1th data line 2;

[0103] The third pixel electrode P3 is located at the nth row and the m+2th column, and is electrically connected to the second gate line 32 of the Nth gate line group 3 and the M+2th data line 2;

[0104] The fourth pixel electrode P4 is located at the nth row and the m+3th column, and is electrically connected to the first gate line 31 of the N+1th gate line group 3 and the M+2th data line 2;

[0105] The fifth pixel electrode P5 is located at the nth row and the m+4th column, and is electrically connected to the first gate line 31 of the N+1th gate line group 3 and the M+3th data line 2;

[0106] The sixth pixel electrode P6 is located at the nth row and the m+5th column, and is electrically connected to the second gate line 32 of the Nth gate line group 3 and the M+3th data line 2;

[0107] The seventh pixel electrode P7 is located at the n+1th row and the mth column, and is electrically connected to the second gate line 32 of the N+1th gate line group 3 and the Mth data line 2;

[0108] The eighth pixel electrode P8 is located at the n+1th row and the m+1th column, and is electrically connected to the first gate line 31 of the N+2th gate line group 3 and the Mth data line 2;

[0109] The ninth pixel electrode P9 is located at the n+1th row and the m+2th column, and is electrically connected to the second gate line 32 of the N+1th gate line group 3 and the M+1th data line 2;

[0110] The tenth pixel electrode P10 is located at the n+1th row and the m+3th column, and is electrically connected to the first gate line 31 of the N+2th gate line group 3 and the M+1th data line 2;

[0111] The eleventh pixel electrode P11 is located at the (n+1)th row and the (m+4)th column, and is electrically connected to the first gate line 31 of the (N+2)th gate line group 3 and the (M+2)th data line 2;

[0112] The twelfth pixel electrode P12 is located at the (n+1)th row and the (m+5)th column, and is electrically connected to the second gate line 32 of the (N+1)th gate line group 3 and the (M+2)th data line 2;

[0113] The first type of pixel electrode 41 includes the fourth pixel electrode P4, the sixth pixel electrode P6, the ninth pixel electrode P9 and the twelfth pixel electrode P12; the second type of pixel electrode 42 includes the second pixel electrode P2, the fifth pixel electrode P5, the eighth pixel electrode P8 and the eleventh pixel electrode P11; and the third type of pixel electrode 43 includes the first pixel electrode P1, the fourth pixel electrode P4, the seventh pixel electrode P7 and the tenth pixel electrode P10.

[0114] Based on the same inventive concept, the embodiment of the present disclosure further provides a display panel, which comprises the array substrate provided by the embodiment of the present disclosure, and further comprises a counter substrate arranged opposite to the array substrate, wherein the counter substrate comprises a common electrode layer.

[0115] Based on the same inventive concept, the embodiment of the present disclosure further provides a display device, which comprises the display panel provided by the embodiment of the present disclosure. The implementation of the display device can refer to the above-mentioned embodiments of the display panel, and the repeated parts will not be described herein.

[0116] In the implementation, the display device can be any product or component with display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, etc. Other essential components of the display device are well understood by those skilled in the art, and will not be described herein, and should not be regarded as a limitation on the present disclosure.

[0117] Although the preferred embodiments of the present disclosure have been described, those skilled in the art can make further changes and modifications to the embodiments once they know the basic inventive concept. Therefore, the appended claims are intended to be interpreted as including all changes and modifications falling within the scope of the present disclosure.

[0118] Obviously, various modifications and changes can be made to the present disclosure by those skilled in the art without departing from the spirit and scope of the present disclosure. Thus, it is intended that the present disclosure embrace all such modifications and changes and, accordingly, the appended claims are intended to cover all such modifications and changes as falling within the scope of the present disclosure.

Claims

1. An array substrate, wherein, The display panel comprises: a substrate; a plurality of data lines and a plurality of transistors; a plurality of gate lines located on one side of the substrate, the plurality of gate lines comprising: a plurality of gate line groups extending along a first direction, each of the gate line groups comprising: a first gate line and a second gate line extending along the first direction, and in an Nth gate line group, the first gate line is located on a side of the second gate line away from an N+1th gate line group; a plurality of pixel electrodes, the plurality of pixel electrodes comprising: a plurality of first-type pixel electrodes and a plurality of second-type pixel electrodes; between the Nth gate line group and the N+1th gate line group, the first-type pixel electrodes are electrically connected to the second gate line in the Nth gate line group through the transistors, and the second-type pixel electrodes are electrically connected to the first gate line in the N+1th gate line group through the transistors; a plurality of common lines; wherein a projection of the first-type pixel electrodes on the substrate overlaps with a projection of the common lines on the substrate to form a first overlapping area, and a projection of the second-type pixel electrodes on the substrate overlaps with the projection of the common lines on the substrate to form a second overlapping area, and an area of the first overlapping area is greater than an area of the second overlapping area.

2. The array substrate of claim 1, wherein, The plurality of common lines comprises: a first common compensation line extending along the first direction; and a projection of the first common compensation line on the substrate overlaps with an edge area of the projection of the first-type pixel electrodes on the substrate.

3. The array substrate of claim 1 or 2, wherein, The plurality of common lines comprises: a first common line extending along a second direction; the projection of the first common line on the substrate overlaps with a gap between the projection of the first-type pixel electrodes on the substrate and the projection of the second-type pixel electrodes on the substrate; an overlapping area of the projection of the first common line on the substrate and the projection of the second-type pixel electrodes on the substrate is less than an overlapping area of the projection of the first common line on the substrate and the projection of the first-type pixel electrodes on the substrate.

4. The array substrate of claim 3, wherein, The first-type pixel electrodes have first pixel outer edges facing a side of the first common line; the second-type pixel electrodes have second pixel outer edges facing a side of the first common line; The first common line has a first outer edge extending along the second direction and a second outer edge; the projection of the first outer edge on the substrate overlaps with the projection of the first-type pixel electrodes on the substrate, and the projection of the second outer edge on the substrate overlaps with the projection of the second-type pixel electrodes on the substrate; a distance between the projection of the second pixel outer edges on the substrate and the projection of the second outer edges on the substrate is less than a distance between the projection of the first pixel outer edges on the substrate and the projection of the first outer edges on the substrate.

5. The array substrate of any one of claims 1-4, wherein, The plurality of common lines comprises a second common line extending in the second direction; the second common line comprises a first sub-common line and a second sub-common line extending in the second direction; the first sub-common line and the second sub-common line in the same second common line are located on both sides of the data line in the orthographic projection of the substrate; The first sub-common line has a first sub-outer edge away from the side of the data line, and the second sub-common line has a second sub-outer edge away from the side of the data line; the minimum distance between the first sub-outer edge in the orthographic projection of the substrate and the data line in the orthographic projection of the substrate is less than the minimum distance between the second sub-outer edge in the orthographic projection of the substrate and the data line in the orthographic projection of the substrate.

6. The array substrate of claim 5, wherein, The width of the first sub-common line in the first direction is less than the width of the second sub-common line in the first direction.

7. The array substrate of any one of claims 1-6, wherein, The minimum distance between the orthographic projection of the first type of pixel electrode on the substrate and the orthographic projection of the second gate line electrically connected on the orthographic projection of the substrate is greater than the minimum distance between the orthographic projection of the second type of pixel electrode on the substrate and the orthographic projection of the first gate line electrically connected on the orthographic projection of the substrate.

8. The array substrate of claim 7, wherein, The first type of pixel electrode has a third pixel outer edge facing the second gate line in the Nth gate line group between the Nth gate line group and the N+1th gate line group; The second type of pixel electrode has a fourth pixel outer edge facing the first gate line in the N+1th gate line group; The third outer edge extension line in the orthographic projection of the substrate overlaps with the orthographic projection of the second type of pixel electrode on the substrate; the fourth outer edge extension line in the orthographic projection of the substrate does not overlap with the orthographic projection of the first type of pixel electrode on the substrate.

9. The array substrate of claim 7, wherein, The second gate line in the Nth gate line group has a first notch in the area opposite to the first type of pixel electrode; the first gate line in the N+1th gate line group has a first protrusion in the area opposite to the second type of pixel electrode.

10. The array substrate of claim 9, wherein, The length of the first notch in the first direction is greater than or equal to the length of the first type of pixel electrode in the first direction; the length of the first notch in the second direction is less than the width of the second gate line in the second direction; The length of the first protrusion in the first direction is less than or equal to the length of the second type of pixel electrode in the first direction.

11. The array substrate of any of claims 1-10, wherein, The transistor comprises a plurality of first transistors and a plurality of second transistors; the first type of pixel electrode is electrically connected with the gate line and the data line through the first transistor, and the second type of pixel electrode is electrically connected with the gate line and the data line through the second transistor; The transistor includes: a first electrode electrically connected with the pixel electrode; the first electrode includes: a first part extending along the first direction; in the first transistor, the projection of the gate line electrically connected with the first transistor on the substrate has a first interval with the projection of the first part on the substrate; in the second transistor, the projection of the gate line electrically connected with the second transistor on the substrate has a second interval with the projection of the first part on the substrate; the first interval is greater than the second interval.

12. The array substrate of any of claims 1-11, wherein, The plurality of pixel electrodes further include: a third pixel electrode; between the Nth gate line group and the N+1th gate line group, part of the third pixel electrode is electrically connected to the second gate line in the Nth gate line group through the transistor, and part of the third pixel electrode is electrically connected to the first gate line of the N+1th gate line group through the transistor; The light-emitting waveband range of the region where the first type of pixel electrode is located is greater than the light-emitting waveband range of the region where the second type of pixel electrode is located; the light-emitting waveband range of the region where the second type of pixel electrode is located is greater than the light-emitting waveband range of the region where the third pixel electrode is located.

13. The array substrate of claim 12, wherein, The array substrate includes a plurality of periodically arranged pixel electrode units; The pixel electrode unit includes: a first pixel electrode, a second pixel electrode, a third pixel electrode, a fourth pixel electrode, a fifth pixel electrode, a sixth pixel electrode, a seventh pixel electrode, an eighth pixel electrode, a ninth pixel electrode, a tenth pixel electrode, an eleventh pixel electrode, and a twelfth pixel electrode; The first pixel electrode is located in the nth row and the mth column and is electrically connected to the second gate line of the Nth gate line group and the M+1th data line; The second pixel electrode is located in the nth row and the m+1th column and is electrically connected to the first gate line of the N+1th gate line group and the M+1th data line; The third pixel electrode is located in the nth row and the m+2th column and is electrically connected to the second gate line of the Nth gate line group and the M+2th data line; The fourth pixel electrode is located in the nth row and the m+3th column and is electrically connected to the first gate line of the N+1th gate line group and the M+2th data line; The fifth pixel electrode is located in the nth row and the m+4th column and is electrically connected to the first gate line of the N+1th gate line group and the M+3th data line; The sixth pixel electrode is located in the nth row and the m+5th column and is electrically connected to the second gate line of the Nth gate line group and the M+3th data line; The seventh pixel electrode is located in the n+1th row and the mth column and is electrically connected to the second gate line of the N+1th gate line group and the Mth data line; The eighth pixel electrode is located in the n+1th row and the m+1th column and is electrically connected to the first gate line of the N+2th gate line group and the Mth data line; The ninth pixel electrode is located in the n+1th row and the m+2th column and is electrically connected to the second gate line of the N+1th gate line group and the M+1th data line; The tenth pixel electrode is located at the (n+1)th row and the (m+3)th column and is electrically connected to the first gate line of the (N+2)th gate line group and the (M+1)th data line; The eleventh pixel electrode is located at the (n+1)th row and the (m+4)th column and is electrically connected to the first gate line of the (N+2)th gate line group and the (M+2)th data line; The twelfth pixel electrode is located at the (n+1)th row and the (m+5)th column and is electrically connected to the second gate line of the (N+1)th gate line group and the (M+2)th data line; The first type of pixel electrode includes the fourth pixel electrode, the sixth pixel electrode, the ninth pixel electrode and the twelfth pixel electrode; the second type of pixel electrode includes the second pixel electrode, the fifth pixel electrode, the eighth pixel electrode and the eleventh pixel electrode; and the third type of pixel electrode includes the first pixel electrode, the fourth pixel electrode, the seventh pixel electrode and the tenth pixel electrode.

14. A display panel, wherein, The display panel includes the array substrate and an opposite substrate opposite to the array substrate, wherein the opposite substrate includes a common electrode layer.

15. A display device, wherein, The display panel includes the array substrate and an opposite substrate opposite to the array substrate, wherein the opposite substrate includes a common electrode layer.

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