Display panel and electronic device including same

Abstract

This display panel comprises: a substrate; a light-emitting element disposed on the substrate; and a pixel driving unit connected to the light-emitting element, wherein the pixel driving unit includes: a first transistor including a first-1 semiconductor pattern, a second-1 semiconductor pattern disposed on the first-1 semiconductor pattern, and a barrier disposed between the first-1 semiconductor pattern and the second-1 semiconductor pattern; and a second transistor including a first-2 semiconductor pattern and a second-2 semiconductor pattern disposed on the first-2 semiconductor pattern.

Description

Display panel and electronic device including the same

[0001] The present invention relates to a display panel and an electronic device including the same, and more particularly, to a display panel including a transistor with improved reliability and an electronic device including the same.

[0002] Multimedia electronic devices such as televisions, mobile phones, tablets, computers, navigation systems, and game consoles may include a display panel for displaying images. The display panel may include a plurality of pixels for displaying images, and each pixel may include a light-emitting element that generates light and a pixel driver that drives the light-emitting element.

[0003] The pixel driver may include a switching transistor and a driving transistor. The switching transistor may have high mobility to have advantageous on-off characteristics. The driving transistor may have a wide driving range to facilitate grayscale expression.

[0004] An object of the present invention is to provide a display panel including a switching transistor having high mobility and a driving transistor having a wide driving range.

[0005] An object of the present invention is to provide an electronic device including the above display panel.

[0006] A display panel according to one embodiment of the present invention includes a substrate; a light-emitting element disposed on the substrate; and a pixel driver connected to the light-emitting element, wherein the pixel driver includes a first transistor including a first semiconductor pattern, a second semiconductor pattern disposed on the first semiconductor pattern, and a barrier disposed between the first semiconductor pattern and the second semiconductor pattern; and a second transistor including a first semiconductor pattern and a second semiconductor pattern disposed on the first semiconductor pattern.

[0007] The first transistor may be a driving transistor, and the second transistor may be a switching transistor.

[0008] The above 1-1 semiconductor pattern, the 2-1 semiconductor pattern, the 1-2 semiconductor pattern, and the 2-2 semiconductor pattern may each include an oxide semiconductor.

[0009] The oxygen content of the above 2-1 semiconductor pattern may be greater than the oxygen content of the above 1-1 semiconductor pattern, and the oxygen content of the above 2-2 semiconductor pattern may be greater than the oxygen content of the above 1-2 semiconductor pattern.

[0010] The above 1-1 semiconductor pattern and the above 1-2 semiconductor pattern may each include a crystalline oxide semiconductor.

[0011] The above 1-1 semiconductor pattern and the above 1-2 semiconductor pattern each include indium atoms and gallium atoms, and the composition ratio of indium atoms to gallium atoms per unit volume in the 1-1 semiconductor pattern and the above 1-2 semiconductor pattern may be 2 or more.

[0012] The composition of the above 1-1 semiconductor pattern and the composition of the above 2-1 semiconductor pattern may be the same, and the composition of the above 1-2 semiconductor pattern and the composition of the above 2-2 semiconductor pattern may be the same.

[0013] The above-mentioned 1-1 semiconductor pattern and the above-mentioned 1-2 semiconductor pattern may each be a multilayer structure having different compositions.

[0014] The above barrier may have a single-layer structure or a multi-layer structure.

[0015] The above barrier may include a metal layer.

[0016] The metal layer may include at least one of titanium, molybdenum, aluminum, copper, tungsten, tantalum, and alloys containing these.

[0017] The first transistor further includes a first gate disposed on the second-first semiconductor pattern, and on a plane, the first gate can be disposed corresponding to the second-first semiconductor pattern.

[0018] On the plane, the second-first semiconductor pattern and the first gate can be arranged corresponding to the barrier.

[0019] On a plane, the 2-1 semiconductor pattern and the first gate are arranged to overlap a portion of the barrier, and further include an insulating layer arranged on the first gate, and a connecting electrode arranged on the insulating layer, and a first contact hole penetrating the insulating layer and a second contact hole penetrating the insulating layer and spaced apart from the first contact hole on a plane are defined in the insulating layer, and on a plane, the first contact hole overlaps the barrier and does not overlap the 2-1 semiconductor pattern and the first gate, and on a plane, the second contact hole overlaps the barrier, the 2-1 semiconductor pattern, and the first gate, and the connecting electrode can be connected to the barrier through the first contact hole and to the first gate through the second contact hole.

[0020] On a plane, the 2-1 semiconductor pattern and the first gate are arranged to overlap a part of the barrier, and further include an insulating layer arranged on the first gate, and a connection electrode arranged on the insulating layer, and a contact hole penetrating the insulating layer is defined in the insulating layer, and on a plane, a part of the contact hole overlaps the barrier and does not overlap the 2-1 semiconductor pattern and the first gate, and the remaining part of the contact hole overlaps the barrier, the 2-1 semiconductor pattern, and the first gate, and the connection electrode can be connected to the barrier and the first gate, respectively, through the contact hole.

[0021] It may further include an inorganic insulating layer disposed on the above barrier.

[0022] The above-mentioned inorganic insulating layer may include at least one of silicon oxide, silicon nitride, and aluminum oxide.

[0023] The second transistor further includes a second gate disposed on the second-2 semiconductor pattern, and on a plane, the second gate can be disposed corresponding to the second-2 semiconductor pattern.

[0024] An electronic device according to one embodiment of the present invention includes a substrate; a light-emitting element disposed on the substrate; and a pixel driver connected to the light-emitting element, wherein the pixel driver includes a first transistor including a first-first semiconductor pattern sequentially stacked, a first insulating layer, a barrier including at least one metal layer, a second-first semiconductor pattern, and a first gate, wherein the first-first semiconductor pattern and the second-first semiconductor pattern may each include an oxide semiconductor.

[0025] The pixel driver further includes a second transistor including a first-second semiconductor pattern, a second insulating layer, a second-second semiconductor pattern, and a second gate sequentially stacked, and the first-second semiconductor pattern and the second-second semiconductor pattern may each include an oxide semiconductor.

[0026] The display panel and the electronic device including the same according to the present invention simultaneously include a switching transistor having high mobility and a driving transistor having a wide driving range, and reliability can be improved.

[0027] Figure 1 is a perspective view of a display device according to one embodiment of the present invention.

[0028] Figure 2 is a cross-sectional view of a display device according to one embodiment of the present invention.

[0029] Figure 3 is a cross-sectional view of a display panel according to one embodiment of the present invention.

[0030] Figure 4 is a block diagram of a display device according to one embodiment of the present invention.

[0031] FIGS. 5A to 5C are diagrams each showing an equivalent circuit of a pixel according to one embodiment of the present invention.

[0032] FIGS. 6A and 6B are cross-sectional views of a portion of a display panel according to an embodiment of the present invention, respectively.

[0033] FIGS. 7A to 7C are plan views of some configurations of a circuit element layer according to one embodiment of the present invention, respectively.

[0034] FIG. 8 is a plan view of some configurations of a circuit element layer according to one embodiment of the present invention.

[0035] Figure 9 is a block diagram of an electronic device according to one embodiment of the present invention.

[0036] FIG. 10 is a schematic diagram of various electronic devices according to one embodiment of the present invention.

[0037] The present invention is susceptible to various modifications and takes various forms. Specific embodiments are illustrated in the drawings and described in detail herein. However, this is not intended to limit the present invention to specific disclosed forms, but rather to encompass all modifications, equivalents, and alternatives falling within the spirit and technical scope of the present invention.

[0038] In this specification, singular expressions include plural expressions unless the context clearly indicates otherwise.

[0039] In this specification, terms such as “include” or “have” are intended to specify the presence of a feature, number, step, operation, component, part or combination thereof described in the specification, but should be understood not to exclude in advance the possibility of the presence or addition of one or more other features, numbers, steps, operations, components, parts or combinations thereof.

[0040] In this specification, when it is said that a component (or region, layer, part, etc.) is “on,” “connected to,” or “coupled to” another component, it means that it can be directly disposed / connected / coupled to the other component, or a third component may be disposed between them.

[0041] In this specification, terms such as "below," "lower," "above," and "upper" are used to describe the relationships between components depicted in the drawings. These terms are relative concepts and are described based on the directions indicated in the drawings.

[0042] In this specification, “placed on” may refer to being placed on the upper side as well as the lower side of a member.

[0043] In this specification, "directly disposed" may mean that there are no additional layers, films, regions, plates, etc., between a portion of a layer, film, region, plate, etc. and another portion. For example, "directly disposed" may mean that two layers or two elements are disposed without using an additional element, such as an adhesive element, between them.

[0044] In this specification, “and / or” includes any combination of one or more of the associated components that can be defined.

[0045] In this specification, terms such as "first" and "second" may be used to describe various components, but these components should not be limited by these terms. These terms are used solely to distinguish one component from another. For example, without departing from the scope of the present invention, a first component could be referred to as a "second component," and similarly, a second component could be referred to as a "first component."

[0046] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those skilled in the art to which this invention pertains. Furthermore, terms defined in commonly used dictionaries should be interpreted to have a meaning consistent with their meaning in the relevant technical context, and should not be interpreted in an overly idealistic or overly formal sense unless explicitly defined herein.

[0047] Identical drawing symbols indicate identical components. Furthermore, in the drawings, the thicknesses, proportions, and dimensions of components are exaggerated for the purpose of effectively illustrating the technical content.

[0048] Hereinafter, a display panel and a display device according to one embodiment of the present invention will be described with reference to the drawings.

[0049] Figure 1 is a perspective view of a display device according to one embodiment of the present invention.

[0050] As illustrated in FIG. 1, the display device (DD) may have long sides extending parallel to a first direction (DR1) and short sides extending parallel to a second direction (DR2) intersecting the first direction (DR1).

[0051] Hereinafter, a direction substantially perpendicular to the plane defined by the first direction (DR1) and the second direction (DR2) is defined as a third direction (DR3). In addition, in this specification, the meaning of when viewed on a plane is defined as a state viewed from the third direction (DR3).

[0052] The front surface of the display device (DD) can be defined as a display surface (DS) and can have a plane defined by a first direction (DR1) and a second direction (DR2). Images (IM) generated in the display device (DD) can be provided to a user through the display surface (DS).

[0053] The display surface (DS) may include a display area (DA) and a non-display area (NDA) surrounding the display area (DA). The display area (DA) may be an area where an image is displayed, and the non-display area (NDA) may be an area where an image is not displayed. The non-display area (NDA) may be adjacent to at least one side of the display area (DA). In the present embodiment, the non-display area (NDA) may have a frame shape surrounding the display area (DA).

[0054] The display device (DD) can detect inputs applied from outside the display device (DD). For example, the display device (DD) can detect a first input by a touch pen (PEN) and a second input by a touch (TC). In this case, the touch pen (PEN) can be defined as an input device, and the display area (DA) can provide the user with a detection area capable of detecting inputs in addition to displaying an image.

[0055] The touch pen (PEN) may be an active pen or an electromagnetic pen. The second input by the touch (TC) may include various forms of external input, such as a part of the user's body, light, heat, or pressure. The touch pen (PEN) includes an active pen, a passive pen, an electromagnetic pen, and the like, and is not limited to any one embodiment.

[0056] The display device (DD) can be used in large electronic devices such as televisions, monitors, or outdoor billboards. Furthermore, the display device (DD) can also be used in small and medium-sized electronic devices such as personal computers, laptop computers, personal digital assistants, car navigation systems, game consoles, smartphones, tablets, or cameras. However, this is merely an example, and the display device (DD) according to one embodiment of the present invention can be used in various electronic devices and is not limited to any one embodiment.

[0057] Fig. 2 is a cross-sectional view of a display device according to one embodiment of the present invention. Fig. 3 is a cross-sectional view of a display panel according to one embodiment of the present invention.

[0058] Referring to FIG. 2, the display device (DD) may include a display panel (DP), an input sensing unit (ISP), an anti-reflection layer (RPL), a window (WIN), a panel protection film (PPF), and first and second adhesive layers (AL1, AL2).

[0059] The display panel (DP) according to one embodiment of the present invention may be a light-emitting display panel. For example, the display panel (DP) may be an organic light-emitting display panel or an inorganic light-emitting display panel. The light-emitting layer of the organic light-emitting display panel may include an organic light-emitting material. The light-emitting layer of the inorganic light-emitting display panel may include quantum dots or quantum rods. Hereinafter, the display panel (DP) will be described as an organic light-emitting display panel by way of example.

[0060] Referring to FIG. 3, the display panel (DP) may include a substrate (SUB), a circuit element layer (DP-CL) disposed on the substrate (SUB), a display element layer (DP-OLED) disposed on the circuit element layer (DP-CL), and a thin film encapsulation layer (TFE) disposed on the display element layer (DP-OLED).

[0061] The substrate (SUB) may include a display area (DA) and a non-display area (NDA) surrounding the display area (DA). The substrate (SUB) may include glass or a flexible plastic material such as polyimide (PI). A display element layer (DP-OLED) may be disposed in the display area (DA).

[0062] A plurality of pixels may be arranged on the circuit element layer (DP-CL) and the display element layer (DP-OLED). Each pixel may include a transistor arranged on the circuit element layer (DP-CL) and a light-emitting element arranged on the display element layer (DP-OLED) and connected to the transistor.

[0063] A thin film encapsulation layer (TFE) may be disposed on a circuit element layer (DP-CL) to cover a display element layer (DP-OLED). The thin film encapsulation layer (TFE) may protect pixels from external foreign substances such as moisture, oxygen, and dust. In the present embodiment, the thin film encapsulation layer (TFE) is illustrated as covering the entire area of ​​the substrate (SUB), but according to an embodiment of the present invention, the substrate (SUB) may include a portion exposed from the thin film encapsulation layer (TFE). Alternatively, the area exposed from the thin film encapsulation layer (TFE) may be formed along an edge of the substrate (SUB), and the present invention is not limited to any one embodiment.

[0064] An input sensing unit (ISP) may be arranged on a display panel (DP). The input sensing unit (ISP) may include a plurality of sensing units for sensing an external input in a capacitive manner. The input sensing unit (ISP) may be formed directly on the display panel (DP) during the manufacturing of the display device (DD). Specifically, a conductive pattern or an insulating layer constituting the input sensing unit (ISP) may be directly deposited or patterned on the display panel (DP). However, the present invention is not limited thereto, and the input sensing unit (ISP) may be manufactured as a separate panel from the display panel (DP) and attached to the display panel (DP) via an adhesive layer, and is not limited to any one embodiment.

[0065] An anti-reflection layer (RPL) may be disposed on an input sensing unit (ISP). The anti-reflection layer (RPL) may reduce external light reflectance of a display device (DD) to improve the visibility of an image displayed on the display device (DD). The anti-reflection layer (RPL) may include a phase retarder, a polarizer, a black matrix, a color filter, and the like, and is not limited to any one embodiment. The anti-reflection layer (RPL) may be directly formed on the input sensing unit (ISP) through a coating or deposition process, or may be provided in a film form and attached to the input sensing unit (ISP) through an adhesive layer, and is not limited to any one embodiment.

[0066] The window (WIN) can be placed on an anti-reflection layer (RPL). The window (WIN) can protect the display panel (DP), the input sensor (ISP), and the anti-reflection layer (RPL) from external scratches and impacts.

[0067] A panel protection film (PPF) may be placed under a display panel (DP). The panel protection film (PPF) may support the display panel (DP) and protect the lower portion of the display panel (DP). The panel protection film (PPF) may have insulating properties. For example, the panel protection film (PPF) may include, but is not limited to, a plastic such as polyethylene terephthalate (PET), polyimide (PI), or polypropylene (PP).

[0068] A first adhesive layer (AL1) is disposed between a display panel (DP) and a panel protection film (PPF), and the display panel (DP) and the panel protection film (PPF) can be bonded to each other by the first adhesive layer (AL1). A second adhesive layer (AL2) is disposed between a window (WIN) and an anti-reflection layer (RPL), and the window (WIN) and the anti-reflection layer (RPL) can be bonded to each other by the second adhesive layer (AL2).

[0069] Figure 4 is a block diagram of a display device according to one embodiment of the present invention.

[0070] Referring to FIG. 4, the display device (DD) may include a display panel (DP), a timing controller (TC), a scan driver (SDV), a data driver (DDV), a light emission driver (EDV), and a voltage generator (VG).

[0071] The display panel (DP) may include a plurality of scanning lines (GIL1 to GILm, GCL1 to GCLm, GWL1 to GWLm, GBL1 to GBLm), a plurality of light-emitting lines (EML1 to EMLm), a plurality of data lines (DL1 to DLn), and a plurality of pixels (PX). m and n are natural numbers.

[0072] The pixels (PX) can be electrically connected to scan lines (GIL1 to GILm, GCL1 to GCLm, GWL1 to GWLm, GBL1 to GBLm), emission lines (EML1 to EMLm), and data lines (DL1 to DLn), respectively. Each of the pixels (PX) can be electrically connected to four corresponding scan lines, one corresponding data line, and one corresponding emission line.

[0073] The scan lines (GIL1 to GILm, GCL1 to GCLm, GWL1 to GWLm, GBL1 to GBLm) may include a plurality of initialization scan lines (GIL1 to GILm), a plurality of compensation scan lines (GCL1 to GCLm), a plurality of write scan lines (GWL1 to GWLm), and a plurality of bias scan lines (GBL1 to GBLm).

[0074] Each of the pixels (PX) can be connected to a corresponding one of the initialization scan lines (GIL1 to GILm), a corresponding one of the compensation scan lines (GCL1 to GCLm), a corresponding one of the write scan lines (GWL1 to GWLm), and a corresponding one of the bias scan lines (GBL1 to GBLm).

[0075] The scan lines (GIL1 to GILm, GCL1 to GCLm, GWL1 to GWLm, GBL1 to GBLm) are connected to the scan driver (SDV), extend in a first direction (DR1), and can be arranged in a second direction (DR2). The light emitting lines (EML1 to EMLm) are connected to the light emitting driver (EDV), extend in a first direction (DR1), and can be arranged in a second direction (DR2). The data lines (DL1 to DLn) are connected to the data driver (DDV), extend in a second direction (DR2), and can be arranged in the first direction (DR1).

[0076] In the present embodiment, the scan driver (SDV), the emission driver (EDV), and the data driver (DDV) may be substantially arranged on the display panel (DP). Alternatively, at least one of the scan driver (SDV), the emission driver (EDV), and the data driver (DDV) may be provided on a separate circuit board and electrically connected to the display panel (DP) to provide electrical signals to the pixels (PX), and is not limited to any one embodiment.

[0077] The timing controller (TC) can receive a video signal (RGB) and a control signal (CTRL). The timing controller (TC) can generate a video data signal (DAS) by converting the data format of the video signal (RGB) to meet the interface specifications with the data driver (DDV). In response to the control signal (CTRL), the timing controller (TC) can output a scan control signal (SCS), a data control signal (DCS), and an emission control signal (ECS).

[0078] A voltage generator (VG) can generate voltages required for the operation of a display panel (DP). The voltage generator (VG) can generate a first driving voltage (ELVDD), a second driving voltage (ELVSS), a first initialization voltage (VINT), and a second initialization voltage (VAINT). The first driving voltage (ELVDD), the second driving voltage (ELVSS), the first initialization voltage (VINT), and the second initialization voltage (VAINT) can be applied to pixels (PX).

[0079] The scan driver (SDV) can receive a scan control signal (SCS) from a timing controller (TC). The scan driver (SDV) can output scan signals to scan lines (GIL1 to GILm, GCL1 to GCLm, GWL1 to GWLm, GBL1 to GBLm) in response to the scan control signal (SCS). The scan signals can be applied to pixels (PX) through the scan lines (GIL1 to GILm, GCL1 to GCLm, GWL1 to GWLm, GBL1 to GBLm).

[0080] The data driver (DDV) can receive a data control signal (DCS) and an image data signal (DAS) from a timing controller (TC). The data driver (DDV) can convert the image data signal (DAS) into data signals and output them. The data signals can be defined as analog voltages corresponding to the grayscale levels of the image data signal (DAS). The data signals can be applied to the pixels (PX) through data lines (DL1 to DLn).

[0081] The emission driver (EDV) can receive an emission control signal (ECS) from a timing controller (TC). The emission driver (EDV) can output emission signals to the emission lines (EML1 to EMLm) in response to the emission control signal (ECS). The emission signals can be applied to the pixels (PX) through the emission lines (EML1 to EMLm).

[0082] Pixels (PX) can receive data voltages in response to scanning signals. Pixels (PX) can display images by emitting light with a brightness corresponding to the data voltages in response to light emission signals.

[0083] FIGS. 5A to 5C are diagrams each illustrating an equivalent circuit of a pixel according to an embodiment of the present invention. FIGS. 5A to 5C are diagrams illustrating an equivalent circuit of any one of the pixels illustrated in FIG. 4.

[0084] For example, Fig. 5a illustrates a pixel (PXij) connected to the jth data line (DLj), the ith scan lines (GWLi, GCLi, GILi, GBLi), and the ith emission line (EMLi). i and j are natural numbers.

[0085] Referring to FIG. 5a, a pixel (PXij) may include a pixel driver (PC) and a light-emitting element (OLED) connected to the pixel driver (PC). The pixel driver (PC) may drive the light-emitting element (OLED).

[0086] The pixel driver (PC) may include a plurality of transistors (T1 to T8) and a capacitor (CST). The transistors (T1 to T8) and the capacitor (CST) may control the amount of current flowing to the light-emitting element (OLED). The light-emitting element (OLED) may generate light having a brightness depending on the amount of current supplied.

[0087] The ith write scan line (GWLi) can receive the ith write scan signal (GWi), the ith compensation scan line (GCLi) can receive the ith compensation scan signal (GCi), the ith initialization scan line (GILi) can receive the ith initialization scan signal (GIi), the ith bias scan line (GBLi) can receive the ith bias scan signal (GBi), and the ith emission line (EMLi) can receive the ith emission signal (EMi).

[0088] A pixel (PXij) can be connected to a j-th data line (DLj), an i-th write scan line (GWLi), an i-th compensation scan line (GCLi), an i-th initialization scan line (GILi), an i-th bias scan line (GBLi), an i-th emission line (EMLi), a first initialization line (VIL1), a second initialization line (VIL2), a bias line (VBL), and first and second power lines (PL1, PL2).

[0089] The first initialization line (VIL1) can receive the first initialization voltage (VINT), and the second initialization line (VIL2) can receive the second initialization voltage (VAINT). The bias line (VBL) can receive the bias voltage (VBIAS). The first power line (PL1) can receive the first driving voltage (ELVDD), and the second power line (PL2) can receive the second driving voltage (ELVSS).

[0090] Each of the transistors (T1 to T8) may include a source electrode, a drain electrode, and a gate electrode. Hereinafter, in FIG. 5A, for convenience, one of the source electrode and the drain electrode is defined as the first electrode, and the other is defined as the second electrode. In addition, the gate electrode is defined as the control electrode.

[0091] The transistors (T1 to T8) may include first to eighth transistors (T1 to T8). The first, second, and fifth to eighth transistors (T1, T2, T5 to T8) may be PMOS transistors. The third and fourth transistors (T3, T4) may be NMOS transistors.

[0092] The first transistor (T1) may be defined as a driving transistor, the second transistor (T2) may be defined as a switching transistor, the third transistor (T3) may be defined as a compensation transistor, the fourth transistor (T4) and the seventh transistor (T7) may be defined as initialization transistors, the fifth transistor (T5) and the sixth transistor (T6) may be defined as light-emitting control transistors, and the eighth transistor (T8) may be defined as a bias transistor.

[0093] The light-emitting element (OLED) may be defined as an organic light-emitting element. The light-emitting element (OLED) may include an anode (AE) and a cathode (CE). The anode (AE) may receive a first driving voltage (ELVDD) through the sixth, first, and fifth transistors (T6, T1, T5). The first driving voltage (ELVDD) may be applied to the pixel driver (PC) through the first power line (PL1).

[0094] The cathode (CE) can receive a second driving voltage (ELVSS) having a lower level than the first driving voltage (ELVDD). The second driving voltage (ELVSS) can be applied to the pixel driver (PC) through a second power line (PL2).

[0095] A first transistor (T1) is disposed between a fifth transistor (T5) and a sixth transistor (T6), and can be connected to the fifth transistor (T5) and the sixth transistor (T6). The first transistor (T1) can be connected to a first power line (PL1) through the fifth transistor (T5), and to an anode (AE) through the sixth transistor (T6).

[0096] The first transistor (T1) may include a first electrode connected to the first power line (PL1) via a fifth transistor (T5), a second electrode connected to the anode (AE) via a sixth transistor (T6), and a control electrode connected to the first node (N1).

[0097] A first electrode of a first transistor (T1) may be connected to a fifth transistor (T5), and a second electrode of the first transistor (T1) may be connected to a sixth transistor (T6). The first transistor (T1) may control the amount of current flowing to the light-emitting element (OLED) according to the voltage of the first node (N1) applied to the control electrode of the first transistor (T1).

[0098] A second transistor (T2) may be disposed between the first transistor (T1) and the j-th data line (DLj) and may be connected to the first transistor (T1) and the j-th data line (DLj). The second transistor (T2) may include a first electrode connected to the j-th data line (DLj), a second electrode connected to the first electrode of the first transistor (T1), and a control electrode connected to the i-th write scan line (GWLi).

[0099] The second transistor (T2) can be turned on by the i-th write scan signal (GWi) applied through the i-th write scan line (GWLi) to electrically connect the j-th data line (DLj) and the first electrode of the first transistor (T1). The second transistor (T2) can perform a switching operation of providing the data voltage (VD) (corresponding to the aforementioned data signal) applied through the j-th data line (DLj) to the first electrode of the first transistor (T1).

[0100] A third transistor (T3) may be connected to the second electrode of the first transistor (T1) and the first node (N1). The third transistor (T3) may include a first electrode connected to the second electrode of the first transistor (T1), a second electrode connected to the first node (N1), and a control electrode connected to the ith compensation scan line (GCLi).

[0101] The third transistor (T3) can be turned on by the i-th compensation scan signal (GCi) applied through the i-th compensation scan line (GCLi) to electrically connect the second electrode of the first transistor (T1) and the control electrode of the first transistor (T1). When the third transistor (T3) is turned on, the first transistor (T1) and the third transistor (T3) can be connected in a diode form.

[0102] A fourth transistor (T4) may be connected to a first node (N1). The fourth transistor (T4) may include a first electrode connected to the first node (N1), a second electrode connected to a first initialization line (VIL1), and a control electrode connected to an ith initialization scan line (GILi). The fourth transistor (T4) may be turned on by an ith initialization scan signal (GIi) applied through the ith initialization scan line (GILi) and may provide a first initialization voltage (VINT) applied through the first initialization line (VIL1) to the first node (N1).

[0103] The fifth transistor (T5) may include a first electrode connected to the first power line (PL1), a second electrode connected to the first electrode of the first transistor (T1), and a control electrode connected to the ith light emitting line (EMLi).

[0104] The sixth transistor (T6) may include a first electrode connected to the second electrode of the first transistor (T1), a second electrode connected to the anode (AE), and a control electrode connected to the ith light emitting line (EMLi).

[0105] The fifth transistor (T5) and the sixth transistor (T6) can be turned on by the ith light-emitting signal (EMi) applied through the ith light-emitting line (EMLi). The first driving voltage (ELVDD) is provided to the light-emitting element (OLED) by the turned-on fifth transistor (T5) and sixth transistor (T6), so that a driving current can flow to the light-emitting element (OLED). Therefore, the light-emitting element (OLED) can emit light.

[0106] The seventh transistor (T7) may include a first electrode connected to the anode (AE), a second electrode connected to the second initialization line (VIL2), and a control electrode connected to the ith bias scan line (GBLi). The seventh transistor (T7) may be turned on by the ith bias scan signal (GBi) applied through the ith bias scan line (GBLi), and may provide the second initialization voltage (VAINT) received through the second initialization line (VIL2) to the anode (AE) of the light-emitting element (OLED).

[0107] In an embodiment of the present invention, the second initialization voltage (VAINT) may have a different level from the first initialization voltage (VINT), but is not limited thereto and may have the same level as the first initialization voltage (VINT).

[0108] The seventh transistor (T7) can improve the black expression capability of the pixel (PXij). When the seventh transistor (T7) is turned on, the parasitic capacitor (not shown) of the light-emitting element (OLED) can be discharged. Therefore, when implementing black luminance, the light-emitting element (OLED) does not emit light due to the leakage current of the first transistor (T1), and thus the black expression capability can be improved.

[0109] The capacitor (CST) may include a first electrode connected to a first power line (PL1) and a second electrode connected to a first node (N1). When the fifth transistor (T5) and the sixth transistor (T6) are turned on, the amount of current flowing to the first transistor (T1) may be determined according to the voltage stored in the capacitor (CST).

[0110] The eighth transistor (T8) may include a first electrode connected to a bias line (VBL), a second electrode connected to the first electrode of the first transistor (T1), and a control electrode connected to an i-th bias scan line (GBLi).

[0111] The eighth transistor (T8) is turned on by the i-th bias scan signal (GBi) and can provide a bias voltage (VBIAS) applied through the bias line (VBL) to the first electrode of the first transistor (T1).

[0112] Referring to FIG. 5b, the pixel driver (PC-1) may include six transistors (T11, T21, T31, T41, T51, T61) and two capacitors (CST, CHD).

[0113] The first transistor (T11) can be defined as a driving transistor, and the second transistor (T21) can be defined as a switching transistor.

[0114] The third transistor (T31) may be defined as a reset transistor. The third transistor (T31) provides a reference voltage (VREF) to the first node (N1) in response to a reset signal (GRi) transmitted from the gate driving circuit. The first node (N1) is reset to the reference voltage (VREF), thereby minimizing the influence of the voltage remaining in the previous step.

[0115] The fourth transistor (T41) may be defined as an anode initialization transistor. The fourth transistor (T41) may correspond to the seventh transistor (T7, see FIG. 5A) illustrated in FIG. 5A. The fourth transistor (T41) may initialize the anode of the light-emitting element to the second initialization voltage (VAINT) in response to the initialization signal (GIi).

[0116] The fifth transistor (T51) and the sixth transistor (T61) may be defined as light-emitting control transistors. In the present embodiment, the fifth transistor (T51) and the sixth transistor (T61) may be driven by different light-emitting control signals. Specifically, the fifth transistor (T51) transmits the first voltage (ELVDD) to the first transistor (T11) in response to the first light-emitting control signal (EMi), and the sixth transistor (T61) may be turned on in response to the second light-emitting control signal (EMBi). According to the present invention, the fifth transistor (T51) and the sixth transistor (T61) may be turned on or off at different timings, so that independent driving may be performed. However, this is merely an example, and the first light-emitting control signal (EMi) and the second light-emitting control signal (EMBi) may be applied at the same timing and are not limited to any one embodiment.

[0117] Referring to FIG. 5c, the pixel driver (PC-2) may include seven transistors (T12, T22, T32, T42, T52, T62, T72) and two capacitors (CST, CHD).

[0118] The first transistor (T12) can be defined as a driving transistor, and the second transistor (T22) can be defined as a switching transistor.

[0119] The third transistor (T32) may be defined as a reset transistor, the fourth transistor (T42) may be defined as an anode initialization transistor, and the fifth transistor (T52) and the sixth transistor (T62) may be defined as light-emitting control transistors.

[0120] Compared to FIG. 5B, the pixel driver (PC-2) may further include a seventh transistor (T72). The seventh transistor (T72) may be disposed between the first power voltage (ELVDD) and the drain of the first transistor (T12). The seventh transistor (T72) may provide the first power voltage (ELVDD) to the first transistor (T12) in response to the reset signal (GRi). ​​At this time, the seventh transistor (T72) and the third transistor (T32) may be turned on simultaneously at the same timing. That is, the drain of the first transistor (T12) may receive the first power voltage (ELVDD) at the timing when the first node (N1) is reset.

[0121] The sixth transistor (T62) can be driven by the first light emission control signal (EMi). That is, the sixth transistor (T62) can be turned on simultaneously with the fifth transistor (T52) at the same timing.

[0122] FIGS. 6A and 6B are cross-sectional views of a portion of a display panel according to an embodiment of the present invention, respectively. FIGS. 6A and 6B are diagrams exemplarily illustrating cross-sections of a portion of a display panel (DP, DP-1), respectively. FIGS. 6A and 6B illustrate an area where three transistors (T1, T2, T3) and a light-emitting element (OLED) among the configurations of each pixel (Pxij, PXij-1, PXij-2) illustrated in FIGS. 5A to 5C are arranged.

[0123] Referring to FIG. 6a, the display panel (DP) may include a substrate (SUB), a circuit element layer (DP-CL), a display element layer (DP-OLED), and an encapsulation layer (TFE).

[0124] The substrate (SUB) may include a glass substrate, a sapphire substrate, a plastic film, or an organic / inorganic laminated film. The substrate (SUB) may have a multilayer or single-layer structure. For example, the substrate (SUB) may have a laminated structure of multiple plastic films bonded with an adhesive, or may have a laminated structure of a glass substrate and a plastic film bonded with an adhesive. The substrate (SUB) may have flexibility. For example, the substrate (SUB) may include polyimide (PI). However, this is described as an example, and the substrate (SUB) may be provided in a rigid state and is not limited to any one embodiment.

[0125] A circuit element layer (DP-CL) is disposed on a substrate (SUB). The circuit element layer (DP-CL) may include a driving element and a plurality of insulating layers (10, 20, 30, 40, 50). The three transistors (T1, T2, T3) described above may be elements constituting the circuit element layer (DP-CL). The insulating layers (10, 20, 30, 40, 50) may include first to fifth insulating layers (10, 20, 30, 40, 50) sequentially stacked on the substrate (SUB), but this is merely an example and the number of insulating layers constituting the circuit element layer (DP-CL) may vary and is not limited to any one embodiment.

[0126] Three transistors (TR1, TR2, TR3) are arranged on a substrate (SUB). The three transistors (TR1, TR2, TR3) include a first driving element (TR1), a second driving element (TR2), and a third driving element (TR3). The first driving element (TR1), the second driving element (TR2), and the third driving element (TR3) may be referred to as a first thin film transistor (TR1), a second thin film transistor (TR2), and a third thin film transistor (TR3), respectively. The first thin film transistor (TR1) may be a driving transistor, and the second and third thin film transistors (TR2, TR3) may be switching transistors.

[0127] In this embodiment, a lower barrier layer (BML) and first and second insulating layers (10, 20) may be placed between three transistors (TR1, TR2, TR3) and a substrate (SUB).

[0128] A lower blocking layer (BML) may be disposed on the first insulating layer (10). The lower blocking layer (BML) may block light incident on the first thin film transistor (TR1) from below. The lower blocking layer (BML) may be a light-shielding pattern and may include a black matrix or a reflective conductive material. When the lower blocking layer (BML) includes a conductive material, the lower blocking layer (BML) may be electrically floated or connected to the first thin film transistor (TR1).

[0129] The first insulating layer (10) is disposed on the substrate (SUB) and covers the entire upper surface of the substrate (SUB). The first insulating layer (10) may include a barrier layer. That is, the first insulating layer (10) may prevent oxygen or moisture flowing in through the substrate (SUB) from penetrating into the pixel (PXij).

[0130] A second insulating layer (20) is disposed on the first insulating layer (10) and covers the lower blocking layer (BML). The second insulating layer (20) can cover the entire substrate (SUB). The second insulating layer (20) can include a buffer layer. That is, the second insulating layer (20) can reduce the surface energy of a surface on which a circuit element layer (DP-CL) is formed so that a pixel (PXij) is stably formed on the substrate (SUB). The buffer layer can include at least one inorganic layer, and for example, the buffer layer can include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide.

[0131] At least one of the barrier layer and the buffer layer may be provided in multiples or may be omitted. In addition, in the display panel (DP) according to one embodiment of the present invention, the first insulating layer (10) and / or the second insulating layer (20) may be omitted and are not limited to any one embodiment.

[0132] The first thin film transistor (TR1) may include a first-first semiconductor pattern (SP1) and a first gate (G1). The first thin film transistor (TR1) may be a driving transistor that is arranged on a current path between the first power line (PL1) described above and the light emitting element (OLED) and controls the amount of current flowing to the light emitting element (OLED).

[0133] In the present embodiment, the first-first semiconductor pattern (SP1) may include an oxide semiconductor. The first-first semiconductor pattern (SP1) may include a metal oxide semiconductor material. The metal oxide semiconductor material may be a crystalline or amorphous oxide. For example, the first-first semiconductor pattern (SP1) may include a metal oxide such as zinc (Zn), indium (In), gallium (Ga), tin (Sn), titanium (Ti), or a mixture of metals such as zinc (Zn), indium (In), gallium (Ga), tin (Sn), titanium (Ti) and their oxides. In one embodiment, the metal oxide semiconductor material may include indium-tin oxide (ITO), indium-gallium-zinc oxide (IGZO), zinc oxide (ZnO), indium-zinc oxide (IZnO), zinc-indium oxide (ZIO), indium oxide (InO), titanium oxide (TiO), indium-zinc-tin oxide (IZTO), zinc-tin oxide (ZTO), or the like.

[0134] The first-first semiconductor pattern (SP1) may include a plurality of regions having different electrical properties. For example, the first-first semiconductor pattern (SP1) may include a plurality of regions that are distinguished depending on whether a metal oxide is reduced. The first-first semiconductor pattern (SP1) may include a first source (S1), a first drain (D1), and a first channel (A1) that are distinguished depending on conductivity. Specifically, the first channel (A1) may be a region having relatively lower conductivity than the first source (S1) and the first drain (D1), and may be a region having semiconductor properties. Each of the first source (S1) and the first drain (D1) may be a region having higher conductivity than the first channel (A1), and may be a region having conductive properties. The first channel (A1) may also be referred to as a first active (A1).

[0135] Each of the first source (S1) and the first drain (D1) may be formed through doping or reduction. For example, in a semiconductor pattern, a highly doped region with a relatively high dopant concentration may have high conductivity. Some regions of the semiconductor pattern may be doped to become sources / drains, and the remaining regions may become channels. The dopants may be P-type dopants or N-type dopants, and are not limited to any one embodiment.

[0136] Alternatively, for example, in an oxide semiconductor pattern, a reduced region may have higher conductivity than a non-reduced region. Since the metal oxide constituting the oxide semiconductor pattern is precipitated into a metal through a reduction process, the region where the metal oxide is reduced may become a source / drain, and the remaining region may become a channel.

[0137] In this embodiment, the first source (S1) and the first drain (D1) may be formed on the 1-1 semiconductor pattern (SP1). However, this is merely an example, and the source / drain of the first thin film transistor (TR1) may be provided as a separate conductive pattern connected to the 1-1 semiconductor pattern (SP1), and is not limited to any one embodiment.

[0138] A first gate (G1) may be disposed on a semiconductor pattern of a first thin film transistor (TR1). The first gate (G1) may overlap a first channel (A1). A first insulating pattern (31) may be disposed between the first gate (G1) and the semiconductor pattern. The first insulating pattern (31) may be patterned in a shape aligned with the first gate (G1).

[0139] A second-first semiconductor pattern (OS1) may be arranged between the first insulating pattern (31) and the first gate (G1). The second-first semiconductor pattern (OS1) may be arranged directly under the first gate (G1). The second-first semiconductor pattern (OS1) may include the same material as the first-first semiconductor pattern (SP1) described above. The oxygen content of the second-first semiconductor pattern (OS1) may be greater than the oxygen content of the first-first semiconductor pattern (SP1).

[0140] A barrier (BR) may be arranged between the first insulating pattern (31) and the second-first semiconductor pattern (OS1). The barrier (BR) may be arranged directly on the first insulating pattern (31). The barrier (BR) may be arranged directly under the second-first semiconductor pattern (OS1). The barrier (BR) may prevent oxygen of the second-first semiconductor pattern (OS1) from penetrating into the first-first semiconductor pattern (SP1).

[0141] The barrier (BR) may be a metal layer. For example, the barrier (BR) may include at least one of titanium (Ti), molybdenum (Mo), aluminum (Al), copper (Cu), tungsten (W), tantalum (Ta), and alloys thereof. The barrier (BR) may have a single-layer structure or a multi-layer structure.

[0142] The second thin film transistor (TR2) may include a second gate (G2) and a first-second semiconductor pattern (SP2). The second thin film transistor (TR2) may be an initialization transistor (T4: see FIG. 5a) that is turned on through the aforementioned initialization scan line (GILi) and provides the first initialization voltage (VINT) transmitted through the first initialization line (VIL1) to the pixel circuit, but is not limited thereto.

[0143] The first-second semiconductor pattern (SP2) may be arranged on the same layer as the first-first semiconductor pattern (SP1). The first-second semiconductor pattern (SP2) may include an oxide semiconductor. The first-second semiconductor pattern (SP2) may include a metal oxide semiconductor material. The metal oxide semiconductor material may be a crystalline or amorphous oxide. For example, the first-second semiconductor pattern (SP2) may include a metal oxide such as zinc (Zn), indium (In), gallium (Ga), tin (Sn), titanium (Ti), or a mixture of a metal such as zinc (Zn), indium (In), gallium (Ga), tin (Sn), titanium (Ti) and an oxide thereof. In one embodiment, the metal oxide semiconductor material may include indium-tin oxide (ITO), indium-gallium-zinc oxide (IGZO), zinc oxide (ZnO), indium-zinc oxide (IZnO), zinc-indium oxide (ZIO), indium oxide (InO), titanium oxide (TiO), indium-zinc-tin oxide (IZTO), zinc-tin oxide (ZTO), and the like.

[0144] The first-second semiconductor pattern (SP2) may include a plurality of regions having different electrical properties. For example, the first-second semiconductor pattern (SP2) may include a plurality of regions that are distinguished depending on whether a metal oxide is reduced. The first-second semiconductor pattern (SP2) may include a second source (S2), a second drain (D2), and a second channel (A2) that are distinguished depending on conductivity. Specifically, the second channel (A2) may be a region having relatively lower conductivity than the second source (S2) and the second drain (D2), and may be a region having semiconductor properties. Each of the second source (S2) and the second drain (D2) may be a region having higher conductivity than the second channel (A2), and may be a region having conductive properties. The second channel (A2) may also be referred to as a second active (A2).

[0145] Each of the second source (S2) and the second drain (D2) can be formed through doping or reduction. For example, in a semiconductor pattern, a highly doped region with a relatively high dopant concentration can have high conductivity. Some regions of the semiconductor pattern can be doped to become sources / drains, and the remaining regions can become channels. The dopants can be P-type dopants or N-type dopants, and are not limited to any one embodiment.

[0146] Alternatively, for example, in an oxide semiconductor pattern, a reduced region may have higher conductivity than a non-reduced region. Since the metal oxide constituting the oxide semiconductor pattern is precipitated into a metal through a reduction process, the region where the metal oxide is reduced may become a source / drain, and the remaining region may become a channel.

[0147] In this embodiment, the second source (S2) and the second drain (D2) may be formed on the first-second semiconductor pattern (SP2). However, this is merely an example, and the source / drain of the second thin film transistor (TR2) may be provided as a separate conductive pattern connected to the first-second semiconductor pattern (SP2), and is not limited to any one embodiment.

[0148] The second gate (G2) may be disposed on the semiconductor pattern of the second thin film transistor (TR2). The second gate (G2) may overlap the second channel (A2). A second insulating pattern (32) may be disposed between the second gate (G2) and the semiconductor pattern. The second insulating pattern (32) may be patterned in a shape aligned with the second gate (G2).

[0149] A second-second semiconductor pattern (OS2) may be arranged between the second insulating pattern (32) and the second gate (G2). The second-second semiconductor pattern (OS2) may be arranged directly below the second gate (G2). The second-second semiconductor pattern (OS2) may be arranged directly on the second insulating pattern (32). The second-second semiconductor pattern (OS2) may include the same material as the first-second semiconductor pattern (SP2) described above. The oxygen content of the second-second semiconductor pattern (OS2) may be greater than the oxygen content of the first-second semiconductor pattern (SP2). The second-second semiconductor pattern (OS2) may supply oxygen to the first-second semiconductor pattern (SP2).

[0150] The third thin film transistor (TR3) may be provided with the same structure as the second thin film transistor (TR2). The third thin film transistor (TR3) may include a third gate (G3) and a first-third semiconductor pattern (SP3). The first-third semiconductor pattern (SP3) may be arranged on the same layer as the first-first semiconductor pattern (SP1) and the first-second semiconductor pattern (SP2).

[0151] The first-third semiconductor pattern (SP3) may include an oxide semiconductor. The first-third semiconductor pattern (SP3) may include a metal oxide semiconductor material. The metal oxide semiconductor material may be a crystalline or amorphous oxide. For example, the first-third semiconductor pattern (SP3) may include a metal oxide such as zinc (Zn), indium (In), gallium (Ga), tin (Sn), titanium (Ti), or a mixture of metals such as zinc (Zn), indium (In), gallium (Ga), tin (Sn), titanium (Ti) and their oxides. In one embodiment, the metal oxide semiconductor material may include indium-tin oxide (ITO), indium-gallium-zinc oxide (IGZO), zinc oxide (ZnO), indium-zinc oxide (IZnO), zinc-indium oxide (ZIO), indium oxide (InO), titanium oxide (TiO), indium-zinc-tin oxide (IZTO), zinc-tin oxide (ZTO), or the like.

[0152] The first-third semiconductor pattern (SP3) may include a plurality of regions having different electrical properties. For example, the first-third semiconductor pattern (SP3) may include a plurality of regions that are distinguished depending on whether a metal oxide is reduced. The first-third semiconductor pattern (SP3) may include a third source (S3), a third drain (D3), and a third channel (A3) that are distinguished depending on conductivity. Specifically, the third channel (A3) may be a region having relatively lower conductivity than the third source (S3) and the third drain (D3), and may be a region having semiconductor properties. Each of the third source (S3) and the third drain (D3) may be a region having higher conductivity than the third channel (A3), and may be a region having conductive properties. The third channel (A3) may also be referred to as a third active (A3).

[0153] Each of the third source (S3) and the third drain (D3) can be formed through doping or reduction. For example, in a semiconductor pattern, a highly doped region with a relatively high dopant concentration can have high conductivity. Some regions of the semiconductor pattern can be doped to become sources / drains, and the remaining regions can become channels. The dopants can be P-type or N-type dopants, and are not limited to any one embodiment.

[0154] Alternatively, for example, in an oxide semiconductor pattern, a reduced region may have higher conductivity than a non-reduced region. Since the metal oxide constituting the oxide semiconductor pattern is precipitated into a metal through a reduction process, the region where the metal oxide is reduced may become a source / drain, and the remaining region may become a channel.

[0155] In this embodiment, the third source (S3) and the third drain (D3) may be formed on the 1-3 semiconductor pattern (SP3). However, this is merely an example, and the source / drain of the third thin film transistor (TR3) may be provided as a separate conductive pattern connected to the 1-3 semiconductor pattern (SP3), and is not limited to any one embodiment.

[0156] The third gate (G3) may be arranged on the semiconductor pattern of the third thin film transistor (TR3). The third gate (G3) may overlap the third channel (A3). A third insulating pattern (33) may be arranged between the third gate (G3) and the semiconductor pattern. The third insulating pattern (33) may be patterned in a shape aligned with the third gate (G3).

[0157] A second-third semiconductor pattern (OS3) may be arranged between the third insulating pattern (33) and the third gate (G3). The second-third semiconductor pattern (OS3) may be arranged directly below the third gate (G3). The second-third semiconductor pattern (OS3) may be arranged directly on the third insulating pattern (33). The second-third semiconductor pattern (OS3) may include the same material as the first-third semiconductor pattern (SP3) described above. The oxygen content of the second-third semiconductor pattern (OS3) may be greater than the oxygen content of the first-third semiconductor pattern (SP3). The second-third semiconductor pattern (OS3) may supply oxygen to the first-third semiconductor pattern (SP3).

[0158] The third thin film transistor (TR3) may be a light emitting control transistor (T6: see FIG. 5a) that is arranged on a current path between the first thin film transistor (TR1) and the light emitting element (OLED) and provides the driving current transmitted by the first thin film transistor (TR1) to the light emitting element (OLED) in response to a signal transmitted through the above-described light emitting line (EMLi), but is not limited thereto.

[0159] According to the present embodiment, the first thin film transistor (TR1) functioning as a driving transistor includes a barrier (BR), so that the threshold voltage (Vth) is positioned more negatively, and the amount of deterioration under voltage or temperature stress can be reduced. In other words, the reliability of the driving transistor can be secured.

[0160] In addition, since the second and third thin film transistors (TR2, TR3) functioning as switching transistors include oxide semiconductors (OS2, OS3), the oxygen concentration of the semiconductor patterns (SP2, SP3) can be controlled. Accordingly, the threshold voltage (Vth) of a short channel length can be effectively controlled. That is, the threshold voltage (Vth) is positioned more positively, and the phenomenon of Vth going to negative in a short channel length can be reduced.

[0161] The first to third insulating patterns (31, 32, 33) may be provided in the form of a layer that is connected to each other and has an integral shape. In this case, the third insulating layer (30) may be provided as a single insulating layer having an integral shape rather than as a plurality of separate patterns (31, 32, 33), and is not limited to any one embodiment.

[0162] The circuit element layer (DP-CL) may further include a plurality of connection electrodes (CN1, CN2, CN3, CN4, CN5, CN6). The first connection electrode (CN1) may be connected to the source (S1) of the first thin film transistor (TR1) through the first contact hole (CH1), and the second connection electrode (CN2) may be connected to the drain (D1) of the first thin film transistor (TR1) through the second contact hole (CH2). The third connection electrode (CN3) may be connected to the source (S2) of the second thin film transistor (TR2) through the third contact hole (CH3), and the fourth connection electrode (CN4) may be connected to the drain (D2) of the second thin film transistor (TR2) through the fourth contact hole (CH4). The fifth connection electrode (CN5) can be connected to the source (S3) of the third thin film transistor (TR3) through the fifth contact hole (CH5), and the sixth connection electrode (CN6) can be connected to the drain (D3) of the third thin film transistor (TR3) through the sixth contact hole (CH6).

[0163] The fifth insulating layer (50) is placed on the fourth insulating layer (40) and covers the connection electrodes (CN1, CN2, CN3, CN4, CN5, CN6). The light-emitting element (OLED) is connected to the circuit element layer (DP-CL) through a contact hole formed in the fifth insulating layer (50).

[0164] In the present embodiment, each of the first to fifth insulating layers (10, 20, 30, 40, 50) may include an inorganic layer and / or an organic layer. For example, the first insulating layer (10) and the second insulating layer (20) may include silicon nitride and / or silicon oxide, and each of the first to third insulating patterns (31, 32, 33) constituting the third insulating layer (30) may include silicon oxide. The fourth insulating layer (40) may include a sequentially laminated silicon oxynitride layer and a silicon nitride layer, and the fifth insulating layer (50) may include an organic layer. However, this is merely an example, and the material or laminated form of each of the first to fifth insulating layers (10, 20, 30, 40, 50) may be variously changed and is not limited to any one embodiment.

[0165] A display element layer (DP-OLED) may be disposed on a circuit element layer (DP-CL). The display element layer (DP-OLED) may include a light-emitting element (OLED) and a pixel defining layer (PDL). The light-emitting element (OLED) may include a first electrode (AE), a hole control layer (HCL), an emission layer (EML), an electron control layer (ECL), and a second electrode (CE).

[0166] The first electrode (AE) may be disposed on the fifth insulating layer (50). The first electrode (AE) may be connected to the fifth connection electrode (CN5) by penetrating the fifth insulating layer (50). This is illustrated as an example, and if the first electrode (AE) can be connected to the third thin film transistor (TR3), it may be connected through a separate additional connection electrode or directly connected to the source (S3) of the third thin film transistor (TR3), and is not limited to any one embodiment.

[0167] A pixel defining layer (PDL) may be disposed on the fifth insulating layer (50). The pixel defining layer (PDL) may expose at least a portion of the first electrode (AE). That is, an opening may be defined in the pixel defining layer (PDL) to expose a portion of the first electrode (AE).

[0168] A hole control layer (HCL) may be disposed on a first electrode (AE) and a pixel defining layer (PDL). The hole control layer (HCL) may be disposed commonly in both an emitting area and a non-emitting area. The hole control layer (HCL) may include a layer having high hole mobility to facilitate movement of holes from the first electrode (AE) to the emitting layer (EML). For example, the hole control layer (HCL) may include at least one of a hole transport layer, a hole injection layer, and an electron blocking layer, and each layer may have a single-layer or multi-layer stacked structure.

[0169] An emission layer (EML) may be disposed on a hole control layer (HCL). The emission layer (EML) may be disposed in an area corresponding to an opening of a pixel defining layer (PDL). The emission layer (EML) may include an organic material and / or an inorganic material. The emission layer (EML) may generate light of any one of red, green, and blue.

[0170] An electron control layer (ECL) may be disposed on the light emitting layer (EML) and the hole control layer (HCL). The electron control layer (ECL) may be disposed commonly in both the light emitting region and the non-light emitting region. The electron control layer (ECL) may include a layer having high electron mobility to facilitate the movement of electrons from the second electrode (CE) to the light emitting layer (EML). For example, the electron control layer (ECL) may include at least one of an electron transport layer, an electron injection layer, and a hole blocking layer, and each layer may have a single-layer or multi-layer stacked structure.

[0171] The second electrode (CE) may be disposed on the electronic control layer (ECL). The second electrode (CE) may be commonly disposed on the pixels (PX). That is, the second electrode (CE) may be formed in an integral shape on the light-emitting layers (EML) of the pixels (PX). However, this is merely an example, and the second electrode (CE) may be provided in a separate pattern for each pixel (PX) and is not limited to any one embodiment. The second electrode (CE) may be semi-transparent or transparent. The second electrode (CE) may be provided in various forms, such as a transparent conductive oxide layer, a thin-film metal layer having transparency, or a layer having a stacked structure of a metal layer / oxide layer. When the light-emitting element (OLED) has a bottom-emitting structure, the second electrode (CE) may be a reflective electrode.

[0172] An encapsulation layer (TFE) may be disposed on the display element layer (DP-OLED). The encapsulation layer (TFE) may include an inorganic layer and an organic layer. In the present embodiment, the first inorganic layer (IL1), the organic layer (OL), and the second inorganic layer (IL2) are sequentially laminated, but the laminated structure of the layers constituting the encapsulation layer (TFE) may be varied.

[0173] The first inorganic layer (IL1) and the second inorganic layer (IL2) contain inorganic materials and can protect pixels from moisture / oxygen. The first inorganic layer (IL1) and the second inorganic layer (IL2) may contain the same material or different materials. The organic layer (OL) contains organic materials and can protect the light-emitting element layer (DD-OLED) or the circuit element layer (DP-CL) from foreign substances.

[0174] Referring to FIG. 6b, an inorganic layer (INB) may be added to the barrier (BR) according to one embodiment of the present invention. The inorganic layer (INB) may be an insulating layer. The inorganic layer (INB) may include an inorganic material, and may include, for example, at least one of silicon oxide, silicon nitride, and aluminum oxide.

[0175] FIGS. 7A to 7C are plan views of some components of a circuit element layer, respectively, according to one embodiment of the present invention. FIGS. 7A to 7C are exemplary illustrations of a driving transistor (T1) and components arranged around it, respectively, according to one embodiment of the present invention.

[0176] Referring to Fig. 7a, the first gate (G1), the second-first semiconductor pattern (OS1), and the barrier (BR) may overlap each other on a plane. In Fig. 7a, the areas of the first gate (G1), the second-first semiconductor pattern (OS1), and the barrier (BR) are all illustrated as being the same. However, the present invention is not limited thereto, and the second-first semiconductor pattern (OS1) may have a larger area while overlapping the first gate (G1). In addition, the barrier (BR) may have a larger area while overlapping the second-first semiconductor pattern (OS1).

[0177] When the thickness of the 2-1 semiconductor pattern (OS1) is thin, an ohmic contact is formed between the barrier (BR) and the 2-1 semiconductor pattern (OS1) and between the 2-1 semiconductor pattern (OS1) and the first gate (G1) without separately connecting the barrier (BR) and the first gate (G1), so that the charge concentration of the 2-1 semiconductor pattern (OS1) can increase. For example, the thickness of the 2-1 semiconductor pattern (OS1) can be 50 nm or less.

[0178] Unlike FIG. 7a, FIG. 7b and FIG. 7c illustrate a structure in which the barrier (BR) and the first gate (G1) are connected. Unlike FIG. 7a, the first gate (G1) and the second-first semiconductor pattern (OS1) may overlap a portion of the barrier (BR) on a plane.

[0179] The barrier (BR) and the first gate (G1) can be electrically connected through contact holes (CHB, CHG, CHBG). The connection electrode (CNL) can be a connection electrode for connecting the barrier (BR) and the first gate (G1). The connection electrode (CNL) can be disposed on the insulating layer (40).

[0180] Referring to FIG. 7b, the connecting electrode (CNL) can be connected to the barrier (BR) through a barrier contact hole (CHB) penetrating the insulating layer (40), and can be connected to the first gate (G1) through a gate contact hole (CHG) penetrating the insulating layer (40). The barrier contact hole (CHB) may overlap the barrier (BR) on a plane, and may not overlap with the first gate (G1) and the second-first semiconductor pattern (OS1), respectively. The gate contact hole (CHG) may overlap with the barrier (BR), the first gate (G1), and the second-first semiconductor pattern (OS1), respectively.

[0181] Referring to FIG. 7c, the connecting electrode (CNL) can be connected to each of the barrier (BR) and the first gate (G1) through a single contact hole (CHBG) penetrating the insulating layer (40). Here, the contact hole (CHBG) can be an integral through hole extending from a region where the barrier (BR) is disposed and the first gate (G1) and the second-first semiconductor pattern (OS1) are not disposed on a plane to a region where the barrier (BR), the first gate (G1), and the second-first semiconductor pattern (OS1) are all disposed.

[0182] Fig. 8 is a plan view of some components of a circuit element layer according to one embodiment of the present invention. Fig. 8 exemplarily illustrates a switching transistor (T2) and components arranged around it according to one embodiment of the present invention.

[0183] Referring to Fig. 8, the second gate (G2) and the second-second semiconductor pattern (OS2) may overlap each other on a plane. In Fig. 8, the areas of the second gate (G2) and the second-second semiconductor pattern (OS2) are illustrated as being equal to each other. However, this is not limited thereto, and the second-second semiconductor pattern (OS2) may have a larger area while overlapping the second gate (G2).

[0184] A display panel (DP) according to the present invention includes a barrier (BR) on an insulating pattern (31) of a first thin film transistor (TR1) functioning as a driving transistor, and includes oxide semiconductors (OS2, OS3) on insulating patterns (32, 33) of thin film transistors (TR2, TR3) functioning as switching transistors, thereby enabling independent design of each thin film transistor according to its function. Accordingly, the first thin film transistor (TR1) can secure a high driving range without deterioration, so that a display panel capable of expressing various grayscale levels can be provided. In addition, the second and third thin film transistors (TR2, TR3) are formed to have high mobility and a short channel length, so that a pixel driving circuit with reduced leakage current can be provided.

[0185] Although the present invention has been described above with reference to preferred embodiments thereof, it will be understood by those skilled in the art or having ordinary knowledge in the art that various modifications and changes to the present invention can be made without departing from the spirit and technical scope of the present invention as set forth in the claims to be described below.

[0186] Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

[0187] The present invention provides a display panel and display device with improved reliability by simultaneously including a switching transistor with high mobility and a driving transistor with a wide driving range, and thus has industrial applicability.

Claims

1. Substrate; A light emitting element disposed on the substrate; and Including a pixel driver connected to the above light-emitting element, The above pixel driver is, A first transistor including a first semiconductor pattern, a second semiconductor pattern disposed on the first semiconductor pattern, and a barrier disposed between the first semiconductor pattern and the second semiconductor pattern; and A display panel comprising a second transistor including a first semiconductor pattern and a second semiconductor pattern disposed on the first semiconductor pattern.

2. In paragraph 1, The above first transistor is a driving transistor, The above second transistor is a display panel that is a switching transistor.

3. In paragraph 1, A display panel in which the first-first semiconductor pattern, the second-first semiconductor pattern, the first-second semiconductor pattern, and the second-second semiconductor pattern each include an oxide semiconductor.

4. In paragraph 3, The oxygen content of the above 2-1 semiconductor pattern is greater than the oxygen content of the above 1-1 semiconductor pattern, A display panel in which the oxygen content of the above-mentioned 2-2 semiconductor pattern is greater than the oxygen content of the above-mentioned 1-2 semiconductor pattern.

5. In paragraph 3, A display panel in which the first-first semiconductor pattern and the first-second semiconductor pattern each include a crystalline oxide semiconductor.

6. In paragraph 3, The above 1-1 semiconductor pattern and the above 1-2 semiconductor pattern each include indium atoms and gallium atoms, A display panel in which the composition ratio of indium atoms to gallium atoms per unit volume in the above-mentioned 1-1 semiconductor pattern and the above-mentioned 1-2 semiconductor pattern is 2 or more.

7. In paragraph 1, The composition of the above 1-1 semiconductor pattern and the composition of the above 2-1 semiconductor pattern are the same, The composition of the above 1-2 semiconductor pattern and the composition of the above 2-2 semiconductor pattern are the same display panel.

8. In paragraph 1, A display panel in which the first-first semiconductor pattern and the first-second semiconductor pattern each have a multilayer structure with different compositions.

9. In paragraph 1, The above barrier is a display panel having a single-layer structure or a multi-layer structure.

10. In paragraph 1, The above barrier is a display panel including a metal layer.

11. In paragraph 10, A display panel wherein the metal layer comprises at least one of titanium, molybdenum, aluminum, copper, tungsten, tantalum, and an alloy containing these.

12. In paragraph 1, The first transistor further includes a first gate disposed on the second-first semiconductor pattern, On a plane, the first gate is arranged in correspondence with the second-first semiconductor pattern, in a display panel.

13. In paragraph 12, On a plane, the second-first semiconductor pattern and the first gate are arranged in correspondence with the barrier, in a display panel.

14. In paragraph 12, On the plane, the second-first semiconductor pattern and the first gate are arranged to overlap a portion of the barrier, Further comprising an insulating layer disposed on the first gate, and a connecting electrode disposed on the insulating layer, In the insulating layer, a first contact hole penetrating the insulating layer and a second contact hole penetrating the insulating layer and spaced apart from the first contact hole on a plane are defined. On the plane, the first contact hole overlaps with the barrier and does not overlap with the second-first semiconductor pattern and the first gate, On the plane, the second contact hole overlaps the barrier, the second-first semiconductor pattern, and the first gate, A display panel in which the above-mentioned connecting electrode is connected to the barrier through the first contact hole and to the first gate through the second contact hole.

15. In paragraph 12, On the plane, the second-first semiconductor pattern and the first gate are arranged to overlap a portion of the barrier, Further comprising an insulating layer disposed on the first gate, and a connecting electrode disposed on the insulating layer, In the above insulating layer, a contact hole penetrating the insulating layer is defined, On the plane, a portion of the contact hole overlaps the barrier and does not overlap the second-first semiconductor pattern and the first gate, and the remaining portion of the contact hole overlaps the barrier, the second-first semiconductor pattern, and the first gate. A display panel in which the above connecting electrode is connected to the barrier and the first gate, respectively, through the above contact hole.

16. In paragraph 1, A display panel further comprising an inorganic insulating layer disposed on the above barrier.

17. In paragraph 16, A display panel wherein the above-mentioned inorganic insulating layer comprises at least one of silicon oxide, silicon nitride, and aluminum oxide.

18. In paragraph 1, The second transistor further includes a second gate disposed on the second-second semiconductor pattern, On a plane, the second gate is arranged in correspondence with the second-2 semiconductor pattern, in a display panel.

19. Substrate; A light emitting element disposed on the substrate; and Including a pixel driver connected to the above light-emitting element, The pixel driver includes a first transistor including a first-first semiconductor pattern, a first insulating layer, a barrier including at least one metal layer, a second-first semiconductor pattern, and a first gate, which are sequentially stacked. An electronic device wherein the first-first semiconductor pattern and the second-first semiconductor pattern each include an oxide semiconductor.

20. In paragraph 19, The pixel driver further includes a second transistor including a first-second semiconductor pattern, a second insulating layer, a second-second semiconductor pattern, and a second gate, which are sequentially stacked. An electronic device wherein the first and second semiconductor patterns and the second and second semiconductor patterns each include an oxide semiconductor.

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