Topology of multiple computing chips, circuit board cluster, and computing device

Abstract

A topology of multiple computing chips, the topology comprising at least three levels of computing chipsets. A computing chipset at each level comprises at least one computing chipset at a previous level, and each port of each computing chip in a computing chipset at the first level is separately connected to a port of another computing chip in the computing chipset at the first level where the computing chip is located and a computing chip in another computing chipset at a same level of a computing chipset at another level where the computing chip is located, thereby improving the richness of the topology. In the present application, a topology is enriched, so that a divided computing task can be more easily allocated to multiple computing chips, to ensure that input and output data generated after the computing task is executed is transmitted inside the computing chips or between two computing chips directly connected by means of a communication channel, without being transferred by means of another computing chip, thereby ensuring that the frequency of the topology when the computing task is executed is maximized.

Description

A topology for multiple computing chips, a cluster of circuit boards, and a computing device

[0001] This application claims priority to Chinese Patent Application No. 2024112159690, filed on August 31, 2024, entitled "A Topology of Multiple Computing Chips, Circuit Board Cluster and Computing Device", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This invention relates to the field of communication technology, and in particular to a topology of multiple computing chips, a circuit board cluster, and a computing device. Background Technology

[0003] Computing devices can perform computational tasks using a topology composed of multiple computing chips. When multiple computing chips process a task, they inevitably generate input and output data, which is transmitted between the chips. The more times each input and output data is transmitted between the chips, the lower the frequency of computation between the multiple chips. To maximize the frequency of computation, input and output data should be transmitted only between two chips with communication channels, without using a third chip as an intermediary. However, the topologies composed of multiple computing chips in related technologies are relatively simple and cannot guarantee that the input and output data generated during computation is transmitted only between two chips with communication channels. Summary of the Invention

[0004] To address the aforementioned issues, embodiments of this application provide a topology for multiple computing chips. This topology allows for easier allocation of segmented computing tasks across multiple chips, ensuring that input / output data generated after a computing task is executed is transmitted within the computing chip itself or between two directly connected chips with a communication channel, without intermediaries such as other chips. This maximizes the frequency of computing task execution. Furthermore, this application also provides a circuit board cluster and computing device corresponding to this multi-chip topology.

[0005] Therefore, the following technical solutions are adopted in the embodiments of this application:

[0006] In a first aspect, embodiments of this application provide a topology for multiple computing chips, including: multiple first-level computing chip groups, each first-level computing chip group including at least two computing chips; multiple second-level computing chip groups, each second-level computing chip group including at least one first-level computing chip group; and at least one third-level computing chip group, each third-level computing chip group including at least one second-level computing chip group; wherein each computing chip transmits data via a communication channel with other computing chips within its own first-level computing chip group, one computing chip within another first-level computing chip group within its own second-level computing chip group, and one computing chip within another second-level computing chip group within its own third-level computing chip group.

[0007] In this embodiment, the topology includes at least three levels of computing chipsets. The first-level computing chipset includes at least two computing chips, and each of the other levels includes at least one computing chipset from the previous level. Each port of each computing chip in the first-level computing chipset is connected to a port of another computing chip within its own first-level computing chipset, and to a computing chip in another computing chipset of the same level in other levels of computing chipsets, thereby increasing the richness of the topology of the multiple computing chips. By enriching the topology, this application makes it easier to distribute segmented computing tasks across multiple computing chips, ensuring that the input and output data generated after the computing task is executed are transmitted within the computing chip itself, or between two computing chips directly connected by a communication channel, without being relayed through other computing chips, thus maximizing the frequency of computing task execution in this topology.

[0008] In one implementation, the at least two computing chips in the first-level computing chipset are of the same type.

[0009] In this embodiment, the type includes chip types such as CPU, GPU, MCU, and FPGA.

[0010] In this embodiment, all computing chips in the topology of the plurality of computing chips are of the same type, which can reduce the difficulty of designing the connection between computing chips.

[0011] In one embodiment, the computing chip is of the type of CPU, GPU, MCU, or FPGA.

[0012] In one implementation, each of the plurality of first-level computing chipsets includes the same number of computing chips.

[0013] In this embodiment, each first-level computing chip group in the topology of the plurality of computing chips includes the same number of computing chip groups, which can reduce the difficulty of designing the connection between computing chips.

[0014] In one implementation, each of the second-level computing chipsets includes the same number of first-level computing chipsets.

[0015] In this embodiment, each second-level computing chip group in the topology of the plurality of computing chips includes the same number of first-level computing chip groups, which can reduce the difficulty of designing the connection between computing chips.

[0016] In one embodiment, each of the at least one third-level computing chipset includes the same number of second-level computing chipsets.

[0017] In this embodiment, each third-level computing chip group in the topology of the plurality of computing chips includes the same number of second-level computing chip groups, which can reduce the difficulty of designing the connection between computing chips.

[0018] In one embodiment, each computing chip includes multiple ports, and the number of the multiple ports is greater than or equal to the sum of a first number, a second number, and a third number; the first number is the number of other computing chips in the first-level computing chip group where the computing chip is located, the second number is the number of other first-level computing chip groups in the second-level computing chip group where the computing chip is located, and the third number is the number of other second-level computing chip groups in the third-level computing chip group where the computing chip is located.

[0019] For example, this topology includes two third-level computing chipsets, each third-level computing chipset includes three second-level computing chipsets, each second-level computing chipset includes four first-level computing chipsets, and each first-level computing chipset includes five computing chips. In this case, the number of first-level chipsets is 4, and the number of second-level chipsets is 3+2+1=6, so the number of ports per computing chip is greater than or equal to 10.

[0020] In this embodiment, the number of ports for each computing chip in the topology of multiple computing chips is greater than or equal to the sum of the number of other computing chips within its own first-level computing chip group and the number of other computing chip groups at the same level in other levels of computing chip groups. This allows for connecting more computing chips using as few ports as possible. Compared to topologies in related technologies, the topology of this application can construct a cluster of more computing chips with the same number of computing chip ports.

[0021] In one embodiment, each computing chip includes a chip number, which includes a first number, a second number, and a third number; wherein, the first number represents the sequence number of the second-level computing chip group within the third-level computing chip group to which the computing chip is located, the second number represents the sequence number of the first-level computing chip group within the second-level computing chip group to which the computing chip is located, and the third number represents the sequence number of the computing chip within the first-level computing chip group to which the computing chip is located, and each computing chip is connected to a computing chip corresponding to a number that changes by one in its own number.

[0022] In this embodiment, by numbering each computing chip, the connection relationship between multiple computing chips in the topology of multiple computing chips can be represented by a connection matrix, which facilitates the detection of the connection relationship between multiple computing chips in the topology of multiple computing chips, and the determination of other computing chips connected to each computing chip.

[0023] Secondly, this application provides a circuit board cluster, comprising: multiple circuit boards, each circuit board including at least one computing chip; the computing chips in the multiple circuit boards are connected in a manner as described in the topology of the multiple computing chips that may be implemented in the first aspect; and a frame for fixing the multiple circuit boards.

[0024] Thirdly, this application provides a computing device, including: a processor, and at least one topology of a plurality of computing chips as may be implemented in the first aspect; the processor is configured to, upon receiving a computing task, divide the computing task into a plurality of subtasks and assign the plurality of subtasks to computing chips in the topology of the at least one plurality of computing chips respectively. Attached Figure Description

[0025] The accompanying drawings used in the description of the embodiments or prior art are briefly introduced below.

[0026] Figure 1 is a schematic diagram of a multiprocessor interconnect system in the related technology;

[0027] Figure 2 is a schematic diagram of a topology of multiple computing chips provided in an embodiment of this application;

[0028] Figure 3(a) is a schematic diagram of a topology structure of 16 computing chips provided in an embodiment of this application;

[0029] Figure 3(b) is a schematic diagram of the interconnection of 16 computing chips provided in an embodiment of this application;

[0030] Figure 4 is a schematic diagram of a topology structure of 64 computing chips provided in an embodiment of this application;

[0031] Figure 5 is a schematic diagram of a topology structure of 128 computing chips provided in an embodiment of this application;

[0032] Figure 6 is a schematic diagram of the structure of a computing device provided in an embodiment of this application. Detailed Implementation

[0033] The technical solutions in the embodiments of this application will now be described with reference to the accompanying drawings.

[0034] In this article, the term "and / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. The symbol " / " in this article indicates that the related objects are in an "or" relationship; for example, A / B means A or B.

[0035] The terms "first" and "second," etc., used in the specification and claims herein are used to distinguish different objects, not to describe a specific order of objects. For example, "first response message" and "second response message," etc., are used to distinguish different response messages, not to describe a specific order of response messages.

[0036] In the embodiments of this application, the terms "exemplary" or "for example" are used to indicate that something is an example, illustration, or description. Any embodiment or design that is described as "exemplary" or "for example" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or design. Specifically, the use of the terms "exemplary" or "for example" is intended to present the relevant concepts in a specific manner.

[0037] In the description of the embodiments of this application, unless otherwise stated, "multiple" means two or more, for example, multiple processing units means two or more processing units, multiple elements means two or more elements, etc.

[0038] As shown in Figure 1, related technologies provide a multiprocessor interconnect system comprising multiple processors. Each port of each processor is connected to the ports of every other processor, forming a communication channel. Each communication channel allows data to be transmitted between processors only once, maximizing the frequency of computational tasks executed by the processors. However, establishing a communication channel between each processor and other processors requires configuring at least one port, meaning the number of processors in the interconnect system is related to the number of ports on each processor. Typically, the number of ports on a processor is very limited, at most a few dozen ports, resulting in a very limited number of processors in the interconnect system. This makes it difficult to allocate partitioned computational tasks among the processors in the interconnect system.

[0039] To address the shortcomings of related technologies, this application provides a topology for multiple computing chips, comprising at least three levels of computing chip groups. Each level of computing chip group includes at least one computing chip group of the previous level, and each port of each computing chip in the first-level computing chip group is connected to ports of other computing chips within its own first-level computing chip group, as well as to one computing chip in another computing chip group of the same level in other levels of computing chip groups, thereby increasing the richness of the topology. By enriching the topology, this application allows for easier allocation of segmented computing tasks across multiple computing chips, ensuring that input and output data generated after the execution of computing tasks are transmitted within the computing chip itself, or between two computing chips directly connected by a communication channel, without being relayed through other computing chips, thus maximizing the frequency of computing task execution.

[0040] Computing chips can refer to chips such as central processing units (CPUs), graphics processing units (GPUs), microcontroller units (MCUs), and FPGAs. The following description of the technical solution protected in this application will use an FPGA chip as an example.

[0041] This application provides a topology for multiple computing chips, comprising multiple computing chips. Each computing chip includes multiple ports. The ports of the computing chips can be connected to each other via optical fibers, electrical cables, or other wires, enabling the ports of the computing chips to receive data from other computing chips and to output data to other computing chips.

[0042] The topology of the multiple computing chips can include at least three levels of computing chipsets. The first level of computing chipset includes multiple computing chips. The second level of computing chipset includes at least one first-level computing chipset. And so on, with each level of computing chipset including at least one computing chipset from the previous level.

[0043] Each computing chip has a portion of its ports connected to other computing chips in its first-level computing chip group to establish a communication channel. Another portion of each computing chip's ports is connected to one computing chip in another first-level computing chip group within its second-level computing chip group to establish a communication channel. This process continues, with the remaining ports of each computing chip connecting to one computing chip in another computing chip group within the same level of its own computing chip group to establish a communication channel.

[0044] For example, as shown in Figure 2, the topology 200 of the plurality of computing chips includes N×M×L computing chips. Here, N, M, and L are all positive integers greater than or equal to 1. Each computing chip includes at least (N-1)+(M-1)+(L-1) ports.

[0045] The topology 200 of the multiple computing chips includes three levels of computing chipsets. The first level computing chipset includes N computing chips. Each computing chip has (N-1) ports connected to one port of each of the other (N-1) computing chips in the first level computing chipset to establish a communication channel.

[0046] Each level 2 computing chipset comprises M level 1 computing chipsets. Each computing chip has (M-1) ports connected to the other (M-1) level 1 computing chipsets in its level 2 computing chipset to establish a communication channel.

[0047] Each Level 3 computing chipset includes L Level 2 computing chipsets. Each computing chip has (L-1) ports connected to (L-1) other Level 2 computing chipsets outside of its own Level 3 computing chipset to establish communication channels.

[0048] In this embodiment, the number of ports of each computing chip is greater than or equal to the sum of the number of other computing chips in the first-level computing chip group and the number of other computing chip groups in the same level of the other levels of computing chip groups in which it is located.

[0049] For example, if the number of ports on each computing chip is greater than the sum of the number of other computing chips within its own first-level computing chip group and the number of other computing chip groups at the same level in other levels, the excess ports of the computing chip can be connected to other computing chips in other levels to establish a communication channel. This application, by increasing the number of ports on computing chips, allows the computing chip to connect to more computing chips, further enhancing the richness of the topology of these multiple computing chips.

[0050] In this embodiment, the multiple computing chips in the topology can be of the same type, such as a CPU, GPU, MCU, FPGA, etc. Since all computing chips in the topology of this application are of the same type, the difficulty of designing the connections between computing chips can be reduced.

[0051] Optionally, the multiple computing chips in the topology of the multiple computing chips can also be of various types, such as multiple types of chips including CPU, GPU, MCU, and FPGA. For example, if the multiple computing chips in the topology of the multiple computing chips are of two types, then each first-level computing chip group includes two different types of computing chips. This application, by setting multiple different types of computing chips within the first-level computing chip group, enables each computing chip to connect with other types of computing chips, further enhancing the richness of the topology of the multiple computing chips.

[0052] In this embodiment, the number of computing chips in each first-level computing chipset can be the same. The number of computing chips in each first-level computing chipset can be partially or completely different. The number of computing chips in each second-level or higher-level computing chipset that includes the computing chipset of the previous level can be the same. The number of computing chips in each second-level or higher-level computing chipset that includes the computing chipset of the previous level can be partially or completely different.

[0053] In this embodiment of the application, when designing the topology of multiple computing chips, the designer can define a number for each computing chip, represented as (gx-1,…,g1,g0). Here, gx-1 represents the sequence number of the computing chip group at level x-1 in the topology, …, g1 represents the sequence number of the first-level computing chip group within the second-level computing chip group, and g0 represents the sequence number of the computing chip within the first-level computing chip group. For example, taking the gray computing chip in Figure 2 as an example, the chip's number is (g2=1,g1=2,g0=n+2).

[0054] In this embodiment, each computing chip is connected to a computing chip whose serial number changes by one bit. For example, a computing chip numbered (gx-1,…,g1,g0) can be connected to a computing chip numbered {(fgx-1,…,g1,g0), where fgx-1 = 1, 2,…, fgx-1 ≠ gx-1}. Similarly, this computing chip can be connected to a computing chip numbered {(gx-1,…,fg1,g0), where fg1 = 1, 2,…, fg1 ≠ g1}. This computing chip can also be connected to a computing chip numbered {(gx-1,…,g1,fg0), where fg0 = 1, 2,…, fg0 ≠ g0}.

[0055] In this embodiment, the designer can use a connection matrix to represent the connection relationships between multiple computing chips in a topology of multiple computing chips. For example, consider the topology 200 of multiple computing chips in Figure 2. Since the third-level computing chipset includes L second-level computing chipsets, it can be represented by an L×L matrix. The connection matrix of the third-level computing chipset is:

[0056] Where L represents the number of second-level computing chipsets in a third-level computing chipset. M represents the number of first-level computing chipsets in a second-level computing chipset. N represents the number of computing chips in a first-level computing chipset. A(L,M,N) is a symmetric L×L matrix. The connection matrix A(M,N) of the second-level computing chipsets is located on the diagonal of A(L,M,N).

[0057] I L (M,N) is the identity matrix, which is a matrix whose only diagonal elements are non-zero and equal to 0. L The order of (M,N) and A L The orders of (M, N) are the same, which is M×N. I = \sum_{i=1}^{N-1}(g_i-1)\Pi_{j=0}^{i-1}K_j+g_0. I represents the index of the computing chip. i represents the row number in the connection matrix, and j represents the column number in the connection matrix.

[0058] Since the second-level computing chipset comprises M first-level computing chipsets, it can be represented by an M×M matrix. The connection matrix of the second-level computing chipset is:

[0059] Where A(M,N) is a symmetric M×M matrix. The connection matrix A(N) of the first-level computing chipset is located on the diagonal of A(M,N). M (N) is the identity matrix, which is a matrix whose only diagonal elements are non-zero and equal to 0. M The order of (N) and A M (N) has the same order, which is N.

[0060] Since the first-level computing chipset consists of N computing chips, it can be represented by an N×N matrix. The connection matrix of the first-level computing chipset is:

[0061] Here, A(N) is a symmetric N×N matrix. All elements on the diagonal of A(N) are 0, and all other elements are 1.

[0062] The connection matrix A(N) of the first-level computing chipset is located on the diagonal of A(M,N). M (N) is the identity matrix, which is a matrix whose only diagonal elements are non-zero and equal to 0. M The order of (N) and A M (N) has the same order, which is N.

[0063] Connect the elements of matrix A(N) using a i,j The values ​​of i and j are 0 or 1. i = 0 indicates that there is no connection between this computing chip and other computing chips, and i = 1 indicates that there is a connection between this computing chip and other computing chips. j = 0 indicates that there is no connection between this computing chip and other computing chips, and j = 1 indicates that there is a connection between this computing chip and other computing chips.

[0064] In this way, designers can build connection matrices for different levels of computing chipsets.

[0065] In this embodiment of the application, after receiving the connection relationships of each port of each computing chip in the topology of multiple computing chips and the connection matrices of different levels of computing chip groups, the test device can use the connection matrices of different levels of computing chip groups to detect the connection relationships of each port of each computing chip in the topology of multiple computing chips, so as to detect whether the connection relationships between multiple computing chips in the topology of multiple computing chips satisfy the relationships recorded in the connection matrix, thereby realizing the detection of the connection relationships between multiple computing chips in the topology of multiple computing chips.

[0066] In this embodiment, after obtaining the number of computing chips and the connection matrix of different levels of computing chip groups in the topology of the computing chip, the designer can use the connection matrix of different levels of computing chip groups to connect the ports of a specified number of computing chips according to the connection matrix of different levels of computing chip groups, so as to construct a topology of multiple computing chips including at least three levels of computing chip groups. In this embodiment, the topology of multiple computing chips includes at least three levels of computing chip groups. Each level of computing chip group includes at least one computing chip group of the previous level, and each port of each computing chip in the first level of computing chip group is connected to the ports of other computing chips in the first level of computing chip group, and to one computing chip in the same level of other computing chip groups in other levels of computing chip groups, thereby improving the richness of the topology of multiple computing chips. By enriching the topology, this application makes it easier to allocate the segmented computing tasks to multiple computing chips, and ensures that the input and output data generated after the computing tasks are executed are transmitted within the computing chip or between two computing chips with direct communication channels, without being relayed through other computing chips, thereby maximizing the frequency of the topology when executing computing tasks.

[0067] The technical solution protected by this application is described below using three embodiments.

[0068] Figure 3(a) is a schematic diagram of a topology structure of 16 computing chips provided in an embodiment of this application. As shown in Figure 3(a), the topology structure 300 of the computing chips includes 16 computing chips.

[0069] The computing chip topology 300 includes four levels of computing chipsets. The first-level computing chipset includes two computing chips. The second-level computing chipset includes two first-level computing chipsets. The third-level computing chipset includes two second-level computing chipsets. The fourth-level computing chipset includes two third-level computing chipsets.

[0070] Each computing chip includes four external connection ports. Two ports on each chip connect to one other chip in its first-level computing chip group to establish a communication channel. One port on each chip connects to one other first-level computing chip in its second-level computing chip group to establish a communication channel. One port on each chip connects to one other second-level computing chip in its third-level computing chip group to establish a communication channel. One port on each chip connects to one other third-level computing chip in its fourth-level computing chip group to establish a communication channel.

[0071] Assume the computing chips are numbered (g3, g2, g1, g0), g2 = 1, 2. g1 = 1, 2. g0 = 1, 2. The connection matrix of the fourth-level computing chipset is:

[0072] The connection matrix for the third-level computing chipset is:

[0073] The connection matrix for the second-level computing chipset is:

[0074] The connection matrix for the first-level computing chipset is:

[0075] Finally, the connection matrix of the fourth-level computing chipset is as follows:

[0076] Where I(2,2,2) is an 8th-order identity matrix, I(2,2) is a 4th-order identity matrix, and I(2) is a 2nd-order identity matrix.

[0077] Each computing chip is connected to a computing chip with a number that differs from its own by one digit. As shown in Figure 3(b), taking the computing chip with the number (g3=1,g2=1,g1=1,g0=1) as an example, this computing chip can be directly connected to four computing chips with the number 2,1,1,1,1,1,1,1,1,1,2,1, and 1,1,1,2.

[0078] Figure 4 is a schematic diagram of a topology structure of 64 computing chips provided in an embodiment of this application. As shown in Figure 4, the topology structure 400 of the computing chips includes 64 computing chips.

[0079] The computing chip topology 400 includes three levels of computing chipsets. The first-level computing chipset includes four computing chips. The second-level computing chipset includes four first-level computing chipsets. The third-level computing chipset includes four second-level computing chipsets.

[0080] Each computing chip includes nine external connection ports. Three ports on each chip connect to the other three chips in its first-level computing chip group to establish a communication channel. Three ports on each chip also connect to the other three first-level computing chips in its second-level computing chip group to establish a communication channel. Finally, three ports on each chip connect to the other three second-level computing chips in its third-level computing chip group to establish a communication channel.

[0081] Assume the computing chips are numbered (g2, g1, g0), where g2 = 1, 2, 3, 4, g1 = 1, 2, 3, 4, and g0 = 1, 2, 3, 4. The connection matrix of the third-level computing chipset is:

[0082] The connection matrix for the second-level computing chipset is:

[0083] The connection matrix for the first-level computing chipset is:

[0084] Where I(4,4) is a 16th-order identity matrix and I(4) is a 4th-order identity matrix.

[0085] Each computing chip is connected to a computing chip with a number that differs from its own by one digit. Taking the computing chip numbered (g2=1, g1=2, g0=3) as an example, this computing chip can be directly connected to computing chips with three combinations of numbers, totaling nine: 2,2,3 / 3,2,3 / 4,2,3; 1,1,3 / 1,3,3 / 1,4,3; and 1,2,1 / 1,2,2 / 1,2,4.

[0086] Figure 5 is a schematic diagram of a topology structure of 128 computing chips provided in an embodiment of this application. As shown in Figure 5, the topology structure 500 of the computing chips includes 128 computing chips.

[0087] The computing chip topology 500 includes four levels of computing chipsets. The first-level computing chipset includes four computing chips. The second-level computing chipset includes five first-level computing chipsets. The third-level computing chipset includes three second-level computing chipsets. The fourth-level computing chipset includes two third-level computing chipsets.

[0088] Each computing chip includes 10 external connection ports. Three ports on each chip connect to the other three chips in its first-level computing chip group to establish communication channels. Four ports on each chip connect to the other four first-level computing chip groups in its second-level computing chip group to establish communication channels. Two ports on each chip connect to the other two second-level computing chip groups in its third-level computing chip group to establish communication channels. One port on each chip connects to the other third-level computing chip group in its fourth-level computing chip group to establish a communication channel.

[0089] Assume the computing chips are numbered (g3, g2, g1, g0), where g2 = 1, 2, g2 = 1, 2, 3, g1 = 1, 2, 3, 4, 5, and g0 = 1, 2, 3, 4. The connection matrix of the fourth-level computing chipset is:

[0090] The connection matrix for the third-level computing chipset is:

[0091] The connection matrix for the second-level computing chipset is:

[0092] The connection matrix for the first-level computing chipset is:

[0093] Where I(4,5,3) is a 60th-order identity matrix, I(4,5) is a 20th-order identity matrix, and I(4) is a 4th-order identity matrix.

[0094] Each computing chip is connected to a computing chip with a unique identifier that differs from its own by one digit. For example, a computing chip numbered (g3=1, g2=2, g1=3, g0=4) can be directly connected to computing chips with four combinations of identifiers: 2, 2, 3, 4; 1, 1, 3, 4 / 1, 3, 3, 4; 1, 2, 1, 4 / 1, 2, 2, 4 / 1, 2, 4, 4 / 1, 2, 5, 4; and 1, 2, 3, 2 / 1, 2, 3, 3, totaling 10 computing chips.

[0095] This application provides a circuit board cluster comprising multiple circuit boards and a frame. The multiple circuit boards are respectively fixed to the frame, forming a single integrated structure. Each circuit board includes one or more computing chips.

[0096] In one embodiment, each circuit board includes one computing chip as an example. The computing chips in each circuit board can be connected according to the topology of multiple computing chips described in Figures 2-5 and the corresponding protection schemes above.

[0097] In one embodiment, taking a computing chip in a first-level computing chip group in a topology structure of multiple computing chips as described in Figures 2-5 and the corresponding protection schemes above as an example, each circuit board includes such a computing chip. The computing chips in each circuit board are interconnected, and each circuit board can be connected according to the connection relationship between the first-level computing chip groups in the topology structure of multiple computing chips as described in Figures 2-5 and the corresponding protection schemes above.

[0098] In one embodiment, taking a computing chip whose topology includes multiple computing chips as described in Figures 2-5 and the corresponding protection schemes above as an example, each circuit board can be connected according to the topology of multiple computing chips as described in Figures 2-5 and the corresponding protection schemes above.

[0099] Figure 6 is a schematic diagram of a computing device provided in an embodiment of this application. As shown in Figure 6, the computing device 600 includes a bus 610, a topology 620 of multiple computing chips, a processor 630, a memory 640, and a communication interface 650. The topology 620 of multiple computing chips, the processor 630, the memory 640, and the communication interface 650 communicate with each other through the bus 610. The computing device 600 can be a server, computer, laptop, server rack, etc. It should be understood that this application does not limit the number of processors, memory, and other devices in the computing device 600.

[0100] Bus 610 can be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. Buses can be categorized as address buses, data buses, control buses, etc. For ease of illustration, only one line is used in Figure 6, but this does not imply that there is only one bus or one type of bus. Bus 610 can include pathways for transmitting information between various components of computing device 600 (e.g., a topology 620 of multiple computing chips, processor 630, memory 640, and communication interface 650).

[0101] The topology 620 of multiple computing chips can be the topology of multiple computing chips described in Figures 2-5 and the corresponding protection schemes above. In this embodiment, the connection relationship between the ports of the multiple computing chips in the topology 620 of multiple computing chips is stored in the memory 640 in the form of a diagram.

[0102] Processor 630 can be any one or more of the following: central processing unit (CPU), graphics processing unit (GPU), microprocessor (MP), or digital signal processor (DSP). It should be noted that the chip type of processor 630 differs from the type of computing chips in the multi-chip topology 620. The chip type of processor 630 is the same as one of the types of computing chips in the multi-chip topology 620.

[0103] Optionally, the processor 630 may be one or more computing chips in a topology 620 of multiple computing chips.

[0104] Memory 640 may include volatile memory, such as random access memory (RAM). Memory 640 may also include non-volatile memory, such as read-only memory (ROM), flash memory, hard disk drive (HDD), or solid state drive (SSD).

[0105] The memory 640 stores executable code or program code, which enables the processor 630 to execute the executable code or program code to perform computational tasks.

[0106] The communication interface 650 uses transceiver modules, such as, but not limited to, network interface cards and transceivers, to enable communication between the computing device 650 and other devices or communication networks.

[0107] In this embodiment, after receiving a computing task, the processor 630 models the computing task using methods such as ordinary graphs and hypergraphs to obtain a computing graph of the computing task. The processor 630 can obtain connection matrices at different levels of the topology 620 of multiple computing chips, and then segment the computing graph of the computing task based on the connection matrices at different levels. Two or more subtasks with interdependent relationships are assigned to one computing chip in the topology 620 of multiple computing chips, or two computing chips directly connected by a communication channel. This ensures that the input and output data generated after the computing task is executed are transmitted within the computing chip or between the two computing chips directly connected by a communication channel, without being relayed through other computing chips, thereby maximizing the frequency of the topology 620 of multiple computing chips when executing computing tasks.

[0108] Take FPGA as an example of a computing chip. FPGA chips are characterized by high flexibility, reconfigurability, and short development cycles, and can be widely used in various fields. Since the front-end code of FPGA chips and application-specific integrated circuits (ASICs) is usually developed based on hardware description languages ​​(such as Verilog HDL), the logic structure and design flow of FPGA chips and ASICs have certain similarities. Therefore, FPGA chips can serve as a cost-effective chip verification infrastructure, allowing ASIC code to be compiled and run on FPGA chips.

[0109] Today, FPGA chip prototyping is a mature technology. By porting the register transfer level (RTL) to the FPGA chip, it's possible to verify the functionality and performance of ASICs, application-specific standard products (ASSPs), and systems-of-chips (SoCs). This is currently the mainstream and mature chip verification method. Furthermore, compared to simulators or hardware accelerators, FPGA chips operate at speeds closer to real chips, allowing software developers to collaborate on low-level software development.

[0110] When EDA tools use multiple FPGA chips for simulation, test signals inevitably need to be transmitted between the FPGA chips. Therefore, EDA tools segment the computation graph of the computation task based on different levels of connection matrices, assigning two or more interdependent subtasks to the same FPGA chip or two FPGA chips directly connected by a communication channel. This ensures that the input and output data generated after the computation task is executed are transmitted within the FPGA chip itself or between the two FPGA chips directly connected by a communication channel, without being relayed through other FPGA chips, thus maximizing the frequency of FPGA chip simulation. At the same time, fixed hardware topology connections can effectively reduce manual labor, reduce hardware plug-and-play losses, improve iteration speed, and extend service life.

[0111] In the description of this specification, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples.

[0112] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions in the embodiments of this application.

Claims

1. A topology for multiple computing chips, characterized in that, include: Multiple first-level computing chipsets, each of which includes at least two computing chips; Multiple second-level computing chipsets, each second-level computing chipset including at least one first-level computing chipset; At least one third-level computing chipset, and each third-level computing chipset includes at least one second-level computing chipset; Each computing chip communicates with other computing chips in its first-level computing chip group, another computing chip in its second-level computing chip group, and another computing chip in its third-level computing chip group via a communication channel.

2. The topology according to claim 1, characterized in that, The at least two computing chips in the first-level computing chipset are of the same type.

3. The topology according to claim 2, characterized in that, The computing chips are of the following types: CPU, GPU, MCU, and FPGA.

4. The topology according to any one of claims 1-3, characterized in that, Each of the multiple first-level computing chipsets includes the same number of computing chips.

5. The topology according to any one of claims 1-4, characterized in that, Each second-level computing chipset includes the same number of first-level computing chipsets.

6. The topology according to any one of claims 1-5, characterized in that, Each of the at least one third-level computing chipset includes the same number of second-level computing chipsets.

7. The topology according to any one of claims 1-6, characterized in that, Each computing chip includes multiple ports, and the number of the multiple ports is greater than or equal to the sum of a first number, a second number, and a third number; the first number is the number of other computing chips in the first-level computing chip group where the computing chip is located, the second number is the number of other first-level computing chip groups in the second-level computing chip group where the computing chip is located, and the third number is the number of other second-level computing chip groups in the third-level computing chip group where the computing chip is located.

8. The topology according to any one of claims 1-7, characterized in that, Each computing chip includes a chip number, which comprises a first number, a second number, and a third number; wherein, the first number represents the sequence number of the computing chip in the second-level computing chip group within the third-level computing chip group, the second number represents the sequence number of the computing chip in the first-level computing chip group within the second-level computing chip group, and the third number represents the sequence number of the computing chip in the first-level computing chip group. Each computing chip is connected to a computing chip that corresponds to a different number in its own numbering.

9. A circuit board cluster, characterized in that, include: Multiple circuit boards, each circuit board including at least one computing chip; the computing chips in the multiple circuit boards are connected in a topological manner according to any one of claims 1-8. A frame for securing the plurality of circuit boards.

10. A computing device, characterized in that, include: processor, At least one topology of a plurality of computing chips as described in any one of claims 1-8; The processor is used to, upon receiving a computing task, divide the computing task into multiple subtasks and assign the multiple subtasks to computing chips in the topology of the at least one plurality of computing chips.

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