Nitride semiconductor device

Abstract

A nitride semiconductor device (1) comprises: a substrate (10); an n-type drift layer (12); a p-type block layer (14); a nitride semiconductor layer (21) provided so as to cover the inner surface of a vertical conduction opening (20) and the upper side of the block layer (14); a p-type threshold adjustment layer (28); a gate electrode (32) electrically connected to the threshold adjustment layer (28); a source electrode (34) electrically connected to the nitride semiconductor layer (21); and a drain electrode (36) provided below the substrate (10). The nitride semiconductor layer (21) includes an electron transit layer (22) and an electron supply layer (23) having a larger band gap than the electron transit layer (22). The threshold adjustment layer (28) covers the inner surface of a recess (26) provided in a portion of the electron supply layer (23) located above the upper surface of the block layer (14).

Description

Nitride Semiconductor Devices

[0001] The present disclosure relates to nitride semiconductor devices.

[0002] Nitride semiconductors, such as GaN and AlGaN, have a larger band gap and a higher breakdown field and saturated drift velocity than compound semiconductor materials such as Si semiconductors or GaAs, and are therefore being applied to electronic devices such as high-voltage power devices and high-speed, high-output transistors.

[0003] Patent Document 1 discloses a vertical FET (Field Effect Transistor) formed using a GaN-based semiconductor material. The vertical FET disclosed in Patent Document 1 utilizes, as a channel, a two-dimensional electron gas (2DEG) generated by a polarization effect near the heterointerface of AlGaN / GaN.

[0004] Patent No. 6511645

[0005] The device disclosed in Patent Document 1 has a problem in that it is not possible to reduce the on-resistance while increasing the degree of freedom in setting the threshold voltage.

[0006] Therefore, the present disclosure provides a nitride semiconductor device that can achieve both a reduced on-resistance and an improved degree of freedom in setting the threshold voltage.

[0007] a gate electrode electrically connected to the fourth nitride semiconductor layer; a source electrode provided above the substrate and electrically connected to the third nitride semiconductor layer; and a drain electrode provided below the substrate, wherein the third nitride semiconductor layer includes an electron transit layer and an electron supply layer provided above the electron transit layer and having a band gap larger than that of the electron transit layer, and the fourth nitride semiconductor layer covers an inner surface of a recess provided in a portion of the electron supply layer located above an upper surface of the second nitride semiconductor layer.

[0008] According to the present disclosure, it is possible to achieve both a reduction in on-resistance and an improvement in the degree of freedom in setting the threshold voltage.

[0009] FIG. 1 is a cross-sectional view of a nitride semiconductor device according to an embodiment. FIG. 2 is an enlarged cross-sectional view of a main portion of the nitride semiconductor device according to the embodiment. FIG. 3A is a cross-sectional view for explaining a step of a method for manufacturing a nitride semiconductor device according to the embodiment. FIG. 3B is a cross-sectional view for explaining a step of a method for manufacturing a nitride semiconductor device according to the embodiment. FIG. 3C is a cross-sectional view for explaining a step of a method for manufacturing a nitride semiconductor device according to the embodiment. FIG. 3D is a cross-sectional view for explaining a step of a method for manufacturing a nitride semiconductor device according to the embodiment. FIG. 3E is a cross-sectional view for explaining a step of a method for manufacturing a nitride semiconductor device according to the embodiment. FIG. 3F is a cross-sectional view for explaining a step of a method for manufacturing a nitride semiconductor device according to the embodiment. FIG. 3G is a cross-sectional view for explaining a step of a method for manufacturing a nitride semiconductor device according to the embodiment. FIG. 4 is a cross-sectional view of a nitride semiconductor device according to a modification of the embodiment. FIG. 5A is a cross-sectional view for explaining a step of a method for manufacturing a nitride semiconductor device according to the modification of the embodiment. FIG. 5B is a cross-sectional view for explaining a step of a method for manufacturing a nitride semiconductor device according to the modification of the embodiment. FIG. 5C is a cross-sectional view for explaining a step of a method for manufacturing a nitride semiconductor device according to the modification of the embodiment.

[0010] (Findings that Form the Basis of the Present Disclosure) The present inventors have found that the following problems arise with the conventional devices described in the "Background Art" section.

[0011] In the device disclosed in Patent Document 1, the p-type semiconductor layer raises the potential of the conduction band edge in the channel portion, thereby increasing the threshold voltage and realizing a normally-off FET. In other words, when the gate-source voltage is 0 V, 2DEG is not generated directly below the p-type semiconductor layer.

[0012] The polarization that generates the 2DEG includes spontaneous polarization due to the atomic arrangement of GaN and piezoelectric polarization due to the difference in lattice constant between AlGaN and GaN. Piezoelectric polarization varies depending on the composition and film thickness of AlGaN. Therefore, the concentration of the 2DEG can be changed by adjusting at least one of the composition and film thickness of AlGaN. Increasing the concentration of the 2DEG can reduce the on-resistance.

[0013] However, if the concentration of 2DEG is increased to reduce the on-resistance, the FET cannot be made normally off because the 2DEG does not disappear even directly below the p-type semiconductor layer when the gate-source voltage is 0 V. As such, there is a limit to the range of threshold voltage that can be set to reduce the on-resistance.

[0014] Therefore, an object of the present disclosure is to provide a nitride semiconductor device that can achieve both a reduced on-resistance and an improved degree of freedom in setting the threshold voltage.

[0015] a gate electrode electrically connected to the fourth nitride semiconductor layer; a source electrode provided above the substrate and electrically connected to the third nitride semiconductor layer; and a drain electrode provided below the substrate, wherein the third nitride semiconductor layer includes an electron transit layer and an electron supply layer provided above the electron transit layer and having a band gap larger than that of the electron transit layer, and the fourth nitride semiconductor layer covers an inner surface of a recess provided in a portion of the electron supply layer located above an upper surface of the second nitride semiconductor layer.

[0016] This allows the threshold voltage of the FET to be adjusted by the thickness of the electron supply layer in the recessed portion, thereby increasing the degree of freedom in setting the composition of the electron supply layer and the film thickness of the electron supply layer in the non-recessed portion. Therefore, for example, by adjusting the composition of the electron supply layer and / or the film thickness of the electron supply layer in the non-recessed portion, it is possible to reduce the on-resistance while suppressing the effect on the threshold voltage. Thus, the nitride semiconductor device according to this aspect can achieve both reduced on-resistance and increased freedom in setting the threshold voltage.

[0017] A nitride semiconductor device according to a second aspect of the present disclosure is the nitride semiconductor device according to the first aspect, wherein the electron supply layer includes a side portion provided along a side surface of the first opening and an upper surface portion provided at a position overlapping an upper surface of the second nitride semiconductor layer in a plan view of the substrate, and wherein, when the thickness of a portion of the upper surface portion where the recessed portion is not provided is defined as d1, the thickness of a portion of the electron supply layer where the recessed portion is provided is defined as d2, and the thickness of the side portion is defined as d3, the relationship d2<d1<d3 is satisfied.

[0018] As a result, the threshold voltage of the FET is adjusted by the thickness d2, which increases the degree of freedom in setting the thicknesses d1 and d3. For example, at least one of the thicknesses d1 and d3 can be increased so as to reduce the on-resistance. In this way, the nitride semiconductor device according to this aspect can achieve both a reduced on-resistance and an increased degree of freedom in setting the threshold voltage.

[0019] A nitride semiconductor device according to a third aspect of the present disclosure is the nitride semiconductor device according to the first or second aspect, wherein the recess portion is provided at a position overlapping the second nitride semiconductor layer in a plan view of the substrate.

[0020] This allows the majority of the recess to be provided in the flat portion of the electron supply layer outside the first opening. This reduces manufacturing variations in the dimensions and shape of the recess, thereby reducing variations in threshold voltage. This allows for a highly reliable nitride semiconductor device.

[0021] A nitride semiconductor device according to a fourth aspect of the present disclosure is the nitride semiconductor device according to the third aspect, wherein the recess portion is provided at a position overlapping an upper surface of the second nitride semiconductor layer in a plan view of the substrate.

[0022] This allows a recess to be provided in the flat portion of the electron supply layer outside the first opening. This reduces manufacturing variations in the dimensions and shape of the recess, thereby reducing variations in threshold voltage. This allows for a highly reliable nitride semiconductor device.

[0023] A nitride semiconductor device according to a fifth aspect of the present disclosure is the nitride semiconductor device according to any one of the first to fourth aspects, wherein the gate electrode is provided at a position overlapping each of the first opening and the recess portion in a plan view of the substrate.

[0024] This makes it possible to increase the contact area between the fourth nitride semiconductor layer and the gate electrode, thereby improving the controllability of the channel by the gate electrode.

[0025] A nitride semiconductor device according to a sixth aspect of the present disclosure is the nitride semiconductor device according to any one of the first to fifth aspects, wherein the source electrode is in contact with the electron transit layer and the second nitride semiconductor layer within a second opening that, in a plan view of the substrate, is outside the first opening and penetrates the third nitride semiconductor layer to reach the second nitride semiconductor layer.

[0026] This allows the source electrode to come into contact with the 2DEG, reducing the contact resistance of the source electrode and the on-resistance.

[0027] Hereinafter, the embodiments will be specifically described with reference to the drawings.

[0028] The embodiments described below are all comprehensive or specific examples. The numerical values, shapes, materials, components, component placement and connection configurations, steps, and step order shown in the following embodiments are merely examples and are not intended to limit the present disclosure. Furthermore, among the components in the following embodiments, components not described in the independent claims are described as optional components.

[0029] Furthermore, each figure is a schematic diagram and is not necessarily an exact illustration. Therefore, for example, the scales of the figures do not necessarily match. Furthermore, in each figure, substantially the same components are given the same reference numerals, and redundant explanations are omitted or simplified.

[0030] Furthermore, in this specification, terms indicating the relationship between elements, such as parallel or orthogonal, terms indicating the shape of elements, such as rectangular or trapezoidal, and numerical ranges are not expressions that only express a strict meaning, but are expressions that also include a substantially equivalent range, for example, a difference of about a few percent.

[0031] In this specification, the "thickness direction" of a substrate refers to the direction perpendicular to the main surface of the substrate. The thickness direction is the same as the stacking direction of the semiconductor layers, and is also referred to as the "vertical direction." The direction parallel to the main surface of the substrate may be referred to as the "lateral direction." A "vertical" device refers to a device in which the main path of a main current, such as a drain current or a forward current, is vertical, i.e., a device in which the main current passes vertically through the substrate. A "lateral" semiconductor device refers to a device in which the main path of a main current, such as a drain current or a forward current, is horizontal, i.e., a device in which the main current does not pass through the substrate.

[0032] Furthermore, the side on which the heterostructure is provided with respect to the substrate is considered to be "upper" or "upper side," and the opposite side is considered to be "lower" or "lower side." In this specification, the terms "upper" and "lower" do not refer to the upward direction (vertically upward) and downward direction (vertically downward) in absolute spatial recognition, but are used as terms defined by a relative positional relationship based on the stacking order in the stacked structure. Furthermore, the terms "upper" and "lower" are used not only when two components are arranged with a gap between them and another component is present between them, but also when two components are arranged in close contact with each other and the two components are in contact.

[0033] In this specification, unless otherwise specified, the term "plan view" refers to a view perpendicular to the main surface of the substrate of the nitride semiconductor device, that is, a view of the main surface of the substrate from the front.

[0034] In addition, in this specification, "A and B overlap in a plan view" means that at least a part of A overlaps with at least a part of B. In other words, this includes cases where only a part of A overlaps with only a part of B, where all of A overlaps with B, where all of B overlaps with A, and where A and B completely overlap with each other.

[0035] In this specification, AlGaN refers to a ternary mixed crystal Al ｘ Ga １－ｘ Hereinafter, multi-element mixed crystals are abbreviated by the arrangement of the symbols of the respective constituent elements, such as AlInN, GaInN, etc. For example, AlInN, which is an example of a nitride semiconductor, ｘ Ga １－ｘ－ｙ In ｙ N (0<x<1, 0<y<1, and 0<x+y<1) is abbreviated as AlGaInN, where x, 1-xy, and y represent the composition ratios of Al, Ga, and In, respectively.

[0036] Furthermore, n-type and p-type indicate the conductivity types of semiconductors, and are conductivity types of opposite polarity. ＋ The n-type indicates a state in which a semiconductor is doped with a high concentration of n-type dopants, i.e., a heavily doped semiconductor.－ The term "type" refers to a state in which a semiconductor is doped with a low concentration of n-type dopant, i.e., a so-called lightly doped state. ＋ Type and n － Both types are examples of n-type, and may be referred to as n-type without distinction. ＋ Type and p － The same is true for types.

[0037] Furthermore, "A contains B as a main component" means that B has the highest composition ratio among the elements constituting A. Furthermore, a layer made of A and a layer constituted by A mean that the layer contains substantially only A. However, the layer may contain other elements as impurities, such as elements that are unavoidable in the manufacturing process, at a rate of 1 at % or less.

[0038] Furthermore, in this specification, ordinal numbers such as "first" and "second" do not refer to the number or order of components unless otherwise specified, but are used for the purpose of avoiding confusion and distinguishing between components of the same type.

[0039] (Embodiment) [Configuration] First, the configuration of a nitride semiconductor device according to an embodiment will be described with reference to FIG.

[0040] Fig. 1 is a cross-sectional view of a nitride semiconductor device 1 according to this embodiment. In Fig. 1, components such as semiconductor layers, insulating layers, and electrodes other than an electron transit layer 22 are shaded with diagonal lines to indicate a cross section. This is the same for Fig. 2 and subsequent cross-sectional views.

[0041] The nitride semiconductor device 1 includes a normally-off vertical FET. In the nitride semiconductor device 1, for example, the source electrode 34 is grounded, and a positive potential is applied to the drain electrode 36. The potential applied to the drain electrode 36 is, for example, not limited to, 100 V or more and 1200 V or less. The nitride semiconductor device 1 performs modulation according to the potential applied to the gate electrode 32. For example, when 0 V or a negative potential (e.g., −5 V) is applied to the gate electrode 32, no current flows between the drain electrode 36 and the source electrode 34. That is, the nitride semiconductor device 1 is in a non-conductive state (off). When a positive potential (e.g., +5 V) is applied to the gate electrode 32, a current flows from the drain electrode 36 to the source electrode 34. That is, the nitride semiconductor device 1 is in a conductive state (on). The current flowing from the drain electrode 36 to the source electrode 34 when the device is on is called a drain current. The drain current flows through the substrate 10 in its thickness direction (i.e., vertical direction).

[0042] 1 , the nitride semiconductor device 1 includes a substrate 10, a drift layer 12, a block layer 14, a nitride semiconductor layer 21, a threshold adjustment layer 28, a gate electrode 32, a source electrode 34, and a drain electrode 36. The nitride semiconductor layer 21 includes an electron transit layer 22, an electron supply layer 23, and a 2DEG 24. The electron supply layer 23 has a recess 26. The nitride semiconductor device 1 also includes an insulating layer 40 and a source wiring 50. The nitride semiconductor device 1 also has a vertical conduction opening 20 and a source opening 30.

[0043] The nitride semiconductor device 1 is a device in which a semiconductor layer including a channel contains a nitride semiconductor as a main component. Specifically, the drift layer 12, the block layer 14, the electron transit layer 22, the electron supply layer 23, and the threshold adjustment layer 28 each contain a nitride semiconductor as a main component.

[0044] Each of the components of the nitride semiconductor device 1 will be described in detail below.

[0045] The substrate 10 is made of a nitride semiconductor and has a rectangular shape in plan view, for example, but is not limited to this.

[0046] The substrate 10 has a thickness of, for example, 300 μm and a carrier concentration of 5×10 １８ cm －３ n ＋ The substrate is made of GaN.

[0047] The substrate 10 does not have to be a nitride semiconductor substrate, but may be, for example, a Si substrate, a SiC substrate, or a ZnO substrate.

[0048] The drift layer 12 is an example of an n-type first nitride semiconductor layer provided above the substrate 10. The drift layer 12 is, for example, an n-type first nitride semiconductor layer having a thickness of 8 μm. － The drift layer 12 is a film made of GaN of the type. The donor concentration of the drift layer 12 is, for example, 1×10 １５ cm －３ 1x10 or more １７ cm －３ As an example, １６ cm －３ The carbon concentration (C concentration) of the drift layer 12 is, for example, 1×10 １５ cm －３ 5x10 or more １６ cm －３ The drift layer 12 is provided in contact with, for example, the upper surface (main surface) of the substrate 10 .

[0049] The block layer 14 is an example of a p-type second nitride semiconductor layer provided above the drift layer 12. The block layer 14 has a thickness of 400 nm and a carrier concentration of 1×10 １７ cm －３ The block layer 14 is a film made of p-type GaN, where P is a GaN film. The block layer 14 is provided in contact with the upper surface of the drift layer 12.

[0050] A vertical conduction opening 20 is provided in the block layer 14. The vertical conduction opening 20 is an example of a first opening that penetrates the block layer 14 and reaches the drift layer 12. A bottom surface 20a of the vertical conduction opening 20 is part of the upper surface of the drift layer 12. As shown in FIG. 1 , the bottom surface 20a is located below the lower surface of the block layer 14. The lower surface of the block layer 14 corresponds to the interface between the block layer 14 and the drift layer 12. The bottom surface 20a is, for example, parallel to the major surface of the substrate 10. When the nitride semiconductor device 1 is on, a drain current flows between the drain electrode 36 and the source electrode 34 through the bottom surface 20a of the vertical conduction opening 20.

[0051] In this embodiment, the vertical conductive opening 20 is formed so that the opening area increases as it becomes farther from the substrate 10. Specifically, the side surface 20b of the vertical conductive opening 20 is inclined obliquely. As shown in FIG. 1 , the cross-sectional shape of the vertical conductive opening 20 is an inverted trapezoid, more specifically, an inverted isosceles trapezoid.

[0052] The inclination angle of the side surface 20b with respect to the bottom surface 20a is, for example, 20° to 80°, but may be 30° to 45°. The smaller the inclination angle, the closer the side surface 20b is to the c-plane, thereby improving the film quality of the electron transit layer 22 and other layers formed along the side surface 20b by crystal regrowth. On the other hand, the larger the inclination angle, the more effectively the vertical conduction opening 20 is prevented from becoming too large, thereby realizing a more compact nitride semiconductor device 1. The side surface 20b may be perpendicular to the bottom surface 20a.

[0053] The electron transit layer 22 is an example of a first regrowth layer provided to cover the inner surface of the vertical conduction opening 20 and the upper part of the block layer 14. Specifically, a portion of the electron transit layer 22 is provided along the bottom surface 20a and side surface 20b of the vertical conduction opening 20, and another portion of the electron transit layer 22 is provided on the upper surface 14a of the block layer 14. The electron transit layer 22 is, for example, a film made of undoped GaN with a thickness of 150 nm. Note that although the electron transit layer 22 is assumed to be undoped, a portion of the electron transit layer 22 may be made n-type by, for example, doping with Si.

[0054] The electron transit layer 22 is in contact with the drift layer 12 at the bottom surface 20 a and the side surface 20 b of the vertical conduction opening 20. The electron transit layer 22 is in contact with the block layer 14 at the side surface 20 b of the vertical conduction opening 20. The electron transit layer 22 is in contact with the top surface 14 a of the block layer 14.

[0055] The electron transit layer 22 has a channel region. Specifically, a 2DEG 24, which serves as a channel, is generated near the interface between the electron transit layer 22 and the electron supply layer 23. The 2DEG 24 is bent along the interface between the electron transit layer 22 and the electron supply layer 23, i.e., along the inner surface of the vertical conduction opening 20.

[0056] 1, an AlN layer having a thickness of about 1 nm is provided as a second regrown layer between the electron transit layer 22 and the electron supply layer 23. This suppresses alloy scattering, improves channel mobility, and makes it possible to reduce on-resistance. However, the AlN layer is not necessarily required.

[0057] The electron supply layer 23 is an example of a third regrowth layer provided above the electron transit layer 22. Specifically, the electron supply layer 23 is provided so as to cover the inner surface of the vertical conduction opening 20 and the upper side of the block layer 14. Specifically, a portion of the electron supply layer 23 is provided along the upper surface of the electron transit layer 22 so as to overlap the bottom surface 20 a and side surface 20 b of the vertical conduction opening 20 and the upper surface 14 a of the block layer 14 in a plan view of the substrate 10. The electron supply layer 23 is, for example, a film made of undoped AlGaN. The electron supply layer 23 is formed to a shape that conforms to the upper surface of the electron transit layer 22 and to a substantially uniform thickness.

[0058] The electron supply layer 23 has a larger band gap than the electron transit layer 22. Therefore, an AlGaN / GaN heterointerface is formed between the electron supply layer 23 and the electron transit layer 22. The electron supply layer 23 supplies electrons to a channel region (2DEG 24) formed in the electron transit layer 22.

[0059] The electron transit layer 22 and the electron supply layer 23 are both layers included in the nitride semiconductor layer 21 provided in the nitride semiconductor device 1. The nitride semiconductor layer 21 is an example of a third nitride semiconductor layer provided above the block layer 14. Note that "provided above" means that at least a portion of the nitride semiconductor layer 21 is located above the block layer 14. In other words, at least a portion of the nitride semiconductor layer 21 is located above the block layer 14. In this embodiment, the nitride semiconductor layer 21 is provided so as to cover the inner surface of the vertical conduction opening 20 and the upper portion of the block layer 14.

[0060] The electron supply layer 23 has a recess 26. Specifically, the recess 26 is provided in a portion of the electron supply layer 23 that is located above the upper surface 14a of the block layer 14. The recess 26 will be described in detail later.

[0061] The threshold adjustment layer 28 is an example of a p-type fourth nitride semiconductor layer provided above the nitride semiconductor layer 21 at a position overlapping the vertical conduction opening 20 in a plan view of the substrate 10. Specifically, the threshold adjustment layer 28 is provided between the gate electrode 32 and the nitride semiconductor layer 21. More specifically, the threshold adjustment layer 28 is provided between the upper surface of the electron supply layer 23 and the lower surface of the gate electrode 32 in contact with each other.

[0062] In the present embodiment, the threshold adjustment layer 28 is provided at a position overlapping each of the vertical conductive opening 20 and the block layer 14 in a plan view of the substrate 10. Specifically, the threshold adjustment layer 28 overlaps the bottom surface 20a and side surface 20b of the vertical conductive opening 20 and the upper surface 14a of the block layer 14 in a plan view of the substrate 10. The threshold adjustment layer 28 is disposed at a distance from the source electrode 34 and is electrically isolated from it.

[0063] The threshold adjustment layer 28 has a thickness of 200 nm and a carrier concentration of 5×10 １７ cm －３ The thickness and carrier concentration of the threshold adjustment layer 28 are merely examples and can be changed as appropriate.

[0064] The provision of the threshold adjustment layer 28 raises the potential of the conduction band edge in the channel portion. This reduces the carrier concentration directly below the gate electrode 32, shifting the threshold voltage of the transistor to the positive side. This makes it easy to realize the nitride semiconductor device 1 as a normally-off FET. The threshold adjustment layer 28 may be a film made of p-type AlGaN.

[0065] The source opening 30 is an example of a second opening that penetrates the nitride semiconductor layer 21 and reaches the block layer 14 outside the vertical conduction opening 20 in a plan view of the substrate 10. The source opening 30 is provided at a position away from both the gate electrode 32 and the threshold adjustment layer 28 in a plan view of the substrate 10. Since the source opening 30 penetrates the nitride semiconductor layer 21, the 2DEG 24 is exposed on a side surface 30b of the source opening 30.

[0066] A bottom surface 30a of the source opening 30 is part of the upper surface 14a of the block layer 14. The bottom surface 30a is, for example, parallel to the main surface of the substrate 10. In the example shown in FIG. 1 , the bottom surface 30a is located below the lower surface of the electron transit layer 22. The lower surface of the electron transit layer 22 corresponds to the interface between the electron transit layer 22 and the block layer 14.

[0067] As shown in FIG. 1 , the source opening 30 is formed so that the opening area increases with increasing distance from the substrate 10. Specifically, the side surface 30 b of the source opening 30 is obliquely inclined. For example, the cross-sectional shape of the source opening 30 is an inverted trapezoid, more specifically, an inverted isosceles trapezoid. In this case, the inclination angle of the side surface 30 b relative to the bottom surface 30 a is, for example, in the range of 30° to 60°. The oblique inclination of the side surface 30 b increases the contact area between the source electrode 34 and the 2DEG 24, facilitating ohmic contact. The 2DEG 24 is exposed on the side surface 30 b of the source opening 30 and connected to the source electrode 34 at the exposed portion. The side surface 30 b may also be perpendicular to the bottom surface 30 a.

[0068] The provision of the source opening 30 can reduce the ohmic contact resistance between the 2DEG 24 functioning as a channel and the source electrode 34. That is, the on-resistance of the nitride semiconductor device 1 can be reduced.

[0069] Furthermore, the source electrode 34 and the block layer 14 are electrically connected at the bottom surface 30a of the source opening 30. As a result, the same potential as that applied to the source electrode 34 is supplied to the block layer 14. When a reverse voltage is applied to the pn junction formed by the block layer 14 and the drift layer 12, specifically when the drain electrode 36 has a higher potential than the source electrode 34, a depletion layer extends to the drift layer 12, thereby enabling the nitride semiconductor device 1 to have a high breakdown voltage. In this embodiment, the drain electrode 36 has a higher potential than the source electrode 34 in both the off and on states, except in the case of reverse conduction. As a result, the nitride semiconductor device 1 can have a high breakdown voltage.

[0070] The gate electrode 32 is electrically connected to the threshold adjustment layer 28. Specifically, the gate electrode 32 is provided on the upper surface of the threshold adjustment layer 28 and is in contact with the threshold adjustment layer 28. In the present embodiment, the gate electrode 32 is provided at a position overlapping each of the vertical conductive opening 20 and the block layer 14 in a plan view of the substrate 10. Specifically, the gate electrode 32 overlaps the bottom surface 20 a and the side surface 20 b of the vertical conductive opening 20 and the upper surface 14 a of the block layer 14 in a plan view of the substrate 10. The gate electrode 32 is disposed apart from the source electrode 34 and is electrically isolated from it.

[0071] The gate electrode 32 is formed using a conductive material such as a metal. For example, the gate electrode 32 may be formed using a material that forms an ohmic contact with a p-type nitride semiconductor such as p-type GaN, but is not limited thereto and may also be formed using a material that forms a Schottky contact with the p-type nitride semiconductor. For example, the gate electrode 32 may be formed using Pd, a Ni-based material, WSi, Au, or the like.

[0072] The source electrode 34 is provided above the substrate 10 and electrically connected to the nitride semiconductor layer 21. In this embodiment, the source electrode 34 is in contact with the electron transit layer 22 and the blocking layer 14 within the source opening 30. Specifically, the source electrode 34 is provided in contact with the bottom surface 30a and the side surface 30b of the source opening 30. The source electrode 34 is in direct contact with the 2DEG 24 on the side surface 30b of the source opening 30. This reduces the contact resistance between the source electrode 34 and the 2DEG 24, thereby reducing the on-resistance of the nitride semiconductor device 1.

[0073] The source electrode 34 is formed using a conductive material such as a metal. Examples of the material for the source electrode 34 include Ti / Al (a laminated structure of a Ti layer and an Al layer), which can be ohmically connected to an n-type nitride semiconductor such as n-type GaN by heat treatment.

[0074] The drain electrode 36 is provided below the substrate 10. Specifically, the drain electrode 36 is provided in contact with the lower surface of the substrate 10.

[0075] The drain electrode 36 is formed using a conductive material such as a metal. As with the material of the source electrode 34, the material of the drain electrode 36 may be, for example, Ti / Al, which is a material that forms an ohmic contact with an n-type nitride semiconductor such as n-type GaN.

[0076] The insulating layer 40 is provided above the gate electrode 32. Specifically, the insulating layer 40 is provided so as to cover the gate electrode 32, the threshold adjustment layer 28, the electron supply layer 23, and the source electrode 34. The insulating layer 40 has a laminated structure of a plurality of insulating films. The plurality of insulating films may be made of, for example, SiN, SiO ２ , SiON, Al ２ O ３ The insulating layer 40 may have a single layer structure of one insulating film.

[0077] The source wiring 50 is provided above the insulating layer 40 and is connected to the source electrode 34 through an opening provided in the insulating layer 40. The source wiring 50 is formed using a conductive material such as a metal. For example, the source wiring 50 is a plated film made of Au.

[0078] 1, the recess portion 26, the source opening 30, and the source electrode 34 are provided on both sides of the vertical conductive opening 20 in the lateral direction, but this is not limiting. The recess portion 26, the source opening 30, and the source electrode 34 may be provided on only one side of the vertical conductive opening 20.

[0079] [Characteristic Configuration] Next, the main characteristic configuration of the nitride semiconductor device 1 according to this embodiment will be described. Specifically, the recess portion 26 and the structure in its vicinity will be described with reference to Fig. 2. Fig. 2 is an enlarged cross-sectional view of a main portion of the nitride semiconductor device 1 according to this embodiment.

[0080] 2 shows two areas A1 and A2. Area A1 is the area where the block layer 14 and the threshold adjustment layer 28 overlap in a planar view of the substrate 10. Area A2 is the area where the upper surface 14a of the block layer 14 and the threshold adjustment layer 28 overlap in a planar view of the substrate 10.

[0081] In the present embodiment, the recessed portion 26 is provided in range A2. That is, the recessed portion 26 is provided at a position overlapping the upper surface 14a of the block layer 14 in a plan view of the substrate 10. The recessed portion 26 may also be provided in range A1. That is, the recessed portion 26 may be provided at a position overlapping the block layer 14 in a plan view of the substrate 10. In a plan view of the substrate 10, the entire recessed portion 26 may be provided in a range overlapping the end face of the block layer 14, or only a portion of the recessed portion 26 may be provided in a range overlapping the end face of the block layer 14. The range overlapping the end face of the block layer 14 is the range A1 in FIG. 2 excluding range A2.

[0082] In the nitride semiconductor device 1, the threshold adjustment layer 28 is provided so as to cover the inner surface of the recessed portion 26. Specifically, the threshold adjustment layer 28 is provided so as to cover each of the bottom surface and side surface of the recessed portion 26 and fill the inside of the recessed portion 26. Note that although an example in which the upper surface of the threshold adjustment layer 28 is flat within the range A1 or A2 is shown in FIGS. 1 and 2 , a recess corresponding to the recessed portion 26 may be provided in the upper surface of the threshold adjustment layer 28. Furthermore, the side surface of the recessed portion 26 is perpendicular to the recessed portion 26, but may also be inclined obliquely.

[0083] Furthermore, the gate electrode 32 is provided at a position overlapping each of the vertical conductive opening 20 and the recessed portion 26 in a plan view of the substrate 10. That is, a part of the gate electrode 32 is provided at a position overlapping the vertical conductive opening 20, and another part of the gate electrode 32 is provided within the range A1 or A2.

[0084] The recessed portion 26 is provided in the electron supply layer 23, so that the film thickness of the electron supply layer 23 varies depending on the portion. Specifically, as shown in FIG. 2 , the electron supply layer 23 includes an upper surface portion 23a including a thick portion 23aa and a thin portion 23ab, and a side surface portion 23b. The upper surface portion 23a is a portion of the electron supply layer 23 that is provided at a position overlapping the upper surface 14a of the block layer 14 in a plan view of the substrate 10. The side surface portion 23b is a portion of the electron supply layer 23 that is provided along the side surface 20b of the vertical conductive opening 20.

[0085] The thick film portion 23aa is a part of the upper surface portion 23a where the recess portion 26 is not provided. The thin film portion 23ab is a part of the upper surface portion 23a where the recess portion 26 is provided. In other words, the thin film portion 23ab is a part of the electron supply layer 23 that overlaps the bottom surface of the recess portion 26 in a plan view of the substrate 10.

[0086] In this embodiment, when the thickness of the thick film portion 23aa is d1, the thickness of the thin film portion 23ab is d2, and the thickness of the side surface portion 23b is d3, the relationship d2<d1<d3 is satisfied. Note that, as shown in FIG. 2 , d1 and d2 are expressed as lengths in a direction perpendicular to the top surface 14a of the block layer 14. d3 is expressed as a length in a direction perpendicular to the side surface 20b of the vertical conductive opening 20.

[0087] The thickness of the electron supply layer 23 affects the concentration of 2DEG 24 generated by piezoelectric polarization. Specifically, the thinner the electron supply layer 23, the lower the concentration of 2DEG 24. Therefore, since d2 is the smallest among d1, d2, and d3, the concentration of 2DEG 24 directly below the thin film portion 23ab is lowest. As a result, when 2DEG 24 disappears directly below the thin film portion 23ab, the FET is turned off. However, when 2DEG 24 is generated directly below the thin film portion 23ab, 2DEG 24 is also generated directly below the thick film portion 23aa and along the side surface portion 23b, so the FET is turned on. In other words, the threshold voltage of the FET is determined based on the thickness of the thin film portion 23ab and is hardly affected by the thicknesses of the thick film portion 23aa and the side surface portion 23b.

[0088] Therefore, by increasing the thickness of the thick film portion 23aa and the side surface portion 23b, the concentration of the 2DEG 24 can be increased, thereby reducing the on-resistance. Even if the thickness of the thick film portion 23aa and the side surface portion 23b is increased, the threshold voltage of the FET is not substantially affected. On the other hand, by adjusting the thickness of the thin film portion 23ab, a desired threshold voltage can be achieved. As described above, according to this embodiment, it is possible to achieve both a reduction in on-resistance and an improvement in the degree of freedom in setting the threshold voltage.

[0089] The concentration of the 2DEG 24 generated by piezoelectric polarization is affected not only by the thickness but also by the composition of the electron supply layer 23. Therefore, the threshold voltage of the FET can be adjusted by the thickness and composition of the thin film portion 23ab. For example, if the thin film portion 23ab is made of AlGaN, increasing the Al composition ratio enhances the polarization effect and increases the concentration of the 2DEG 24, thereby lowering the threshold voltage. On the other hand, decreasing the Al composition ratio reduces the polarization effect and decreases the concentration of the 2DEG 24, thereby increasing the threshold voltage.

[0090] In this embodiment, the Al composition ratio of the electron supply layer 23 is uniform regardless of the region. That is, the Al composition ratios of the thick film portion 23aa, the thin film portion 23ab, and the side surface portion 23b are the same, and may be, for example, 10% to 50%, or may be 15% to 25%.

[0091] By increasing the thickness of the thick film portion 23aa, the on-resistance can be reduced. However, on the other hand, there is a risk that misfit dislocations or cracks may occur due to the relaxation of stress caused by lattice mismatch. If misfit dislocations or cracks occur, the stress caused by strain is relaxed, reducing piezoelectric polarization, or the cracks may become a path for leakage current. For this reason, the thickness d1 of the thick film portion 23aa is required to be equal to or less than the upper limit at which misfit dislocations or cracks do not occur.

[0092] The upper limit depends on the composition of the thick film portion 23aa, i.e., the composition of the electron supply layer 23. For example, when the Al composition ratio is 20%, the upper limit of the thickness of the thick film portion 23aa is 70 nm. This makes it possible to suppress the occurrence of misfit dislocations and cracks. Note that the upper limit of the thickness of the thick film portion 23aa tends to decrease as the Al composition ratio increases. For example, when the Al composition ratio is 25%, the upper limit of the thickness of the thick film portion 23aa is 45 nm, and when the Al composition ratio is 30%, the upper limit of the thickness of the thick film portion 23aa is 22 nm.

[0093] The thickness d2 of the thin film portion 23ab is, for example, half or less of the thickness d1 of the thick film portion 23aa, but may be one-third or less. The lower limit of the thickness d2 of the thin film portion 23ab is, for example, 10 nm, but may also be 6 nm. The thickness d2 of the thin film portion 23ab can be, for example, 20 nm. This allows the threshold voltage of the FET to be greater than 0 V, thereby realizing a normally-off FET.

[0094] [Manufacturing Method] Next, a method for manufacturing the nitride semiconductor device 1 according to this embodiment will be described with reference to Figures 3A to 3G. Figures 3A to 3G are cross-sectional views for explaining a step in the method for manufacturing the nitride semiconductor device 1 according to this embodiment. The cross-sectional configuration of the device during manufacturing changes in the order of Figures 3A to 3G.

[0095] First, as shown in FIG. 3A , a drift layer 12 and a block layer 14 are formed in this order by crystal growth above a substrate 10. Specifically, a nitride semiconductor is crystal-grown on the main surface of the substrate 10 by epitaxial growth, such as MOCVD (Metal Oxide Chemical Vapor Deposition) or HVPE (Hydride Vapor Phase Epitaxy). By adjusting growth conditions, such as raw materials, growth temperature, and growth time, the composition, film thickness, impurity concentration, and the like, can be adjusted to values ​​appropriate for each layer. For example, n-type GaN is crystal-grown as the drift layer 12, and then p-type GaN is crystal-grown as the block layer 14. Si, for example, is used as the n-type impurity, and Mg, for example, is used as the p-type impurity. For example, the drift layer 12 and the block layer 14 are formed consecutively in the same growth furnace without being exposed to the atmosphere during the process. Although the block layer 14 is formed by crystal growth, it may also be formed by, for example, implanting Mg into a deposited i-GaN film.

[0096] Next, as shown in FIG. 3B , a vertical conductive opening 20 is formed through the block layer 14. For example, a photosensitive photoresist is applied to the upper surface 14a of the block layer 14 and patterned into a predetermined shape by photolithography. The patterned photosensitive photoresist (i.e., a resist mask) has an opening at a position corresponding to the vertical conductive opening 20, exposing the upper surface 14a of the block layer 14. At this time, the side surface of the resist mask opening can be sloped by adjusting baking conditions such as the baking temperature of the resist mask. Then, the vertical conductive opening 20 is formed by removing a portion of the block layer 14 and the drift layer 12 in an area not covered by the resist mask by dry etching or the like. The side surface 20b of the vertical conductive opening 20 is inclined according to the slope of the side surface of the resist mask opening. After the vertical conductive opening 20 is formed, the resist mask is peeled off.

[0097] 3C , an electron transit layer 22 and an electron supply layer 23 are formed in this order by crystal growth (second crystal growth) so as to cover the vertical conduction opening 20 and the block layer 14. For example, undoped GaN is epitaxially grown as the electron transit layer 22 so as to entirely cover the bottom surface 20 a and side surface 20 b of the vertical conduction opening 20 and the upper surface 14 a of the block layer 14, and then undoped AlGaN is successively grown as the electron supply layer 23. After the formation of undoped GaN, undoped AlGaN may be formed before the formation of undoped AlGaN.

[0098] 3D , a recess 26 is formed on the upper surface of the electron supply layer 23. Specifically, similar to the formation of the vertical conductive opening 20, the recess 26 is formed by forming a resist mask by photolithography and then performing dry etching. In this embodiment, the recess 26 is formed at a position overlapping the upper surface 14a of the block layer 14 in a plan view of the substrate 10. As a result, a thick film portion 23aa and a thin film portion 23ab are formed on the upper surface 23a of the electron supply layer 23.

[0099] 3E , the threshold adjustment layer 28 is formed by crystal growth (third crystal growth) so as to cover the recessed portion 26. For example, p-type GaN is grown as the threshold adjustment layer 28 by epitaxial growth so as to cover the entire upper surface of the electron supply layer 23 including the inner surface of the recessed portion 26.

[0100] Next, as shown in FIG. 3F , a portion of the crystal-grown threshold adjustment layer 28 is removed to pattern the threshold adjustment layer 28 into a predetermined shape. Furthermore, a source opening 30 that penetrates the nitride semiconductor layer 21 is formed. The removal of the portion of the threshold adjustment layer 28 and the formation of the source opening 30 are performed in two steps by forming a resist mask by photolithography and then dry etching. The source opening 30 is formed after patterning the threshold adjustment layer 28, but this is not limiting. For example, after the source opening 30 is formed, a portion of the threshold adjustment layer 28 in the range from the opening edge of the source opening 30 to the opening edge of the vertical conduction opening 20 may be removed.

[0101] 3G, the gate electrode 32 and the source electrode 34 are formed. For example, a metal film is formed by sputtering or EB (Electron Beam) deposition using a metal material that can be ohmic-contacted to an n-type nitride semiconductor, and then the source electrode 34 is formed in a predetermined shape by etching or lift-off. Next, a metal film is formed by sputtering or EB deposition using a metal material that can be ohmic-contacted to a p-type nitride semiconductor, and then the gate electrode 32 is formed in a predetermined shape by etching or lift-off.

[0102] Next, the nitride semiconductor device 1 shown in FIG. 1 is manufactured by forming an insulating layer 40, a source wiring 50, and a drain electrode 36. For example, first, the insulating layer 40 is formed by plasma CVD, atomic layer deposition (ALD), or the like so as to cover the gate electrode 32, the source electrode 34, and the like. Then, an opening exposing at least a portion of the source electrode 34 is formed in the insulating layer 40 by dry etching or the like. Next, the source wiring 50 is formed by plating or the like so as to contact the source electrode 34 within the formed opening. Also, although not shown, a gate wiring, a source pad, a gate pad, and the like connected to the gate electrode 32 are also formed. Finally, the drain electrode 36 is formed on the lower surface of the substrate 10 by sputtering, EB evaporation, or the like.

[0103] Through the above steps, the nitride semiconductor device 1 shown in Fig. 1 is manufactured. Note that the above-described manufacturing method is merely an example, and the order of steps and specific processing can be changed as appropriate.

[0104] [Modification] Next, a modification of the embodiment will be described with reference to Figures 4, 5A, 5B, and 5C. Figure 4 is a cross-sectional view of a nitride semiconductor device 2 according to this modification. Figures 5A, 5B, and 5C are cross-sectional views for explaining a step in a manufacturing method of the nitride semiconductor device 2 according to this modification. The following description will focus on differences from the embodiment, and description of commonalities will be omitted or simplified.

[0105] 4 differs from the nitride semiconductor device 1 in that a recess 126 is provided in the electron transit layer 22. The recess 126 is provided at a position overlapping the recess 26 in a plan view of the substrate 10. The electron supply layer 23 is provided along the inner surface of the recess 126, and the recess 26 is provided on the upper surface of the electron supply layer 23 at a position overlapping the recess 126 in a plan view.

[0106] The nitride semiconductor device 2 according to this modification is manufactured by partially modifying the manufacturing method of the nitride semiconductor device 1. For example, as shown in FIGS. 3A and 3B , after forming the drift layer 12 and the block layer 14 above the substrate 10, the vertical conduction opening 20 is formed. Next, as shown in FIG. 5A , the electron transit layer 22 and the electron supply layer 23A are formed so as to cover the vertical conduction opening 20. The formation of the electron transit layer 22 and the electron supply layer 23A is the same as the process described using FIG. 3C . For example, the electron supply layer 23A is formed to a thickness thinner than the electron supply layer 23 shown in FIG. 3C .

[0107] 5B , a recess 126 is formed so as to penetrate the electron supply layer 23A and remove at least a portion of the electron transit layer 22. Specifically, similar to the formation of the vertical conduction opening 20, the recess 126 is formed by forming a resist mask by photolithography and then performing dry etching.

[0108] Next, as shown in Fig. 5C, a nitride semiconductor film (specifically, a p-type AlGaN film) constituting the electron supply layer 23 and the threshold adjustment layer 28 are formed by crystal growth (third crystal growth) so as to cover the recessed portion 126. That is, in this modification, the electron supply layer 23 is formed in two stages. The subsequent steps are the same as those described with reference to Figs. 3F and 3G. In this way, the nitride semiconductor device 2 according to this modification can be manufactured.

[0109] In this way, the thickness of the electron supply layer 23 provided so as to overlap the recessed portion 126 can be adjusted by crystal growth. This makes it easier to adjust the thickness than when adjusting by etching, and thus makes it easier to adjust the threshold value.

[0110] While nitride semiconductor devices according to one or more aspects have been described above based on embodiments, the present disclosure is not limited to these embodiments. As long as they do not deviate from the gist of the present disclosure, various modifications conceivable by those skilled in the art to the present embodiments and configurations constructed by combining components of different embodiments are also included within the scope of the present disclosure.

[0111] For example, in the nitride semiconductor devices 1 and 2, a first high-resistance layer having a higher resistance than the block layer 14 may be provided between the drift layer 12 and the block layer 14. The first high-resistance layer is, for example, a 100 nm thick film made of carbon-doped GaN (C—GaN). The carbon concentration of the first high-resistance layer is, for example, 3×10 １７ cm －３ That's all, but 1 x 10 １８ cm －３ The first high-resistance layer is provided in contact with each of the drift layer 12 and the block layer 14. The first high-resistance layer may contain n-type impurities such as Si. The concentration of the n-type impurities contained in the first high-resistance layer is lower than the carbon concentration and oxygen concentration of the first high-resistance layer, and may be, for example, 5×10 １６ cm －３ or less than or equal to 2×10 １６ cm －３ or less. Providing the first high-resistance layer can suppress punch-through and increase the breakdown voltage of the nitride semiconductor devices 1 and 2. When the first high-resistance layer is formed, the vertical conduction opening 20 penetrates the first high-resistance layer. This prevents the first high-resistance layer from being located on the path of the drain current when the FET is on, thereby suppressing an increase in on-resistance.

[0112] Furthermore, for example, in the nitride semiconductor devices 1 and 2, a second high-resistance layer having a higher resistance than the block layer 14 may be provided between the block layer 14 and the electron transit layer 22. For example, the second high-resistance layer is an undoped GaN film with a thickness of 200 nm, but it may also be a carbon-doped GaN film. The second high-resistance layer is formed by crystal growth continuously from the formation of the block layer 14. When the second high-resistance layer is formed, the vertical conduction opening 20 penetrates the second high-resistance layer. By providing the second high-resistance layer, an npn parasitic transistor is not formed by the 2DEG 24, the p-type block layer 14, and the n-type drift layer 12, and malfunction of the nitride semiconductor devices 1 and 2 can be suppressed.

[0113] The source opening 30 may not be provided. In this case, the source electrode 34 is provided on the upper surface of the electron supply layer 23.

[0114] Furthermore, for example, the distance between the bottom surface 20a of the vertical conductive opening 20 and the substrate 10 may be shorter than the distance between the block layer 14 and the substrate 10. This allows the electric field between the drain and the source to be dispersed also to the lower surface of the threshold adjustment layer 28. This makes it possible to suppress the electric field concentration at the lower end of the block layer 14, thereby increasing the breakdown voltage of the FET.

[0115] Furthermore, for example, the gate electrode 32 and the recess portion 26 may not overlap in a plan view of the substrate 10. For example, the gate electrode 32 may overlap only the bottom surface 20 a of the vertical conductive opening 20, or only the bottom surface 20 a and the side surface 20 b, and may not overlap the top surface of the block layer 14.

[0116] Furthermore, for example, the drift layer 12 may have a graded structure in which the impurity concentration (donor concentration) gradually decreases from the substrate 10 side to the block layer 14 side. The donor concentration may be controlled by Si, which acts as a donor, or by carbon, which acts as an acceptor that compensates for Si. Alternatively, the drift layer 12 may have a stacked structure of multiple nitride semiconductor layers with different impurity concentrations. Specifically, the drift layer may be two-layered, with a layer with a low donor concentration disposed below the block layer and a layer with a high donor concentration disposed on the substrate side. By providing a vertical conductive opening 20 that penetrates the layer with a low donor concentration, current flows through the layer with a high donor concentration through the vertical conductive opening 20 when the transistor is on, thereby reducing the on-resistance. Conversely, when the transistor is off, a high electric field is maintained by the layer with a low donor concentration, thereby achieving both low on-resistance and high breakdown voltage.

[0117] Furthermore, various modifications, substitutions, additions, omissions, etc. can be made to the above-described embodiments within the scope of the claims or their equivalents.

[0118] The nitride semiconductor device according to the present disclosure is useful as a power device used in, for example, power supply circuits of electrical equipment, inverter circuits, etc.

[0119] REFERENCE SIGNS LIST 1, 2 Nitride semiconductor device 10 Substrate 12 Drift layer 14 Block layer 14a Top surface 20 Vertical conduction opening 20a, 30a Bottom surface 20b, 30b Side surface 21 Nitride semiconductor layer 22 Electron transit layer 23, 23A Electron supply layer 23a Top surface portion 23aa Thick film portion 23ab Thin film portion 23b Side surface portion 24 2DEG 26, 126 Recess portion 28 Threshold adjustment layer 30 Source opening 32 Gate electrode 34 Source electrode 36 Drain electrode 40 Insulating layer 50 Source wiring

Claims

a first n-type nitride semiconductor layer provided above the substrate; a second p-type nitride semiconductor layer provided above the first nitride semiconductor layer; a third nitride semiconductor layer provided so as to cover an inner surface of a first opening which penetrates the second nitride semiconductor layer to reach the first nitride semiconductor layer and an upper portion of the second nitride semiconductor layer; a fourth p-type nitride semiconductor layer provided above the third nitride semiconductor layer at a position which overlaps the first opening in a plan view of the substrate; a gate electrode electrically connected to the fourth nitride semiconductor layer; a source electrode provided above the substrate and electrically connected to the third nitride semiconductor layer; and a drain electrode provided below the substrate, wherein the third nitride semiconductor layer includes an electron transit layer and an electron supply layer provided above the electron transit layer and having a band gap larger than that of the electron transit layer, and the fourth nitride semiconductor layer covers an inner surface of a recess provided in a portion of the electron supply layer which is located above an upper surface of the second nitride semiconductor layer. Nitride semiconductor devices.

2. The nitride semiconductor device according to claim 1, wherein the electron supply layer includes a side portion provided along a side surface of the first opening, and an upper surface portion provided at a position overlapping an upper surface of the second nitride semiconductor layer in a plan view of the substrate, and wherein, when the thickness of a portion of the upper surface portion where the recess portion is not provided is d1, the thickness of a portion of the electron supply layer where the recess portion is provided is d2, and the thickness of the side portion is d3, the relationship d2<d1<d3 is satisfied.

3. The nitride semiconductor device according to claim 1 or 2, wherein the recessed portion is provided at a position overlapping the second nitride semiconductor layer in a plan view of the substrate.

4. The nitride semiconductor device according to claim 3, wherein the recessed portion is provided at a position overlapping an upper surface of the second nitride semiconductor layer in a plan view of the substrate.

5. The nitride semiconductor device according to claim 1 or 2, wherein the gate electrode is provided at a position overlapping each of the first opening and the recessed portion in a plan view of the substrate.

6. The nitride semiconductor device according to claim 1 or 2, wherein the source electrode is in contact with the electron transit layer and the second nitride semiconductor layer within a second opening that penetrates the third nitride semiconductor layer outside the first opening in a plan view of the substrate and reaches the second nitride semiconductor layer.

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