Three-dimensional memory device and manufacturing method therefor

Abstract

A three-dimensional memory device and a manufacturing method therefor are disclosed. According to the present invention, a method in which local annealing (heat treatment) can be performed on a desired area in a short time and uniformity of annealing properties can be ensured depending on the position, for example, the position in the vertical direction is provided such that a three-dimensional memory device having a high density and excellent performance and uniformity can be implemented and manufactured. In addition, according to embodiments of the present invention, a predetermined semiconductor layer is made into crystalline close to polycrystalline or monocrystalline through laser annealing of the provided method, and thus a three-dimensional memory device capable of ensuring excellent electrical characteristics such as low leakage current and high carrier mobility can be implemented.

Description

3D memory device and manufacturing method thereof

[0001] The present invention relates to semiconductor / electronic devices and methods for manufacturing the same, and more particularly, to memory devices and methods for manufacturing the same.

[0002] There is a continuous demand for increasing the performance and integration of semiconductor devices. The two-dimensional arrangement of semiconductor unit cells, i.e., planar arrangement, has reached its limit in increasing the integration of semiconductor devices. Therefore, attempts are being made to develop technologies that significantly increase the integration of semiconductor devices by integrating semiconductor unit cells three-dimensionally. In this regard, various attempts are being made to increase the integration of memory devices, such as NAND devices and DRAM devices. Furthermore, research and development is continuously being conducted to improve the performance and operating characteristics of memory devices.

[0003] In the fabrication of channels for three-dimensional memory devices, such as multi-stacked memory devices, polycrystalline semiconductor materials are preferred over single-crystalline semiconductor materials due to their ease of processing. Since electrical characteristics of polycrystalline semiconductor materials, such as leakage current and carrier mobility, are affected by grain boundaries and grain size, it may be desirable for the material to have as few grain boundaries as possible and large grain sizes. Here, the semiconductor material may include, for example, Si or SiGe.

[0004] Typically, grain growth in semiconductor materials is achieved using a furnace. Furnace-based methods require considerable processing time, requiring time to achieve the appropriate temperature conditions for grain growth, time for grain growth to occur, and cooling time after the process.

[0005] Laser annealing (heat treatment) is a method to improve this. Using lasers for heat treatment can produce semiconductor layers with high crystallinity by locally applying high energy in a short period of time. However, due to the nature of the 3D memory device manufacturing process, a temperature difference occurs between the upper layer directly affected by the laser and the lower layer, preventing uniform / consistent device characteristics across the entire memory device. Therefore, conventional methods can be difficult to use to manufacture 3D memory devices with superior performance and uniformity.

[0006] The technical problem to be achieved by the present invention is to provide a method for manufacturing a three-dimensional memory device having high integration and excellent performance and uniformity by proposing a method for performing local annealing in a desired area in a short period of time and ensuring uniformity of annealing characteristics according to location, and to provide a three-dimensional memory device manufactured by the method.

[0007] In addition, the technical problem to be achieved by the present invention is to provide a method for manufacturing a three-dimensional memory device capable of securing excellent electrical characteristics such as low leakage current and high carrier mobility by making a predetermined semiconductor layer into a crystal quality close to a polycrystal or single crystal through a given method of laser annealing, and a three-dimensional memory device manufactured by the method.

[0008] In addition, the technical task to be achieved by the present invention is to provide a three-dimensional memory device that can increase the degree of integration, secure excellent performance and uniformity, and also secure ease of process.

[0009] The problems to be solved by the present invention are not limited to the problems mentioned above, and other problems not mentioned can be understood by those skilled in the art from the description below.

[0010] According to one embodiment of the present invention, a method for manufacturing a three-dimensional memory device is provided, including the steps of: forming a laminate having a structure in which semiconductor layers and insulating layers are alternately and repeatedly laminated on a substrate; forming a vertical hole in the laminate; forming a heat-conducting layer covering the vertical hole on the laminate; irradiating a laser to the heat-conducting layer to perform annealing on a portion of the semiconductor layer around the vertical hole to form a channel layer from the portion of the semiconductor layer; removing the heat-conducting layer; defining a gate insulating layer covering an inner surface of the vertical hole; forming a word line on the gate insulating layer that at least partially fills the vertical hole; removing the semiconductor layer from one side of the channel layer to expose a first side region of the channel layer and forming a bit line electrically connected to the first side region of the channel layer; and removing the semiconductor layer from the other side of the channel layer to expose a second side region of the channel layer and forming a capacitor electrically connected to the second side region of the channel layer.

[0011] The above thermally conductive layer may include doped polycrystalline silicon.

[0012] A metallic material layer may be further formed on the laminate, the vertical hole may be formed in the laminate by penetrating the metallic material layer, and the thermally conductive layer covering the vertical hole may be formed on the metallic material layer.

[0013] After the step of forming a vertical hole in the laminate, a step of forming a diffusion barrier layer covering the vertical hole on the laminate may be further included, and the thermally conductive layer may be formed on the diffusion barrier layer.

[0014] The above thermally conductive layer may include a metallic material.

[0015] After the step of forming the word line, the method may further include the step of etching a portion of the laminate to form an etched portion exposing both sides of the channel layer; and the step of filling the etched portion with an insulating material.

[0016] The step of forming the bit line may include the steps of: etching a portion of the laminate to form a first trench; removing a portion of the semiconductor layer exposed by the first trench to form a first recess portion exposing the first side region of the channel layer; and forming the bit line within the first recess portion.

[0017] The step of forming the capacitor may include: etching a portion of the laminate to form a second trench; removing a portion of the semiconductor layer exposed by the second trench to form a second recess portion exposing the second side region of the channel layer; forming a first electrode for a capacitor within the second recess portion; removing an insulating material around the first electrode to expose a surface of the first electrode; forming a dielectric layer for a capacitor on the exposed surface of the first electrode; and forming a second electrode for a capacitor on the dielectric layer for a capacitor.

[0018] According to another embodiment of the present invention, a method for manufacturing a three-dimensional memory device is provided, comprising: forming a laminate having a structure in which a sacrificial layer and an insulating layer are alternately and repeatedly laminated on a substrate; forming a vertical hole in the laminate; recessing a portion of the sacrificial layer around the vertical hole to form a recessed region; forming a channel material layer filling at least the recessed region; performing direct or indirect laser annealing on the channel material layer and defining a channel layer disposed in the recessed region from the channel material layer; defining a gate insulating layer covering an inner surface of the vertical hole; forming a word line on the gate insulating layer, at least partially filling the vertical hole; removing the sacrificial layer from one side of the channel layer to expose a first side region of the channel layer and forming a bit line electrically connected to the first side region of the channel layer; and removing the sacrificial layer from the other side of the channel layer to expose a second side region of the channel layer and forming a capacitor electrically connected to the second side region of the channel layer.

[0019] The channel material layer can be formed to cover the vertical hole while filling the recessed region on the laminate, and after the laser annealing, the remaining portion of the channel material layer except for the portion disposed within the recessed region can be removed.

[0020] A metallic material layer may be further formed on the laminate, the vertical hole may be formed in the laminate by penetrating the metallic material layer, the channel material layer may be formed on the metallic material layer to cover the vertical hole while filling the recessed area, and after the laser annealing, the remaining portion of the channel material layer except for the portion disposed within the recessed area may be removed.

[0021] The channel material layer may be formed to fill the recessed region, and the step of forming a diffusion barrier layer covering the vertical hole on the laminate may further include the step of forming a thermally conductive layer on the diffusion barrier layer.

[0022] The above thermally conductive layer may include a metallic material.

[0023] After the step of forming the word line, the method may further include the step of etching a portion of the laminate to form an etched portion exposing both sides of the channel layer; and the step of filling the etched portion with an insulating material.

[0024] The step of forming the bit line may include: etching a portion of the laminate to form a first trench; removing a portion of the sacrificial layer exposed by the first trench to form a first recess portion exposing the first side region of the channel layer; and forming the bit line within the first recess portion.

[0025] The step of forming the capacitor may include: etching a portion of the laminate to form a second trench; removing a portion of the sacrificial layer exposed by the second trench to form a second recess portion exposing the second side region of the channel layer; forming a first electrode for a capacitor within the second recess portion; removing an insulating material around the first electrode to expose a surface of the first electrode; forming a dielectric layer for a capacitor on the exposed surface of the first electrode; and forming a second electrode for a capacitor on the dielectric layer for a capacitor.

[0026] According to another embodiment of the present invention, a three-dimensional memory device is provided, including: a word line extending in a vertical direction; a plurality of channel layers having a shape surrounding the word line and spaced apart from each other in the vertical direction; a plurality of bit lines electrically connected to first side regions of the plurality of channel layers and extending in a horizontal direction; a plurality of capacitors electrically connected to second side regions of the plurality of channel layers and arranged vertically adjacent to each other; and an insulating layer arranged between the plurality of channel layers.

[0027] The capacitor may include a first electrode electrically contacting the second side region of the channel layer and having a shape protruding from the second side region; a dielectric layer arranged to cover the upper surface, lower surface, front surface, rear surface, and side surface of the first electrode; and a second electrode arranged on the dielectric layer.

[0028] The word line may be arranged within a vertical hole of the stack, and a gate insulating layer may be arranged between the inner surface of the vertical hole and the word line.

[0029] The word line, the plurality of channel layers, the plurality of bit lines, and the plurality of capacitors may form a first memory stack, and a second memory stack may be provided that is horizontally spaced from the first memory stack, and the first memory stack and the second memory stack may form a structure that is symmetrical with respect to a separator provided therebetween.

[0030] The channel layer of the first memory stack may be disposed between the separator and the capacitor of the first memory stack, and the bit line of the first memory stack may be disposed between the separator and the channel layer of the first memory stack.

[0031] According to embodiments of the present invention, a method is provided to perform local annealing (heat treatment) in a desired area in a short period of time and to ensure uniformity of annealing characteristics according to location, for example, vertical location, thereby enabling implementation and manufacture of a three-dimensional memory device having high integration and excellent performance and uniformity. In addition, according to embodiments of the present invention, a three-dimensional memory device having excellent electrical characteristics, such as low leakage current and high carrier mobility, can be implemented by making a predetermined semiconductor layer into a crystal quality close to a polycrystalline or single crystal through a given method of laser annealing. In addition, according to embodiments of the present invention, a three-dimensional memory device having high integration, excellent performance and uniformity, and ease of process can be implemented. The three-dimensional memory device may be a DRAM device.

[0032] In one embodiment, when manufacturing a three-dimensional memory device, it may be possible to crystallize semiconductor materials in channel regions to a similar level in a short period of time, regardless of their position in the vertical direction (i.e., depth direction), by utilizing a laser.

[0033] According to one embodiment, a heat-conducting layer having high thermal conductivity can be used in laser annealing, and the heat-conducting layer can serve to transfer heat induced by the laser in the extension direction of a vertical hole, for example, a gate hole, so that similar annealing characteristics can be secured for a plurality of semiconductor regions in the vertical direction. A semiconductor material for forming a channel of a 3D memory device can be positioned perpendicular to the vertical hole (gate hole) in a region adjacent to the vertical hole, and a high level of crystallization of the semiconductor material can be possible. Accordingly, it may be possible to minimize the number of grain boundaries in the channel layer and maximize the size of the grains. Therefore, the effect of high-energy laser annealing can be secured regardless of the position in the depth direction in the 3D memory device, and as a result, the electrical characteristics of the 3D memory device can be improved by minimizing the number of grain boundaries and maximizing the size of the grains.

[0034] However, the effects of the present invention are not limited to the above effects, and can be expanded in various ways without departing from the technical spirit and scope of the present invention.

[0035] FIGS. 1 to 3 are cross-sectional views illustrating a channel formation method that can be applied to a method for manufacturing a three-dimensional memory device according to one embodiment of the present invention.

[0036] FIGS. 4 to 6 are cross-sectional views illustrating a channel formation method that can be applied to a method for manufacturing a three-dimensional memory device according to another embodiment of the present invention.

[0037] FIGS. 7 to 9 are cross-sectional views illustrating a channel formation method that can be applied to a method for manufacturing a three-dimensional memory device according to another embodiment of the present invention.

[0038] FIGS. 10 to 12 are cross-sectional views illustrating a method for manufacturing a three-dimensional memory device according to one embodiment of the present invention.

[0039] FIGS. 13A to 16B are drawings for explaining a channel formation method that can be applied to a method for manufacturing a three-dimensional memory device according to one embodiment of the present invention.

[0040] FIGS. 17A to 20B are drawings for explaining a channel formation method that can be applied to a method for manufacturing a three-dimensional memory device according to another embodiment of the present invention.

[0041] FIGS. 21A to 24B are drawings for explaining a channel formation method that can be applied to a method for manufacturing a three-dimensional memory device according to another embodiment of the present invention.

[0042] FIGS. 25a to 39b are cross-sectional views illustrating a method for manufacturing a three-dimensional memory device according to another embodiment of the present invention.

[0043] FIG. 39a and FIG. 39b are drawings for explaining a three-dimensional memory device according to one embodiment of the present invention.

[0044] FIGS. 40 to 44 are cross-sectional views illustrating a channel formation method that can be applied to a method for manufacturing a three-dimensional memory device according to another embodiment of the present invention.

[0045] FIGS. 45 to 49 are cross-sectional views illustrating a channel formation method that can be applied to a method for manufacturing a three-dimensional memory device according to another embodiment of the present invention.

[0046] FIGS. 50 to 54 are cross-sectional views illustrating a channel formation method that can be applied to a method for manufacturing a three-dimensional memory device according to another embodiment of the present invention.

[0047] FIGS. 55 to 57 are cross-sectional views illustrating a method for manufacturing a three-dimensional memory device according to another embodiment of the present invention.

[0048] FIGS. 58a to 62b are drawings for explaining a channel formation method that can be applied to a method for manufacturing a three-dimensional memory device according to another embodiment of the present invention.

[0049] FIGS. 63a to 67b are drawings for explaining a channel formation method that can be applied to a method for manufacturing a three-dimensional memory device according to another embodiment of the present invention.

[0050] FIGS. 68a to 72b are drawings for explaining a channel formation method that can be applied to a method for manufacturing a three-dimensional memory device according to another embodiment of the present invention.

[0051] FIGS. 73a to 87b are cross-sectional views illustrating a method for manufacturing a three-dimensional memory device according to another embodiment of the present invention.

[0052] FIG. 87a and FIG. 87b are drawings for explaining a three-dimensional memory device according to another embodiment of the present invention.

[0053] Hereinafter, embodiments of the present invention will be described in detail with reference to the attached drawings.

[0054] The embodiments of the present invention described below are provided to more clearly explain the present invention to a person having ordinary skill in the art, and the scope of the present invention is not limited by the following embodiments, and the following embodiments can be modified in various other forms.

[0055] The terminology used herein is used to describe particular embodiments and is not intended to limit the present invention. The singular forms used herein may include the plural forms unless the context clearly dictates otherwise. In addition, the terms "comprise" and / or "comprising" used herein specify the presence of a stated feature, step, number, operation, element, element, and / or group thereof, but do not exclude the presence or addition of one or more other features, steps, numbers, operations, elements, elements, and / or groups thereof. In addition, the term "connected" used herein not only means that certain elements are directly connected, but also includes a concept that indirectly connects elements by interposing another element between them.

[0056] Furthermore, in the description of this specification, terms such as "first" and "second," "upper" or "top," and "lower" or "bottom" are used to distinguish elements, and are not used to limit the elements themselves or to imply a specific order. Rather, they imply a relative positional relationship, and do not limit specific cases in which another element is introduced into direct contact with the element or at an interface between the elements. The same interpretation may be applied to other expressions describing the relationship between components.

[0057] In addition, when it is said in this specification that a certain element is located "on" another element, this includes not only cases where a certain element is in contact with another element, but also cases where another element exists between the two elements. The term "and / or" as used in this specification includes any one of the listed items and any and all combinations of one or more of them. In addition, terms of degree such as "about", "substantially", etc. as used in this specification are used to mean a range of or close to the numerical value or degree, taking into account inherent manufacturing and material tolerances, and are used to prevent infringers from unfairly using the disclosure that mentions exact or absolute numbers provided to help the understanding of this specification.

[0058] Hereinafter, embodiments of the present invention will be described in detail with reference to the attached drawings. The sizes and thicknesses of areas or parts illustrated in the attached drawings may be somewhat exaggerated for clarity and convenience of explanation. Like reference numbers designate like components throughout the detailed description.

[0059] FIGS. 1 to 3 are cross-sectional views illustrating a channel formation method that can be applied to a method for manufacturing a three-dimensional memory device according to one embodiment of the present invention.

[0060] Referring to FIG. 1, a laminate (S100) having a structure in which a semiconductor layer (SL10) and an insulating layer (NL10) are alternately and repeatedly laminated can be formed on a substrate (SUB10). The substrate (SUB10) can include at least one of a semiconductor, an insulator, and a conductor. A substrate material that can be used in a general semiconductor process can be applied to the substrate (SUB10). Preferably, the substrate (SUB10) can be, as a non-limiting example, a group IV substrate such as silicon, silicon-germanium (SiGe), or silicon-carbon (SiC), a group III-V substrate such as GaAs, InP, or GaN, or a group II-IV compound substrate such as ZnO, ZnS, CdS, or CdTe, and can also be a semiconductor substrate having a laminated structure such as silicon-on-insulator (SOI) for suppressing a body effect, or a semiconductor layer obtained through epitaxial growth. As another example, the substrate (SUB10) may be a wiring board such as a lead frame or a ceramic interposer. The laminate (S100) may include a plurality of semiconductor layers (SL10) and a plurality of insulating layers (NL10) that are alternately laminated. For example, the insulating layer (NL10) may be disposed at the lowermost portion of the laminate (S100), and the semiconductor layer (SL10) and the insulating layer (NL10) may be alternately and repeatedly laminated on the lowermost insulating layer (NL10). However, in some cases, the semiconductor layer (SL10) may also be disposed at the lowermost portion of the laminate (S100).

[0061] The semiconductor layer (SL10) may include, but is not limited to, at least one of Si, Ge, and SiGe. The semiconductor layer (SL10) may be, for example, an amorphous layer. Alternatively, the semiconductor layer (SL10) may be a polycrystalline layer having a relatively low crystallinity. As another example, the semiconductor layer (SL10) may include an oxide semiconductor, such as indium gallium zinc oxide (IGZO), which is non-silicon.

[0062] The insulating layer (NL10) may include at least one of an oxide, a nitride, and an oxynitride. For example, the insulating layer (NL10) may be, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, or other insulating materials.

[0063] Referring to Fig. 2, a vertical hole (H10) can be formed in the laminate (S100). A predetermined region of the laminate (S100) can be etched in a vertical direction to form the vertical hole (H10). The vertical hole (H10) can be formed to penetrate a plurality of semiconductor layers (SL10) and a plurality of insulating layers (NL10). The vertical hole (H10) can be formed to penetrate the laminate (S100). The vertical hole (H10) can be a 'gate hole' or a 'word line hole'.

[0064] Then, a thermally conductive layer (HC10) covering the vertical hole (H10) can be formed on the laminate (S100). The thermally conductive layer (HC10) can be formed of, as a non-limiting example, highly doped polycrystalline silicon. In other words, the thermally conductive layer (HC10) can be formed of polycrystalline silicon doped with a dopant to have conductivity. In one embodiment, the doping concentration of the thermally conductive layer (HC10) is about 10 16 atoms / cm 3 10 inland 22 atoms / cm 3 It can be a degree. The thermal conductive layer (HC10) can be formed by a deposition method such as CVD (chemical vapor deposition) or ALD (atomic layer deposition), and the doping of the thermal conductive layer (HC10) can be in-situ doped during the deposition process.

[0065] The heat-conducting layer (HC10) can be formed conformally according to the top surface of the laminate (S100) and the surface shape of the vertical hole (H10). The heat-conducting layer (HC10) can be formed with a thickness that does not completely fill the vertical hole (H10). In one embodiment, the thickness of the heat-conducting layer (HC10) can be, for non-limiting examples, about 1 nm to 7000 nm, or about 1 nm to 500 nm, or about 1.5 nm to 50 nm, and when these conditions are satisfied, the heat-conducting layer (HC10) can rapidly promote partial crystallization of the semiconductor layer (SL10) in a laser annealing process. The thickness of the heat-conducting layer (HC10) can preferably be, for non-limiting examples, less than or equal to half the bottom size (diameter) of the vertical hole (H10).

[0066] Referring to FIG. 3, a laser is irradiated onto a heat-conducting layer (HC10) to perform annealing on a portion of the semiconductor layer (SL10) around the vertical hole (H10), thereby forming a channel layer (CL10) from the portion of the semiconductor layer (SL10). Through the laser annealing process of irradiating a laser onto the heat-conducting layer (HC10), a portion of the semiconductor layer (SL10) around the vertical hole (H10) can be crystallized, thereby forming a crystallized channel layer (CL10). Since the heat-conducting layer (HC10) formed in the vertical hole (H10) can perform an excellent heat-conducting function, a uniform laser annealing effect can be obtained for a plurality of semiconductor layers (SL10) arranged around the vertical hole (H10) and spaced apart in the vertical direction. Therefore, a plurality of channel layers (CL10) having uniform characteristics can be formed. The laser may be, for example, a laser (laser beam) generated from any one of a YAG (yttrium aluminum garnet) laser generator, a CO2 laser generator, a diode laser generator, and a fiber laser generator. The laser may have, for example, a wavelength in a range of about 0.01 μm to 50 μm.

[0067] Through rapid heating by the laser annealing, a portion of the semiconductor layer (SL10) around the heat-conducting layer (HC10) can be crystallized, and a channel layer (CL10) having excellent crystal characteristics can be formed. The channel layer (CL10) can have a crystalline structure close to a polycrystal or a single crystal, and can advantageously serve to secure excellent electrical characteristics such as low leakage current and high carrier mobility. After the laser annealing, the heat-conducting layer (HC10) can be removed. The above-described disclosures regarding the heat-conducting layer (HC10) and laser annealing may be equally referenced in the embodiments described below, unless contradictory.

[0068] FIGS. 4 to 6 are cross-sectional views illustrating a channel formation method that can be applied to a method for manufacturing a three-dimensional memory device according to another embodiment of the present invention.

[0069] Referring to FIG. 4, a laminate (S100) having a structure in which a semiconductor layer (SL10) and an insulating layer (NL10) are alternately and repeatedly laminated on a substrate (SUB10) can be formed. The laminate (S100) can include a plurality of semiconductor layers (SL10) and a plurality of insulating layers (NL10) that are alternately laminated.

[0070] In the present embodiment, a metallic material layer (ML10) may be further formed on the laminate (S100). The metallic material layer (ML10) may include at least one of a metal, a metallic compound, and an alloy. The metallic material layer (ML10) may be a material layer for increasing heat absorption in a subsequent laser annealing process. The metallic material layer (ML10) for increasing heat absorption may be a metallic thin film having a high absorption coefficient for the laser wavelength used. As a non-limiting example, the metallic material layer (ML10) may include at least one of metal compounds such as Au, Ag, Ti, TiN, TiSi, Ta, TaN, Co, CoSi, Ni, NiSi, Ru, W, WSi, Cu, Re, Mo, Nb, Cr, Pd, Mg, Li, and nitrides that improve the stability of these metals. Alternatively, the metallic material layer (ML10) may be a laser penetration prevention film for preventing laser penetration into a lower structure in a subsequent laser annealing process. The metallic material layer (ML10) may include a metallic material having a high absorption coefficient for laser. As a non-limiting example, the metallic material layer (ML10) may include at least one metal or metal compound such as Ti, TiN, TiSi, Ta, TaN, Co, CoSi, Ni, NiSi, Ru, W, WSi, Cu, Re, Mo, Nb, and Cr.

[0071] The thickness of the metallic material layer (ML10) may be, for example, about 1 nm to 7000 nm or about 1 nm to 500 nm. When these conditions are satisfied, the metallic material layer (ML10) can exhibit excellent heat absorption and laser penetration prevention effects in the laser annealing process. The transmittance may vary depending on the thickness of the type of metallic material layer (ML10) and the laser wavelength. For example, when a laser having a wavelength of 532 nm is used, the transmittance may be 0% at room temperature when W is 80 nm, Ti is 110 nm, Pd is 75 nm, Mo is 115 nm, Mg is 85 nm, and Li is 180 nm or more, and the thickness of the metallic material layer (ML10) can be determined by considering these conditions. Since the absorption increases at a higher temperature, the thickness may be reduced.

[0072] Referring to FIG. 5, a vertical hole (H10) can be formed in the laminate (S100). The vertical hole (H10) can be formed in the laminate (S100) by penetrating the metallic material layer (ML10). The vertical hole (H10) can be a 'gate hole' or a 'word line hole'.

[0073] Then, a thermally conductive layer (HC10) covering the vertical hole (H10) can be formed on the laminate (S100). The thermally conductive layer (HC10) can be formed on the metallic material layer (ML10) to cover the vertical hole (H10). The thermally conductive layer (HC10) can be formed of, as a non-limiting example, highly doped polycrystalline silicon. The thermally conductive layer (HC10) can be formed by a deposition method such as CVD or ALD. The thermally conductive layer (HC10) can be formed conformally according to the upper surface of the metallic material layer (ML10) and the surface shape of the vertical hole (H10). The thermally conductive layer (HC10) can be formed with a thickness that does not completely fill the vertical hole (H10). The thermally conductive layer (HC10) can refer to the thermally conductive layer (HC10) of FIG. 2, as long as it is not contradictory.

[0074] Referring to FIG. 6, a laser is irradiated onto a heat-conducting layer (HC10) to perform annealing on a portion of a semiconductor layer (SL10) around a vertical hole (H10), thereby forming a channel layer (CL10) from the portion of the semiconductor layer (SL10). Through the laser annealing process of irradiating a laser onto the heat-conducting layer (HC10), a portion of the semiconductor layer (SL10) around the vertical hole (H10) can be crystallized, thereby forming a crystallized channel layer (CL10). Since the heat-conducting layer (HC10) formed in the vertical hole (H10) can perform an excellent heat-conducting function, a uniform (substantially uniform) laser annealing effect can be obtained for a plurality of semiconductor layers (SL10) arranged around the vertical hole (H10) and spaced apart in the vertical direction. Therefore, a plurality of channel layers (CL10) having uniform characteristics can be formed.

[0075] Through rapid heating by the laser annealing described above, a portion of the semiconductor layer (SL10) surrounding the thermal conductive layer (HC10) can be crystallized, thereby forming a channel layer (CL10) having excellent crystal characteristics. The channel layer (CL10) can have a crystalline structure close to a polycrystal or a single crystal, and can advantageously serve to secure excellent electrical characteristics such as low leakage current and high carrier mobility. After the laser annealing described above, the thermal conductive layer (HC10) and the metallic material layer (ML10) can be removed.

[0076] FIGS. 7 to 9 are cross-sectional views illustrating a channel formation method that can be applied to a method for manufacturing a three-dimensional memory device according to another embodiment of the present invention.

[0077] Referring to Fig. 7, a laminate (S100) having a structure in which a semiconductor layer (SL10) and an insulating layer (NL10) are alternately and repeatedly laminated on a substrate (SUB10) can be formed. This may be the same as described in Fig. 1.

[0078] Referring to Fig. 8, a vertical hole (H10) can be formed in the laminate (S100). The vertical hole (H10) can be formed to penetrate a plurality of semiconductor layers (SL10) and a plurality of insulating layers (NL10). The vertical hole (H10) can be referred to as a 'gate hole' or a 'word line hole'.

[0079] After the step of forming a vertical hole (H10) in the laminate (S100), a diffusion barrier layer (DB11) covering the vertical hole (H10) can be formed on the laminate (S100). Then, a thermally conductive layer (HC11) can be formed on the diffusion barrier layer (DB11). The diffusion barrier layer (DB11) and the thermally conductive layer (HC11) can be formed by a deposition method. The diffusion barrier layer (DB11) and the thermally conductive layer (HC11) can be formed conformally according to the shape of the upper surface of the laminate (S100) and the surface of the vertical hole (H10). The diffusion barrier layer (DB11) and the thermally conductive layer (HC11) can be formed with a thickness that does not completely fill the vertical hole (H10).

[0080] The diffusion barrier layer (DB11) may serve to prevent the material (e.g., metallic material) of the thermally conductive layer (HC11) from diffusing into the semiconductor layer (SL10) during a subsequent laser annealing process. For example, the diffusion barrier layer (DB11) may be a layer that prevents the diffusion of the metallic material. The diffusion barrier layer (DB11) may, as a non-limiting example, include at least one of silicon nitride and silicon carbide. However, the material of the diffusion barrier layer (DB11) is not limited to the above and may vary. The diffusion barrier layer (DB11) may be an insulating layer or an inorganic insulating layer. The thickness of the diffusion barrier layer (DB11) may be smaller than the thickness of the thermally conductive layer (HC10).

[0081] The heat-conducting layer (HC11) may include, for example, a metallic material. The metallic material may include at least one of a metal, a metal compound, and an alloy. The heat-conducting layer (HC11) may be a material layer capable of increasing heat absorption in a subsequent laser annealing process. The heat-conducting layer (HC11) may be a metallic thin film having a high absorption coefficient for the laser wavelength used. As a non-limiting example, for a laser having a wavelength of 532 nm, the heat-conducting layer (HC11) may include at least one of Au, Ag, W, Ti, Pd, Ni, Mg, Li, and a nitride thereof. The heat-conducting layer (HC11) may refer to the heat-conducting layer (HC10) described with reference to FIG. 2, unless otherwise contradictory.

[0082] Referring to FIG. 9, by irradiating a laser to the heat-conducting layer (HC11), annealing can be performed on a portion of the semiconductor layer (SL10) around the vertical hole (H10), thereby forming a channel layer (CL10) from the portion of the semiconductor layer (SL10). Through the laser annealing process of irradiating a laser to the heat-conducting layer (HC11), the portion of the semiconductor layer (SL10) around the vertical hole (H10) can be crystallized, and a crystallized channel layer (CL10) can be formed. Since the heat-conducting layer (HC11) formed in the vertical hole (H10) can perform an excellent heat-conducting function, a uniform (substantially uniform) laser annealing effect can be obtained for a plurality of semiconductor layers (SL10) arranged around the vertical hole (H10) and spaced apart in the vertical direction. Therefore, a plurality of channel layers (CL10) having uniform characteristics can be formed.

[0083] Through rapid heating by the laser annealing, a portion of the semiconductor layer (SL10) around the heat-conducting layer (HC11) can be crystallized, and a channel layer (CL10) having excellent crystal characteristics can be formed. The channel layer (CL10) can have a crystalline structure close to a polycrystal or a single crystal, and can advantageously serve to secure excellent electrical characteristics such as low leakage current and high carrier mobility. After the laser annealing, the heat-conducting layer (HC11) and the diffusion barrier layer (DB11) can be removed. However, in some cases, at least a portion of the diffusion barrier layer (DB11) may not be removed.

[0084] FIGS. 10 to 12 are cross-sectional views illustrating a method for manufacturing a three-dimensional memory device according to one embodiment of the present invention. The manufacturing processes of FIGS. 10 to 12 can be commonly applied as a subsequent process to the manufacturing processes of FIGS. 1 to 3, FIGS. 4 to 6, and FIGS. 7 to 9 described above.

[0085] Referring to Fig. 10, after forming the channel layer (CL10) through laser annealing, the thermal conductive layer can be removed. For example, in Fig. 3, the thermal conductive layer (HC10) can be removed, in Fig. 6, the thermal conductive layer (HC10) and the metallic material layer (ML10) can be removed, and in Fig. 9, the thermal conductive layer (HC11) and the diffusion barrier layer (DB11) can be removed.

[0086] Then, a gate insulating layer (GN10) covering the inner surface of the vertical hole (H10) can be defined. As a non-limiting example, the gate insulating layer (GN10) can be formed using a deposition method such as atomic layer deposition (ALD). The gate insulating layer (GN10) can be formed conformally according to the top surface of the stack (S100) and the surface shape of the vertical hole (H10). The gate insulating layer (GN10) can be formed to have a relatively thin thickness. The gate insulating layer (GN10) can include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, or a high-k material, and in another embodiment, can include a stacked structure composed of two or more different insulating layers, but the present invention is not limited thereto. Any material that can be used as a gate insulating material in a general transistor device can be applied as a material of the gate insulating layer (GN10). The high-k material may be hafnium oxide (HfO2), zirconium oxide (ZrO2), or a combination thereof, which have a higher dielectric constant than silicon nitride. If at least a portion of the diffusion barrier layer (DB11) in the structure of FIG. 9 is left untouched, at least a portion of the diffusion barrier layer (DB11) may be used as a gate insulating layer material.

[0087] Next, a word line (WL10) that at least partially fills the vertical hole (H10) can be formed on the gate insulating layer (GN10). The word line (WL10) may be referred to as a 'gate' or a 'gate line'. The word line (WL10) may be formed to fill the vertical hole (H10) on the gate insulating layer (GN10) and may be a vertically extending wiring. If there is a conductive material of the word line (WL10) deposited above the vertical hole (H10) and above the upper surface of the stack (S100), it can be removed, for example, through an etch-back process.

[0088] Referring to FIG. 11, a semiconductor layer (SL10) may be removed from one side of a channel layer (CL10) to expose a first side region of the channel layer (CL10), and a bit line (BL10) electrically connected to the first side region of the channel layer (CL10) may be formed. A source layer (SC10) may further be formed in the first side region of the channel layer (CL10), and in this case, the bit line (BL10) may be formed to be in contact with the source layer (SC10). The source layer (SC10) may include an ohmic contact layer. However, the formation of the source layer (SC10) and the ohmic contact layer may be optional.

[0089] Referring to FIG. 12, the semiconductor layer (SL10) can be removed from the other side of the channel layer (CL10) to expose a second side region of the channel layer (CL10), and a capacitor (CP10) electrically connected to the second side region of the channel layer (CL10) can be formed.

[0090] The capacitor (CP10) may include a first electrode (EL10) in electrical contact with the second side region of the channel layer (CL10). An insulating material may be removed around the first electrode (EL10), and the first electrode (EL10) may have a shape that protrudes, for example, laterally, from the second side region of the channel layer (CL10). If necessary, an ohmic contact layer may be further disposed between the first electrode (EL10) and the channel layer (CL10). The ohmic contact layer may be considered to be included in the first electrode (EL10). The use of the ohmic contact layer may be optional.

[0091] The capacitor (CP10) may include a dielectric layer (DL10) arranged to cover the upper surface, lower surface, front surface, rear surface, and side surfaces of the first electrode (EL10). The dielectric layer (DL10) may be arranged to surround the exposed surfaces of the first electrode (EL10). Therefore, the contact area of ​​the dielectric layer (DL10) with respect to the first electrode (EL10) may be significantly increased. In addition, the capacitor (CP10) may include a second electrode (EL20) arranged on the dielectric layer (DL10). The second electrode (EL20) may be a common electrode commonly applied to a plurality of first electrodes (EL10). A plurality of capacitors (CP10) may be arranged to be electrically connected to the second side regions of the plurality of channel layers (CL10), respectively. The plurality of capacitors (CP10) may be arranged to be adjacent to each other in the vertical direction.

[0092] In FIG. 11 and FIG. 12, a case in which the bit line (BL10) is formed first and the capacitor (CP10) is formed later is illustrated and described, but in some cases, the capacitor (CP10) may be formed first and the bit line (BL10) may be formed later.

[0093] FIGS. 13A to 16B are drawings for explaining a channel formation method that can be applied to a method for manufacturing a three-dimensional memory device according to one embodiment of the present invention.

[0094] In FIGS. 13a to 16b, the same drawing numbers (e.g., FIG. 13 in FIGS. 13a and 13b) represent the same steps. FIGS. 13a, 14a, 15a, and 16a are cross-sectional views taken along the XZ plane. FIGS. 13b, 14b, 15b, and 16b are cross-sectional views taken along the XY plane. FIG. 13b is a cross-sectional view taken along the line A-A' of FIG. 13a, and FIG. 13a is a cross-sectional view taken along the line B-B' of FIG. 13b. This relationship is the same in FIGS. 14a and 14b, 15a and 15b, and 16a and 16b. FIGS. 13a to 16b show a method of forming a channel for a memory array.

[0095] Referring to FIGS. 13a and 13b, a laminate (S100) having a structure in which a semiconductor layer (SL10) and an insulating layer (NL10) are alternately and repeatedly laminated on a substrate (SUB10) can be formed. The laminate (S100) can include a plurality of semiconductor layers (SL10) and a plurality of insulating layers (NL10) that are alternately laminated.

[0096] Referring to FIGS. 14a and 14b, a vertical hole (H10) can be formed in the laminate (S100). A predetermined region of the laminate (S100) can be etched in a vertical direction to form the vertical hole (H10). The vertical hole (H10) can be formed to penetrate a plurality of semiconductor layers (SL10) and a plurality of insulating layers (NL10). The vertical hole (H10) can be formed to penetrate the laminate (S100). The vertical hole (H10) can be a 'gate hole' or a 'word line hole'. A plurality of vertical holes (H10) can be formed to be spaced apart from each other.

[0097] Referring to FIGS. 15a and 15b, a thermally conductive layer (HC10) covering a vertical hole (H10) can be formed on a laminate (S100). The thermally conductive layer (HC10) can be formed, as a non-limiting example, of highly doped polycrystalline silicon. In other words, the thermally conductive layer (HC10) can be formed of polycrystalline silicon doped with a dopant to have conductivity. The thermally conductive layer (HC10) can be formed conformally according to the top surface of the laminate (S100) and the surface shape of the vertical hole (H10). The thermally conductive layer (HC10) can be formed with a thickness that does not completely fill the vertical hole (H10).

[0098] Referring to FIGS. 16a and 16b, a laser is irradiated onto the heat-conducting layer (HC10) to perform annealing on a portion of the semiconductor layer (SL10) around the vertical hole (H10), thereby forming a channel layer (CL10) from the portion of the semiconductor layer (SL10). Through the laser annealing process of irradiating the heat-conducting layer (HC10) with a laser, the portion of the semiconductor layer (SL10) around the vertical hole (H10) can be crystallized, thereby forming a crystallized channel layer (CL10). The channel layer (CL10) may have a crystalline structure close to a polycrystal or a single crystal. Each of the channel layers (CL10) may have a structure surrounding the vertical hole (H10). Each of the channel layers (CL10) may have a rectangular ring shape, a polygonal ring shape, a circular ring shape, an elliptical ring shape, or a similar shape. A plurality of channel layers (CL10) can be arranged vertically and spaced apart from each other around each vertical hole (H10).

[0099] FIGS. 17A to 20B are drawings for explaining a channel formation method that can be applied to a method for manufacturing a three-dimensional memory device according to another embodiment of the present invention.

[0100] In FIGS. 17A to 20B, the same drawing numbers (e.g., FIG. 17 in FIGS. 17A and 17B) represent the same steps. FIGS. 17A, 18A, 19A, and 20A are cross-sectional views taken along the XZ plane. FIGS. 17B, 18B, 19B, and 20B are cross-sectional views taken along the XY plane. FIG. 17B is a cross-sectional view taken along the line A-A' of FIG. 17A, and FIG. 17A is a cross-sectional view taken along the line B-B' of FIG. 17B. This relationship is the same in FIGS. 18A and 18B, 19A and 19B, and 20A and 20B. FIGS. 17A to 20B show a method of forming a channel for a memory array.

[0101] Referring to FIGS. 17a and 17b, a laminate (S100) having a structure in which a semiconductor layer (SL10) and an insulating layer (NL10) are alternately and repeatedly laminated can be formed on a substrate (SUB10). The laminate (S100) can include a plurality of alternately laminated semiconductor layers (SL10) and a plurality of insulating layers (NL10). A metallic material layer (ML10) can be further formed on the laminate (S100).

[0102] Referring to FIGS. 18a and 18b, a vertical hole (H10) can be formed in the laminate (S100). The vertical hole (H10) can be formed in the laminate (S100) by penetrating the metallic material layer (ML10). The vertical hole (H10) can be a 'gate hole' or a 'word line hole'. A plurality of vertical holes (H10) can be formed spaced apart from each other.

[0103] Referring to FIGS. 19a and 19b, a thermally conductive layer (HC10) covering a vertical hole (H10) can be formed on a laminate (S100). The thermally conductive layer (HC10) can be formed on a metallic material layer (ML10) to cover the vertical hole (H10). As a non-limiting example, the thermally conductive layer (HC10) can be formed of highly doped polycrystalline silicon. The thermally conductive layer (HC10) can be formed conformally according to the top surface of the metallic material layer (ML10) and the surface shape of the vertical hole (H10). The thermally conductive layer (HC10) can be formed with a thickness that does not completely fill the vertical hole (H10).

[0104] Referring to FIGS. 20a and 20b, a laser is irradiated onto the heat-conducting layer (HC10) to perform annealing on a portion of the semiconductor layer (SL10) around the vertical hole (H10), thereby forming a channel layer (CL10) from the portion of the semiconductor layer (SL10). Through the laser annealing process of irradiating the heat-conducting layer (HC10) with a laser, a portion of the semiconductor layer (SL10) around the vertical hole (H10) can be crystallized, thereby forming a crystallized channel layer (CL10). The channel layer (CL10) may have a crystalline structure close to a polycrystal or a single crystal. Each of the channel layers (CL10) may have a structure surrounding the vertical hole (H10). Each of the channel layers (CL10) may have a rectangular ring shape, a polygonal ring shape, a circular ring shape, an elliptical ring shape, or a similar shape. A plurality of channel layers (CL10) can be arranged vertically and spaced apart from each other around each vertical hole (H10).

[0105] FIGS. 21A to 24B are drawings for explaining a channel formation method that can be applied to a method for manufacturing a three-dimensional memory device according to another embodiment of the present invention.

[0106] In FIGS. 21A to 24B, the same drawing numbers (e.g., FIG. 21 in FIGS. 21A and 21B) represent the same steps. FIGS. 21A, 22A, 23A, and 24A are cross-sectional views taken along the XZ plane. FIGS. 21B, 22B, 23B, and 24B are cross-sectional views taken along the XY plane. FIG. 21B is a cross-sectional view taken along the line A-A' of FIG. 21A, and FIG. 21A is a cross-sectional view taken along the line B-B' of FIG. 21B. This relationship is the same in FIGS. 22A and 22B, FIGS. 23A and 23B, and FIGS. 24A and 24B. FIGS. 21A to 24B show a method of forming a channel for a memory array.

[0107] Referring to FIGS. 21a and 21b, a laminate (S100) having a structure in which a semiconductor layer (SL10) and an insulating layer (NL10) are alternately and repeatedly laminated on a substrate (SUB10) can be formed. This may be the same as described in FIGS. 13a and 13b.

[0108] Referring to FIGS. 22a and 22b, a vertical hole (H10) can be formed in the laminate (S100). The vertical hole (H10) can be formed to penetrate a plurality of semiconductor layers (SL10) and a plurality of insulating layers (NL10). The vertical hole (H10) can be referred to as a 'gate hole' or a 'word line hole'. A plurality of vertical holes (H10) can be formed spaced apart from each other.

[0109] Referring to FIGS. 23a and 23b, a diffusion barrier layer (DB11) covering a vertical hole (H10) can be formed on a laminate (S100). Then, a thermally conductive layer (HC11) can be formed on the diffusion barrier layer (DB11). The diffusion barrier layer (DB11) and the thermally conductive layer (HC11) can be formed by a deposition method. The diffusion barrier layer (DB11) and the thermally conductive layer (HC11) can be formed conformally according to the shape of the upper surface of the laminate (S100) and the surface of the vertical hole (H10). The diffusion barrier layer (DB11) and the thermally conductive layer (HC11) can be formed with a thickness that does not completely fill the vertical hole (H10). The diffusion barrier layer (DB11) can be, for example, an insulating layer (inorganic insulating layer). The thermal conductive layer (HC11) may include, for example, a metallic material.

[0110] Referring to FIGS. 24a and 24b, a laser is irradiated onto the heat-conducting layer (HC11) to perform annealing on a portion of the semiconductor layer (SL10) around the vertical hole (H10), thereby forming a channel layer (CL10) from the portion of the semiconductor layer (SL10). Through the laser annealing process of irradiating the heat-conducting layer (HC11) with a laser, a portion of the semiconductor layer (SL10) around the vertical hole (H10) can be crystallized, thereby forming a crystallized channel layer (CL10). The channel layer (CL10) may have a crystalline structure close to a polycrystal or a single crystal. Each of the channel layers (CL10) may have a structure surrounding the vertical hole (H10). Each of the channel layers (CL10) may have a rectangular ring shape, a polygonal ring shape, a circular ring shape, an elliptical ring shape, or a similar shape. A plurality of channel layers (CL10) can be arranged vertically and spaced apart from each other around each vertical hole (H10).

[0111] FIGS. 25A to 39B are cross-sectional views illustrating a method for manufacturing a three-dimensional memory device according to another embodiment of the present invention. The manufacturing processes of FIGS. 25A to 39B can be commonly applied as a subsequent process to the manufacturing processes of FIGS. 13A to 16B, 17A to 20B, and 21A to 24B described above.

[0112] In FIGS. 25a to 39b, the same drawing numbers (e.g., FIG. 25 in FIGS. 25a and 25b) indicate the same steps. FIGS. 25a, 26a, 27a, 28a, 29a, 30a, 31a, 32a, 33a, 34a, 35a, 36a, 37a, 38a, and 39a are cross-sectional views cut along the XZ plane. FIGS. 25b, 26b, 27b, 28b, 29b, 30b, 31b, 32b, 33b, 34b, 35b, 36b, 37b, 38b, and 39b are cross-sectional views cut along the XY plane. Fig. 25b is a cross-sectional view taken along line A-A' of Fig. 25a, and Fig. 25a is a cross-sectional view taken along line B-B' of Fig. 25b. These relationships are the same in Figs. 26a to 39b. Figs. 25a to 39b illustrate a method for manufacturing a three-dimensional memory array.

[0113] Referring to FIGS. 25a and 25b, after forming the channel layer (CL10) through laser annealing, the thermal conductive layer can be removed. In FIG. 16a, the thermal conductive layer (HC10) can be removed, in FIG. 20a, the thermal conductive layer (HC10) and the metallic material layer (ML10) can be removed, and in FIG. 24a, the thermal conductive layer (HC11) and the diffusion barrier layer (DB11) can be removed.

[0114] Referring to FIGS. 26a and 26b, a gate insulating layer (GN10) covering the inner surface of the vertical hole (H10) can be formed. As a non-limiting example, the gate insulating layer (GN10) can be formed using a deposition method such as ALD. The gate insulating layer (GN10) can be formed conformally according to the upper surface of the stack (S100) and the surface shape of the vertical hole (H10). The gate insulating layer (GN10) can be formed with a relatively thin thickness. If at least a portion of the diffusion barrier layer (DB11) in the structure of FIG. 24a is not removed but remains, at least a portion of the diffusion barrier layer (DB11) can be used as a gate insulating layer material.

[0115] Referring to FIGS. 27a and 27b, a word line (WL10) that at least partially fills a vertical hole (H10) may be formed on a gate insulating layer (GN10). The word line (WL10) may be referred to as a 'gate' or a 'gate line'. The word line (WL10) may be formed to fill the vertical hole (H10) on the gate insulating layer (GN10) and may be a vertically extending wiring. If there is a conductive material of the word line (WL10) deposited above the vertical hole (H10) and above the upper surface of the stack (S100), it may be removed, for example, through an etch-back process.

[0116] Referring to FIGS. 28a and 28b, an etched portion (EP10) that exposes both sides of the channel layer (CL10) can be formed by etching a portion of the laminate (S100). The etched portion (EP10) can be formed by etching a portion of the semiconductor layer (SL10) that exists on both sides of the channel layer (CL10) in the Y-axis direction (second direction). Alternatively, the etched portion (EP10) can be formed by etching a portion of the semiconductor layer (SL10) and a portion of the insulating layer (NL10) that exist on both sides of the channel layer (CL10) in the Y-axis direction (second direction).

[0117] Referring to FIGS. 29a and 29b, an insulating material (NM10) may be filled into the etched portion (EP10). The insulating material (NM10) may be referred to as a filled insulating layer. The insulating material (NM10) may include at least one of various insulating materials.

[0118] Referring to FIGS. 30A and 30B, a first trench (T10) may be formed by etching a portion of the laminate (S100). The first trench (T10) may be formed between two channel layers (CL10) spaced apart in the X-axis direction (first direction). The first trench (T10) may be formed to penetrate the laminate (S100). In addition, the first trench (T10) may have a shape (e.g., a line shape) extending in the Y-axis direction (second direction). Here, the second direction may be a direction perpendicular to the first direction.

[0119] Referring to FIGS. 31A and 31B, a first recess portion (R1) exposing a first side region of a channel layer (CL10) may be formed by removing a portion of a semiconductor layer (SL10) exposed by a first trench (T10). The first side region may be any one region among double-sided regions along the X-axis direction (first direction) of the channel layer (CL10). Then, a source layer (SC10) in contact with the first side region of the channel layer (CL10) may be formed. The source layer (SC10) may be a conductive material layer. The source layer (SC10) may include an ohmic contact layer. However, formation of the source layer (SC10) and the ohmic contact layer may be optional.

[0120] Referring to FIGS. 32A and 32B, a bit line (BL10) can be formed within the first recess portion (R1). For example, after forming a material layer for a bit line that fills the first recess portion (R1) and the first trench (T10), a portion of the material layer for a bit line disposed in the first trench (T10) can be removed to form the bit line (BL10). The bit line (BL10) can have a shape extending in the Y-axis direction (second direction). The bit line (BL10) can be electrically connected to the first side region of the channel layer (CL10).

[0121] Referring to FIGS. 33a and 33b, a separator (SN10) filling the first trench (T10) can be formed. The separator (SN10) may be an insulating material layer. The separator (SN10) may serve to separate cells in a horizontal direction.

[0122] Referring to FIGS. 34a and 34b, a second trench (T20) may be formed by etching a portion of the stack (S100). The second trench (T20) may be formed in a capacitor formation region (a capacitor formation region). The second trench (T20) may be formed by etching a portion of the stack (S100) on the opposite side of the bit line (BL10). The second trench (T20) may be formed to penetrate the stack (S100) and may have a shape (e.g., a line shape) extending in the Y-axis direction (the second direction).

[0123] Referring to FIGS. 35a and 35b, a second recess portion (R2) exposing a second side region of the channel layer (CL10) may be formed by removing a portion of the semiconductor layer (SL10) exposed by the second trench (T20). The second side region may be an opposite region of the first side region. The first side region and the second side region may be opposite side regions of the channel layer (CL10) in the X-axis direction (first direction).

[0124] Referring to FIGS. 36a and 36b, a first electrode (EL10) for a capacitor may be formed within the second recess portion (R2). If necessary, an ohmic contact layer may be formed between the first electrode (EL10) and the channel layer (CL10). The ohmic contact layer may be considered to be included in the first electrode (EL10). The use of the ohmic contact layer may be optional.

[0125] Referring to FIGS. 37a and 37b, the insulating material around the first electrode (EL10) can be removed to expose the surface of the first electrode (EL10). The insulating layer (NL10) portions disposed above and below the first electrode (EL10) can be removed, and further, the insulating material (NM10) portions disposed before and after the first electrode (EL10) can be removed. Accordingly, the upper surface, lower surface, front surface, and rear surface of the first electrode (EL10) can be exposed. Since the side surface (outer side surface) of the first electrode (EL10) may already be exposed, the upper surface (upper surface portion), lower surface (lower surface portion), front surface (front surface portion), rear surface (rear surface portion), and side surface (side surface) of the first electrode (EL10) can be exposed.

[0126] Referring to FIGS. 38a and 38b, a dielectric layer (DL10) for a capacitor may be formed on an exposed surface of a first electrode (EL10). The dielectric layer (DL10) may be formed to cover the upper surface, lower surface, front surface, rear surface, and side surface of the first electrode (EL10). The dielectric layer (DL10) may be arranged to surround the exposed surfaces of the first electrode (EL10). Accordingly, the contact area of ​​the dielectric layer (DL10) with respect to the first electrode (EL10) may be significantly increased. The dielectric layer (DL10) may be formed by a deposition process such as ALD. The dielectric layer (DL10) may be conformally formed on a target surface with a relatively thin thickness.

[0127] Referring to FIGS. 39a and 39b, a second electrode (EL20) for a capacitor may be formed on a dielectric layer (DL10). The second electrode (EL20) may be commonly applied to a plurality of first electrodes (EL10). The second electrode (EL20) may be formed to fill the second trench (T20 of FIG. 36a). The first electrode (EL10), the dielectric layer (DL10), and the second electrode (EL20) may constitute a capacitor (CP10). A plurality of capacitors (CP10) may be arranged to be electrically connected to the second side regions of the plurality of channel layers (CL10), respectively. The plurality of capacitors (CP10) may be arranged to be adjacent to each other in a vertical direction.

[0128] In the embodiments of FIGS. 25a to 39b, the case where the bit line (BL10) is formed first and the capacitor (CP10) is formed later is illustrated and described, but in some cases, the capacitor (CP10) may be formed first and the bit line (BL10) may be formed later.

[0129] Hereinafter, the structure of a three-dimensional memory device according to one embodiment of the present invention will be described with reference to FIGS. 39a and 39b.

[0130] Referring to FIGS. 39A and 39B , a three-dimensional memory device (i.e., a multi-stacked memory device) according to an embodiment of the present invention may include a word line (WL10) extending in a vertical direction, a plurality of channel layers (CL10) having a shape surrounding the word line (WL10) and spaced apart from each other in the vertical direction, a plurality of bit lines (BL10) electrically connected to first side regions of the plurality of channel layers (CL10) and extending in a horizontal direction, a plurality of capacitors (CP10) electrically connected to second side regions of the plurality of channel layers (CL10) and arranged to be adjacent to each other in the vertical direction, and an insulating layer (NL10) arranged between the plurality of channel layers (CL10).

[0131] According to one embodiment, the capacitor (CP10) may include a first electrode (EL10) electrically contacting the second side region of the channel layer (CL10). The first electrode (EL10) may have a shape that protrudes (protrudes laterally) from the second side region. The capacitor (CP10) may include a dielectric layer (DL10) arranged to cover an upper surface (top surface), a lower surface (bottom surface), a front surface (front surface), a rear surface (rear surface), and a side surface (side surface) of the first electrode (EL10). In addition, the capacitor (CP10) may include a second electrode (EL20) arranged on the dielectric layer (DL10).

[0132] According to one embodiment, the word line (WL10) may be arranged within the vertical hole (H10) of the stack, and a gate insulating layer (GN10) may be arranged between the inner surface of the vertical hole (H10) and the word line (WL10).

[0133] According to one embodiment, a word line (WL10), a plurality of channel layers (CL10), a plurality of bit lines (BL10), and a plurality of capacitors (CP10) may constitute a first memory stack. A second memory stack may be provided that is horizontally spaced apart from the first memory stack. The first memory stack and the second memory stack may have a structure that is symmetrical with respect to a separator (SN10) provided therebetween. For example, in FIG. 39a, a stack portion on the left may correspond to the first memory stack, and a stack portion on the right may correspond to the second memory stack.

[0134] According to one embodiment, a channel layer (CL10) of the first memory stack may be disposed between a separator (SN10) and a capacitor (CP10) of the first memory stack. In addition, a bit line (BL10) of the first memory stack may be disposed between the separator (SN10) and the channel layer (CL10) of the first memory stack. This structure may be symmetrically identical in the second memory stack as well.

[0135] A three-dimensional memory device according to an embodiment of the present invention may include a plurality of memory cells stacked in a vertical direction. Each of the plurality of memory cells may include a transistor and a capacitor electrically connected to the side of the transistor. A three-dimensional memory device according to an embodiment of the present invention may have structural features as illustrated in FIGS. 39A and 39B. Although not illustrated, device structures such as those in FIGS. 39A and 39B may be repeatedly arranged in the X-axis direction and may also be repeatedly arranged in the Y-axis direction.

[0136] According to embodiments of the present invention, a three-dimensional memory device having excellent performance, uniformity, and operating characteristics while significantly improving integration density can be realized. The three-dimensional memory device according to embodiments of the present invention may be a three-dimensional dynamic random access memory (DRAM) device.

[0137] FIGS. 40 to 44 are cross-sectional views illustrating a channel formation method that can be applied to a method for manufacturing a three-dimensional memory device according to another embodiment of the present invention.

[0138] Referring to FIG. 40, a laminate (S200) having a structure in which a sacrificial layer (SF10) and an insulating layer (NL10) are alternately and repeatedly laminated can be formed on a substrate (SUB10). The substrate (SUB10) can include at least one of a semiconductor, an insulator, and a conductor. A substrate material that can be used in a general semiconductor process can be applied to the substrate (SUB10). The laminate (S200) can include a plurality of sacrificial layers (SF10) and a plurality of insulating layers (NL10) that are alternately laminated. For example, an insulating layer (NL10) can be disposed at the lowermost portion of the laminate (S200), and the sacrificial layer (SF10) and the insulating layer (NL10) can be alternately and repeatedly laminated on the lowermost insulating layer (NL10). However, in some cases, the sacrificial layer (SF10) may also be disposed at the lowermost portion of the laminate (S200).

[0139] The insulating layer (NL10) may include, but is not limited to, at least one of silicon oxide, silicon nitride, silicon oxynitride, and other insulating materials. The sacrificial layer (SF10) may be composed of a material having an etching selectivity with respect to the insulating layer (NL10) and a channel material layer (CM10 of FIG. 43) to be formed later. For example, when the insulating layer (NL10) is formed of silicon oxide, the sacrificial layer (SF10) may be formed of silicon nitride. However, the material of the sacrificial layer (SF10) is not limited to silicon nitride and may vary.

[0140] Referring to Fig. 41, a vertical hole (H10) can be formed in the laminate (S200). A predetermined region of the laminate (S200) can be etched in a vertical direction to form the vertical hole (H10). The vertical hole (H10) can be formed to penetrate a plurality of sacrificial layers (SF10) and a plurality of insulating layers (NL10). The vertical hole (H10) can be formed to penetrate the laminate (S200). The vertical hole (H10) can be a 'gate hole' or a 'word line hole'.

[0141] Referring to Fig. 42, a portion of the sacrificial layer (SF10) around the vertical hole (H10) can be recessed to form a recess area (A1). For example, a wet etching solution having an etching selectivity for the sacrificial layer (SF10) relative to the insulating layer (NL10) can be used to recess the portion of the sacrificial layer (SF10) around the vertical hole (H10). Each recess area (A1) can have a shape surrounding the vertical hole (H10).

[0142] Referring to FIG. 43, a channel material layer (CM10) filling at least the recess area (A1) can be formed. The channel material layer (CM10) can be formed on the stack (S200) to cover the vertical hole (H10) while filling the recess area (A1). The channel material layer (CM10) can be formed by a deposition method such as CVD or ALD. The channel material layer (CM10) can be formed to a thickness that does not completely fill the vertical hole (H10). The channel material layer (CM10) can include, as a non-limiting example, at least one of Si, Ge, and SiGe. The channel material layer (CM10) can be, for example, an amorphous layer. Alternatively, the channel material layer (CM10) can be a polycrystalline layer having a relatively low crystallinity. The channel material layer (CM10) can have a doping concentration at a general channel level.

[0143] Referring to Fig. 44, direct or indirect laser annealing can be performed on the channel material layer (CM10). In the present embodiment, annealing can be performed on the channel material layer (CM10) by irradiating the channel material layer (CM10) with a laser.

[0144] In the above laser annealing process, the channel material layer (CM10) can function as a type of thermally conductive layer. Accordingly, portions of the channel material layer (CM10) present in a plurality of recessed regions (A1 in FIG. 42) arranged along the longitudinal direction (depth direction) of the vertical hole (H10) can be easily crystallized and can be crystallized uniformly (substantially uniformly). Accordingly, a plurality of channel layer regions having uniform characteristics can be formed.

[0145] Through rapid heating by the laser annealing described above, a channel material layer (CM10) arranged horizontally along the depth direction can be crystallized, thereby forming a channel layer region having excellent crystal characteristics. The channel material layer (CM10) can have a crystal structure close to a polycrystal or a single crystal, and can advantageously serve to secure excellent electrical characteristics such as low leakage current and high carrier mobility.

[0146] After the laser annealing, the remaining portion of the channel material layer (CM10) except for the portion positioned within the recessed region (A1 of FIG. 42) can be removed. For example, the remaining portion of the channel material layer (CM10) except for the portion positioned within the recessed region (A1 of FIG. 42) can be removed through an etch-back process.

[0147] FIGS. 45 to 49 are cross-sectional views illustrating a channel formation method that can be applied to a method for manufacturing a three-dimensional memory device according to another embodiment of the present invention.

[0148] Referring to Fig. 45, a laminate (S200) having a structure in which a sacrificial layer (SF10) and an insulating layer (NL10) are alternately and repeatedly laminated on a substrate (SUB10) can be formed. The laminate (S200) can include a plurality of sacrificial layers (SF10) and a plurality of insulating layers (NL10) that are alternately laminated.

[0149] In the present embodiment, a metallic material layer (ML10) may be further formed on the laminate (S200). The metallic material layer (ML10) may include at least one of a metal, a metal compound, and an alloy. The metallic material layer (ML10) may be a material layer for increasing heat absorption in a subsequent laser annealing process. The metallic material layer (ML10) for increasing heat absorption may be a metallic thin film having a high absorption coefficient for the laser wavelength used. As a non-limiting example, for a laser having a wavelength of 532 nm, the metallic material layer (ML10) may include at least one of Au, Ag, W, Ti, Pd, Ni, Mg, Li, and a nitride thereof.

[0150] Alternatively, the metallic material layer (ML10) may be a laser penetration barrier to prevent laser penetration during a subsequent laser annealing process. The metallic material layer (ML10) may include a metallic material having a high absorption coefficient for laser.

[0151] Referring to Fig. 46, a vertical hole (H10) can be formed in the laminate (S200). The vertical hole (H10) can be formed in the laminate (S200) by penetrating the metallic material layer (ML10). The vertical hole (H10) can be a 'gate hole' or a 'word line hole'.

[0152] Referring to Fig. 47, a portion of the sacrificial layer (SF10) around the vertical hole (H10) can be recessed to form a recess area (A1). For example, a wet etching solution having an etching selectivity for the sacrificial layer (SF10) relative to the insulating layer (NL10) can be used to recess the portion of the sacrificial layer (SF10) around the vertical hole (H10). Each recess area (A1) can have a shape surrounding the vertical hole (H10).

[0153] Referring to FIG. 48, a channel material layer (CM10) filling at least the recess area (A1) can be formed. The channel material layer (CM10) can be formed on a metallic material layer (ML10) to cover the vertical hole (H10) while filling the recess area (A1). The channel material layer (CM10) can be formed by a deposition method such as CVD or ALD. The channel material layer (CM10) can be formed to a thickness that does not completely fill the vertical hole (H10). The channel material layer (CM10) can include, as a non-limiting example, at least one of Si, Ge, and SiGe. The channel material layer (CM10) can be, for example, an amorphous layer. Alternatively, the channel material layer (CM10) can be a polycrystalline layer having a relatively low crystallinity. The channel material layer (CM10) can have a doping concentration at a general channel level.

[0154] Referring to Fig. 49, direct or indirect laser annealing can be performed on the channel material layer (CM10). In the present embodiment, annealing can be performed on the channel material layer (CM10) by irradiating the channel material layer (CM10) with a laser.

[0155] In the above laser annealing process, the channel material layer (CM10) can function as a type of thermally conductive layer. Accordingly, portions of the channel material layer (CM10) present in a plurality of recessed regions (A1 in FIG. 47) arranged along the longitudinal direction (depth direction) of the vertical hole (H10) can be easily crystallized and can be crystallized uniformly (substantially uniformly). Accordingly, a plurality of channel layer regions having uniform characteristics can be formed.

[0156] Through rapid heating by the above laser annealing, the channel material layer (CM10) can be crystallized, and a channel layer region with excellent crystal characteristics can be formed. The channel material layer (CM10) can have a crystalline structure close to a polycrystalline or single crystal, and can advantageously serve to secure excellent electrical characteristics such as low leakage current and high carrier mobility.

[0157] After the laser annealing, the remaining portion of the channel material layer (CM10) except for the portion positioned within the recessed region (A1 of FIG. 47) may be removed. For example, the remaining portion of the channel material layer (CM10) except for the portion positioned within the recessed region (A1 of FIG. 47) may be removed through an etch-back process. Additionally, the metallic material layer (ML10) may also be removed.

[0158] FIGS. 50 to 54 are cross-sectional views illustrating a channel formation method that can be applied to a method for manufacturing a three-dimensional memory device according to another embodiment of the present invention.

[0159] Referring to Fig. 50, a laminate (S200) having a structure in which a sacrificial layer (SF10) and an insulating layer (NL10) are alternately and repeatedly laminated on a substrate (SUB10) can be formed. This may be the same as described in Fig. 40.

[0160] Referring to Fig. 51, a vertical hole (H10) can be formed in the laminate (S200). The vertical hole (H10) can be formed to penetrate multiple sacrificial layers (SF10) and multiple insulating layers (NL10). The vertical hole (H10) can be referred to as a 'gate hole' or a 'word line hole'.

[0161] Referring to Fig. 52, a portion of the sacrificial layer (SF10) around the vertical hole (H10) can be recessed to form a recess area (A1). Each recess area (A1) can have a shape surrounding the vertical hole (H10).

[0162] Referring to Fig. 53, a channel material layer (CM10) filling the recessed area (A1) can be formed. After forming a channel material covering the vertical hole (H10) while filling the recessed area (A1) on the laminate (S200), a portion of the channel material other than the portion disposed within the recessed area (A1 of Fig. 42) is removed through an etch-back process or the like, thereby forming a channel material layer (CM10) remaining only in the recessed area (A1).

[0163] A diffusion barrier layer (DB11) covering a vertical hole (H10) can be formed on a laminate (S200). Then, a thermally conductive layer (HC11) can be formed on the diffusion barrier layer (DB11). The diffusion barrier layer (DB11) and the thermally conductive layer (HC11) can be formed by a deposition method. The diffusion barrier layer (DB11) and the thermally conductive layer (HC11) can be formed conformally according to the shape of the upper surface of the laminate (S200) and the surface of the vertical hole (H10). The diffusion barrier layer (DB11) and the thermally conductive layer (HC11) can be formed with a thickness that does not completely fill the vertical hole (H10).

[0164] The diffusion barrier layer (DB11) may serve to prevent the material (e.g., metallic material) of the thermal conductive layer (HC11) from diffusing into the channel material layer (CM10) during a subsequent laser annealing process. For example, the diffusion barrier layer (DB11) may be a layer that prevents the diffusion of the metallic material. As a non-limiting example, the diffusion barrier layer (DB11) may include at least one of silicon nitride and silicon carbide. However, the material of the diffusion barrier layer (DB11) is not limited to the above and may vary. The diffusion barrier layer (DB11) may be an insulating layer, for example, an inorganic insulating layer.

[0165] The heat-conducting layer (HC11) may include, for example, a metallic material. The metallic material may include at least one of a metal, a metal compound, and an alloy. The heat-conducting layer (HC11) may be a material layer capable of increasing heat absorption in a subsequent laser annealing process. The heat-conducting layer (HC11) may be a metallic thin film having a high absorption coefficient for the laser wavelength used. As a non-limiting example, for a laser having a wavelength of 532 nm, the heat-conducting layer (HC11) may include at least one of Au, Ag, W, Ti, Pd, Ni, Mg, Li, and a nitride thereof.

[0166] Referring to FIG. 54, by irradiating a laser to a heat-conducting layer (HC11), annealing can be performed on a channel material layer (CM10) around a vertical hole (H10). Through a laser annealing process of irradiating a laser to the heat-conducting layer (HC11), the channel material layer (CM10) around the vertical hole (H10) can be crystallized, and a crystallized channel material layer (CM10) can be formed. Since the heat-conducting layer (HC11) formed in the vertical hole (H10) can perform an excellent heat-conducting function, a uniform (substantially uniform) laser annealing effect can be obtained for a plurality of channel material layers (CM10) arranged around the vertical hole (H10) and spaced apart in the vertical direction. Therefore, a plurality of channel material layers (CM10) having uniform characteristics can be obtained.

[0167] Through rapid heating by the above laser annealing, the channel material layer (CM10) can be crystallized, and a channel material layer (CM10) having excellent crystal characteristics can be obtained. The channel material layer (CM10) can have a crystalline structure close to a polycrystal or a single crystal, and can advantageously act to secure excellent electrical characteristics such as low leakage current and high carrier mobility. After the above laser annealing, the thermal conductive layer (HC11) and the diffusion barrier layer (DB11) can be removed. However, in some cases, at least a portion of the diffusion barrier layer (DB11) may not be removed.

[0168] FIGS. 55 to 57 are cross-sectional views illustrating a method for manufacturing a three-dimensional memory device according to another embodiment of the present invention. The manufacturing processes of FIGS. 55 to 57 can be commonly applied as a subsequent process to the manufacturing processes of FIGS. 40 to 44, FIGS. 45 to 49, and FIGS. 50 to 54 described above.

[0169] Referring to FIG. 55, reference numeral CL10 denotes a channel layer defined from the channel material layer (CM10) of FIG. 44, FIG. 49, and FIG. 54. In FIG. 44, the remaining portion of the channel material layer (CM10) except for the portion disposed within the recessed area (A1 of FIG. 42) can be removed. In FIG. 49, the remaining portion of the channel material layer (CM10) except for the portion disposed within the recessed area (A1 of FIG. 47) can be removed, and the metallic material layer (ML10) can also be removed. In FIG. 54, the thermal conductive layer (HC11) and the diffusion barrier layer (DB11) can be removed.

[0170] A gate insulating layer (GN10) covering the inner surface of the vertical hole (H10) can be defined. As a non-limiting example, the gate insulating layer (GN10) can be formed using a deposition method such as ALD. The gate insulating layer (GN10) can be formed conformally according to the top surface of the stack (S200) and the surface shape of the vertical hole (H10). The gate insulating layer (GN10) can be formed with a relatively thin thickness. The gate insulating layer (GN10) can include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, and a high-k material. The high-k material can be a material having a higher permittivity than silicon nitride. If at least a portion of the diffusion barrier layer (DB11) in the structure of FIG. 54 is left without being removed, at least a portion of the diffusion barrier layer (DB11) can be used as the gate insulating layer material.

[0171] Next, a word line (WL10) that at least partially fills the vertical hole (H10) can be formed on the gate insulating layer (GN10). The word line (WL10) may be referred to as a 'gate' or a 'gate line'. The word line (WL10) may be formed to fill the vertical hole (H10) on the gate insulating layer (GN10) and may be a vertically extending wiring. If there is a conductive material of the word line (WL10) deposited above the vertical hole (H10) and above the upper surface of the stack (S200), it can be removed, for example, through an etch-back process.

[0172] Referring to FIG. 56, a sacrificial layer (SF10) may be removed from one side of a channel layer (CL10) to expose a first side region of the channel layer (CL10), and a bit line (BL10) electrically connected to the first side region of the channel layer (CL10) may be formed. A source layer (SC10) may be further formed in the first side region of the channel layer (CL10), and then a bit line (BL10) in contact with the source layer (SC10) may be formed. The source layer (SC10) may include an ohmic contact layer. However, formation of the source layer (SC10) and the ohmic contact layer may be optional.

[0173] Referring to FIG. 57, the sacrificial layer (SF10) can be removed from the other side of the channel layer (CL10) to expose a second side region of the channel layer (CL10), and a capacitor (CP10) electrically connected to the second side region of the channel layer (CL10) can be formed.

[0174] The capacitor (CP10) may include a first electrode (EL10) in electrical contact with the second side region of the channel layer (CL10). An insulating material may be removed around the first electrode (EL10), and the first electrode (EL10) may have a shape that protrudes (protrudes laterally) from the second side region of the channel layer (CL10). If necessary, an ohmic contact layer may be further disposed between the first electrode (EL10) and the channel layer (CL10). The ohmic contact layer may be considered to be included in the first electrode (EL10). The use of the ohmic contact layer may be optional.

[0175] The capacitor (CP10) may include a dielectric layer (DL10) arranged to cover the upper surface, lower surface, front surface, rear surface, and side surfaces of the first electrode (EL10). The dielectric layer (DL10) may be arranged to surround the exposed surfaces of the first electrode (EL10). Therefore, the contact area of ​​the dielectric layer (DL10) with respect to the first electrode (EL10) may be significantly increased. In addition, the capacitor (CP10) may include a second electrode (EL20) arranged on the dielectric layer (DL10). The second electrode (EL20) may be commonly applied to a plurality of first electrodes (EL10). A plurality of capacitors (CP10) may be arranged to be electrically connected to the second side regions of the plurality of channel layers (CL10), respectively. The plurality of capacitors (CP10) may be arranged to be adjacent to each other in the vertical direction.

[0176] In FIG. 56 and FIG. 57, the case where the bit line (BL10) is formed first and the capacitor (CP10) is formed later is illustrated and described, but in some cases, the capacitor (CP10) may be formed first and the bit line (BL10) may be formed later.

[0177] FIGS. 58a to 62b are drawings for explaining a channel formation method that can be applied to a method for manufacturing a three-dimensional memory device according to another embodiment of the present invention.

[0178] In FIGS. 58a to 62b, the same drawing numbers (e.g., FIG. 58 in FIGS. 58a and 58b) represent the same steps. FIGS. 58a, 59a, 60a, 61a, and 62a are cross-sectional views taken along the XZ plane. FIGS. 58b, 59b, 60b, 61b, and 62b are cross-sectional views taken along the XY plane. FIG. 58b is a cross-sectional view taken along line A-A' of FIG. 58a, and FIG. 58a is a cross-sectional view taken along line B-B' of FIG. 58b. This relationship is the same in FIGS. 59a to 62b. FIGS. 58a to 62b show a method of forming a channel for a memory array.

[0179] Referring to FIGS. 58a and 58b, a laminate (S200) having a structure in which a sacrificial layer (SF10) and an insulating layer (NL10) are alternately and repeatedly laminated on a substrate (SUB10) can be formed. The laminate (S200) can include a plurality of sacrificial layers (SF10) and a plurality of insulating layers (NL10) that are alternately laminated.

[0180] Referring to FIGS. 59a and 59b, a vertical hole (H10) can be formed in the laminate (S200). A predetermined region of the laminate (S200) can be etched in a vertical direction to form the vertical hole (H10). The vertical hole (H10) can be formed to penetrate a plurality of sacrificial layers (SF10) and a plurality of insulating layers (NL10). The vertical hole (H10) can be formed to penetrate the laminate (S200). The vertical hole (H10) can be a 'gate hole' or a 'word line hole'. A plurality of vertical holes (H10) can be formed to be spaced apart from each other.

[0181] Referring to FIGS. 60a and 60b, a portion of the sacrificial layer (SF10) around the vertical hole (H10) can be recessed to form a recess area (A1). For example, a wet etching solution having an etching selectivity for the sacrificial layer (SF10) relative to the insulating layer (NL10) can be used to recess the portion of the sacrificial layer (SF10) around the vertical hole (H10). Each recess area (A1) can have a shape surrounding the vertical hole (H10).

[0182] Referring to FIGS. 61A and 61B , a channel material layer (CM10) filling at least the recessed region (A1) may be formed. The channel material layer (CM10) may be formed on the stack (S200) to cover the vertical hole (H10) while filling the recessed region (A1). The channel material layer (CM10) may be formed by a deposition method such as CVD or ALD. The channel material layer (CM10) may be formed to a thickness that does not completely fill the vertical hole (H10). The channel material layer (CM10) may include, but is not limited to, at least one of Si, Ge, and SiGe. The channel material layer (CM10) may be, for example, an amorphous layer. Alternatively, the channel material layer (CM10) may be a polycrystalline layer having a relatively low crystallinity. The channel material layer (CM10) may have a doping concentration at a general channel level.

[0183] Referring to FIGS. 62a and 62b, direct or indirect laser annealing can be performed on the channel material layer (CM10). In the present embodiment, annealing can be performed on the channel material layer (CM10) by irradiating the channel material layer (CM10) with a laser. In the laser annealing process, the channel material layer (CM10) can serve as a type of thermal conductive layer. Therefore, portions of the channel material layer (CM10) existing in a plurality of recessed regions (A1 in FIG. 60a) arranged along the longitudinal direction (depth direction) of the vertical hole (H10) can be easily crystallized and can be uniformly (substantially uniformly) crystallized. The entire channel material layer (CM10) can be substantially uniformly crystallized. The channel material layer (CM10) can have a crystalline structure close to a polycrystalline or single crystal. Each channel layer (CL10) can have a structure surrounding the vertical hole (H10). Each channel layer (CL10) may have a rectangular ring shape, a polygonal ring shape, a circular ring shape, an elliptical ring shape, or a similar shape. A plurality of channel layers (CL10) may be arranged vertically spaced apart from each other around each vertical hole (H10).

[0184] FIGS. 63a to 67b are drawings for explaining a channel formation method that can be applied to a method for manufacturing a three-dimensional memory device according to another embodiment of the present invention.

[0185] In FIGS. 63a to 67b, the same drawing numbers (e.g., FIG. 63 in FIGS. 63a and 63b) represent the same steps. FIGS. 63a, 64a, 65a, 66a, and 67a are cross-sectional views taken along the XZ plane. FIGS. 63b, 64b, 65b, 66b, and 67b are cross-sectional views taken along the XY plane. FIG. 63b is a cross-sectional view taken along line A-A' of FIG. 63a, and FIG. 63a is a cross-sectional view taken along line B-B' of FIG. 63b. This relationship is the same in FIGS. 64a to 67b. FIGS. 63a to 67b show a method of forming a channel for a memory array.

[0186] Referring to FIGS. 63a and 63b, a laminate (S200) having a structure in which a sacrificial layer (SF10) and an insulating layer (NL10) are alternately and repeatedly laminated can be formed on a substrate (SUB10). The laminate (S200) can include a plurality of sacrificial layers (SF10) and a plurality of insulating layers (NL10) that are alternately laminated. A metallic material layer (ML10) can be further formed on the laminate (S200).

[0187] Referring to FIGS. 64a and 64b, a vertical hole (H10) can be formed in the laminate (S200). The vertical hole (H10) can be formed in the laminate (S200) by penetrating the metallic material layer (ML10). The vertical hole (H10) can be a 'gate hole' or a 'word line hole'. A plurality of vertical holes (H10) can be formed spaced apart from each other.

[0188] Referring to FIGS. 65a and 65b, a portion of the sacrificial layer (SF10) around the vertical hole (H10) can be recessed to form a recessed area (A1). Each recessed area (A1) can have a shape surrounding the vertical hole (H10).

[0189] Referring to FIGS. 66a and 66b, a channel material layer (CM10) that fills at least the recess area (A1) can be formed. The channel material layer (CM10) can be formed on the metallic material layer (ML10) to cover the vertical hole (H10) while filling the recess area (A1).

[0190] Referring to FIGS. 67a and 67b, direct or indirect laser annealing can be performed on the channel material layer (CM10). In this embodiment, annealing can be performed on the channel material layer (CM10) by irradiating the channel material layer (CM10) with a laser. In the laser annealing process, the channel material layer (CM10) can serve as a type of thermal conductive layer. Therefore, portions of the channel material layer (CM10) existing in a plurality of recessed regions (A1 in FIG. 65a) arranged along the longitudinal direction (depth direction) of the vertical hole (H10) can be easily crystallized and can be uniformly (substantially uniformly) crystallized. The entire channel material layer (CM10) can be substantially uniformly crystallized. The channel material layer (CM10) can have a crystalline structure close to a polycrystalline or single crystal. Each channel layer (CL10) can have a structure surrounding the vertical hole (H10).

[0191] FIGS. 68a to 72b are drawings for explaining a channel formation method that can be applied to a method for manufacturing a three-dimensional memory device according to another embodiment of the present invention.

[0192] In FIGS. 68a to 72b, the same drawing numbers (e.g., FIG. 68 in FIGS. 68a and 68b) indicate the same steps. FIGS. 68a, 69a, 70a, 71a, and 72a are cross-sectional views taken along the XZ plane. FIGS. 68b, 69b, 70b, 71b, and 72b are cross-sectional views taken along the XY plane. FIG. 68b is a cross-sectional view taken along the line A-A' of FIG. 68a, and FIG. 68a is a cross-sectional view taken along the line B-B' of FIG. 68b. This relationship is the same in FIGS. 69a to 72b. FIGS. 68a to 72b show a method of forming a channel for a memory array.

[0193] Referring to FIGS. 68a and 68b, a laminate (S200) having a structure in which a sacrificial layer (SF10) and an insulating layer (NL10) are alternately and repeatedly laminated on a substrate (SUB10) can be formed. This may be the same as described in FIGS. 58a and 58b.

[0194] Referring to FIGS. 69a and 69b, a vertical hole (H10) can be formed in the laminate (S200). The vertical hole (H10) can be formed to penetrate multiple sacrificial layers (SF10) and multiple insulating layers (NL10). The vertical hole (H10) can be referred to as a 'gate hole' or a 'word line hole'. A plurality of vertical holes (H10) can be formed spaced apart from each other.

[0195] Referring to FIGS. 70a and 70b, a portion of the sacrificial layer (SF10) around the vertical hole (H10) can be recessed to form a recessed area (A1). Each recessed area (A1) can have a shape surrounding the vertical hole (H10).

[0196] Referring to FIGS. 71a and 71b, a channel material layer (CM10) filling the recessed area (A1) can be formed. After forming a channel material covering the vertical hole (H10) while filling the recessed area (A1) on the laminate (S200), a portion of the channel material other than the portion disposed within the recessed area (A1 of FIG. 70a) is removed through an etch-back process or the like, thereby forming a channel material layer (CM10) remaining only in the recessed area (A1).

[0197] A diffusion barrier layer (DB11) covering a vertical hole (H10) can be formed on a laminate (S200). Then, a thermally conductive layer (HC11) can be formed on the diffusion barrier layer (DB11). The diffusion barrier layer (DB11) and the thermally conductive layer (HC11) can be formed by a deposition method. The diffusion barrier layer (DB11) and the thermally conductive layer (HC11) can be formed conformally according to the shape of the upper surface of the laminate (S200) and the surface of the vertical hole (H10). The diffusion barrier layer (DB11) and the thermally conductive layer (HC11) can be formed with a thickness that does not completely fill the vertical hole (H10). The diffusion barrier layer (DB11) can be, for example, an insulating layer (inorganic insulating layer). The thermally conductive layer (HC11) can include, for example, a metallic material.

[0198] Referring to FIGS. 72a and 72b, annealing of the channel material layer (CM10) around the vertical hole (H10) can be performed by irradiating a laser onto the heat-conducting layer (HC11). Through the laser annealing process of irradiating a laser onto the heat-conducting layer (HC11), the channel material layer (CM10) around the vertical hole (H10) can be crystallized, and a crystallized channel material layer (CM10) can be formed. The channel material layer (CM10) can have a crystalline structure close to a polycrystal or a single crystal. Each channel material layer (CM10) can have a rectangular ring shape, a polygonal ring shape, a circular ring shape, an elliptical ring shape, or a similar shape. A plurality of channel material layers (CM10) can be arranged to be spaced apart from each other in the vertical direction around each vertical hole (H10).

[0199] FIGS. 73a to 87b are cross-sectional views illustrating a method for manufacturing a three-dimensional memory device according to another embodiment of the present invention. The manufacturing processes of FIGS. 73a to 87b can be commonly applied as a subsequent process to the manufacturing processes of FIGS. 58a to 62b, FIGS. 63a to 67b, and FIGS. 68a to 72b described above.

[0200] In FIGS. 73a to 87b, the same drawing numbers (e.g., FIG. 73 in FIGS. 73a and 73b) indicate the same steps. FIGS. 73a, 74a, 75a, 76a, 77a, 78a, 79a, 80a, 81a, 82a, 83a, 84a, 85a, 86a, and 87a are cross-sectional views taken along the XZ plane. FIGS. 73b, 74b, 75b, 76b, 77b, 78b, 79b, 80b, 81b, 82b, 83b, 84b, 85b, 86b, and 87b are cross-sectional views taken along the XY plane. Figure 73b is a cross-sectional view taken along line A-A' of Figure 73a, and Figure 73a is a cross-sectional view taken along line B-B' of Figure 73b. These relationships are the same in Figures 74a to 87b. Figures 73a to 87b illustrate a method for manufacturing a three-dimensional memory array.

[0201] Referring to FIGS. 73a and 73b, reference numeral CL10 denotes a channel layer defined from the channel material layer (CM10) of FIGS. 62a, 67a, and 72a. In FIG. 62a, the remaining portion of the channel material layer (CM10) except for the portion disposed within the recessed area (A1 of FIG. 60a) can be removed. In FIG. 67a, the remaining portion of the channel material layer (CM10) except for the portion disposed within the recessed area (A1 of FIG. 65a) can be removed, and the metallic material layer (ML10) can also be removed. In FIG. 72a, the thermal conductive layer (HC11) and the diffusion barrier layer (DB11) can be removed.

[0202] Referring to FIGS. 74a and 74b, a gate insulating layer (GN10) covering the inner surface of the vertical hole (H10) can be defined. As a non-limiting example, the gate insulating layer (GN10) can be formed using a deposition method such as ALD. The gate insulating layer (GN10) can be formed conformally according to the upper surface of the stack (S200) and the surface shape of the vertical hole (H10). The gate insulating layer (GN10) can be formed with a relatively thin thickness. If at least a portion of the diffusion barrier layer (DB11) in the structure of FIG. 72a is left without being removed, at least a portion of the diffusion barrier layer (DB11) can be used as a gate insulating layer material.

[0203] Referring to FIGS. 75a and 75b, a word line (WL10) that at least partially fills a vertical hole (H10) may be formed on a gate insulating layer (GN10). The word line (WL10) may be referred to as a 'gate' or a 'gate line'. The word line (WL10) may be formed to fill the vertical hole (H10) on the gate insulating layer (GN10) and may be a vertically extending wiring. If there is a conductive material of the word line (WL10) deposited above the vertical hole (H10) and above the upper surface of the stack (S200), it may be removed, for example, through an etch-back process.

[0204] Referring to FIGS. 76a and 76b, an etched portion (EP10) can be formed by etching a portion of the laminate (S200) to expose both sides of the channel layer (CL10). The etched portion (EP10) can be formed by etching a portion of the sacrificial layer (SF10) present on both sides of the channel layer (CL10) in the Y-axis direction (second direction). Alternatively, the etched portion (EP10) can be formed by etching a portion of the sacrificial layer (SF10) and a portion of the insulating layer (NL10) present on both sides of the channel layer (CL10) in the Y-axis direction (second direction).

[0205] Referring to FIGS. 77a and 77b, an insulating material (NM10) may be filled into the etched portion (EP10). The insulating material (NM10) may be referred to as a filled insulating layer. The insulating material (NM10) may include at least one of various insulating materials.

[0206] Referring to FIGS. 78a and 78b, a first trench (T10) may be formed by etching a portion of the laminate (S200). The first trench (T10) may be formed between two channel layers (CL10) spaced apart in the X-axis direction (first direction). The first trench (T10) may be formed to penetrate the laminate (S200). In addition, the first trench (T10) may have a shape (e.g., a line shape) extending in the Y-axis direction (second direction). Here, the second direction may be a direction perpendicular to the first direction.

[0207] Referring to FIGS. 79a and 79b, a first recess portion (R1) exposing a first side region of a channel layer (CL10) may be formed by removing a portion of a sacrificial layer (SF10) exposed by a first trench (T10). The first side region may be any one region among double-sided regions along the X-axis direction (first direction) of the channel layer (CL10). Then, a source layer (SC10) in contact with the first side region of the channel layer (CL10) may be formed. The source layer (SC10) may be a conductive material layer. The source layer (SC10) may include an ohmic contact layer. However, formation of the source layer (SC10) and the ohmic contact layer may be optional.

[0208] Referring to FIGS. 80A and 80B, a bit line (BL10) may be formed within the first recess portion (R1). For example, after forming a material layer for a bit line that fills the first recess portion (R1) and the first trench (T10), a portion of the material layer for a bit line disposed in the first trench (T10) may be removed to form the bit line (BL10). The bit line (BL10) may have a shape extending in the Y-axis direction (second direction). The bit line (BL10) may be electrically connected to the first side region of the channel layer (CL10).

[0209] Referring to FIGS. 81a and 81b, a separator (SN10) filling the first trench (T10) can be formed. The separator (SN10) may be an insulating material layer. The separator (SN10) may serve to separate cells in a horizontal direction.

[0210] Referring to FIGS. 82a and 82b, a second trench (T20) may be formed by etching a portion of the stack (S200). The second trench (T20) may be formed in a capacitor formation region (a capacitor formation region). The second trench (T20) may be formed by etching a portion of the stack (S200) on the opposite side of the bit line (BL10). The second trench (T20) may be formed to penetrate the stack (S200) and may have a shape (e.g., a line shape) extending in the Y-axis direction (the second direction).

[0211] Referring to FIGS. 83a and 83b, a second recess portion (R2) exposing a second side region of the channel layer (CL10) may be formed by removing a portion of the sacrificial layer (SF10) exposed by the second trench (T20). The second side region may be an opposite region of the first side region. The first side region and the second side region may be opposite side regions of the channel layer (CL10) in the X-axis direction (first direction).

[0212] Referring to FIGS. 84a and 84b, a first electrode (EL10) for a capacitor may be formed within the second recess portion (R2). If necessary, an ohmic contact layer may be formed between the first electrode (EL10) and the channel layer (CL10). The ohmic contact layer may be considered to be included in the first electrode (EL10). The use of the ohmic contact layer may be optional.

[0213] Referring to FIGS. 85a and 85b, the insulating material around the first electrode (EL10) can be removed to expose the surface of the first electrode (EL10). The insulating layer (NL10) portions disposed above and below the first electrode (EL10) can be removed, and further, the insulating material (NM10) portions disposed before and after the first electrode (EL10) can be removed. Accordingly, the upper surface, lower surface, front surface, and rear surface of the first electrode (EL10) can be exposed. Since the side surface (outer side surface) of the first electrode (EL10) may already be exposed, the upper surface (upper surface portion), lower surface (lower surface portion), front surface (front surface portion), rear surface (rear surface portion), and side surface (side surface) of the first electrode (EL10) can be exposed.

[0214] Referring to FIGS. 86a and 86b, a dielectric layer (DL10) for a capacitor may be formed on an exposed surface of a first electrode (EL10). The dielectric layer (DL10) may be formed to cover the upper surface, lower surface, front surface, rear surface, and side surface of the first electrode (EL10). The dielectric layer (DL10) may be arranged to surround the exposed surfaces of the first electrode (EL10). Accordingly, the contact area of ​​the dielectric layer (DL10) with respect to the first electrode (EL10) may be significantly increased. The dielectric layer (DL10) may be formed by a deposition process such as ALD. The dielectric layer (DL10) may be conformally formed on a target surface with a relatively thin thickness.

[0215] Referring to FIGS. 87a and 87b, a second electrode (EL20) for a capacitor may be formed on a dielectric layer (DL10). The second electrode (EL20) may be commonly applied to a plurality of first electrodes (EL10) as a common electrode. The second electrode (EL20) may be formed to fill the second trench (T20 of FIG. 84a). The first electrode (EL10), the dielectric layer (DL10), and the second electrode (EL20) may constitute a capacitor (CP10). A plurality of capacitors (CP10) may be arranged to be electrically connected to the second side regions of the plurality of channel layers (CL10), respectively. The plurality of capacitors (CP10) may be arranged to be adjacent to each other in a vertical direction.

[0216] In the embodiments of FIGS. 73a to 87b, the case where the bit line (BL10) is formed first and the capacitor (CP10) is formed later is illustrated and described, but in some cases, the capacitor (CP10) may be formed first and the bit line (BL10) may be formed later.

[0217] A three-dimensional memory device according to an embodiment of the present invention may have structural features as illustrated in FIGS. 87a and 87b. The three-dimensional memory device according to the embodiment illustrated in FIGS. 87a and 87b may have the same or nearly the same structure and features as the three-dimensional memory device described above with reference to FIGS. 39a and 39b.

[0218] According to the embodiments of the present invention described above, by suggesting a method for performing local annealing (heat treatment) in a desired area in a short period of time and ensuring uniformity of annealing characteristics according to the position (position in the vertical direction), a three-dimensional memory device having high integration and excellent performance and uniformity can be implemented (manufactured). In addition, according to the embodiments of the present invention, by making a predetermined semiconductor layer into a crystal quality close to a polycrystalline or single crystal through a given method of laser annealing, a three-dimensional memory device having excellent electrical characteristics such as low leakage current and high carrier mobility can be implemented. In addition, according to the embodiments of the present invention, a three-dimensional memory device having high integration, excellent performance and uniformity, and ease of process can be implemented. The three-dimensional memory device may be a DRAM device.

[0219] In one embodiment, when manufacturing a three-dimensional memory device, it may be possible to crystallize semiconductor materials in channel regions to a similar level in a short period of time, regardless of their position in the vertical direction (i.e., in the depth direction), by utilizing a laser. In one embodiment, a heat-conducting layer having high thermal conductivity may be used in laser annealing, and the heat-conducting layer may serve to transfer heat received through the laser in the extension direction of a vertical hole (gate hole), and as a result, similar annealing characteristics may be secured for a plurality of semiconductor regions in the vertical direction. A semiconductor material for forming a channel of a three-dimensional memory device may be positioned perpendicular to the vertical hole in a region adjacent to the vertical hole (gate hole), and a high level of crystallization of the semiconductor material may be possible. Therefore, it may be possible to minimize the number of grain boundaries in the channel layer and maximize the size of the grains. Therefore, the effect of high-energy laser annealing can be secured regardless of the position in the depth direction in a 3D memory device, and as a result, the electrical characteristics of the 3D memory device can be improved by minimizing the number of crystal grain boundaries and maximizing the crystal grain size.

[0220] In this specification, preferred embodiments of the present invention have been disclosed, and although specific terms have been used, they have been used in a general sense only to easily explain the technical contents of the present invention and to help the understanding of the invention, and are not intended to limit the scope of the present invention. It will be apparent to those skilled in the art that other modifications based on the technical idea of ​​the present invention can be implemented in addition to the embodiments disclosed herein. Those skilled in the art will appreciate that the three-dimensional memory device and the manufacturing method thereof according to the embodiments described with reference to FIGS. 1 to 87b can be variously substituted, changed, and modified without departing from the technical idea of ​​the present invention. Therefore, the scope of the invention should not be defined by the described embodiments, but by the technical idea described in the claims.

[0221] The present invention relates to a three-dimensional memory device and a manufacturing method thereof. When manufacturing a three-dimensional memory device, a laser can be easily utilized to crystallize semiconductor materials in channel regions to a similar level in a short period of time, regardless of the position in the vertical direction (i.e., depth direction).

Claims

1. A step of forming a laminate having a structure in which semiconductor layers and insulating layers are alternately and repeatedly laminated on a substrate; A step of forming a vertical hole in the above laminate; A step of forming a heat-conducting layer covering the vertical hole on the laminate; A step of irradiating a laser onto the heat-conducting layer to perform annealing on a portion of the semiconductor layer around the vertical hole, thereby forming a channel layer from the portion of the semiconductor layer; A step of removing the above thermal conductive layer; A step of defining a gate insulating layer covering the inner surface of the vertical hole; A step of forming a word line that at least partially fills the vertical hole on the gate insulating layer; A step of removing the semiconductor layer from one side of the channel layer to expose a first side region of the channel layer and forming a bit line electrically connected to the first side region of the channel layer; and A method for manufacturing a three-dimensional memory device, comprising the step of removing the semiconductor layer from the other side of the channel layer to expose a second side region of the channel layer, and forming a capacitor electrically connected to the second side region of the channel layer.

2. In paragraph 1, A method for manufacturing a three-dimensional memory device, wherein the above thermally conductive layer comprises doped polycrystalline silicon.

3. In paragraph 1, A metallic material layer is further formed on the above laminate, The above vertical hole is formed in the laminate by penetrating the metallic material layer, A method for manufacturing a three-dimensional memory device, wherein the thermally conductive layer covering the vertical hole is formed on the metallic material layer.

4. In paragraph 1, After the step of forming a vertical hole in the laminate, the step of forming a diffusion barrier layer covering the vertical hole on the laminate is further included. A method for manufacturing a three-dimensional memory element, wherein the above thermally conductive layer is formed on the above diffusion barrier layer.

5. In paragraph 4, A method for manufacturing a three-dimensional memory device, wherein the above thermal conductive layer includes a metallic material.

6. In the first paragraph, after the step of forming the word line, A step of etching a part of the laminate to form an etched portion exposing both sides of the channel layer; and A method for manufacturing a three-dimensional memory device further comprising a step of filling an insulating material into the etched portion.

7. In the first paragraph, the step of forming the bit line comprises: A step of etching a portion of the above laminate to form a first trench; A step of forming a first recess portion that exposes the first side region of the channel layer by removing the portion of the semiconductor layer exposed by the first trench; and A method for manufacturing a three-dimensional memory device, comprising the step of forming the bit line within the first recess portion.

8. In the first paragraph, the step of forming the capacitor comprises: A step of etching a portion of the above laminate to form a second trench; A step of forming a second recess portion that exposes the second side region of the channel layer by removing a portion of the semiconductor layer exposed by the second trench; A step of forming a first electrode for a capacitor within the second recess portion; A step of removing an insulating material around the first electrode to expose the surface of the first electrode; A step of forming a dielectric layer for a capacitor on the exposed surface of the first electrode; and A method for manufacturing a three-dimensional memory device, comprising the step of forming a second electrode for a capacitor on the dielectric layer for the capacitor.

9. A step of forming a laminate having a structure in which a sacrificial layer and an insulating layer are alternately and repeatedly laminated on a substrate; A step of forming a vertical hole in the above laminate; A step of forming a recessed area by recessing a portion of the sacrificial layer around the vertical hole; A step of forming a channel material layer that fills at least the recessed area; A step of performing direct or indirect laser annealing on the channel material layer and defining a channel layer disposed in the recess region from the channel material layer; A step of defining a gate insulating layer covering the inner surface of the vertical hole; A step of forming a word line that at least partially fills the vertical hole on the gate insulating layer; A step of removing the sacrificial layer from one side of the channel layer to expose a first side region of the channel layer and forming a bit line electrically connected to the first side region of the channel layer; and A method for manufacturing a three-dimensional memory device, comprising the step of removing the sacrificial layer from the other side of the channel layer to expose a second side region of the channel layer, and forming a capacitor electrically connected to the second side region of the channel layer.

10. In paragraph 9, The channel material layer is formed to cover the vertical hole while filling the recessed area on the laminate, A method for manufacturing a three-dimensional memory device, wherein after the laser annealing, the remaining portion of the channel material layer except for the portion positioned within the recess region is removed.

11. In paragraph 9, A metallic material layer is further formed on the above laminate, The above vertical hole is formed in the laminate by penetrating the metallic material layer, The channel material layer is formed to cover the vertical hole while filling the recess area on the metallic material layer, A method for manufacturing a three-dimensional memory device, wherein after the laser annealing, the remaining portion of the channel material layer except for the portion positioned within the recess region is removed.

12. In paragraph 9, The above channel material layer is formed to fill the recess area, A method for manufacturing a three-dimensional memory device, further comprising: forming a diffusion barrier layer covering the vertical hole on the laminate; and forming a thermally conductive layer on the diffusion barrier layer.

13. In paragraph 12, A method for manufacturing a three-dimensional memory device, wherein the above thermal conductive layer includes a metallic material.

14. In the 9th paragraph, after the step of forming the word line, A step of etching a part of the laminate to form an etched portion exposing both sides of the channel layer; and A method for manufacturing a three-dimensional memory device further comprising a step of filling an insulating material into the etched portion.

15. In the 9th paragraph, the step of forming the bit line comprises: A step of etching a portion of the above laminate to form a first trench; A step of forming a first recess portion that exposes the first side region of the channel layer by removing the portion of the sacrificial layer exposed by the first trench; and A method for manufacturing a three-dimensional memory device, comprising the step of forming the bit line within the first recess portion.

16. In the 9th paragraph, the step of forming the capacitor comprises: A step of etching a portion of the above laminate to form a second trench; A step of forming a second recess portion that exposes the second side region of the channel layer by removing the portion of the sacrificial layer exposed by the second trench; A step of forming a first electrode for a capacitor within the second recess portion; A step of removing an insulating material around the first electrode to expose the surface of the first electrode; A step of forming a dielectric layer for a capacitor on the exposed surface of the first electrode; and A method for manufacturing a three-dimensional memory device, comprising the step of forming a second electrode for a capacitor on the dielectric layer for the capacitor.

17. Word lines extending vertically; A plurality of channel layers having a shape surrounding the word line and spaced apart from each other in the vertical direction; A plurality of bit lines electrically connected to the first side region of the plurality of channel layers and extending in a horizontal direction; A plurality of capacitors each electrically connected to a second side region of the plurality of channel layers and arranged vertically adjacent to each other; and A three-dimensional memory device comprising an insulating layer disposed between the plurality of channel layers.

18. In the 17th paragraph, the capacitor, A first electrode electrically contacting the second side region of the channel layer and having a shape protruding from the second side region; A dielectric layer arranged to cover the upper surface, lower surface, front surface, rear surface and side surface of the first electrode; A three-dimensional memory device comprising a second electrode disposed on the dielectric layer.

19. In paragraph 17, The above word lines are arranged within the vertical holes of the laminate, A three-dimensional memory device in which a gate insulating layer is disposed between the inner surface of the vertical hole and the word line.

20. In paragraph 17, The word line, the plurality of channel layers, the plurality of bit lines, and the plurality of capacitors constitute one first memory stack, A second memory stack is provided that is horizontally spaced from the first memory stack, A three-dimensional memory device in which the first memory stack and the second memory stack have a mutually symmetrical structure based on a separator provided between them.

21. In paragraph 20, The channel layer of the first memory stack is disposed between the separator and the capacitor of the first memory stack, A three-dimensional memory device in which the bit line of the first memory stack is arranged between the separator and the channel layer of the first memory stack.

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