Transistor and method for manufacturing same

Abstract

A transistor comprising an epi layer formed within a substrate. A first dopant layer formed within the epi layer. A plurality of second dopant layers formed within a recessed portion and the protruding portion of the first dopant layer. A plurality of third dopant layers formed within the protruding portion of the first dopant layer. A fourth dopant layer formed within the protruding portion of the first dopant layer. A plurality of gate contacts operatively connected to the respective second dopant layer. A source contact operatively connected to the plurality of third dopant layers and the fourth dopant layer.

Description

INTERNATIONAL PCT PATENT APPLICATIONATTORNEY DOCKET NO.: 0026725.0000329TRANSISTOR AND METHOD FOR MANUFACTURING SAMECROSS-REFERENCE TO RELATED APPLICATION

[0001] The present application claims priority to U.S. Non-Provisional Patent Application No. 19 / 057,792, filed February 19, 2025, and U.S. Provisional Patent Application No. 63 / 687,043 filed on August 26, 2024, the contents of which are hereby incorporated by reference in their entirety.TECHNICAL FIELD

[0002] The present disclosure relates generally to transistors, and more specifically to Junction Field Effect Transistors and methods for manufacturing same to improve the performance of the transistor.SUMMARY

[0003] According to an aspect of one or more examples, there is provided a transistor that may include a substrate, an epi layer formed within the substrate, a first dopant layer formed within the epi layer, the first dopant layer may have a recessed portion and a protruding portion, a plurality of second dopant layers formed within the recessed portion of the first dopant layer and formed within the protruding portion of the first dopant layer, a plurality of third dopant layers formed within the protruding portion of the first dopant layer, a fourth dopant layer formed within the protruding portion of the first dopant layer, a plurality of gate contacts operatively connected to the respective second dopant layer, and a source contact operatively connected to the plurality of third dopant layers and the fourth dopant layer. The substrate may comprise a first concentration of a first type dopant. The epi layer may comprise a second concentration of the first type dopant.The first concentration may be greater than the second concentration. The first dopant layer may comprise a third concentration of the first type dopant. The plurality of second dopant layers may160251968 v1INTERNATIONAL PCT PATENT APPLICATIONATTORNEY DOCKET NO.: 0026725.0000329 comprise a fourth concentration of a second type dopant. The plurality of third dopant layers may comprise a fifth concentration of the first type dopant. The fourth dopant layer may comprise a sixth concentration of the second type dopant. The first type dopant may comprise an n-type dopant and the second type dopant may comprise a p-type dopant. The first type dopant may comprise a p-type dopant and the second type dopant may comprise an n-type dopant.

[0004] According to an aspect of one or more examples, there is provided method of manufacturing a transistor. The method may include providing a substrate, forming an epi layer within the substrate, implanting a first dopant layer into the epi layer, forming a recessed portion and a protruding portion in the first dopant layer, implanting a plurality of second dopant layers into the recessed portion of the first dopant layer and into the protruding portion of the first dopant layer, implanting a plurality of third dopant layers into the protruding portion of the first dopant layer, implanting a fourth dopant layer into the protruding portion of the first dopant layer, forming a plurality of gate contacts operatively connected to the respective second dopant layer; and forming a source contact operatively connected to the plurality of third dopant layers and the fourth dopant layer. The substrate may comprise a first concentration of a first type dopant. The epi layer may comprise a second concentration of the first type dopant. The first concentration may be greater than the second concentration. The first dopant layer may comprise a third concentration of the first type dopant. The plurality of second dopant layers may comprise a fourth concentration of a second type dopant. The plurality of third dopant layers may comprise a fifth concentration of the first type dopant. The fourth dopant layer may comprise a sixth concentration of the second type dopant. The first type dopant may comprise an n-type dopant and the second type dopant may comprise a p-type dopant. The first type dopant may comprise a p-type dopant and the second type dopant may comprise an n-type dopant.260251968 v1INTERNATIONAL PCT PATENT APPLICATIONATTORNEY DOCKET NO.: 0026725.0000329BRIEF DESCRIPTION OF DRAWINGS

[0005] FIG. 1 shows an illustration of a transistor according to one or more examples.

[0006] FIG. 2A is a cross sectional view of some of the steps in a method of manufacturing a transistor according to one or more examples.

[0007] FIG. 2B is a cross sectional view of some of the steps in a method of manufacturing a transistor according to one or more examples.

[0008] FIG. 2C is a cross sectional view of some of the steps in a method of manufacturing a transistor according to one or more examples.

[0009] FIG. 2D is a cross sectional view of some of the steps in a method of manufacturing a transistor according to one or more examples.DETAILED DESCRIPTION OF VARIOUS EXAMPLES

[0010] Reference will now be made in detail to the following various examples, which are illustrated in the accompanying drawings, wherein like reference numerals refer to like elements throughout. The following examples may be in various forms without being limited to the examples set forth herein.

[0011] FIG. 1 shows an illustration of a transistor 10 according to one or more examples.Transistor 10 may represent, and may be called a junction field-effect transistor, without limitation. The example transistor 10 (junction field-effect transistor) of FIG. 1 includes a substrate 20. The substrate 20 shown in FIG. 1 may have a first concentration of a first type dopant, e.g., 5E18 (i.e. 5 x 1018). A drain contact 25 may be formed at a first side of the substrate 20. The example transistor 10 (junction field-effect transistor) of FIG. 1 may include an epi layer 30 formed within the substrate 20 at a second side of the substrate 20. The second360251968 v1INTERNATIONAL PCT PATENT APPLICATIONATTORNEY DOCKET NO.: 0026725.0000329 side of the substrate 20 is opposite the first side of the substrate 20 where the drain contact 25 was formed. The epi layer 30 may comprise a second concentration of the first type dopant, wherein the first concentration of first type dopant in the substrate 20 is greater than the second concentration of first type dopant in the epi layer 30. The example transistor 10 (junction fieldeffect transistor) of FIG. 1 may include a first dopant layer 40 formed within the epi layer 30. The first dopant layer 40 may have a recessed portion 44 and a protruding portion 46. The first dopant layer 40 may comprise a third concentration of the first type dopant. The example transistor 10 (junction field-effect transistor) of FIG. 1 may include a plurality of second dopant layers 50 formed within the recessed portion 44 of the first dopant layer 40 and formed within the protruding portion 46 of the first dopant layer 40. The plurality of second dopant layers 50 may comprise a fourth concentration of a second type dopant that may have a peak doping in the range 1E17 to 5E18. The example transistor 10 (junction field-effect transistor) of FIG. 1 may include a plurality of third dopant layers 60 formed within the protruding portion 46 of the first dopant layer 40. The plurality of third dopant layers 60 may comprise a fifth concentration of the first type dopant (the fifth concentration of first type dopant is greater than the first concentration of first type dopant). The example transistor 10 (junction field-effect transistor) of FIG. 1 may include a fourth dopant layer 70 within the protruding portion 46 of the first dopant layer 40. The fourth dopant layer 70 may comprise a sixth concentration of the second type dopant. The example transistor 10 (junction field-effect transistor) of FIG. 1 may include a plurality of gate contacts 80 operatively connected to the respective second dopant layer 50. The plurality of gate contacts 80 may be made from a metal, polysilicon, or other suitable material. The example transistor 10 (junction field-effect transistor) of FIG. 1 may include a source contact 90 operatively connected to the plurality of third dopant layers 60 and the fourth dopant460251968 v1INTERNATIONAL PCT PATENT APPLICATIONATTORNEY DOCKET NO.: 0026725.0000329 layer 70. The source contact 90 may be made from a metal, polysilicon, or other suitable material. When a gate-to-source voltage is applied to the transistor 10 (junction field-effect transistor) of FIG. 1, current flows through a channel created between the plurality of second dopants 50 from the source contact 90 to the drain contact 25, thereby creating a shielded source 90.

[0012] In one example of the example transistor 10 (junction field-effect transistor) of FIG. 1, the first type dopant may be an n-type dopant and the second type dopant may be a p- type dopant. In another example of the example transistor 10 (junction field-effect transistor) of FIG. 1, the first type dopant may be a p-type dopant and the second type dopant may be an n- type dopant.

[0013] FIGS. 2A-2D show a method of manufacturing transistor 10 according to one or more examples. Although the example method shown in FIGS. 2A-2D include steps shown in a particular order, the steps may be performed in a different order, and may include additional steps that are not explicitly shown.

[0014] FIG. 2A is a cross sectional view of some of the steps in a method of manufacturing a transistor 10 according to one or more examples. Transistor 10 may represent, and may be called a junction field-effect transistor, without limitation. In FIG. 2A, the example method shows a substrate 20 that may have a first concentration of a first type dopant, e.g., 5E18 (i.e. 5 x 1018). In FIG. 2A, the method may include forming an epi layer 30 within the substrate 20. The epi layer 30 may comprise a second concentration of the first type dopant, wherein the first concentration of first type dopant in the substrate 20 is greater than the second concentration of first type dopant in the epi layer 30.560251968 v1INTERNATIONAL PCT PATENT APPLICATIONATTORNEY DOCKET NO.: 0026725.0000329

[0015] FIG. 2B is a cross sectional view of some of the steps in a method of manufacturing a transistor 10 according to one or more examples. In FIG. 2B, the method may include implanting a first dopant layer 40 into the epi layer 30.

[0016] FIG. 2C is a cross sectional view of some of the steps in a method of manufacturing a transistor 10 according to one or more examples. In the method step shown in FIG. 2C, the method may include forming a recessed portion 44 and a protruding portion 46 in the first dopant layer 40.

[0017] FIG. 2D is a cross sectional view of some of the steps in a method of manufacturing a transistor 10 according to one or more examples. In FIG. 2D, the method may include implanting a plurality of second dopant layers 50 into recessed portion 44 of the first dopant layer 40 and into the protruding portion 46 of the first dopant layer 40. The method may include implanting a plurality of third dopant layers 60 into the protruding portion 46 of the first dopant layer 40. The plurality of third dopant layers 60 may have a fifth concentration of the first type dopant (the fifth concentration of first type dopant is greater than the first concentration of first type dopant). The method may include implanting a fourth dopant layer 70 into the protruding portion 46 of the first dopant layer 40. The fourth dopant layer 70 may have a sixth concentration of the second type dopant. In FIG. 2D, the method may include forming a plurality of gate contacts 80 operatively connected to the respective second dopant layer 50. The plurality of gate contacts 80 may be made from a metal, polysilicon, or other suitable material. In FIG. 2D, the method may include forming a source contact 90 operatively connected to the plurality of third dopant layers 60 and the fourth dopant layer 70. The source contact 90 may be made from a metal, polysilicon, or other suitable material. In FIG. 2D, the method may include forming a drain contact 25 on the opposite side of the substrate 20 to the epi layer 30. The drain660251968 v1INTERNATIONAL PCT PATENT APPLICATIONATTORNEY DOCKET NO.: 0026725.0000329 contact 25 may be made from a metal, poly silicon, or other suitable material. When a gate-to- source voltage is applied to the transistor 10 (junction field-effect transistor) of FIG. 2D, current flows through a channel created between the plurality of second dopants 50 from the source contact 90 to the drain contact 25, thereby creating a shielded source 60.

[0018] The example method of manufacturing transistor 10 of FIGS. 2A-2D may have the first type dopant be an n-type dopant with the second type dopant being a p-type dopant. Alternatively, the first type dopant may be a p-type dopant with the second type dopant being an n-type dopant.

[0019] Various examples have been disclosed herein, in connection with the above description and the drawings. It will be understood that it would be unduly repetitious to literally describe and illustrate every combination and subcombination of these examples. Accordingly, all examples may be combined in any way and / or combination, and the present specification, including the drawings, shall be construed to constitute a complete written description of all combinations and subcombinations of the examples described herein, and of the manner and process of making and using them, and shall support claims to any such combination or subcombination.

[0020] It will be appreciated by persons skilled in the art that the examples described herein are not limited to what has been particularly shown and described herein above. In addition, unless mention was made above to the contrary, it should be noted that all of the accompanying drawings are not to scale. A variety of modifications and variations are possible in light of the above teachings.760251968 v1

Claims

INTERNATIONAL PCT PATENT APPLICATIONATTORNEY DOCKET NO.: 0026725.0000329What is claimed is:

1. A transistor comprising: a substrate; an epi layer formed within the substrate; a first dopant layer formed within the epi layer, the first dopant layer having a recessed portion and a protruding portion; a plurality of second dopant layers formed within the recessed portion of the first dopant layer and formed within the protruding portion of the first dopant layer; a plurality of third dopant layers formed within the protruding portion of the first dopant layer; a fourth dopant layer formed within the protruding portion of the first dopant layer; a plurality of gate contacts operatively connected to the respective second dopant layer; and a source contact operatively connected to the plurality of third dopant layers and the fourth dopant layer.

2. The transistor of claim 1, wherein the substrate comprises a first concentration of a first type dopant.

3. The transistor of claim 2, wherein the epi layer comprises a second concentration of the first type dopant, the first concentration greater than the second concentration.

4. The transistor of claim 3, wherein the first dopant layer comprises a third concentration of the first type dopant.860251968 v1INTERNATIONAL PCT PATENT APPLICATIONATTORNEY DOCKET NO.: 0026725.00003295. The transistor of claim 4, wherein the plurality of second dopant layers comprises a fourth concentration of a second type dopant.

6. The transistor of claim 5, wherein the plurality of third dopant layers comprises a fifth concentration of the first type dopant.

7. The transistor of claim 6, wherein the fourth dopant layer comprises a sixth concentration of the second type dopant.

8. The transistor of claim 7, wherein the first type dopant comprises an n-type dopant and the second type dopant comprises a p-type dopant.

9. The transistor of claim 7, wherein the first type dopant comprises a p-type dopant and the second type dopant comprises an n-type dopant.

10. A method of manufacturing a transistor, the method comprising: providing a substrate; forming an epi layer within the substrate; implanting a first dopant layer into the epi layer; forming a recessed portion and a protruding portion in the first dopant layer; implanting a plurality of second dopant layers into the recessed portion of the first dopant layer and into the protruding portion of the first dopant layer; implanting a plurality of third dopant layers into the protruding portion of the first dopant layer; implanting a fourth dopant layer into the protruding portion of the first dopant layer;960251968 v1INTERNATIONAL PCT PATENT APPLICATIONATTORNEY DOCKET NO.: 0026725.0000329 forming a plurality of gate contacts operatively connected to the respective second dopant layer; and forming a source contact operatively connected to the plurality of third dopant layers and the fourth dopant layer.

11. The method of claim 10, wherein the substrate comprises a first concentration of a first type dopant.

12. The method of claim 11, wherein the epi layer comprises a second concentration of the first type dopant, the first concentration greater than the second concentration.

13. The method of claim 12, wherein the first dopant layer comprises a third concentration of the first type dopant.

14. The method of claim 13, wherein the plurality of second dopant layers comprises a fourth concentration of a second type dopant.

15. The method of claim 14, wherein the plurality of third dopant layers comprises a fifth concentration of the first type dopant.

16. The method of claim 15, wherein the gate implant layer comprises a sixth concentration of the second type dopant.

17. The method of claim 16, wherein the first type dopant comprises an n-type dopant and the second type dopant comprises a p-type dopant.

18. The method of claim 16, wherein the first type dopant comprises a p-type dopant and the second type dopant comprises an n-type dopant.1060251968 v1

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