Heterojunction photovoltaic cell and method of making the same

Abstract

A heterojunction photovoltaic cell including (a) a doped semiconductor substrate including a front surface, a rear surface, and an edge, (b) a front intrinsic semiconductor layer and a rear intrinsic semiconductor layer encapsulating the doped semiconductor substrate, (c) a rear doped semiconductor layer disposed (i) over the at least one rear intrinsic semiconductor layer facing the rear surface of the doped semiconductor substrate and (ii) over the at least one rear intrinsic semiconductor layer facing the edge of the doped semiconductor substrate, and (d) a front doped semiconductor layer disposed (i) over the at least one front intrinsic semiconductor layer facing the front surface of the doped semiconductor substrate and (ii) over the at least one rear doped semiconductor layer facing the edge of the doped semiconductor substrate. The doped semiconductor substrate and the at least one front doped semiconductor layer are doped with dopants of the same conductivity type.

Description

Attorney Docket No. SP24-158PCTHETEROJUNCTION PHOTOVOLTAIC CELL AND METHOD OF MAKING THE SAMECROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims the benefit of priority under 35 U.S.C. § 119 of U.S. Provisional Application No. 63 / 688,373 filed August 29, 2024, the content of which is incorporated herein by reference in its entirety.TECHNICAL FIELD

[0002] The present disclosure pertains to heterojunction photovoltaic cells and methods of making the same.BACKGROUND

[0003] A photovoltaic cell, when integrated into an electrical circuit, uses energy from Sun- originated photons to generate electrical current. The photovoltaic cell is sometimes of the heterojunction variety. With a heterojunction photovoltaic cell, the photovoltaic cell sometimes includes a doped semiconductor substrate presenting a front surface and a back surface, front and back intrinsic semiconductor layers over both the front and back surfaces, front and back doped semiconductor layers over the front and back intrinsic semiconductor layers, front and back transparent conduction layers over the front and back doped semiconductor layers, and front and back contacts on the front and back transparent conduction layers.

[0004] Those layers over the semiconductor substrate are sometimes added via chemical vapor deposition processes. The order in which the layers are added to the semiconductor substrate affects the shunt resistance and the reverse saturation current that the photovoltaic cell generates, because the chemical vapor deposition process utilized to form any given layer overlaps the previously added layer at an edge of the semiconductor substrate.

[0005] A historical method of depositing those layers involved turning the semiconductor substrate over only one time during the deposition process. More specifically, assuming the semiconductor substrate is n-doped, the at least one front intrinsic semiconductor layer is deposited over the front surface of the doped semiconductor substrate, and then the at least one front doped semiconductor layer (n-doped) is deposited over the at least one front intrinsic semiconductor layer. Then the semiconductor substrate is flipped over. After flipping, the at least one rear intrinsic semiconductor layer is deposited onto the rear surface of the dopedAttorney Docket No. SP24-158PCT semiconductor substrate, and then the at least one rear doped semiconductor layer (p-doped) is deposited over the at least one rear intrinsic semiconductor layer.

[0006] The resulting heterojunction photovoltaic cell produced by this “one flip” historical method has been problematic. For example, the heterojunction photovoltaic cells made via that method exhibit suboptimal shunt resistance and high reverse saturation current. High reverse saturation current indicates high electron-hole pair recombination, which lowers efficiency. This might be understood by the fact that the at least one front intrinsic semiconductor layer and front semiconductor layer are deposited first on the front of the semiconductor substrate (also n-doped). Therefore, there is the possibility that the at least one front doped semiconductor layer (n-doped) wraps around an edge of the doped semiconductor substrate (n-doped) and contacts the rear surface thereof. As the at least one front doped semiconductor layer (n-doped) is conductive to electrons, this contact of the rear surface would allow electrons to exit the rear surface of the doped semiconductor substrate (n-doped) in addition to the front surface, reducing charge separation and, consequently, decreasing shunt resistance. Stated another way, the intention is for electrons to exit the photovoltaic cell through the front metal contacts, but some electrons will likely recombine with a hole before reaching the front metal contacts if the electrons exit the rear surface of the doped semiconductor substrate. Another problem that is posed is that the at least one front intrinsic semiconductor layer and the at least one rear intrinsic semiconductor layer do not completely envelop the doped semiconductor substrate. The lack of complete envelopment decreases passivation of the front and rear surfaces of the doped semiconductor substrate, and causes higher recombination, and higher reverse saturation current.

[0007] Later, a “two-flip” layer deposition process began to be utilized. The order of processing steps was (i) to deposit the at least one rear intrinsic semiconductor layer onto the rear surface of the doped semiconductor substrate (n-doped), (ii) to flip the doped semiconductor substrate over a first time, (iii) to deposit the at least one front intrinsic semiconductor layer onto the front surface of the doped semiconductor substrate, (iv) to deposit the at least one front doped semiconductor layer (n-doped) on the at least one front intrinsic semiconductor layer, (v) to flip the doped semiconductor substrate over a second time, and (iv) to deposit the at least one rear doped semiconductor layer (p-doped) on the at least one rear intrinsic semiconductor layer.

[0008] However, the resulting heterojunction photovoltaic cell produced by this “two flip” historical method may be suboptimal. For example, because of the order of processing steps, at the edge of the heterojunction photovoltaic cell, the at least one front doped semiconductorAttorney Docket No. SP24-158PCT layer (n-doped) is closer to the doped semiconductor substrate (also n-doped) than the at least one rear doped semiconductor layer (p-doped). That could be problematic, because it may result in the photovoltaic cell having suboptimal efficiency.

[0009] Thus, for at least these reasons, improved and advantaged heterojunction photovoltaic cells are needed, including methods for making the same.SUMMARY

[0010] The present disclosure addresses that problem with a different order of processing steps that creates a heterojunction photovoltaic cell where, at the edge of the semiconductor substrate, the at least one front doped semiconductor layer, closer to the semiconductor substrate, has a dopant with the opposite conductivity type as the dopant of the semiconductor substrate, while the rear doped semiconductor substrate layer, further from the semiconductor substrate, has a dopant with the same conductivity type as the dopant of the semiconductor substrate. That relative spatial orientation may improve the efficiency of the photovoltaic cell by reducing recombination.

[0011] According to a first aspect of the present disclosure, a heterojunction photovoltaic cell comprises: (a) a doped semiconductor substrate comprising a front surface, a rear surface, and an edge, the doped semiconductor substrate being doped with either an n-dopant or a p-dopant; (b) at least one front intrinsic semiconductor layer disposed (i) over the front surface of the doped semiconductor substrate and (ii) at least partially over the edge of the doped semiconductor substrate; (c) at least one rear intrinsic semiconductor layer disposed (i) over the rear surface of the doped semiconductor substrate and (ii) at least partially over the at least one front intrinsic semiconductor layer facing the edge of the doped semiconductor substrate; (d) at least one rear doped semiconductor layer disposed (i) over the at least one rear intrinsic semiconductor layer facing the rear surface of the doped semiconductor substrate and (ii) at least partially over the at least one rear intrinsic semiconductor layer facing the edge of the doped semiconductor substrate, the at least one rear doped semiconductor layer being doped with either an n-dopant or a p-dopant, whichever the doped semiconductor substrate is not doped with; and (e) at least one front doped semiconductor layer disposed (i) over the at least one front intrinsic semiconductor layer facing the front surface of the doped semiconductor substrate and (ii) at least partially over the at least one rear doped semiconductor layer facing the edge of the doped semiconductor substrate, the at least one front doped semiconductor layer being doped with either an n-dopant or a p-dopant, whichever the doped semiconductor substrate is doped with.Attorney Docket No. SP24-158PCT

[0012] According to a second aspect of the present disclosure, the heterojunction photovoltaic cell of the first aspect is presented, wherein the doped semiconductor substrate comprises silicon.

[0013] According to a third aspect of the present disclosure, the heterojunction photovoltaic cell of any one of the first through second aspects is presented, wherein the n-dopant with which the doped semiconductor substrate is doped comprises one or more of phosphorous, arsenic, and antimony.

[0014] According to a fourth aspect of the present disclosure, the heterojunction photovoltaic cell of any one of the first through second aspects is presented, wherein the p-dopant with which the doped semiconductor substrate is doped comprises one or more of boron, gallium, indium, and aluminum.

[0015] According to a fifth aspect of the present disclosure, the heterojunction photovoltaic cell of any one of the first through fourth aspects is presented, wherein the at least one rear doped semiconductor layer comprises nanocrystalline or microcrystalline silicon.

[0016] According to a sixth aspect of the present disclosure, the heterojunction photovoltaic cell of any one of the first through fifth aspects is presented, wherein the least one front doped semiconductor layer comprises nanocrystalline or microcrystalline silicon.

[0017] According to a seventh aspect of the present disclosure, the heterojunction photovoltaic cell of any one of the first through fourth aspects is presented, wherein (i) either the at least one rear doped semiconductor layer or the at least one front doped semiconductor layer comprises amorphous silicon without nanocrystalline or microcrystalline silicon, and (ii) the other of the at least one rear doped semiconductor layer and the at least one front doped semiconductor layer comprises nanocrystalline or microcrystalline silicon.

[0018] According to an eighth aspect of the present disclosure, the heterojunction photovoltaic cell of any one of the first through fourth aspects is presented, wherein both the at least one rear doped semiconductor layer and the at least one front doped semiconductor layer comprise amorphous silicon without nanocrystalline or microcrystalline silicon.

[0019] According to a ninth aspect of the present disclosure, the heterojunction photovoltaic cell of any one of the first through eighth aspects is presented, wherein at least a portion of the at least one rear doped semiconductor layer is sandwiched between the edge of the doped semiconductor substrate and the at least one front doped semiconductor layer.

[0020] According to a tenth aspect of the present disclosure, the heterojunction photovoltaic cell of any one of the first through ninth aspects further comprises: (a) at least one front transparent conducting layer disposed over the at least one front doped semiconductor layer;Attorney Docket No. SP24-158PCT and (b) at least one rear transparent conducting layer disposed over the at least one rear doped semiconductor layer.

[0021] According to an eleventh aspect of the present disclosure, the heterojunction photovoltaic cell of the tenth aspect is presented, wherein the at least one front transparent conducting layer and the at least one rear transparent conducting layer both comprise a transparent conductive oxide.

[0022] According to a twelfth aspect of the present disclosure, the heterojunction photovoltaic cell of the eleventh aspect is presented, wherein the transparent conductive oxide is indium tin oxide (ITO), zinc oxide (ZnO), aluminum-doped zinc oxide (AZO), tin oxide (SnO?), fluorinedoped tin oxide (FTO), or tungsten-doped indium oxide (IWO).

[0023] According to a thirteenth aspect of the present disclosure, the heterojunction photovoltaic cell of any one of the eleventh through twelfth aspects is presented, wherein the at least one rear transparent conducting layer on the at least one rear doped semiconductor layer is not flush with the edge of the doped semiconductor substrate so as to form edge regions over the at least one rear doped semiconductor layer where the at least one rear transparent conducting layer is not present.

[0024] According to a fourteenth aspect of the present disclosure, the heterojunction photovoltaic cell of any one of the tenth through thirteenth aspects further comprises: (a) front contacts disposed on the at least one front transparent conducting layer; and (b) rear contacts disposed on the at least one rear transparent conducting layer.

[0025] According to a fifteenth aspect of the present disclosure, a method of making a heterojunction photovoltaic cell comprises, in order: (1) a front intrinsic semiconductor forming step comprising forming at least one front intrinsic semiconductor layer over a front surface of a doped semiconductor substrate, the doped semiconductor substrate being doped with either an n-dopant or a p-dopant; (2) a rear intrinsic semiconductor forming step comprising forming at least one rear intrinsic semiconductor layer over a rear surface of the doped semiconductor substrate; (3) a rear doped semiconductor forming step comprising forming at least one rear doped semiconductor layer over the at least one rear intrinsic semiconductor layer, the at least one rear doped semiconductor layer being doped with either an n-dopant or a p-dopant, whichever the doped semiconductor substrate is not doped with; and (4) a front doped semiconductor forming step comprising forming at least one front doped semiconductor layer over the at least one front intrinsic semiconductor layer, the at least one front doped semiconductor layer being doped with either an n-dopant or a p-dopant, whichever the doped semiconductor substrate is doped with.Attorney Docket No. SP24-158PCT

[0026] According to a sixteenth aspect of the present disclosure, the method of the fifteenth aspect is presented, wherein the front intrinsic semiconductor forming step comprises forming the at least one front intrinsic semiconductor layer via a plasma enhanced chemical vapor deposition (PECVD) method.

[0027] According to a seventeenth aspect of the present disclosure, the method of any one of the fifteenth through sixteenth aspects is presented, wherein the rear intrinsic semiconductor forming step comprises forming the at least one rear intrinsic semiconductor layer via a PECVD method.

[0028] According to an eighteenth aspect of the present disclosure, the method of any one of the fifteenth through seventeenth aspects is presented, wherein after the front intrinsic semiconductor forming step and the rear intrinsic semiconductor forming step, the at least one front intrinsic semiconductor layer and the at least one rear intrinsic semiconductor layer at least partially envelope the doped semiconductor substrate.

[0029] According to a nineteenth aspect of the present disclosure, the method of any one of the fifteenth through eighteenth aspects is presented, wherein (i) the doped semiconductor substrate is doped with an n-dopant, (ii) the at least one rear doped semiconductor layer is doped with a p-dopant, and (iii) the at least one front doped semiconductor layer is doped with an n-dopant.

[0030] According to a twentieth aspect of the present disclosure, the method of any one of the fifteenth through eighteenth aspects is presented, wherein (i) the doped semiconductor substrate is doped with a p-dopant, (ii) the at least one rear doped semiconductor layer is doped with an n-dopant, and (iii) the at least one front doped semiconductor layer is doped with a p-dopant.

[0031] According to a twenty -first aspect of the present disclosure, the method of any one of the fifteenth through twentieth aspects further comprises, in no particular order: (1) a front transparent conductor forming step comprising forming at least one front transparent conducting layer over the at least one front doped semiconductor layer; and (2) a rear transparent conductor forming step comprising forming at least one rear transparent conducting layer over the at least one rear doped semiconductor layer.

[0032] According to a twenty-second aspect of the present disclosure, the method of any one of the fifteenth through twenty-first aspects is presented, wherein the rear intrinsic semiconductor forming step and the rear doped semiconductor forming step occur in the same reaction enclosure.BRIEF DESCRIPTION OF THE DRAWINGSAttorney Docket No. SP24-158PCT

[0033] In the Drawings:

[0034] FIG. 1 is a cross-sectional elevation view of a heterojunction photovoltaic cell of the present disclosure at an intermediate point in time during a method of manufacturing the heterojunction photovoltaic cell, illustrating (i) at least one front intrinsic semiconductor layer and at least one rear intrinsic semiconductor layer together enveloping a doped semiconductor substrate and (ii) at least one rear doped semiconductor layer disposed closer to an edge of the doped semiconductor substrate than at least one front doped semiconductor layer;

[0035] FIG. 2 is a cross-sectional elevation view of the heterojunction photovoltaic cell after the method of manufacturing;

[0036] FIG. 3 is a schematic diagram of a method of manufacturing the heterojunction photovoltaic cell, illustrating, in order, at least a front intrinsic semiconductor forming step, a rear intrinsic semiconductor forming step, a rear doped semiconductor forming step, and a front doped semiconductor forming step; and

[0037] FIG. 4 is a schematic diagram of a device that can be used to perform the method to make the heterojunction photovoltaic cell.DETAILED DESCRIPTION

[0001] Additional features and advantages will be set forth in the detailed description which follows, and in part will be readily apparent to those skilled in the art from that description or recognized by practicing the embodiments as described herein, including the detailed description which follows, the claims, as well as the appended drawings.

[0002] It is to be understood that both the foregoing general description and the following detailed description are merely exemplary and are intended to provide an overview or framework to understanding the nature and character of the claims. The accompanying drawings are included to provide a further understanding and are incorporated in and constitute a part of this specification. The drawings illustrate one or more embodiments, and together with the description, explain principles and operation of the various embodiments.

[0038] Reference will now be made in detail to the present preferred embodiments, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals will be used throughout the drawings to refer to the same or like parts.

[0039] Referring to FIGS. 1 and 2, a heterojunction photovoltaic cell 10 is herein described. The heterojunction photovoltaic cell 10 includes a doped semiconductor substrate 12, at least one front intrinsic semiconductor layer 14, at least one rear intrinsic semiconductor layer 16, at least one rear doped semiconductor layer 18, and at least one front doped semiconductor layer 20. For purposes of this disclosure, “front” and rear” are relative to each other, withAttorney Docket No. SP24-158PCT“front” intended to be disposed closer to a source 22 of photons 24 (e.g., the Sun) than the “rear.”

[0040] The doped semiconductor substrate 12 includes a front surface 26, a rear surface 28, and an edge 30. The front surface 26 and the rear surface 28 face in generally opposite directions. The front surface 26 and the rear surface 28 can be planar and parallel to each other. The edge 30 transitions the front surface 26 to the rear surface 28. The edge 30 can be approximately orthogonal to the front surface 26 and the rear surface 28. In embodiments, the doped semiconductor substrate 12 is made of, or at least includes, silicon, germanium, or gallium arsenide.

[0041] The doped semiconductor substrate 12 is doped with either an n-dopant or a p-dopant. The n-dopant can be one or more of phosphorous, arsenic, and antimony. The p-dopant can be one or more of boron, gallium, indium, and aluminum. Those lists of n-dopants and p-dopants are not meant to be exhaustive.

[0042] The at least one front intrinsic semiconductor layer 14 is disposed over the front surface 26 of the doped semiconductor substrate 12. In addition, due to the deposition process by which the at least one front intrinsic semiconductor layer 14 is added, the at least one front intrinsic semiconductor layer 14 is further disposed at least partially over the edge 30 of the doped semiconductor substrate 12. In short, the at least one front intrinsic semiconductor layer 14 covers both the front surface 26 of the doped semiconductor substrate 12 and at least a portion of the edge 30 of the doped semiconductor substrate 12. The at least one front intrinsic semiconductor layer 14 can be made of, or at least include, silicon, germanium, or gallium arsenide.

[0043] The at least one rear intrinsic semiconductor layer 16 is disposed over the rear surface 28 of the doped semiconductor substrate 12. In addition, due to the deposition process by which the at least one rear intrinsic semiconductor layer 16 is added, the at least one rear intrinsic semiconductor layer 16 is further disposed at least partially over the at least one front intrinsic semiconductor layer 14 facing the edge 30 of the doped semiconductor substrate 12. In short, the at least one rear intrinsic semiconductor layer 16 covers both the rear surface 28 of the doped semiconductor substrate 12 and sandwiches, with the edge 30 of the doped semiconductor substrate 12, at least a portion of the at least one front intrinsic semiconductor layer 14. The at least one rear intrinsic semiconductor layer 16 likewise can be made of, or at least include, silicon, germanium, or gallium arsenide.

[0044] The at least one rear doped semiconductor layer 18 is disposed over the at least one rear intrinsic semiconductor layer 16 facing the rear surface 28 of the doped semiconductorAttorney Docket No. SP24-158PCT substrate 12. The at least one rear intrinsic semiconductor layer 16 is sandwiched between the at least one rear doped semiconductor layer 18 and the rear surface 28 of the doped semiconductor substrate 12. In addition, due to the deposition process by which the at least one rear doped semiconductor layer 18 is added, the at least one rear doped semiconductor layer 18 is disposed at least partially over the at least one rear intrinsic semiconductor layer 16 facing the edge 30 of the doped semiconductor substrate 12. At least a portion of the at least one rear intrinsic semiconductor layer 16 is sandwiched between the at least one rear doped semiconductor layer 18 and the edge 30 of the doped semiconductor substrate 12.

[0045] In embodiments, the at least one rear doped semiconductor layer 18 includes amorphous silicon. In other embodiments, the at least one rear doped semiconductor layer 18 includes nanocrystalline or microcrystalline silicon within an amorphous silicon phase. In other embodiments, the at least one rear doped semiconductor layer 18 includes nanocrystalline or microcrystalline silicon and is substantially free of amorphous silicon. The at least one rear doped semiconductor layer 18 is doped with either an n-dopant or a p-dopant, whichever the doped semiconductor substrate 12 is not doped with. If the doped semiconductor substrate 12 is doped with an n-dopant, then the at least one rear doped semiconductor layer 18 is doped with a p-dopant. However, if the doped semiconductor substrate 12 is doped with a p-dopant, then the at least one rear doped semiconductor layer 18 is doped with an n-dopant.

[0046] The at least one front doped semiconductor layer 20 is disposed over the at least one front intrinsic semiconductor layer 14 facing the front surface 26 of the doped semiconductor substrate 12. The at least one front intrinsic semiconductor layer 14 is sandwiched between the at least one front doped semiconductor layer 20 and the doped semiconductor substrate 12. In addition, the at least one front doped semiconductor layer 20 is disposed at least partially over the at least one rear doped semiconductor layer 18 facing the edge 30 of the doped semiconductor substrate 12. At least a portion of the at least one rear doped semiconductor layer 18 is sandwiched between the at least one front doped semiconductor layer 20 and the edge 30 of the doped semiconductor substrate 12.

[0047] In embodiments, the at least one front doped semiconductor layer 20 includes amorphous silicon. In other embodiments, the at least one front doped semiconductor layer 20 includes nanocrystalline or microcrystalline silicon within an amorphous silicon phase. In other embodiments, the at least one front doped semiconductor layer 20 includes nanocrystalline or microcrystalline silicon and is substantially free of amorphous silicon. In some instances, either the at least one rear doped semiconductor layer 18 or the least one front doped semiconductor layer 20 includes amorphous silicon without nanocrystalline orAttorney Docket No. SP24-158PCT microcrystalline silicon, while the other of the at least one rear doped semiconductor layer 18 and the least one front doped semiconductor layer 20 comprises nanocrystalline or microcrystalline silicon. In some instances, both the at least one rear doped semiconductor layer 18 and the at least one front doped semiconductor layer 20 include amorphous silicon without nanocrystalline or microcrystalline silicon.

[0048] The at least one front doped semiconductor layer 20 is doped with either an n-dopant or a p-dopant, whichever the doped semiconductor substrate 12 is doped with. If the doped semiconductor substrate 12 is doped with an n-dopant, then the at least one front doped semiconductor layer 20 is doped with an n-dopant. However, if the doped semiconductor substrate 12 is doped with a p-dopant, then the at least one front doped semiconductor layer 20 is doped with a p-dopant.

[0049] In embodiments, the heterojunction photovoltaic cell 10 further includes at least one front transparent conducting layer 32 (see FIG. 2). The at least one front transparent conducting layer 32 is disposed over the at least one front doped semiconductor layer 20. The at least one front doped semiconductor layer 20 and the at least one front intrinsic semiconductor layer 14 are disposed between the front surface 26 of the doped semiconductor substrate 12 and the at least one front transparent conducting layer 32. The at least one front transparent conducting layer 32 is electrically conductive. In embodiments, the at least one front transparent conductive layer is or includes a transparent conductive oxide, such as indium tin oxide (ITO), zinc oxide (ZnO), aluminum-doped zinc oxide (AZO), tin oxide (SnO?), fluorine-doped tin oxide (FTO), or tungsten-doped indium oxide (IWO).

[0050] In embodiments, the heterojunction photovoltaic cell 10 further includes at least one rear transparent conducting layer 34. The at least one rear transparent conducting layer 34 is disposed over the at least one rear doped semiconductor layer 18. The at least one rear doped semiconductor layer 18 and the at least one rear intrinsic semiconductor layer 16 are sandwiched between the rear surface 28 of the doped semiconductor substrate 12 and the at least one rear transparent conducting layer 34. The at least one rear transparent conducting layer 34 is electrically conductive. In embodiments, the at least one rear transparent conductive layer is or includes a transparent conductive oxide, such as indium tin oxide (ITO), zinc oxide (ZnO), aluminum-doped zinc oxide (AZO), tin oxide (SnO?), fluorine-doped tin oxide (FTO), or tungsten-doped indium oxide (IWO). The at least one rear transparent conducting layer 34 on the at least one rear doped semiconductor layer 18 is not flush with the edge 30 of the doped semiconductor substrate 12 so as to form edge regions 42 over the at least one rear doped semiconductor layer 18 where the at least one rear transparent conducting layer 34 is notAttorney Docket No. SP24-158PCT present. Depositing the at least one rear transparent conducting layer 34 while maintaining the edge regions 42 free thereof helps prevent electrical contact between the at least one rear transparent conducting layer 34 and the at least one front transparent conducting layer 32. The edge regions 42 can be formed by masking the at least one rear doped semiconductor layer 18 near the edge 30 of the doped semiconductor substrate 12 while depositing the at least one rear transparent conducting layer 34.

[0051] In embodiments, the heterojunction photovoltaic cell 10 further includes front contacts 36 and rear contacts 38. The front contacts 36 are disposed on the at least one front transparent conducting layer 32. The rear contacts 38 are disposed on the at least one rear transparent conducting layer 34. The front contacts 36 and the rear contacts 38 can be made of silver, among other options.

[0052] In embodiments, the heterojunction photovoltaic cell 10 further includes one or more insulating oxide layers 40. The one or more insulating oxide layers 40 may form due to oxidation in the presence of air during the manufacturing process.

[0053] Referring now to FIG. 3, a method 100 of making the heterojunction photovoltaic cell 10 is herein disclosed. The method 100 includes, in order, a front intrinsic semiconductor forming step 102, a rear intrinsic semiconductor forming step 104, a rear doped semiconductor forming step 106, and a front doped semiconductor forming step 108.

[0054] The front intrinsic semiconductor forming step 102 includes forming the at least one front intrinsic semiconductor layer 14 over the front surface 26 of the doped semiconductor substrate 12. In embodiments, the at least one front intrinsic semiconductor layer 14 is formed via a plasma enhanced chemical vapor deposition (PECVD) method 100. Other vapor deposition methods can be utilized.

[0055] The rear intrinsic semiconductor forming step 104 includes forming the at least one rear intrinsic semiconductor layer 16 over the rear surface 28 of the doped semiconductor substrate 12. In embodiments, the at least one rear intrinsic semiconductor layer 16 is formed via a PECVD method 100. Other vapor deposition methods can be utilized.

[0056] After the front intrinsic semiconductor forming step 102 and the rear intrinsic semiconductor forming step 104, the at least one front intrinsic semiconductor layer 14 and the at least one rear intrinsic semiconductor layer 16 at least partially envelope the doped semiconductor substrate 12. As mentioned above, after the rear intrinsic semiconductor forming step 104, at least a portion of the at least one front intrinsic semiconductor layer 14 is sandwiched between the edge 30 of the doped semiconductor substrate 12 and the at least one rear intrinsic semiconductor layer 16.Attorney Docket No. SP24-158PCT

[0057] The rear doped semiconductor forming step 106 includes forming the at least one rear doped semiconductor layer 18 over the at least one rear intrinsic semiconductor layer 16. Again, as mentioned, the at least one rear doped semiconductor layer 18 is doped with either an n-dopant or a p-dopant, whichever the doped semiconductor substrate 12 is not doped with. After the rear doped semiconductor forming step 106, at least a portion of both the at least one rear intrinsic semiconductor layer 16 and the at least one front intrinsic semiconductor layer 14 are sandwiched between the edge 30 of the doped semiconductor substrate 12 and the at least one rear doped semiconductor layer 18. In embodiments, the rear intrinsic semiconductor forming step 104 and the rear doped semiconductor forming step 106 can both occur in the same reaction enclosure.

[0058] The front doped semiconductor forming step 108 includes forming the at least one front doped semiconductor layer 20 over the at least one front intrinsic semiconductor layer 14. Again, as mentioned, the at least one front doped semiconductor layer 20 is doped with either an n-dopant or a p-dopant, whichever the doped semiconductor substrate 12 is doped with. After the front doped semiconductor forming step 108, at least a portion of each of the at least one rear doped semiconductor layer 18, the at least one rear intrinsic semiconductor layer 16, and the at least one front intrinsic semiconductor layer 14 are sandwiched between the edge 30 of the doped semiconductor substrate 12 and the at least one front doped semiconductor layer 20.

[0059] In embodiments, the doped semiconductor substrate 12 is doped with an n-dopant, the at least one rear doped semiconductor layer 18 is doped with a p-dopant, and the at least one front doped semiconductor layer 20 is doped with an n-dopant. In other embodiments, the doped semiconductor substrate 12 is doped with a p-dopant, the at least one rear doped semiconductor layer 18 is doped with an n-dopant, and the at least one front doped semiconductor layer 20 is doped with a p-dopant.

[0060] In embodiments, the method 100 further includes a front transparent conductor forming step 110 and a rear transparent conductor forming step 112. The front transparent conductor forming step 110 includes forming the at least one front transparent conducting layer 32 over the at least one front doped semiconductor layer 20. The rear transparent conductor forming step 112 includes forming the at least one rear transparent conducting layer 34 over the at least one rear doped semiconductor layer 18. The front transparent conductor forming step 110 can occur before or after the rear transparent conductor forming step 112.

[0061] The heterojunction photovoltaic cell 10 and the method 100 of the present disclosure address the problems set forth in the Background, in a variety of ways. Among them, becauseAttorney Docket No. SP24-158PCT the method 100 deposits the at least one front intrinsic semiconductor layer 14 and then the at least one rear intrinsic semiconductor layer 16 before the at least one front doped semiconductor layer 20, and the at least one front doped semiconductor layer 20 cannot wrap around the edge 30 of the doped semiconductor substrate 12 to contact the rear surface 28 of the doped semiconductor substrate 12. Thus, the issue with shunt resistance is avoided.

[0062] In addition, the at least one rear doped semiconductor layer 18 faces the edge 30 of the doped semiconductor substrate 12 and separates (at least partially) the edge 30 of the doped semiconductor substrate 12 from the at least one front doped semiconductor layer 20. The at least one rear doped semiconductor layer 18 is doped with the opposite conductivity type dopant as the doped semiconductor substrate 12. For example, if the doped semiconductor substrate 12 is p-doped, then the at least one rear doped semiconductor layer 18 is n-doped. Placing the at least one p-doped rear doped semiconductor layer 18 closer to the edge 30 of the n-doped doped semiconductor substrate 12 than the at least one n-doped front doped semiconductor layer 20 may improve the efficiency of the heterojunction photovoltaic cell 10. In the “two-flip” method described in the Background, the at least one front doped semiconductor layer (sharing the same conductivity type dopant as the doped semiconductor substrate) is deposited before the at least one rear doped semiconductor layer. Thus, the at least one front doped semiconductor layer is disposed closer to the edge of the doped semiconductor substrate than the at least one rear doped semiconductor layer. The at least one rear doped semiconductor layer (having the opposite conductivity type dopant) does not separate the at least one front doped semiconductor layer and the doped semiconductor substrate.

[0063] Referring now to FIG. 4, a device 200 is herein described that can be utilized to form the heterojunction photovoltaic cell 10, such as via the method 100. The device 200 includes a loading and unloading mechanism 202 and a first reactor 204. The loading and unloading mechanism 202 accepts the doped semiconductor substrate 12 and moves the doped semiconductor substrate 12 to the first reactor 204. At the first reactor 204, the front intrinsic semiconductor forming step 102 can be performed to deposit the at least one front intrinsic semiconductor layer 14 over the front surface 26 of the doped semiconductor substrate 12. The loading and unloading mechanism 202 can then remove the first workpiece that is the doped semiconductor substrate 12 with the at least one front intrinsic semiconductor layer 14 from the first reactor 204 and transport the first workpiece to a conveyor 206.

[0064] The conveyor 206 can convey the first workpiece to another loading and unloading mechanism 208. The loading and unloading mechanism 208 retrieves the first workpiece from the conveyor 206 and deposits the first workpiece to a flipping system 210. The flipping systemAttorney Docket No. SP24-158PCT210 flips the first workpiece to position the rear surface 28 of the doped semiconductor substrate 12 to accept further layers. The flipping system 210 then moves the first workpiece to a second reactor 212. At the second reactor 212, the rear intrinsic semiconductor forming step 104 is performed to deposit the at least one rear intrinsic semiconductor layer over the rear surface 28 of the doped semiconductor substrate 12. In the same second reactor 212, the rear doped semiconductor forming step 106 is performed to form the at least one rear doped semiconductor layer 18 over the at least one rear intrinsic semiconductor layer 16. The result is a second workpiece. The flipping system 210 then retrieves the second workpiece from the second reactor 212 and flips the second workpiece so that the at least one front intrinsic semiconductor layer 14 is positioned to accept a further layer. The loading and unloading mechanism 208 can then transport the second workpiece to the conveyor 206.

[0065] The conveyor 206 then conveys the second workpiece to another loading and unloading mechanism 214. The loading and unloading mechanism 214 retrieves the second workpiece from the conveyor 206 and deposits the second workpiece to a third reactor 216. At the third reactor 216, the front doped semiconductor forming step 108 is performed to form the at least one front doped semiconductor layer 20 over the at least one front intrinsic semiconductor layer 14. The result is a third workpiece. The third workpiece can then be further processed according to the method 100 to form the heterojunction photovoltaic cell 10.

Claims

Attorney Docket No. SP24-158PCTCLAIM(S)What is claimed is:

1. A heterojunction photovoltaic cell comprising: a doped semiconductor substrate comprising a front surface, a rear surface, and an edge, the doped semiconductor substrate being doped with either an n-dopant or a p-dopant; at least one front intrinsic semiconductor layer disposed (i) over the front surface of the doped semiconductor substrate and (ii) at least partially over the edge of the doped semiconductor substrate; at least one rear intrinsic semiconductor layer disposed (i) over the rear surface of the doped semiconductor substrate and (ii) at least partially over the at least one front intrinsic semiconductor layer facing the edge of the doped semiconductor substrate; at least one rear doped semiconductor layer disposed (i) over the at least one rear intrinsic semiconductor layer facing the rear surface of the doped semiconductor substrate and (ii) at least partially over the at least one rear intrinsic semiconductor layer facing the edge of the doped semiconductor substrate, the at least one rear doped semiconductor layer being doped with either an n-dopant or a p-dopant, whichever the doped semiconductor substrate is not doped with; and at least one front doped semiconductor layer disposed (i) over the at least one front intrinsic semiconductor layer facing the front surface of the doped semiconductor substrate and (ii) at least partially over the at least one rear doped semiconductor layer facing the edge of the doped semiconductor substrate, the at least one front doped semiconductor layer being doped with either an n-dopant or a p-dopant, whichever the doped semiconductor substrate is doped with.

2. The heterojunction photovoltaic cell of claim 1, wherein the doped semiconductor substrate comprises silicon.

3. The heterojunction photovoltaic cell of any one of claims 1-2, wherein the n-dopant with which the semiconductor substrate is doped comprises one or more of phosphorous, arsenic, and antimony.

4. The heterojunction photovoltaic cell of any one of claims 1-2, wherein the p-dopant with which the doped semiconductor substrate is doped comprises one or more of boron, gallium, indium, and aluminum.Attorney Docket No. SP24-158PCT5. The heterojunction photovoltaic cell of any one of claims 1-4, wherein the at least one rear doped semiconductor layer comprises nanocrystalline or microcrystalline silicon.

6. The heterojunction photovoltaic cell of any one of claims 1-5, wherein the at least one front doped semiconductor layer comprises nanocrystalline or microcrystalline silicon.

7. The heterojunction photovoltaic cell of any one of claims 1-4, wherein either the at least one rear doped semiconductor layer or the least one front doped semiconductor layer comprises amorphous silicon without nanocrystalline or microcrystalline silicon, and the other of the at least one rear doped semiconductor layer and the least one front doped semiconductor layer comprises nanocrystalline or microcrystalline silicon.

8. The heterojunction photovoltaic cell of any one of claims 1-4, wherein both the at least one rear doped semiconductor layer and the at least one front doped semiconductor layer comprise amorphous silicon without nanocrystalline or microcrystalline silicon.

9. The heterojunction photovoltaic cell of any one of claims 1-8, wherein at least a portion of the at least one rear doped semiconductor layer is sandwiched between the edge of the doped semiconductor substrate and the at least one front doped semiconductor layer.

10. The heterojunction photovoltaic cell of any one of claims 1-9 further comprising: at least one front transparent conducting layer disposed over the at least one front doped semiconductor layer; and at least one rear transparent conducting layer disposed over the at least one rear doped semiconductor layer.

11. The heterojunction photovoltaic cell of claim 10, whereinAttorney Docket No. SP24-158PCT the at least one front transparent conducting layer and the at least one rear transparent conducting layer both comprise a transparent conductive oxide.

12. The heterojunction photovoltaic cell of claim 11, wherein the transparent conductive oxide is indium tin oxide (ITO), zinc oxide (ZnO), aluminum-doped zinc oxide (AZO), tin oxide (SnO?), fluorine-doped tin oxide (FTO), or tungsten-doped indium oxide (IWO).

13. The heterojunction photovoltaic cell of any one of claims 11-12, wherein the at least one rear transparent conducting layer on the at least one rear doped semiconductor layer is not flush with the edge of the doped semiconductor substrate so as to form edge regions over the at least one rear doped semiconductor layer where the at least one rear transparent conducting layer is not present.

14. The heterojunction photovoltaic cell of any one of claims 10-13 further comprising: front contacts disposed on the at least one front transparent conducting layer; and rear contacts disposed on the at least one rear transparent conducting layer.

15. A method of making a heterojunction photovoltaic cell comprising, in order: a front intrinsic semiconductor forming step comprising forming at least one front intrinsic semiconductor layer over a front surface of a doped semiconductor substrate, the doped semiconductor substrate being doped with either an n-dopant or a p-dopant; a rear intrinsic semiconductor forming step comprising forming at least one rear intrinsic semiconductor layer over a rear surface of the doped semiconductor substrate; a rear doped semiconductor forming step comprising forming at least one rear doped semiconductor layer over the at least one rear intrinsic semiconductor layer, the at least one rear doped semiconductor layer being doped with either an n-dopant or a p-dopant, whichever the doped semiconductor substrate is not doped with; and a front doped semiconductor forming step comprising forming at least one front doped semiconductor layer over the at least one front intrinsic semiconductor layer, the at least one front doped semiconductor layer being doped with either an n-dopant or a p-dopant, whichever the doped semiconductor substrate is doped with.

16. The method of claim 15, whereinAttorney Docket No. SP24-158PCT the front intrinsic semiconductor forming step comprises forming the at least one front intrinsic semiconductor layer via a plasma enhanced chemical vapor deposition (PECVD) method.

17. The method of any one of claims 15-16, wherein the rear intrinsic semiconductor forming step comprises forming the at least one rear intrinsic semiconductor layer via a PECVD method.

18. The method of any one of claims 15-17, wherein after the front intrinsic semiconductor forming step and the rear intrinsic semiconductor forming step, the at least one front intrinsic semiconductor layer and the at least one rear intrinsic semiconductor layer at least partially envelope the doped semiconductor substrate.

19. The method of any one of claims 15-18, wherein the doped semiconductor substrate is doped with an n-dopant, the at least one rear doped semiconductor layer is doped with a p-dopant, and the at least one front doped semiconductor layer is doped with an n-dopant.

20. The method of any one of claims 15-18, wherein the doped semiconductor substrate is doped with a p-dopant, the at least one rear doped semiconductor layer is doped with an n-dopant, and the at least one front doped semiconductor layer is doped with a p-dopant.

21. The method of any one of claims 15-20 further comprising, in no particular order: a front transparent conductor forming step comprising forming at least one front transparent conducting layer over the at least one front doped semiconductor layer; and a rear transparent conductor forming step comprising forming at least one rear transparent conducting layer over the at least one rear doped semiconductor layer.

22. The method of any one of claims 15-21, wherein the rear intrinsic semiconductor forming step and the rear doped semiconductor forming step occur in the same reaction enclosure.

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