Heterojunction photovoltaic cell with one or more of nanocrystalline and microcrystalline silicon and method of making the same

Abstract

A heterojunction photovoltaic cell including: (a) a semiconductor substrate including a composition including a semiconductor material doped with a dopant; (b) at least one rear intrinsic semiconductor layer disposed over a rear primary surface of the semiconductor substrate and including an intrinsic semiconductor material; (c) at least one front intrinsic semiconductor layer disposed over a front primary surface of the semiconductor substrate and including an intrinsic semiconductor material; (d) at least one front doped semiconductor layer disposed over the at least one front intrinsic semiconductor layer and including a semiconductor material doped with a dopant; and (e) at least one rear doped semiconductor layer disposed over the at least one rear intrinsic semiconductor layer and including a semiconductor material doped with a dopant.

Description

Attorney Docket No. SP24-159PCTHETEROJUNCTION PHOTOVOLTAIC CELL WITH ONE OR MORE OF NANOCRYSTALLINE AND MICROCRYSTALLINE SILICON AND METHOD OF MAKING THE SAMECROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims the benefit of priority under 35 U.S.C. § 119 of U.S. Provisional Application No. 63 / 688,359 filed August 29, 2024, the content of which is incorporated herein by reference in its entirety.TECHNICAL FIELD

[0002] The present disclosure pertains to heterojunction photovoltaic cells and, more particularly, to heterojunction photovoltaic cells that include one or more of nanocrystalline and microcrystalline silicon and, in some instances, at least one layer without amorphous silicon.BACKGROUND

[0003] A photovoltaic cell, when integrated into an electrical circuit, uses energy from Sun- originated photons to generate electrical current. The photovoltaic cell is sometimes of the heterojunction variety. With a heterojunction photovoltaic cell, the photovoltaic cell includes a doped semiconductor substrate (sometimes referred to as an absorber) presenting a front surface and a rear surface, front and rear intrinsic semiconductor layers over both the front and rear surfaces (sometimes referred to as passivation or buffer layers), front and rear doped semiconductor layers over the front and rear intrinsic semiconductor layers, front and rear transparent conduction layers over the front and rear doped semiconductor layers, and front and rear contacts on the front and rear transparent conduction layers. Those intrinsic semiconductor layers and doped semiconductor layers include amorphous silicon. Amorphous silicon has been utilized, among other reasons, because amorphous silicon has a larger bandgap than crystalline silicon. This means that the intrinsic semiconductor layers and doped semiconductor layers, including amorphous silicon, can absorb photons associated with a narrower range of wavelengths than crystalline silicon. The narrower range of absorption is generally desirable because the doped semiconductor substrate is intended to be the absorber of photons and not the surrounding intrinsic semiconductor layers and doped semiconductor layers.

[0004] However, there is a problem in that photovoltaic cells including amorphous silicon have demonstrated degradation issues. For example, elevated temperatures and ultraviolet electromagnetic radiation can alter the atomic structure of the amorphous silicon, introducingAttorney Docket No. SP24-159PCT defects therewithin. The defects in the amorphous silicon serve as recombination centers for electrons and holes, which lower the efficiency of the heterojunction photovoltaic cell.

[0005] Thus, there exists a need for advantaged and improved heterojunction photovoltaic cells with one or more nanocrystalline and microcrystalline silicon, including various embodiments thereof, with advantaged and improved embodiments of methods for making the same.SUMMARY

[0006] The present disclosure addresses that issue, among other ways, with a heterojunction photovoltaic cell that includes one or more layers where the semiconductor material includes one or more of nanocrystalline and microcrystalline silicon. In some instances, at least one of the layers does not include any amorphous silicon. The inclusion of one or more of nanocrystalline and microcrystalline silicon and the reduction of amorphous silicon should help alleviate the degradation issues that the presence of amorphous silicon causes.

[0007] According to a first aspect of the present disclosure, a heterojunction photovoltaic cell comprises: (a) a semiconductor substrate comprising a front primary surface, a rear primary surface, and a composition comprising a semiconductor material doped with an n-dopant or a p-dopant; (b) at least one rear intrinsic semiconductor layer disposed over the rear primary surface of the semiconductor substrate, the at least one rear intrinsic semiconductor layer comprising an intrinsic semiconductor material; (c) at least one front intrinsic semiconductor layer disposed over the front primary surface of the semiconductor substrate, the at least one front intrinsic semiconductor layer comprising an intrinsic semiconductor material; (d) at least one front doped semiconductor layer disposed over the at least one front intrinsic semiconductor layer, the at least one front doped semiconductor layer comprising a semiconductor material doped with an n-dopant or a p-dopant; and (e) at least one rear doped semiconductor layer disposed over the at least one rear intrinsic semiconductor layer, the at least one rear doped semiconductor layer comprising a semiconductor material doped with an n-dopant or a p-dopant, wherein, at least one of the intrinsic semiconductor material of the at least one rear intrinsic semiconductor layer, the intrinsic semiconductor material of the at least one front intrinsic semiconductor layer, the semiconductor material of the at least one front doped semiconductor layer, and the semiconductor material of the at least one rear doped semiconductor layer comprises one or more of nanocrystalline and microcrystalline silicon.

[0008] According to a second aspect of the present disclosure, the heterojunction photovoltaic cell of the first aspect is presented, wherein the semiconductor material of the semiconductor substrate comprises crystalline silicon.Attorney Docket No. SP24-159PCT

[0009] According to a third aspect of the present disclosure, the heterojunction photovoltaic cell of any one of the first through second aspects is presented, wherein the semiconductor material of the semiconductor substrate comprises one or more of germanium, gallium arsenide, cadmium telluride, copper indium gallium selenide, and amorphous silicon.

[0010] According to a fourth aspect of the present disclosure, the heterojunction photovoltaic cell of any one of the first through third aspects is presented, wherein the semiconductor material of the composition of the semiconductor substrate is doped with an n-dopant.

[0011] According to a fifth aspect of the present disclosure, the heterojunction photovoltaic cell of any one of the first through third aspects is presented, wherein the semiconductor material of the composition of the semiconductor substrate is doped with a p-dopant.

[0012] According to a sixth aspect of the present disclosure, the heterojunction photovoltaic cell of any one of the first through third aspects is presented, wherein (i) the semiconductor material of the semiconductor substrate is doped with a p-dopant, (ii) the semiconductor material of the at least one front doped semiconductor layer is doped with a p-dopant, and (iii) the semiconductor material of the at least one rear doped semiconductor layer is doped with an n-dopant.

[0013] According to a seventh aspect of the present disclosure, the heterojunction photovoltaic cell of any one of the first through third aspects is presented, wherein (i) the semiconductor material of the semiconductor substrate is doped with an n-dopant, (ii) the semiconductor material of the at least one front doped semiconductor layer is doped with an n-dopant, and (iii) the semiconductor material of the at least one rear doped semiconductor layer is doped with a p-dopant.

[0014] According to an eighth aspect of the present disclosure, the heterojunction photovoltaic cell of any one of the first through seventh aspects is presented, wherein the intrinsic semiconductor material of the at least one rear intrinsic semiconductor layer comprises one or more of nanocrystalline and microcrystalline silicon.

[0015] According to a ninth aspect of the present disclosure, the heterojunction photovoltaic cell of any one of the first through eighth aspects is presented, wherein the intrinsic semiconductor material of the at least one front intrinsic semiconductor layer comprises one or more of nanocrystalline and microcrystalline silicon.

[0016] According to a tenth aspect of the present disclosure, the heterojunction photovoltaic cell of any one of the first through ninth aspects is presented, wherein the semiconductor material of the at least one front doped semiconductor layer comprises one or more of nanocrystalline and microcrystalline silicon.Attorney Docket No. SP24-159PCT

[0017] According to an eleventh aspect of the present disclosure, the heterojunction photovoltaic cell of any one of the first through tenth aspects is presented, wherein the semiconductor material of the at least one rear doped semiconductor layer comprises one or more of nanocrystalline and microcrystalline silicon.

[0018] According to a twelfth aspect of the present disclosure, the heterojunction photovoltaic cell of any one of the first through eleventh aspects is presented, wherein the n-dopant is one or more of phosphorous, arsenic, bismuth, and antimony.

[0019] According to a thirteenth aspect of the present disclosure, the heterojunction photovoltaic cell of any one of the first through twelfth aspects is presented, wherein the p- dopant is one or more of boron, aluminum, gallium, and indium.

[0020] According to a fourteenth aspect of the present disclosure, the heterojunction photovoltaic cell of any one of the first through thirteenth aspects is presented, wherein at least one of the intrinsic semiconductor material of the at least one rear intrinsic semiconductor layer, the intrinsic semiconductor material of the at least one front intrinsic semiconductor layer, the semiconductor material of the at least one front doped semiconductor layer, and the semiconductor material of the at least one rear doped semiconductor layer is substantially free of amorphous silicon.

[0021] According to a fifteenth aspect of the present disclosure, the heterojunction photovoltaic cell of any one of the first through fourteenth aspects further comprises: (i) at least one front transparent conducting layer disposed over the at least one front doped semiconductor layer; and (ii) at least one rear transparent conducting layer disposed over the at least one rear doped semiconductor layer.

[0022] According to a sixteenth aspect of the present disclosure, the heterojunction photovoltaic cell of the fifteenth aspect is presented, wherein at least one of the at least one front transparent conducting layer and the at least one rear transparent conducting layer comprise a transparent conductive oxide.

[0023] According to a seventeenth aspect of the present disclosure, the heterojunction photovoltaic cell of the sixteenth aspect is presented, wherein the transparent conductive oxide comprises one or more of indium tin oxide (ITO), zinc oxide (ZnO), aluminum-doped zinc oxide (AZO), tin oxide (SnO?), fluorine-doped tin oxide (FTO), and tungsten-doped indium oxide (IWO).

[0024] According to an eighteenth aspect of the present disclosure, the heterojunction photovoltaic cell of any one of the fifteenth through seventeenth aspects is presented, wherein the at least one rear transparent conducting layer on the at least one rear doped semiconductorAttorney Docket No. SP24-159PCT layer is not flush with the edge of the doped semiconductor substrate so as to form edge regions over the at least one rear doped semiconductor layer where the at least one rear transparent conducting layer is not present.

[0025] According to a nineteenth aspect of the present disclosure, the heterojunction photovoltaic cell of any one of the fifteenth through eighteenth aspects further comprises: (i) front contacts disposed on the at least one front transparent conducting layer; and rear contacts disposed on the at least one rear transparent conducting layer.

[0026] According to a twentieth aspect of the present disclosure, a method of making a heterojunction photovoltaic cell comprises: (a) a rear intrinsic semiconductor forming step comprising forming at least one rear intrinsic semiconductor layer over a rear primary surface of a semiconductor substrate, the semiconductor substrate comprising a semiconductor material doped with an n-dopant or a p-dopant and the at least one rear intrinsic semiconductor layer comprising an intrinsic semiconductor material; (b) a front intrinsic semiconductor forming step comprising forming at least one front intrinsic semiconductor layer over a front primary surface of the semiconductor substrate, the at least one front intrinsic semiconductor layer comprising an intrinsic semiconductor material; (c) a front doped semiconductor forming step comprising forming at least one front doped semiconductor layer over the at least one front intrinsic semiconductor layer, the at least one front doped semiconductor layer comprising a semiconductor material doped with an n-dopant or a p-dopant; and (d) a rear doped semiconductor forming step comprising forming at least one rear doped semiconductor layer over the at least one rear intrinsic semiconductor layer, the at least one rear doped semiconductor layer comprising a semiconductor material doped with an n-dopant or a p- dopant, wherein, at least one of the intrinsic semiconductor material of the at least one rear intrinsic semiconductor layer, the intrinsic semiconductor material of the at least one front intrinsic semiconductor layer, the semiconductor material of the at least one front doped semiconductor layer, and the semiconductor material of the at least one rear doped semiconductor layer comprises one or more of nanocrystalline and microcrystalline silicon.

[0027] According to a twenty-first aspect of the present disclosure, the method of the twentieth aspect is presented, wherein the rear intrinsic semiconductor forming step, the front intrinsic semiconductor forming step, the front doped semiconductor forming step, and the rear doped semiconductor forming step are performed in that order relative to each other.

[0028] According to a twenty-second aspect of the present disclosure, the method of any one of the twentieth through twenty-first aspects is presented, wherein (i) the front intrinsic semiconductor forming step comprises forming the at least one front intrinsic semiconductorAttorney Docket No. SP24-159PCT layer via a plasma enhanced chemical vapor deposition (PECVD) method, and (ii) the rear intrinsic semiconductor forming step comprises forming the at least one rear intrinsic semiconductor layer via a PECVD method.

[0029] According to a twenty-third aspect of the present disclosure, the method of any one of the twentieth through twenty-second aspects is presented, wherein after the front intrinsic semiconductor forming step and the rear intrinsic semiconductor forming step, the at least one front intrinsic semiconductor layer and the at least one rear intrinsic semiconductor layer at least partially envelope the semiconductor substrate.

[0030] According to a twenty-fourth aspect of the present disclosure, the method of any one of the twentieth through twenty-third aspects further comprises, in no particular order: (i) a front transparent conductor forming step comprising forming at least one front transparent conducting layer over the at least one front doped semiconductor layer; and (ii) a rear transparent conductor forming step comprising forming at least one rear transparent conducting layer over the at least one rear doped semiconductor layer.

[0031] According to a twenty-fifth aspect of the present disclosure, the method of any one of the twentieth through twenty-fourth aspects is presented, wherein the front intrinsic semiconductor forming step and the front doped semiconductor forming step occur in the same reaction enclosure.

[0032] According to a twenty-sixth aspect of the present disclosure, the method of any one of the twentieth through twenty-fifth aspects is presented, wherein at least one of the intrinsic semiconductor material of the at least one rear intrinsic semiconductor layer, the intrinsic semiconductor material of the at least one front intrinsic semiconductor layer, the semiconductor material of the at least one front doped semiconductor layer, and the semiconductor material of the at least one rear doped semiconductor layer is substantially free of amorphous silicon.BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In the Drawings:

[0034] FIG. 1 is a cross-sectional elevation view of a heterojunction photovoltaic cell of the present disclosure at an intermediate point in time during a method of manufacturing the heterojunction photovoltaic cell, illustrating at least one front intrinsic semiconductor layer and at least one rear intrinsic semiconductor layer together enveloping a semiconductor substrate, as well as at least one front doped semiconductor layer and at least one rear doped semiconductor layer;Attorney Docket No. SP24-159PCT

[0035] FIG. 2 is a cross-sectional elevation view of the heterojunction photovoltaic cell after the method of manufacturing;

[0036] FIG. 3 is a schematic diagram of a method of manufacturing the heterojunction photovoltaic cell, illustrating, in order, at least a rear intrinsic semiconductor forming step, a front intrinsic semiconductor forming step, a front doped semiconductor forming step, and a rear doped semiconductor forming step; and

[0037] FIG. 4 is a schematic diagram of a device that can be used to perform the method to make the heterojunction photovoltaic cell.DETAILED DESCRIPTION

[0038] Additional features and advantages will be set forth in the detailed description which follows, and in part will be readily apparent to those skilled in the art from that description or recognized by practicing the embodiments as described herein, including the detailed description which follows, the claims, as well as the appended drawings.

[0039] It is to be understood that both the foregoing general description and the following detailed description are merely exemplary and are intended to provide an overview or framework to understanding the nature and character of the claims. The accompanying drawings are included to provide a further understanding and are incorporated in and constitute a part of this specification. The drawings illustrate one or more embodiments, and together with the description, explain principles and operation of the various embodiments.

[0040] Reference will now be made in detail to the present preferred embodiments, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals will be used throughout the drawings to refer to the same or like parts.

[0041] Referring to FIG. 1, a heterojunction photovoltaic cell 10 includes a semiconductor substrate 12, at least one rear intrinsic semiconductor layer 14, at least one front intrinsic semiconductor layer 16, at least one front doped semiconductor layer 18, and at least one rear doped semiconductor layer 20. For purposes of this disclosure, “front” and rear” are relative to each other, with “front” intended to be disposed closer to a source 19 of photons 21 (e.g., the Sun) than the “rear.”

[0042] The semiconductor substrate 12 includes a front primary surface 22 and a rear primary surface 24. The front primary surface 22 and the rear primary surface 24 face in generally opposite directions. The front primary surface 22 and the rear primary surface 24 can be planar and parallel to each other. The semiconductor substrate 12 further includes a composition. The composition includes a semiconductor material that is doped with an n-dopant or a p-dopant. In embodiments, the semiconductor material of the semiconductor substrate 12 is or includesAttorney Docket No. SP24-159PCT crystalline silicon. In other embodiments, the semiconductor material of the semiconductor substrate 12 is or includes one or more of germanium, gallium arsenide, cadmium telluride, copper indium gallium selenide, and amorphous silicon. The n-dopant can be one or more of phosphorous, arsenic, bismuth, and antimony. The p-dopant can be one or more of boron, aluminum, gallium, and indium. Those lists of n-dopants and p-dopants are not meant to be exhaustive.

[0043] The at least one rear intrinsic semiconductor layer 14 is disposed over the rear primary surface 24 of the semiconductor substrate 12. The at least one rear intrinsic semiconductor layer 14 includes an intrinsic semiconductor material (e.g., a semiconductor material without a dopant). In embodiments, the intrinsic semiconductor material includes one or more of nanocrystalline and microcrystalline silicon. In embodiments, the intrinsic semiconductor material includes one or more of nanocrystalline and microcrystalline silicon within a matrix of amorphous silicon. In embodiments, the intrinsic semiconductor material is substantially free of (or free of) amorphous silicon. “Substantially free” for purposes of this disclosure means that the mentioned ingredient (here amorphous silicon) is not intentionally added but may be present unintentionally due to manufacturing imprecision and / or contamination, such as in a trace amount.

[0044] The at least one front intrinsic semiconductor layer 16 is disposed over the front primary surface 22 of the semiconductor substrate 12. The at least one front intrinsic semiconductor layer 16 includes an intrinsic semiconductor material (e.g., a semiconductor material without a dopant). In embodiments, the intrinsic semiconductor material includes one or more of nanocrystalline and microcrystalline silicon. In embodiments, the intrinsic semiconductor material includes one or more of nanocrystalline and microcrystalline silicon within a matrix of amorphous silicon. In embodiments, the intrinsic semiconductor material is substantially free of (or free of) amorphous silicon.

[0045] The at least one front doped semiconductor layer 18 is disposed over the at least one front intrinsic semiconductor layer 16. The at least one front doped semiconductor layer 18 faces the front primary surface 22 of the semiconductor substrate 12. The at least one front intrinsic semiconductor layer 16 is sandwiched between the at least one front doped semiconductor layer 18 and the semiconductor substrate 12. The at least one front doped semiconductor layer 18 includes a semiconductor material that is doped with either an n-dopant or a p-dopant, whichever the semiconductor material of the semiconductor substrate 12 is doped with. If the semiconductor material of the semiconductor substrate 12 is doped with an n-dopant, then the semiconductor material of the at least one front doped semiconductor layerAttorney Docket No. SP24-159PCT 18 is doped with an n-dopant. However, if the semiconductor material of the semiconductor substrate 12 is doped with a p-dopant, then the semiconductor material of the at least one front doped semiconductor layer 18 is doped with a p-dopant. In embodiments, the semiconductor material of the at least one front doped semiconductor layer 18 includes or is made of one or more of nanocrystalline and microcrystalline silicon. In embodiments, the semiconductor material includes one or more of nanocrystalline and microcrystalline silicon within a matrix of amorphous silicon. In embodiments, the semiconductor material is substantially free of (or free of) amorphous silicon.

[0046] The at least one rear doped semiconductor layer 20 is disposed over the at least one rear intrinsic semiconductor layer 14. The at least one rear doped semiconductor layer 20 faces the rear primary surface 24 of the semiconductor substrate 12. The at least one rear intrinsic semiconductor layer 14 is sandwiched between the at least one rear doped semiconductor layer 20 and the rear primary surface 24 of the semiconductor substrate 12. The at least one rear doped semiconductor layer 20 includes a semiconductor material doped with an n-dopant or a p-dopant, whichever the semiconductor material of the semiconductor substrate 12 is not doped with. If the semiconductor material of the semiconductor substrate 12 is doped with an n- dopant, then the semiconductor material of the at least one rear doped semiconductor layer 20 is doped with a p-dopant. However, if the semiconductor material of the semiconductor substrate 12 is doped with a p-dopant, then the semiconductor material of the at least one rear doped semiconductor layer 20 is doped with an n-dopant. In embodiments, the semiconductor material of the at least one rear doped semiconductor layer 20 includes or is made of one or more of nanocrystalline and microcrystalline silicon. In embodiments, the semiconductor material includes one or more of nanocrystalline and microcrystalline silicon within a matrix of amorphous silicon. In embodiments, the semiconductor material is substantially free of (or free of) amorphous silicon.

[0047] In embodiments, the semiconductor material of the semiconductor substrate 12 is doped with a p-dopant. In those embodiments, the semiconductor material of the at least one front doped semiconductor layer 18 is doped with a p-dopant and the semiconductor material of the at least one rear doped semiconductor layer 20 is doped with an n-dopant.

[0048] In other embodiments, the semiconductor material of the semiconductor substrate 12 is doped with an n-dopant. In those embodiments, the semiconductor material of the at least one front doped semiconductor layer 18 is doped with an n-dopant and the semiconductor material of the at least one rear doped semiconductor layer 20 is doped with a p-dopant.Attorney Docket No. SP24-159PCT

[0049] In embodiments, at least one of the intrinsic semiconductor material of the at least one rear intrinsic semiconductor layer 14, the intrinsic semiconductor material of the at least one front intrinsic semiconductor layer 16, the semiconductor material of the at least one front doped semiconductor layer 18, and the semiconductor material of the at least one rear doped semiconductor layer 20 is substantially free (or free) of amorphous silicon. For example, at least one of the intrinsic semiconductor material of the at least one rear intrinsic semiconductor layer 14, the intrinsic semiconductor material of the at least one front intrinsic semiconductor layer 16, the semiconductor material of the at least one front doped semiconductor layer 18, and the semiconductor material of the at least one rear doped semiconductor layer 20 is made primarily or entirely of one or more of nanocrystalline and microcrystalline silicon, except for the n-dopant(s) and p-dopant(s) for the semiconductor material of the at least one front doped semiconductor layer 18 and the semiconductor material of the at least one rear doped semiconductor layer 20. As another example, both the intrinsic semiconductor material of the at least one rear intrinsic semiconductor layer 14 and the intrinsic semiconductor material of the at least one front intrinsic semiconductor layer 16 can be made primarily or entirely of one or more of nanocrystalline and microcrystalline silicon.

[0050] In embodiments, the heterojunction photovoltaic cell 10 further includes at least one front transparent conducting layer 26 and at least one rear transparent conducting layer 28. The at least one front transparent conducting layer 26 is disposed over the at least one front doped semiconductor layer 18. The at least one front doped semiconductor layer 18 is sandwiched between the at least one front transparent conducting layer 26 and the at least one front intrinsic semiconductor layer 16. The at least one rear transparent conducting layer 28 is disposed over the at least one rear doped semiconductor layer 20. The at least one rear doped semiconductor layer 20 is sandwiched between the at least one rear transparent conducting layer 28 and the at least one rear intrinsic semiconductor layer 14. Both the at least one front transparent conducting layer 26 and the at least one rear transparent conducting layer 28 are electrically conductive. In embodiments, either or both of the at least one front transparent conducting layer 26 and the at least one rear transparent conducting layer 28 is or includes a transparent conductive oxide, such as indium tin oxide (ITO). Other examples of a suitable transparent conductive oxide include zinc oxide (ZnO), aluminum-doped zinc oxide (AZO), tin oxide (SnO?), fluorine-doped tin oxide (FTO), and tungsten-doped indium oxide (IWO).

[0051] The at least one rear transparent conducting layer 28 on the at least one rear doped semiconductor layer 20 is not flush with an edge 112 of the semiconductor substrate 12 so as to form edge regions 42 over the at least one rear doped semiconductor layer 20 where the atAttorney Docket No. SP24-159PCT least one rear transparent conducting layer 28 is not present. Depositing the at least one rear transparent conducting layer 28 while maintaining the edge regions 42 free thereof helps prevent electrical contact between the at least one rear transparent conducting layer 28 and the at least one front transparent conducting layer 26. The edge regions 42 can be formed by masking the at least one rear doped semiconductor layer 20 near the edge 112 of the semiconductor substrate 12 while depositing the at least one rear transparent conducting layer 28.

[0052] In embodiments, the heterojunction photovoltaic cell 10 further includes one or more front contacts 30 and one or more rear contacts 32. The one or more front contacts 30 are disposed on the at least one front transparent conducting layer 26. The one or more rear contacts 32 are disposed on the at least one rear transparent conducting layer 28. The one or more front contacts 30 and the one or more rear contacts 32 can be made of silver, among other options.

[0053] Referring now to FIG. 3, a method 100 of making the heterojunction photovoltaic cell 10 of the present disclosure is herein described. The method 100 includes, a rear intrinsic semiconductor forming step 102, a front intrinsic semiconductor forming step 104, a front doped semiconductor forming step 106, and a rear doped semiconductor forming step 108. In embodiments, those steps 102-108 are performed in that order relative to each other. Other not mentioned steps can be performed in between the steps 102-108 that are mentioned.

[0054] The rear intrinsic semiconductor forming step 102 includes forming the at least one rear intrinsic semiconductor layer 14 over the rear primary surface 24 of the semiconductor substrate 12. In embodiments, the rear intrinsic semiconductor forming step 102 includes subjecting the semiconductor substrate 12 to a chemical vapor deposition (CVD), such as a plasma enhanced CVD process (PECVD), by which a precursor gas reacts on the rear primary surface 24 of the semiconductor substrate 12 to form the at least one rear intrinsic semiconductor layer 14. Other deposition methods can be utilized.

[0055] The front intrinsic semiconductor forming step 104 includes forming the at least one front intrinsic semiconductor layer 16 over the front primary surface 22 of the semiconductor substrate 12. In embodiments, the front intrinsic semiconductor forming step 104 includes subjecting the semiconductor substrate 12 to a CVD process, such as a PECVD process, by which a precursor gas reacts on the front primary surface 22 of the semiconductor substrate 12 to form the at least one front intrinsic semiconductor layer 16. Other deposition methods can be utilized.Attorney Docket No. SP24-159PCT

[0056] The front doped semiconductor forming step 106 includes forming the at least one front doped semiconductor layer 18 over the at least one front intrinsic semiconductor layer 16. Again, the front doped semiconductor forming step 106 can include a CVD process where a gas mixture including precursor semiconductor material (e.g., silane - SiTU) and precursor dopant material (e.g., phosphine - PH3 or diborane - B2H6) is added to initiate a chemical reaction to deposit the at least one front doped semiconductor layer 18. Other deposition methods can be utilized. In embodiments, the front intrinsic semiconductor forming step 104 and the front doped semiconductor forming step 106 can both occur in the same reaction enclosure.

[0057] The rear doped semiconductor forming step 108 includes forming the at least one rear doped semiconductor layer 20 over the at least one rear intrinsic semiconductor layer 14. Again, the rear doped semiconductor forming step 108 can include a CVD process similar to the front doped semiconductor forming step 106 but with the oppositely charged dopant. Other deposition methods can be utilized.

[0058] In embodiments, after the rear intrinsic semiconductor forming step 102 and the front intrinsic semiconductor forming step 104, the at least one front intrinsic semiconductor layer 16 and the at least one rear intrinsic semiconductor layer 14 at least partially envelope the semiconductor substrate 12. After the front intrinsic semiconductor forming step 104, at least a portion 110 of the at least one rear intrinsic semiconductor layer 14 can be sandwiched between the edge 112 of the semiconductor substrate 12 and the at least one front intrinsic semiconductor layer 16. On the other hand, if the rear intrinsic semiconductor forming step 102 is performed after the front intrinsic semiconductor forming step 104, then at least a portion (not separately illustrated) of the at least one front intrinsic semiconductor layer 16 can be sandwiched between the edge 112 of the semiconductor substrate 12 and the at least one rear intrinsic semiconductor layer 14.

[0059] In embodiments, the method 100 further includes a front transparent conductor forming step 114 and a rear transparent conductor forming step 116. The former can be performed before or after the latter. The front transparent conductor forming step 114 includes forming the at least one front transparent conducting layer 26 over the at least one front doped semiconductor layer 18. The rear transparent conductor forming step 116 includes forming the at least one rear transparent conducting layer 28 over the rear doped semiconductor layer 20. The front transparent conductor forming step 114 and the rear transparent conductor forming step 116 can include a physical vapor deposition (PVD) process where a source of a transparent conductor material (e.g., ITO) is bombarded with ions to cause atoms of the elements formingAttorney Docket No. SP24-159PCT the transparent conductor material (e.g., atoms of indium, tin, and oxygen) to eject from the source and then deposit on the at least one rear doped semiconductor layer 20 or the at least one front doped semiconductor layer 18, as the case may be (or both), as the layer of the transparent conductor material. Other deposition methods are envisioned.

[0060] The heterojunction photovoltaic cell 10 and the method 100 of the present disclosure address the problem set forth in the Background, among other problems, by reducing or eliminating the presence of amorphous silicon in the heterojunction photovoltaic cell 10. At least one of the intrinsic semiconductor material of the at least one rear intrinsic semiconductor layer 14, the intrinsic semiconductor material of the at least one front intrinsic semiconductor layer 16, the semiconductor material of the at least one front doped semiconductor layer 18, and the semiconductor material of the at least one rear doped semiconductor layer 20 comprises one or more of nanocrystalline and microcrystalline silicon. The presence of the one or more of nanocrystalline and microcrystalline silicon can mean the reduced presence of amorphous silicon by the same or similar amount. Nanocrystalline or microcrystalline silicon can permit the absence of amorphous silicon altogether. As the percentage of one or more of nanocrystalline and microcrystalline silicon in the heterojunction photovoltaic cell 10 increases, the percentage of amorphous silicon in the heterojunction photovoltaic cell 10 decreases. As the percentage of amorphous silicon in the heterojunction photovoltaic cell 10 decreases, the level of degradation caused by the presence of amorphous silicon ought to decrease as well.

[0061] Referring now to FIG. 4, a device 200 is herein described that can be utilized to form the heterojunction photovoltaic cell 10, such as via the method 100. The device 200 includes a loading and unloading mechanism 202 and a first reactor 204. The loading and unloading mechanism 202 accepts the semiconductor substrate 12 and moves the semiconductor substrate 12 to the first reactor 204. At the first reactor 204, the rear intrinsic semiconductor forming step 102 can be performed to deposit the at least one rear intrinsic semiconductor layer 14 over the rear primary surface 24 of the semiconductor substrate 12. The loading and unloading mechanism 202 can then remove the first workpiece that is the semiconductor substrate 12 with the at least one rear intrinsic semiconductor layer 14 from the first reactor 204 and transport the first workpiece to a conveyor 206.

[0062] The conveyor 206 can convey the first workpiece to another loading and unloading mechanism 208. The loading and unloading mechanism 208 retrieves the first workpiece from the conveyor 206 and deposits the first workpiece to a flipping system 210. The flipping system 210 flips the first workpiece to position the front primary surface 22 of the semiconductorAttorney Docket No. SP24-159PCT substrate 12 to accept further layers. The flipping system 210 then moves the first workpiece to a second reactor 212. At the second reactor 212, the front intrinsic semiconductor forming step 104 is performed to deposit the at least one front intrinsic semiconductor layer 16 over the front primary surface 22 of the semiconductor substrate 12. In the same second reactor 212, the front doped semiconductor forming step 106 is performed to form the at least one front doped semiconductor layer 18 over the at least one front intrinsic semiconductor layer 16. The result is a second workpiece. The flipping system 210 then retrieves the second workpiece from the second reactor 212 and flips the second workpiece so that the at least one rear intrinsic semiconductor layer 14 is positioned to accept a further layer. The loading and unloading mechanism 208 can then transport the second workpiece to the conveyor 206.

[0063] The conveyor 206 then conveys the second workpiece to another loading and unloading mechanism 214. The loading and unloading mechanism 214 retrieves the second workpiece from the conveyor 206 and deposits the second workpiece to a third reactor 216. At the third reactor 216, the rear doped semiconductor forming step 108 is performed to form the at least one rear doped semiconductor layer 20 over the at least one rear intrinsic semiconductor layer 14. The result is a third workpiece. The third workpiece can then be further processed according to the method 100 to form the heterojunction photovoltaic cell 10.

Claims

Attorney Docket No. SP24-159PCTCLAIM(S)What is claimed is:

1. A heterojunction photovoltaic cell comprising: a semiconductor substrate comprising a front primary surface, a rear primary surface, and a composition comprising a semiconductor material doped with an n-dopant or a p-dopant; a rear intrinsic semiconductor layer disposed over the rear primary surface of the semiconductor substrate, the at least one rear intrinsic semiconductor layer comprising an intrinsic semiconductor material; at least one front intrinsic semiconductor layer disposed over the front primary surface of the semiconductor substrate, the at least one front intrinsic semiconductor layer comprising an intrinsic semiconductor material; at least one front doped semiconductor layer disposed over the at least one front intrinsic semiconductor layer, the at least one front doped semiconductor layer comprising a semiconductor material doped with an n-dopant or a p-dopant; and at least one rear doped semiconductor layer disposed over the at least one rear intrinsic semiconductor layer, the at least one rear doped semiconductor layer comprising a semiconductor material doped with an n-dopant or a p-dopant, wherein, at least one of the intrinsic semiconductor material of the at least one rear intrinsic semiconductor layer, the intrinsic semiconductor material of the at least one front intrinsic semiconductor layer, the semiconductor material of the at least one front doped semiconductor layer, and the semiconductor material of the at least one rear doped semiconductor layer comprises one or more of nanocrystalline and microcrystalline silicon.

2. The heterojunction photovoltaic cell of claim 1, wherein the semiconductor material of the semiconductor substrate comprises crystalline silicon.

3. The heterojunction photovoltaic cell of any one of claims 1-2, wherein the semiconductor material of the semiconductor substrate comprises one or more of germanium, gallium arsenide, cadmium telluride, copper indium gallium selenide, and amorphous silicon.

4. The heterojunction photovoltaic cell of any one of claims 1-3, whereinAttorney Docket No. SP24-159PCT the semiconductor material of the composition of the semiconductor substrate is doped with an n-dopant.

5. The heterojunction photovoltaic cell of any one of claims 1-3, wherein the semiconductor material of the composition of the semiconductor substrate is doped with a p-dopant.

6. The heterojunction photovoltaic cell of any one of claims 1-3, wherein the semiconductor material of the semiconductor substrate is doped with a p-dopant, the semiconductor material of the at least one front doped semiconductor layer is doped with a p-dopant, and the semiconductor material of the at least one rear doped semiconductor layer is doped with an n-dopant.

7. The heterojunction photovoltaic cell of any one of claims 1-3, wherein the semiconductor material of the semiconductor substrate is doped with an n-dopant, the semiconductor material of the at least one front doped semiconductor layer is doped with an n-dopant, and the semiconductor material of the at least one rear doped semiconductor layer is doped with a p-dopant.

8. The heterojunction photovoltaic cell of any one of claims 1-7, wherein the intrinsic semiconductor material of the at least one rear intrinsic semiconductor layer comprises one or more of nanocrystalline and microcrystalline silicon.

9. The heterojunction photovoltaic cell of any one of claims 1-8, wherein the intrinsic semiconductor material of the at least one front intrinsic semiconductor layer comprises one or more of nanocrystalline and microcrystalline silicon.

10. The heterojunction photovoltaic cell of any one of claims 1-9, wherein the semiconductor material of the at least one front doped semiconductor layer comprises one or more of nanocrystalline and microcrystalline silicon.

11. The heterojunction photovoltaic cell of any one of claims 1-10, whereinAttorney Docket No. SP24-159PCT the semiconductor material of the at least one rear doped semiconductor layer comprises one or more of nanocrystalline and microcrystalline silicon.

12. The heterojunction photovoltaic cell of any one of claims 1-11, wherein the n-dopant is one or more of phosphorous, arsenic, bismuth, and antimony.

13. The heterojunction photovoltaic cell of any one of claims 1-12, wherein the p-dopant is one or more of boron, aluminum, gallium, and indium.

14. The heterojunction photovoltaic cell of any one of claims 1-13, wherein at least one of the intrinsic semiconductor material of the at least one rear intrinsic semiconductor layer, the intrinsic semiconductor material of the at least one front intrinsic semiconductor layer, the semiconductor material of the at least one front doped semiconductor layer, and the semiconductor material of the at least one rear doped semiconductor layer is substantially free of amorphous silicon.

15. The heterojunction photovoltaic cell of any one of claims 1-14 further comprising: at least one front transparent conducting layer disposed over the at least one front doped semiconductor layer; and at least one rear transparent conducting layer disposed over the at least one rear doped semiconductor layer.

16. The heterojunction photovoltaic cell of claim 15, wherein at least one of the at least one front transparent conducting layer and the at least one rear transparent conducting layer comprise a transparent conductive oxide.

17. The heterojunction photovoltaic cell of claim 16, wherein the transparent conductive oxide comprises one or more of indium tin oxide (ITO), zinc oxide (ZnO), aluminum-doped zinc oxide (AZO), tin oxide (SnO?), fluorine-doped tin oxide (FTO), and tungsten-doped indium oxide (IWO).

18. The heterojunction photovoltaic cell of any one of claims 15-17, wherein the at least one rear transparent conducting layer on the at least one rear doped semiconductor layer is not flush with the edge of the doped semiconductor substrate so as toAttorney Docket No. SP24-159PCT form edge regions over the at least one rear doped semiconductor layer where the at least one rear transparent conducting layer is not present.

19. The heterojunction photovoltaic cell of any one of claims 15-18 further comprising: front contacts disposed on the at least one front transparent conducting layer; and rear contacts disposed on the at least one rear transparent conducting layer.

20. A method of making a heterojunction photovoltaic cell comprising: a rear intrinsic semiconductor forming step comprising forming at least one rear intrinsic semiconductor layer over a rear primary surface of a semiconductor substrate, the semiconductor substrate comprising a semiconductor material doped with an n-dopant or a p- dopant and the at least one rear intrinsic semiconductor layer comprising an intrinsic semiconductor material; a front intrinsic semiconductor forming step comprising forming at least one front intrinsic semiconductor layer over a front primary surface of the semiconductor substrate, the at least one front intrinsic semiconductor layer comprising an intrinsic semiconductor material; a front doped semiconductor forming step comprising forming at least one front doped semiconductor layer over the at least one front intrinsic semiconductor layer, the at least one front doped semiconductor layer comprising a semiconductor material doped with an n-dopant or a p-dopant; and a rear doped semiconductor forming step comprising forming at least one rear doped semiconductor layer over the at least one rear intrinsic semiconductor layer, the at least one rear doped semiconductor layer comprising a semiconductor material doped with an n-dopant or a p-dopant, wherein, at least one of the intrinsic semiconductor material of the at least one rear intrinsic semiconductor layer, the intrinsic semiconductor material of the at least one front intrinsic semiconductor layer, the semiconductor material of the at least one front doped semiconductor layer, and the semiconductor material of the at least one rear doped semiconductor layer comprises one or more of nanocrystalline and microcrystalline silicon.

21. The method of claim 20, wherein the rear intrinsic semiconductor forming step, the front intrinsic semiconductor forming step, the front doped semiconductor forming step, and the rear doped semiconductor forming step are performed in that order relative to each other.Attorney Docket No. SP24-159PCT22. The method of any one of claims 20-21, wherein the front intrinsic semiconductor forming step comprises forming the at least one front intrinsic semiconductor layer via a plasma enhanced chemical vapor deposition (PECVD) method, and the rear intrinsic semiconductor forming step comprises forming the at least one rear intrinsic semiconductor layer via a PECVD method.

23. The method of any one of claims 20-22, wherein after the front intrinsic semiconductor forming step and the rear intrinsic semiconductor forming step, the at least one front intrinsic semiconductor layer and the at least one rear intrinsic semiconductor layer at least partially envelope the semiconductor substrate.

24. The method of any one of claims 20-23 further comprising, in no particular order: a front transparent conductor forming step comprising forming at least one front transparent conducting layer over the at least one front doped semiconductor layer; and a rear transparent conductor forming step comprising forming at least one rear transparent conducting layer over the at least one rear doped semiconductor layer.

25. The method of any one of claims 20-24, wherein the front intrinsic semiconductor forming step and the front doped semiconductor forming step occur in the same reaction enclosure.

26. The method of any one of claims 20-25, wherein at least one of the intrinsic semiconductor material of the at least one rear intrinsic semiconductor layer, the intrinsic semiconductor material of the at least one front intrinsic semiconductor layer, the semiconductor material of the at least one front doped semiconductor layer, and the semiconductor material of the at least one rear doped semiconductor layer is substantially free of amorphous silicon.

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