Array substrate, display panel, and display device

Abstract

An array substrate, a display panel, and a display device. The array substrate comprises a plurality of sub-pixels, and at least one of the plurality of sub-pixels comprises a first transistor; the array substrate further comprises a base substrate, a gate layer, an active layer, and a light-shielding conductive layer; the gate layer comprises a gate pattern of the first transistor; the active layer comprises an active layer pattern of the first transistor; the light-shielding conductive layer comprises a first pattern and a second pattern; the orthographic projection of the active layer pattern of the first transistor on the base substrate is located within the orthographic projection of the first pattern on the base substrate; the distance between a boundary of the orthographic projection of the first pattern on the base substrate and a boundary of the orthographic projection of the active layer pattern of the first transistor on the base substrate falls within a set spacing range; the transmittance of the first pattern is less than or equal to that of the second pattern; and the second pattern is connected to the gate pattern of the first transistor.

Description

Array substrate, display panel and display device

[0001] The present application claims priority to the Chinese patent application No. 202411239686.X, filed on September 04, 2024, the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0002] The present disclosure relates to the technical field of display, and in particular, to an array substrate, a display panel and a display device. BACKGROUND

[0003] Liquid Crystal Display (LCD) has the characteristics of small volume, low power consumption, thinness, no radiation, etc., and has been widely used in the display field. With the development of display technology, its display quality is also continuously improved with the progress of manufacturing process technology. SUMMARY

[0004] In one aspect, an array substrate is provided. The array substrate includes a plurality of sub-pixels, at least one of the plurality of sub-pixels includes a first transistor; the array substrate includes a substrate, a gate layer, an active layer and a light-shielding conductive layer. The gate layer is disposed on one side of the substrate, and the gate layer includes a gate pattern of the first transistor; the active layer is disposed on a side of the gate layer away from the substrate, and the active layer includes an active layer pattern of the first transistor; the light-shielding conductive layer is disposed on a side of the active layer away from the substrate, and the light-shielding conductive layer includes a light-shielding conductive pattern, the light-shielding conductive pattern includes a first pattern and a second pattern, a normal projection of the active layer pattern of the first transistor on the substrate is located within a normal projection of the first pattern on the substrate, and a distance between a boundary of the normal projection of the first pattern on the substrate and a boundary of the normal projection of the active layer pattern of the first transistor on the substrate is within a set distance range; a transmittance of the first pattern is less than or equal to a transmittance of the second pattern; and the second pattern is connected with the gate pattern of the first transistor.

[0005] In some embodiments, the light-shielding conductive layer includes a first sub-layer, the first pattern and the second pattern are located in the first sub-layer; a material of the second pattern is transparent conductive oxide, and a material of the first pattern is blackened transparent conductive oxide; the blackened transparent conductive oxide is obtained by blackening treatment of the transparent conductive oxide, wherein the process condition of weakened light transmittance is that the source power ranges from 5kW to 7kW, the hydrogen flow rate ranges from 70000sccm to 80000sccm, the working pressure ranges from 900mt to 1200mt, and the processing time ranges from 10S to 20S.

[0006] In some embodiments, the light-shielding conductive layer comprises a first sub-layer, and the first pattern and the second pattern are located in the first sub-layer; the material of the first pattern and the second pattern is metal, and the transmittance of the first pattern is equal to the transmittance of the second pattern.

[0007] In some embodiments, the light-shielding conductive layer comprises a first sub-layer, and the first pattern and the second pattern are located in the first sub-layer; the material of the second pattern is transparent conductive oxide, and the material of the first pattern is metal or organic light-shielding material.

[0008] In some embodiments, the light-shielding conductive layer comprises a first sub-layer and a second sub-layer, and the second sub-layer is located on the side of the first sub-layer away from the substrate; the transmittance of the second sub-layer is less than the transmittance of the first sub-layer; the first pattern comprises a first sub-pattern located in the first sub-layer and a second sub-pattern located in the second sub-layer, and the second pattern is located in the first sub-layer.

[0009] In some embodiments, the material of the first sub-layer is transparent conductive oxide, and the material of the second sub-layer is metal or organic light-shielding material.

[0010] In some embodiments, the set interval range is 1 μm to 2.5 μm.

[0011] In some embodiments, the sub-pixel further comprises a pixel electrode and a common electrode; the light-shielding conductive layer comprises a first sub-layer, and the first sub-layer further comprises a pixel electrode pattern; the gate layer further comprises a common electrode pattern and a common signal line, the material of the common electrode pattern is transparent conductive material, and the common signal line is connected with the common electrode pattern; the pixel electrode pattern overlaps with the common signal line.

[0012] In some embodiments, the gate layer comprises a gate line, the gate pattern of the first transistor is the part of the gate line overlapping with the active layer pattern of the first transistor; the second pattern is connected with the gate line.

[0013] In some embodiments, the array substrate comprises a gate driving circuit, the gate driving circuit comprises at least one second transistor and a storage capacitor; the gate layer further comprises a gate control line, the gate control line comprises a gate pattern of the second transistor; the active layer further comprises an active layer pattern of the second transistor; the array substrate further comprises a source-drain metal layer disposed on a side of the active layer away from the substrate, the source-drain metal layer is in contact with the active layer, and the source-drain metal layer comprises a first plate pattern of the storage capacitor; the light-shielding conductive layer further comprises a conductive pattern, the conductive pattern overlaps with the active layer pattern of the second transistor and overlaps with the first plate pattern of the storage capacitor; the conductive pattern is connected with the gate control line; and the gate control line overlaps with the first plate pattern of the storage capacitor.

[0014] In some embodiments, a distance between the first plate pattern of the storage capacitor and the conductive pattern is equal to a distance between the first plate pattern of the storage capacitor and the gate control line.

[0015] In another aspect, a display panel is provided, comprising the array substrate of any one of the embodiments of the above aspect.

[0016] In some embodiments, the display panel further comprises a color filter substrate disposed on the array substrate and at least one spacer disposed between the array substrate and the color filter substrate; the spacer comprises a first spacer, the first spacer is disposed on a side of the second pattern and is in contact with the second pattern.

[0017] In some embodiments, the spacer comprises a second spacer, a height of the first spacer is higher than a height of the second spacer; and the second spacer is disposed on a side of the second pattern.

[0018] In another aspect, a display device is provided, comprising the display panel of any one of the embodiments of the above another aspect and a backlight module; the display panel comprises a display side and a non-display side, the backlight module is disposed on the non-display side of the display panel, and the backlight module is configured to provide a backlight source. BRIEF DESCRIPTION OF DRAWINGS

[0019] In order to more clearly illustrate the technical solutions in the present disclosure, the following will briefly introduce the drawings needed to be used in some embodiments of the present disclosure. Obviously, the drawings described in the following description are only the drawings of some embodiments of the present disclosure, and other drawings can also be obtained by those skilled in the art according to these drawings. In addition, the drawings described in the following description can be regarded as schematic diagrams, and are not limited to the actual size, actual process, actual time sequence, etc. of the products involved in the embodiments of the present disclosure.

[0020] FIG. 1 is a plan view of an array substrate according to some embodiments of the present disclosure;

[0021] FIG. 2A is a structure view of a sub-pixel according to some embodiments of the present disclosure;

[0022] FIG. 2B is a stack structure view of a light-shielding conductive layer and an active layer in a sub-pixel according to some embodiments of the present disclosure;

[0023] FIG. 3A is a cross-sectional structure view of an array substrate according to some embodiments of the present disclosure;

[0024] FIG. 3B is a cross-sectional structure view of an array substrate according to some embodiments of the present disclosure;

[0025] FIG. 3C is a graph of indium tin oxide transmittance vs. hydrogen flow rate according to some embodiments of the present disclosure;

[0026] FIG. 3D is a scanning electron microscope (SEM) test structure view of an array substrate according to some embodiments of the present disclosure;

[0027] FIG. 3E is a flowchart of a forming step of a first pattern and a second pattern according to some embodiments of the present disclosure;

[0028] FIG. 4A is a cross-sectional structure view of an array substrate according to some embodiments of the present disclosure;

[0029] FIG. 4B is a cross-sectional structure view of an array substrate according to some embodiments of the present disclosure;

[0030] FIG. 5A is a cross-sectional structure view of an array substrate according to some embodiments of the present disclosure;

[0031] FIG. 5B is a cross-sectional structure view of an array substrate according to some embodiments of the present disclosure;

[0032] FIG. 6A is a cross-sectional structure view of an array substrate according to some embodiments of the present disclosure;

[0033] FIG. 6B is a cross-sectional structure view of an array substrate according to some embodiments of the present disclosure;

[0034] FIG. 7A is a cross-sectional structure view of an array substrate according to some embodiments of the present disclosure;

[0035] FIG. 7B is a cross-sectional structure view of an array substrate according to some embodiments of the present disclosure;

[0036] FIG. 8A is a cross-sectional structure view of an array substrate according to some embodiments of the present disclosure;

[0037] FIG. 8B is a cross-sectional structure diagram of an array substrate, according to some embodiments of the present disclosure;

[0038] FIG. 9A is a plan structure diagram of an array substrate, according to some embodiments of the present disclosure;

[0039] FIG. 9B is a cross-sectional structure diagram of an array substrate, according to some embodiments of the present disclosure;

[0040] FIG. 9C is a circuit structure diagram of an array substrate, according to some embodiments of the present disclosure;

[0041] FIG. 10A is a band structure diagram of a double-gate transistor in a non-energized state, according to some embodiments of the present disclosure;

[0042] FIG. 10B is a band structure diagram of a double-gate transistor in an on state, according to some embodiments of the present disclosure;

[0043] FIG. 10C is a band structure diagram of a bottom-gate transistor in an on state, according to some embodiments of the present disclosure;

[0044] FIG. 10D is a band structure diagram of a double-gate transistor in an off state, according to some embodiments of the present disclosure;

[0045] FIG. 10E is a band structure diagram of a bottom-gate transistor in an off state, according to some embodiments of the present disclosure;

[0046] FIG. 11A is a plan structure diagram of a display panel, according to some embodiments of the present disclosure;

[0047] FIG. 11B is a cross-sectional structure diagram of a display panel, according to some embodiments of the present disclosure;

[0048] FIG. 12A is a plan structure diagram of a display panel, according to some embodiments of the present disclosure;

[0049] FIG. 12B is a cross-sectional structure diagram of a display panel, according to some embodiments of the present disclosure;

[0050] FIG. 13A is a structure diagram of a spacer being displaced by an external force, according to some embodiments of the present disclosure;

[0051] FIG. 13B is a structure diagram of a spacer being displaced by an external force, according to some embodiments of the present disclosure;

[0052] FIG. 14 is a cross-sectional structure diagram of a display panel, according to some embodiments of the present disclosure;

[0053] FIG. 15 is a plan structure diagram of a display device, according to some embodiments of the present disclosure;

[0054] FIG. 16 is a structural diagram of a display device according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0055] The technical solutions in some embodiments of the present disclosure will be clearly and completely described below with reference to the drawings. Obviously, the described embodiments are only some of the embodiments of the present disclosure, but not all the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by those of ordinary skill in the art belong to the scope of protection of the present disclosure.

[0056] Unless otherwise required by context, the term "comprise" and other forms of the term "comprise", such as "comprises" and "comprising", are used in the sense of "including, but not limited to", and permit the inclusion of additional elements without departing from the scope of the concept disclosed. In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "example", "specific example" or "some examples" are intended to mean that the specific features, structures, materials or characteristics related to the embodiment or example include in at least one embodiment or example of the present disclosure. The illustrative representation of the above terms does not necessarily mean the same embodiment or example. In addition, the specific features, structures, materials or characteristics described can be included in any one or more embodiments or examples in any appropriate manner.

[0057] Hereinafter, the terms "first" and "second" are used only for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined with "first" and "second" can explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, the meaning of "a plurality of" is two or more, unless otherwise specified.

[0058] In describing some embodiments, "coupled" and "connected," along with their derivatives, can be used. It should be understood that these terms are not intended as synonyms for each other. Rather, "connected" can be used to indicate that two or more elements are in direct physical or electrical contact with each other. "Coupled" can be used to indicate that two or more elements are in either physical or electrical contact with each other, even at a remote location from each other. The term "coupled" as used herein encompasses the case where one or more intervening elements can exist. The embodiments disclosed herein are not necessarily limited to the details of the embodiments described.

[0059] "A, B, and C at least one of" is synonymous with "at least one of A, B, or C," and includes the following combinations: A only, B only, C only, a combination of A and B, a combination of A and C, a combination of B and C, and a combination of A, B, and C.

[0060] "A and / or B" includes the following three combinations: A alone, B alone, and a combination of A and B.

[0061] As used herein, the term "if' can, optionally, be construed to mean "when" or "when a or when a determined," or "in response to a determination" or "in response to detecting," according to context. Similarly, the phrase "if it is determined" or "if [a stated condition or event] is detected" can, optionally, be construed to mean "upon it being determined" or "upon the occurrence of [the stated condition or event] "or "in response to the determination," or "in response to the occurrence [of the stated condition or event]," according to context.

[0062] The use of "adapted to" or "configured to," as used herein, means an open and inclusive language that does not exclude additional tasks or steps.

[0063] Additionally, the use of "based on" means an open and inclusive language that does not exclude additional conditions or values.

[0064] As used herein, "about," "approximately," or "circa" includes the recited value and the average value within an acceptable range of deviation from the stated value, as determined by one of ordinary skill in the art considering the measurement in question and the error in measuring the particular quantity (i.e., the limitations of the measurement system).

[0065] As used herein, "parallel," "perpendicular," "equal" include the recited condition and conditions that are approximately the recited condition, the range of approximation being within an acceptable deviation range as determined by one of ordinary skill in the art taking into account the measurement being discussed and the error associated with the measurement of the particular quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallel and near parallel, where the acceptable deviation range for near parallel can be, for example, within 5°; "perpendicular" includes absolute perpendicular and near perpendicular, where the acceptable deviation range for near perpendicular can also be, for example, within 5°. "Equal" includes absolute equality and near equality, where the acceptable deviation range for near equality can be, for example, a difference between the two that is less than or equal to 5% of either.

[0066] It will be understood that when a layer or element is referred to as being "on" another layer or substrate, it can be directly on the other layer or substrate or intervening layers can also be present.

[0067] Exemplary embodiments are described herein with reference to cross-sectional and / or plan view illustrations that are idealized examples. In the interest of clarity, not all of the scale of the layers and regions can be shown in the drawings, which can distort the dimensions of the layers and regions. Thus, the exemplary embodiments should not be construed as limited to the precise shapes and dimensions illustrated in the drawings, but rather, the exemplary embodiments are to include shapes and dimensions that are within the scope of what is illustrated in the drawings. For example, etched regions shown as rectangular will typically have curved features. Thus, the regions illustrated in the drawings are schematic and not intended to be limiting of the scope of the exemplary embodiments.

[0068] The display device includes a plurality of sub-pixels, a plurality of gate lines and a gate driving circuit, the gate driving circuit is connected with the plurality of gate lines, the gate driving circuit outputs a gate signal to the plurality of gate lines, the plurality of gate lines is connected with the plurality of sub-pixels, the gate line transmits the gate signal, controls the sub-pixel connected therewith to turn on or turn off, the writing of the data signal is carried out when the sub-pixel is turned on, the sub-pixel emits light, and the display device realizes display. The gate signal output by the gate driving circuit has a gate opening voltage VGH and a gate closing voltage VGL, in the case that the voltage value of the gate opening voltage VGH and the voltage value of the gate closing voltage VGL meet the working voltage range, the sub-pixel can normally turn on or turn off under the control of the gate signal, the display device can normally display, if the voltage value of the gate opening voltage VGH and the voltage value of the gate closing voltage VGL do not meet the working voltage range, the sub-pixel cannot normally turn on or turn off under the control of the gate signal, thereby affecting the normal display of the display device, which may result in the problem of poor display.

[0069] With the increasingly wide application of display devices in outdoor, the display device applications including electronic signs, monitors, multimedia displays, etc. generally have the use requirements of wide temperature, high brightness and uninterrupted work. At present, the existing display devices frequently have the problems of screen flickering and the human eye visible crosstalk of black and white in dark state after long time outdoor use. The reason is that in the more severe outdoor use environment, such as high and low temperature, higher backlight brightness, uninterrupted lighting, etc., the display device itself deteriorates at a faster speed, thereby causing the working voltage range of the gate-on voltage VGH and the gate-off voltage VGL to change, and the voltage values of the gate-on voltage VGH and the gate-off voltage VGL cannot meet the working voltage range under outdoor conditions.

[0070] In view of the above-mentioned problem of frequent screen flickering, the present inventors finally determine that the positive bias of the threshold voltage of the transistor responsible for output and cascade in the gate drive circuit causes the current output by the transistor to be low, thereby causing the gate-on voltage VGH of the gate signal output by the gate drive circuit to be low, which cannot meet the requirement of normally opening the sub-pixel in the display area. In order to solve this problem, the process parameters related to the transistor characteristics need to be adjusted so that the gate-on voltage VGH meets the voltage requirement of controlling the normal opening of the sub-pixel in the display area.

[0071] On the other hand, in view of the above-mentioned problem of the human eye visible crosstalk of black and white in dark state in some areas, the present inventors finally determine that the negative bias of the threshold voltage of the transistor in the sub-pixel causes the leakage current to increase, and the data line voltage feeding into the pixel electrode increases, which causes the gate-off voltage VGL within the original working voltage range to be unable to meet the requirement of turning off the transistor in the sub-pixel in the display area. In order to solve this problem, the process parameters related to the transistor characteristics need to be adjusted so that the gate-off voltage VGL meets the voltage requirement of controlling the normal closing of the sub-pixel.

[0072] In summary, the characteristic parameters of the transistor in the display device need to be optimized so that the voltage range of the gate-on voltage and the gate-off voltage can meet the above-mentioned more severe outdoor use conditions.

[0073] Based on this, some embodiments of the present disclosure provide an array substrate, a display panel and a display device. By adjusting the structure of part of the film layers in the array substrate, the light shielding position is reasonably set, and the double-gate structure of the transistor is set, thereby avoiding the problem of poor display caused by complex environment, improving the working voltage range of the gate signal voltage, and improving the reliability of the display device.

[0074] The array substrate, the display panel and the display device provided by the present disclosure are introduced below respectively.

[0075] As shown in FIGS. 2A, 2B and 3A, the present disclosure provides various embodiments of the array substrate. In order to clearly describe the film layer structure of the array substrate, the film layers included in the array substrate are listed as follows. The array substrate 10 includes a substrate substrate 101, and a gate layer 102, a first insulating layer 103, an active layer 104, a source-drain metal layer 105, a second insulating layer 106 and a light-shielding conductive layer 107 which are sequentially stacked on the substrate substrate 101.

[0076] Exemplarily, the substrate substrate 101 can be a flexible substrate substrate 101 such as a Polyethyleneterephthalate (PET) film, a Polyimide (PI) film, etc., or a rigid substrate substrate 101 such as a glass substrate substrate 101.

[0077] Exemplarily, the first insulating layer can be made of silicon oxide SiOx, silicon nitride SiNx, silicon oxynitride SiON, etc., and can be a single-layer, double-layer or multi-layer structure to achieve the effect of blocking water and oxygen and blocking alkali ions.

[0078] Exemplarily, the material of the active layer 104 includes any one of low-temperature polysilicon, indium gallium zinc oxide or low-temperature polysilicon oxide.

[0079] The array substrates mentioned in the following embodiments all conform to the above film layer arrangement. The film layer structures are introduced in detail as follows.

[0080] In some embodiments, as shown in FIG. 1, the array substrate 10 includes a plurality of sub-pixels PX, and at least one of the plurality of sub-pixels PX includes a first transistor T1.

[0081] Exemplarily, as shown in FIG. 1, the array substrate 10 comprises a display area AA, wherein the display area AA is provided with a plurality of sub-pixels PX arranged in multiple rows and multiple columns, each of the sub-pixels PX comprising a first transistor T1. The display area AA further comprises a plurality of gate lines GT and a plurality of common signal lines COM arranged along the row direction X, and a plurality of data signal lines DT arranged along the column direction, wherein each of the sub-pixels PX is electrically connected with one of the gate lines GT, one of the common signal lines COM and one of the data signal lines DT. Referring to FIG. 2A, which is a structural diagram of one sub-pixel, it can be obtained from FIG. 2A that the sub-pixel PX is connected with the gate line GT, the common signal line COM and the data signal line DT respectively, wherein the gate line GT, the common signal line COM and the data signal line DT provide a gate signal, a common electrode signal and a data signal for the sub-pixel PX respectively.

[0082] Continuing to refer to FIG. 1, each of the sub-pixels PX comprises a liquid crystal capacitor Clc and a storage capacitor Cst, wherein the liquid crystal capacitor Clc is an equivalent capacitor of the liquid crystal which is a capacitive material, and the size of the liquid crystal capacitor Clc can be 0.1 pF. However, during the operation of each of the sub-pixels PX, parasitic capacitances such as Cpg, Cpd, Cgd and Cgs will inevitably exist, which will cause certain interference to the transmission of the voltage signal and affect the display. The liquid crystal capacitor Clc cannot well keep the voltage signal transmitted thereby, and thus it is necessary to work in cooperation with the storage capacitor Cst to better keep the voltage signal transmitted thereby, so as to ensure the continuous display of the picture.

[0083] Referring to FIGS. 3A-8B and FIG. 2B, wherein FIGS. 3A, 4A, 5A, 6A, 7A, 8A are sectional structure diagrams obtained by sectioning along the section line CC' in FIG. 2A in different schemes, and FIGS. 3B, 4B, 5B, 6B, 7B, 8B are sectional structure diagrams obtained by sectioning along the section line DD' in FIG. 2A in different schemes. The array substrate 10 comprises a substrate substrate 101, a gate layer 102, an active layer 104, and a light-shielding conductive layer 107. The gate layer 102 is disposed on one side of the substrate substrate 101, the active layer 104 is disposed on the side of the gate layer 102 away from the substrate substrate 101, and the light-shielding conductive layer 107 is disposed on the side of the active layer 104 away from the substrate substrate 101. The gate layer 102 comprises a gate pattern 1021 of a first transistor T1, the active layer 104 comprises an active layer pattern 1041 of the first transistor T1, the light-shielding conductive layer 107 comprises a light-shielding conductive pattern 1071, the light-shielding conductive pattern 1071 comprises a first pattern 1071a and a second pattern 1071b, the active layer pattern 1041 of the first transistor T1 is located in the orthographic projection of the first pattern 1071a on the substrate substrate 101, and the distance between the boundary of the orthographic projection of the first pattern 1071a on the substrate substrate 101 and the boundary of the orthographic projection of the active layer pattern 1041 of the first transistor T1 on the substrate substrate 101 is within a set interval S. The transmittance of the first pattern 1071a is less than or equal to the transmittance of the second pattern 1071b. The second pattern 1071b is connected with the gate pattern 1021 of the first transistor T1.

[0084] Exemplarily, the first pattern 1071a has the function of light blocking.

[0085] It should be noted that the transmittance of the first pattern 1071a is less than or equal to the transmittance of the second pattern 1071b, that is, the first pattern 1071a and the second pattern 1071b can be prepared by patterning the same material, and for the area of the first pattern 1071a, the first pattern 1071a can be obtained by light transmittance weakening treatment, so that the transmittance of the first pattern 1071a is less than the transmittance of the second pattern 1071b; or the first pattern 1071a and the second pattern 1071b can be prepared by patterning the same material, and without other process treatment, the transmittance of the first pattern 1071a is equal to the transmittance of the second pattern 1071b; or the first pattern 1071a and the second pattern 1071b can be prepared by patterning different materials, so that the transmittance of the first pattern 1071a is less than the transmittance of the second pattern 1071b.

[0086] In some embodiments, referring to FIG. 3A, FIG. 3B, FIG. 4A and FIG. 4B, the light-shielding conductive layer 107 comprises a first sub-layer 107a, and the first pattern 1071a and the second pattern 1071b are located on the first sub-layer 107a. For example, referring to FIG. 3A, FIG. 3B, FIG. 4A and FIG. 4B, the light-shielding conductive layer 107 comprises one film layer, and the first pattern 1071a and the second pattern 1071b are located on the same layer, that is, the first pattern 1071a and the second pattern 1071b can be prepared by patterning the same material.

[0087] In some embodiments, referring to FIG. 3A and FIG. 3B, the material of the second pattern is a transparent conductive oxide, and the material of the first pattern is a blackened transparent conductive oxide; the transmittance of the first pattern 1071a is less than that of the second pattern 1071b.

[0088] In some embodiments, the material of the first pattern 1071a is a blackened transparent conductive oxide; the blackened transparent conductive oxide is a transparent conductive oxide obtained through blackening treatment, wherein the process condition for reducing light transmittance is that the source power ranges from 5 kW to 7 kW, the hydrogen flow rate ranges from 70,000 to 80,000 sccm, the working pressure ranges from 900 to 1,200 mT, and the processing time ranges from 10 to 20 s.

[0089] It should be noted that in the process of preparing the first pattern 1071a under the above process conditions, the blackening treatment effect is good, and the first pattern 1071a meeting the transmittance requirements of the present application can be prepared according to the need for reducing light transmittance. For example, referring to FIG. 3C and FIG. 3D, FIG. 3C shows the transmittance of a transparent conductive oxide, for example, indium tin oxide (ITO), versus the hydrogen flow rate. As can be seen from the figure, when the hydrogen flow rate is less than 70,000 sccm, the transmittance of the indium tin oxide increases, that is, the blackening effect will deteriorate sharply during the blackening treatment. In combination with FIG. 3D, FIG. 3D is an electron microscope test diagram when the hydrogen flow rate exceeds 80,000 sccm. As shown in FIG. 3D, the film layers stacked from bottom to top in FIG. 3D are the substrate 101, the gate layer 102, the first insulating layer 103, the second insulating layer 106, and the light-shielding conductive layer 107. For example, the material of the gate layer 102 is indium tin oxide, and as shown in the circle position in the figure, indium or indium oxide (In / InOx) particles will be precipitated on the surface of the gate layer 102 at this time. Referring to FIG. 3D, for example, the substrate 101 is provided with silicon nitride, and the precipitated indium or indium oxide (In / InOx) particles will corrode the silicon nitride and expose the substrate 101. Therefore, by controlling the process conditions within the above range, the light transmittance reduction treatment (blackening treatment) effect is better, and other film layers will not be damaged.

[0090] Exemplarily, the material of the transparent conductive oxide can be, but is not limited to, ITO (Indium Tin Oxide), FTO (SnO2:F), ATO (Sn2O:Sb), etc.

[0091] The forming steps S1-S7 of the first pattern 1071a and the second pattern 1071b are exemplarily described below with the transparent conductive oxide as an example. As shown in FIG. 3E, the forming steps S1-S7 are specifically as follows:

[0092] S1, an initial first sub-layer 107a' of the light-shielding conductive layer 107 is formed on the second insulating layer 106.

[0093] Exemplarily, the initial first sub-layer 107a' can be formed by depositing the transparent conductive oxide material on the second insulating layer 106.

[0094] It should be noted that the initial first sub-layer 107a' is a whole layer of film laid on the second insulating layer 106, and the initial first sub-layer 107a' is not subjected to a patterning process.

[0095] S2, a photoresist layer is formed on the initial first sub-layer 107a'.

[0096] S3, the photoresist layer is exposed and developed by using a mask, to obtain a patterned photoresist layer.

[0097] It should be noted that the mask includes a plurality of openings, a half-tone area and a full-tone area, the part of the photoresist layer corresponding to the plurality of openings is removed, and part of the initial first sub-layer 107a' is exposed. The part of the photoresist layer corresponding to the half-tone area and the full-tone area is retained, to form the patterned photoresist layer. In the patterned photoresist layer, the thickness of the part corresponding to the half-tone area is less than the thickness of the part corresponding to the full-tone area, and the part corresponding to the half-tone area and the part corresponding to the full-tone area are connected.

[0098] The part of the patterned photoresist layer corresponding to the half-tone area covers the active layer of the first transistor and the region of the active layer of the first transistor with a set distance range.

[0099] S4, the initial first sub-layer 107a' exposed to the developed photoresist layer is etched, to form an initial light-shielding conductive pattern 1071'.

[0100] S5, the patterned photoresist layer is thinned until the part of the patterned photoresist layer corresponding to the half-tone area is removed, to expose the first part (corresponding to the first pattern) of the initial light-shielding conductive pattern 1071'.

[0101] Exemplarily, the thinning of the photoresist layer can be performed by wet etching, dry etching or laser etching. In this example, dry etching, also known as photoresist ashing, is performed in an ECCP (Enhanced Cathode Coupling Plasma) dry etching device using NF3and O2as working gases, and the process conditions are as follows: source power / Bias power is 12 kW / 10 kW, the flow rate of NF3 / O2is 1500 / 10000 sccm, and the working pressure is 40 mt.

[0102] It should be noted that, since the thickness of the part of the patterned photoresist layer corresponding to the half-tone area is less than the thickness of the part corresponding to the full-tone area, when the photoresist layer is thinned until the first part of the initial light-shielding conductive pattern 1071' is exposed, the second part (corresponding to the second pattern) of the initial light-shielding conductive pattern 1071' still has photoresist thereon, so as to protect the second part of the initial light-shielding conductive pattern from being weakened in light transmittance during the subsequent light transmittance weakening process.

[0103] S6, performing a light transmittance weakening process on the first part of the initial light-shielding conductive pattern 1071' to form the first part of the initial light-shielding conductive pattern 1071' into a first pattern 1071a and the second part of the initial light-shielding conductive pattern 1071' into a second pattern.

[0104] Exemplarily, the light transmittance weakening process performed on the first part of the initial light-shielding conductive pattern 1071' can also be referred to as a blackening process performed on the first part of the initial light-shielding conductive pattern 1071'. Since the material of the initial first sub-layer 107a' is transparent conductive oxide, hydrogen reduction is generally performed on the transparent conductive oxide to generate transparent conductive oxide that is not transparent (black), and the amount of transparent conductive oxide generated can be controlled by controlling the reaction conditions, such as reaction time, temperature, and the amount of hydrogen, so as to achieve light transmittance weakening, or even complete light blocking. For example, the light transmittance weakening process can be performed in a plasma-enhanced chemical vapor deposition device using H2as a working gas. The process conditions are as follows: the source power ranges from 5 kW to 7 kW, the flow rate of H2ranges from 70000 to 80000 sccm, the working pressure ranges from 900 to 1200 mt, and the processing time ranges from 10 to 20 S. Exemplarily, the source power is 6 kW, the flow rate of H2is 80000 sccm, the working pressure is 1000 mt, and the processing time is 15 S. Of course, other processing times can also be used according to the need for light transmittance weakening.

[0105] Exemplarily, the first part of the initial light-shielding conductive pattern 1071' can also be subjected to the light transmittance weakening treatment by laser. By irradiating the transparent conductive oxide on the first part of the initial light-shielding conductive pattern 1071' with laser, the second insulating layer of silicon nitride material under the transparent conductive oxide can release hydrogen to reduce the transparent conductive oxide. By adjusting the laser power, only the surface layer of the transparent conductive oxide can be treated without damaging other functional film layers under the surface layer.

[0106] It can be understood that the transmittance of the first pattern 1071a subjected to the light transmittance weakening treatment is less than the transmittance of the second pattern 1071b, that is, the first pattern 1071a has the light blocking effect relative to the second pattern 1071b.

[0107] S7, stripping the remaining photoresist.

[0108] Exemplarily, the distance between the orthographic projection boundary of the first pattern 1071a on the substrate 101 and the orthographic projection boundary of the active layer pattern 1041 of the first transistor T1 on the substrate 101 is within the set distance S range, that is, the orthographic projection of the first pattern 1071a on the substrate 101 can completely cover the orthographic projection of the active layer pattern 1041 on the substrate 101, that is, the first pattern 1071a can block most of the light from the side of the first pattern 1071a away from the active layer pattern 1041 to the active layer pattern 1041, thereby improving the light shielding effect and avoiding the influence of light on the characteristics of the first transistor T1.

[0109] Exemplarily, the orthographic projection of the active layer pattern 1041 of the first transistor T1 on the substrate 101 is located within the orthographic projection of the first pattern 1071a on the substrate 101, that is, the active layer pattern 1041 of the first transistor T1 can be completely blocked by the first pattern 1071a, and the first pattern 1071a can block the light from the side of the first pattern 1071a away from the active layer pattern 1041 of the first transistor T1 to the active layer pattern 1041 of the first transistor T1, thereby preventing or reducing the photoelectric effect of the active layer pattern 1041 of the first transistor T1, avoiding the accelerated degradation of the characteristics of the first transistor T1, and solving the problem that the light entering the active layer pattern 1041 of the first transistor T1 causes the photoelectric effect of the active layer pattern 1041 of the first transistor T1, which causes the rapid rise of the carrier concentration in the active layer pattern 1041 and the easy occurrence of the off-state leakage phenomenon.

[0110] Exemplarily, the second pattern 1071b is arranged to be connected with the gate pattern 1021 of the first transistor T1, and according to the above description, the first pattern 1071a is connected with the second pattern 1071b, that is, the part of the first pattern 1071a which overlaps with the active layer pattern 1041 of the first transistor T1 constitutes the top gate of the first transistor T1, and the gate pattern 1021 constitutes the bottom gate of the first transistor T1, that is, the second pattern 1071b and the gate pattern 1021 constitute the dual-gate structure of the first transistor T1, so that on one hand, the carrier mobility of the organic field-effect first transistor can be increased, so that the first transistor has a higher current density, that is, the current can be increased, and the performance of the device can be improved; on the other hand, the second pattern 1071b and the gate pattern 1021 jointly control the channel region of the active layer pattern 1041, so that the penetration of the drain power line into the channel region can be effectively inhibited, the threshold voltage drift is greatly reduced, the short channel effect is reduced, the off-state leakage current is reduced, the signal abnormality is improved, and thus the overall signal output capability of the array substrate 10 is improved.

[0111] It should be noted that according to the above description, the second pattern 1071b is arranged to be connected with the gate pattern 1021 of the first transistor T1, and the active layer pattern 1041 of the first transistor T1 is arranged to be located in the projection of the first pattern 1071a on the substrate 101, so that the performance degradation of the first transistor T1 can be reduced. According to the analysis of the inventors of the present application, in a harsh outdoor environment, for example, in a high-temperature and high-brightness environment, the performance of the first transistor T1 will be degraded, for example, the threshold voltage of the first transistor T1 will be reduced, and the gate-off voltage VGL has the function of pulling down the gate voltage of the first transistor T1, and because the threshold voltage of the first transistor T1 is reduced, the first transistor T1 is in a negative voltage state for a long time, which will cause the phenomenon that the first transistor cannot be turned off, that is, because the performance of the first transistor T1 is degraded, the gate-off voltage VGL in the original working voltage range cannot guarantee the normal turn-off of the first transistor T1, and the working voltage range of the gate-off voltage VGL needs to be improved.

[0112] The above working voltage range refers to the gate off voltage VGL within a certain range, which can ensure that the first transistor T1 is normally turned off. For example, when the first transistor T1 is a bottom gate transistor, the gate off voltage VGL of -5V to -10V can normally work, that is, the working voltage range of the gate off voltage VGL is adjusted within 5V, which can meet the requirement of normally turning off the first transistor T1. When the first transistor T1 is a double gate transistor, according to the above content, the off-state leakage current can be reduced, that is, the loss of current is reduced. At the same time, the required gate off voltage VGL does not need to be reduced too much to turn off the first transistor T1. For example, the gate off voltage VGL of -2V can meet the requirement of normally turning off the first transistor T1. At this time, the gate off voltage VGL of -2V to -10V can normally work, that is, the working voltage range of the gate off voltage VGL is adjusted within 8V, which can meet the requirement of normally turning off the first transistor T1. Therefore, the working voltage range of the above gate off voltage VGL is improved compared with the working voltage range when the first transistor T1 is a double gate transistor.

[0113] In some embodiments, for example, display products used outdoors, the requirement for the gate off voltage VGL is higher, and the gate off voltage VGL needs to be controlled within a certain range. Therefore, in order to realize accurate control of the gate off voltage VGL, the inventors determine the working voltage range of the gate off voltage VGL through long-term reliability evaluation, for example, by observing the gate off voltage under the off state of the first transistor T1, recording the critical voltage value of the gate off voltage at which the display device starts to show abnormality, and then comparing the difference with the set gate off voltage value. The larger the difference, the larger the working voltage range of the gate off voltage, that is, the adjustment of the working voltage range is improved. Specifically, the characteristics of the first transistor T1 are accelerated within the first time t1, for example, by changing factors such as light and temperature. The gate off voltage VGL is increased at the second time t2 to observe the gate off voltage VGL at which the display device starts to show abnormality. The difference is compared with the set gate off voltage VGL. The larger the difference, the larger the working voltage range of the gate off voltage, and the adjustment of the working voltage range is improved. The long-term reliability evaluation method can observe the change of the gate off voltage under the corresponding conditions by changing the characteristics of the transistor. The better the characteristics (working voltage range) of the transistor, the better the performance of the gate off voltage. That is, when the characteristic parameters of the transistor are controlled within a certain range, the change range of the gate off voltage can better meet the outdoor conditions. This evaluation method shows that in more severe use environments such as outdoors, the voltage value of the gate off voltage VGL is within the adjusted working voltage range, which can still ensure the normal work of the outdoor product.

[0114] Through the above analysis, it can be known that, due to the setting of the light-shielding conductive pattern 1071, the double-gate design of the first transistor, and the light-shielding design, the active pattern of the first transistor can be prevented from reacting under the action of light, the on-state current of the first transistor can be improved, the leakage current can be reduced, the threshold voltage offset of the first transistor T1 can be improved, and the specific degradation of the first transistor T1 can be reduced, so that the working voltage range of the gate-off voltage VGL is improved.

[0115] In some embodiments, as shown in FIGS. 3B, 4B, 5B, 6B, 7B, and 8B, the set pitch S ranges from 1 μm to 2.5 μm.

[0116] It should be explained that the above maximum set pitch is set to 2.5 μm, which is a consideration of the opening rate and the improvement effect of the gate-off voltage VGL. In order to improve the opening rate, the set pitch is set to a smaller range, that is, the set pitch is greater than 2.5 μm, which also improves the gate-off voltage VGL. The set pitch range S can be 1 μm, 1.5 μm, 2 μm, or 2.5 μm, etc.

[0117] As shown in Table 1 below, the experimental results of the voltage value of the gate-off voltage VGL improvement corresponding to the different values of the set pitch S.

[0118] Table 1

[0119] The above experiment can obtain that the set pitch D ranges from 1 μm to 2.5 μm, which can improve the voltage value of the gate-off voltage VGL by more than 1.5 V, and at the same time, the backlight brightness of the display device can be improved by more than 50%.

[0120] In other embodiments, referring to FIGS. 4A and 4B, the light-shielding conductive layer 107 includes a first sub-layer 107a, and the first pattern 1071a and the second pattern 1071b are located on the first sub-layer 107a; the materials of the first pattern 1071a and the second pattern 1071b are metal, and the transmittance of the first pattern 1071a is equal to the transmittance of the second pattern 1071b.

[0121] For example, the metal can be one of silver, copper, aluminum, molybdenum, and alloys thereof, and thus the first pattern 1071a and the second pattern 1071b can be prepared by depositing a metal material on the second insulating layer and then patterning. Since the materials of the first pattern 1071a and the second pattern 1071b are the same and the process steps are the same, the transmittance of the first pattern 1071a is equal to the transmittance of the second pattern 1071b.

[0122] In some embodiments, referring to FIGS. 5A, 5B, 6A and 6B, the light-shielding conductive layer 107 includes a first sub-layer 107a, and the first pattern 1071a and the second pattern 1071b are located on the first sub-layer 107a; the material of the second pattern 1071b is a transparent conductive oxide, and the material of the first pattern 1071a is a metal or an organic light-shielding material.

[0123] For example, the material of the first pattern 1071a in FIGS. 5A and 5B is a metal, and the material of the first pattern 1071a in FIGS. 6A and 6B is an organic light-shielding material.

[0124] For example, the organic light-shielding material includes but is not limited to one or more of a BM (Black matrix) material, an RGB Resin material or a BPS (4,4'-Biphenyl Sulfone) material. The material of the BM can be Cr (Chromium), CrOx (Chromium Oxide) or Black Resin, etc.

[0125] It should be noted that the process of forming the first pattern 1071a and the second pattern 1071b can be described with reference to the process in the first two embodiments, which will not be described here.

[0126] In some embodiments, referring to FIGS. 7A, 7B, 8A and 8B, the light-shielding conductive layer 107 includes a first sub-layer 107a and a second sub-layer 107b, the second sub-layer 107b is located on the side of the first sub-layer 107a away from the substrate 101; the transmittance of the second sub-layer 107b is less than that of the first sub-layer 107a; the first pattern 1071a includes a first sub-pattern 10711 located on the first sub-layer 107a and a second sub-pattern 10712 located on the second sub-layer 107b, and the second pattern 1071b is located on the first sub-layer 107a.

[0127] For example, referring to FIGS. 7A, 7B, 8A and 8B, the light-shielding conductive layer 107 includes two film layers stacked together, and the transmittances of the two film layers are different; the first pattern 1071a includes a first sub-pattern 10711 and a second sub-pattern 10712, wherein the first sub-pattern 10711 is located on the first sub-layer 107a, and the second sub-pattern 10712 is located on the second sub-layer 107b, that is, the first sub-pattern 10711 and the second sub-pattern 10712 are located on different layers, that is, the first sub-pattern 10711 and the second sub-pattern 10712 should be prepared separately.

[0128] In some embodiments, referring to FIGS. 7A, 7B, 8A and 8B, the material of the first sub-layer 107a is a transparent conductive oxide, and the material of the second sub-layer 107b is a metal or an organic light-shielding material.

[0129] Exemplarily, the material of the first sub-pattern 10711 and the second pattern 1071b in the first sub-layer 107a is transparent conductive oxide, and the material of the second sub-pattern 10712 in the second sub-layer 107b is metal or organic light shielding material, that is, the second sub-pattern 10712 plays a role of light blocking, so that the transmittance of the first pattern 1071a is less than that of the second pattern 1071b, that is, the first pattern 1071a has a light blocking effect relative to the second pattern 1071b, wherein the material of the second sub-pattern 10712 in FIGS. 7A and 7B is metal, and the material of the second sub-pattern 10712 in FIGS. 8A and 8B is organic light shielding material.

[0130] The following introduces the forming steps K1-K8 of the first pattern 1071a and the second pattern 1071b in the case that the light shielding conductive layer 107 includes the first sub-layer 107a and the second sub-layer 107b.

[0131] K1, first form the initial first sub-layer 107a' of the light shielding conductive layer 107 on the second insulating layer 106.

[0132] Exemplarily, forming the initial first sub-layer 107a' can be depositing transparent conductive oxide material on the second insulating layer 106.

[0133] It should be noted that the above-mentioned initial first sub-layer 107a' is a whole layer film layer laid on the second insulating layer 106, and the initial first sub-layer 107a' is not subjected to a patterning process.

[0134] K2, form the initial second sub-layer 107b' on the initial first sub-layer 107a'.

[0135] Exemplarily, forming the initial second sub-layer 107b' can be depositing metal or organic light shielding material on the transparent conductive oxide material.

[0136] It should be noted that the above-mentioned initial second sub-layer 107b' is a whole layer film layer laid on the initial first sub-layer 107a', and the initial second sub-layer 107b' is not subjected to a patterning process.

[0137] K3, form a photoresist layer on the initial second sub-layer 107b'.

[0138] K4, expose and develop the photoresist layer using a mask plate to obtain a patterned photoresist layer.

[0139] It should be noted that the mask includes a plurality of openings, and a half-tone area and a full-tone area, portions of the photoresist layer corresponding to the plurality of openings are removed, and portions of the initial second sub-layer 107b' are exposed, and portions of the photoresist layer corresponding to the half-tone area and the full-tone area are retained to form a patterned photoresist layer, wherein the portions of the patterned photoresist layer corresponding to the half-tone area and the portions corresponding to the full-tone area are connected.

[0140] The portions of the patterned photoresist layer corresponding to the half-tone area cover the active layer of the first transistor and the area around the active layer of the first transistor within a specified distance range.

[0141] K5, etching the initial second sub-layer 107b' exposed in the developed photoresist layer, while etching the initial first sub-layer 107a', to form an initial light-shielding conductive pattern 1071'.

[0142] K6, thinning the patterned photoresist layer until the portions of the patterned photoresist layer corresponding to the half-tone area are removed, and exposing the first portion (corresponding to the first pattern) of the initial light-shielding conductive pattern 1071'.

[0143] Exemplarily, the thinning of the photoresist layer can be performed by wet etching, dry etching or laser etching process. In this example, dry etching process is adopted, which can also be referred to as gray ashing of the photoresist, and is performed in an ECCP (Enhanced Cathode Coupling Plasma) dry etching device using NF3 and O2 as working gas. The process conditions are as follows: source power / bias power (Source power / Bias Power) is 12 kW / 10 kW, the flow rate of NF3 / O2 is 1500 / 10000 sccm, and the working pressure is 40 mt.

[0144] K7, etching the initial light-shielding conductive pattern 1071' located in the portions of the initial second sub-layer 107b' corresponding to the half-tone area to obtain the light-shielding conductive pattern 1071', i.e. to form the second pattern 1071b synchronously.

[0145] K8, stripping the remaining photoresist.

[0146] In some embodiments, referring to FIG. 2A, the sub-pixel PX further includes a pixel electrode 11 and a common electrode 12; the light-shielding conductive layer 107 includes a first sub-layer 107a, and the first sub-layer 107a further includes a pixel electrode pattern 111; the gate electrode layer 102 further includes a common electrode pattern 121 and a common signal line COM, the material of the common electrode pattern 121 is transparent conductive material, the common signal line COM is connected with the common electrode pattern 121; and the pixel electrode pattern 111 overlaps with the common signal line COM.

[0147] It should be noted that the first sub-layer 107a further comprises the pixel electrode pattern 111, that is, the pixel electrode pattern 111 and the second pattern 1071b are located in the same layer, that is, the pixel electrode pattern 111 and the second pattern 1071b are made of the same material, and the second pattern 1071b can be simultaneously patterned during the preparation of the pixel electrode pattern 111, so that the process is simplified.

[0148] For example, as shown in FIG. 2A, the common electrode pattern 121 and the common signal line COM overlap in the orthographic projection of the substrate, and the common electrode pattern 121 and the common signal line COM are located in the same film layer, that is, the gate layer 102, that is, the common electrode pattern 121 and the common signal line COM are connected by lapping in the gate layer 102.

[0149] The pixel electrode pattern 111 and the oppositely arranged common electrode pattern 121 can form a capacitor Cst, and the common electrode pattern 121 and the common signal line COM are connected by lapping, which can increase the capacitance. In addition, the pixel electrode pattern 111 and the common signal line COM overlap, and the overlapping part can be used as a compensation capacitor, which can reduce voltage fluctuation, improve signal transmission effect, and reduce loss.

[0150] For example, the common signal line COM is used to transmit a common voltage signal, and the material of the common signal line can be metal, which has lower resistance than the material of the common electrode layer (indium tin oxide). The use of the common signal line COM to transmit the common voltage signal can improve the voltage uniformity of the common electrode, improve the signal transmission effect, reduce the loss, and further improve the in-plane light uniformity.

[0151] In some embodiments, as shown in FIGS. 2A, 3A and 3B, the gate layer 102 comprises a gate line GT, the gate pattern 1021 of the first transistor T1 is a part of the gate line GT that overlaps the active layer pattern 1041 of the first transistor T1, and the second pattern 1071b is connected to the gate line GT.

[0152] Exemplarily, referring to FIG. 3A and FIG. 3B, the gate pattern 1021 of the first transistor T1 is a part of the gate line GT, which is overlapped with the active layer pattern 1041 of the first transistor T1, that is, the gate pattern 1021 is a part of the gate line GT, the gate pattern 1021 has the same gate voltage signal as the gate line GT, the second pattern 1071b is connected with the gate line GT, and since the material of the second pattern 1071b is transparent conductive oxide material, it is equivalent that the second pattern 1071b can receive the gate voltage signal transmitted by the gate line GT, further, the first pattern 1071a is in contact with the second pattern 1071b, so the first pattern 1071a and the second pattern 1071b can transmit the same gate voltage signal, and the part of the first pattern 1071a overlapped with the active layer pattern 1041 can be used as the top gate structure of the first transistor T1, and the gate pattern 1021 of the first transistor T1 is used as the bottom gate structure of the first transistor T1, thereby the first transistor T1 is a dual-gate transistor, and the above-mentioned method of setting the first transistor T1 as a dual-gate transistor can effectively inhibit the penetration of the drain power line into the channel region, greatly reduce the threshold voltage drift, and reduce the short channel effect, which is beneficial to realize the reduction of off-state leakage current, improve the signal abnormality, and thus improve the overall signal output capability of the array substrate 10.

[0153] In some embodiments, as shown in FIG. 9A and FIG. 9B, the array substrate 10 comprises a gate driving circuit 13, the gate driving circuit 13 comprises at least one second transistor T2 and a storage capacitor C; the gate layer 102 further comprises a gate control line GK, the gate control line GK comprises a gate pattern 1022 of the second transistor T2; the active layer 104 further comprises an active layer pattern 1042 of the second transistor T2; the array substrate 10 further comprises a source-drain metal layer 105 arranged on the side of the active layer 104 away from the substrate 101, the source-drain metal layer 105 is in contact with the active layer 104, and the source-drain metal layer 105 comprises a first plate pattern C1 of the storage capacitor C; the light-shielding conductive layer 107 further comprises a conductive pattern 1072, the conductive pattern 1072 is overlapped with the active layer pattern 1042 of the second transistor T2 and also overlapped with the first plate pattern C1 of the storage capacitor C; the conductive pattern 1072 is connected with the gate control line GK; and the gate control line GK is overlapped with the first plate pattern C1 of the storage capacitor C.

[0154] Exemplarily, referring to FIG. 9A, the array substrate 10 further comprises a non-display area BB arranged outside the display area AA, wherein the non-display area BB is provided with the gate driving circuit 13 located on both sides of the display area AA in the row direction X and the data driving area 14 arranged on one side of the display area AA in the column direction Y.

[0155] It should be noted that the gate drive circuit 13 is used to output a gate signal to the display area to control the opening of each sub-pixel for data signal input. Referring to FIG. 9A, the gate drive circuit 13 includes a plurality of cascaded shift registers, and the same stage shift register in the two gate drive circuits 13 is electrically connected to the same gate line GT, for example, the first stage shift registers of the two gate drive circuits 13 are both electrically connected to the first gate line GT, and simultaneously output a gate scanning signal to the gate line for display, that is, double-sided driving. In this way, the driving efficiency can be improved, the scanning time is saved, the multiple sub-pixels are opened faster, the data signal is written, and the display effect is improved. Alternatively, the present case can also support single-sided driving, that is, the gate drive circuit is arranged on one side of the non-display area BB, which is not limited here.

[0156] Exemplarily, referring to FIG. 9A, the data drive area 14 can include a drive chip connected to the plurality of data signal lines DT. In combination with FIG. 1, the plurality of data signal lines DT respectively transmit data voltage signals to the plurality of sub-pixels PX of the display area AA, wherein the plurality of data signal lines DT extend along the column direction Y, and each data signal line DT is connected to a column of sub-pixels PX.

[0157] Exemplarily, referring to FIG. 9B and FIG. 9C, FIG. 9B is a partial sectional structure diagram of the gate drive circuit, wherein the gate drive circuit 13 includes a plurality of shift registers, and each shift register includes a plurality of transistors and a storage capacitor C. The shift register includes an input end, an output end and a cascaded end. The second transistor T2 is a transistor related to the output voltage signal and the pull-up node voltage signal in the plurality of transistors. Exemplarily, the second transistor T2 includes two, one of which is connected to the output end, and the other is connected to the cascaded end, and both are connected to the storage capacitor C. The storage capacitor C is located in the gap formed between the two second transistors T2. In this way, the area of the region where the gate drive circuit 13 is located can be fully utilized, so that the area utilization rate of the gate drive circuit 13 is improved, and the area occupied by the original capacitor is reduced. Since the gate drive circuit 13 is located in the peripheral area of the display area AA, the area is small, so that a narrow frame can be realized.

[0158] In some embodiments, as shown in FIG. 9C, the shift register further comprises an initial gate-on voltage input end connected to the first electrode of the second transistor T2, the second electrode of the second transistor T2 is connected to the output end Output, the output end Output is connected to the gate line GT, the gate line GT is connected to the control electrode of the first transistor T1 in the display area sub-pixel, and the control electrode of the second transistor is connected to the pull-up node PU. The initial gate-on voltage input end is configured to transmit an initial gate-on voltage signal, for example, the clock signal end CLK, and the voltage value of the gate-on voltage output by the second electrode of the second transistor T2 is related to the initial gate-on voltage VGH'. That is, the voltage value of the gate-on voltage transmitted by the output end Output of the shift register to the display area through the gate line GT connected thereto is related to the initial gate-on voltage VGH'.

[0159] Exemplarily, the gate control line GK comprises a gate pattern 1022 of the second transistor T2, the gate control line GK is used to provide a gate control signal for the second transistor T2, the conductive pattern 1072 is connected to the gate control line GK, that is, the conductive pattern 1072 can transmit the same gate control signal as the gate control line GK, and the conductive pattern 1072 overlaps with the active layer pattern 1042 of the second transistor T2, that is, the overlapping part can serve as the top gate of the second transistor T2, and the gate pattern 1022 of the second transistor T2 is the bottom gate of the second transistor T2. It can be understood that the second transistor T2 is a double-gate transistor. In this way, on the one hand, the carrier mobility of the organic field effect first transistor can be increased, so that the second transistor has a higher current density, that is, the current can be increased, and the problem of insufficient charging rate caused by the decrease of the current of the second transistor due to long-time use of the display device in outdoor or harsh environments can be improved, and the performance of the second transistor can be improved. On the other hand, the conductive pattern 1072 and the gate pattern 1022 of the second transistor T2 jointly control the channel region of the active layer pattern 1042 of the second transistor T2, which can effectively suppress the penetration of the drain power line into the channel region, greatly reduce the threshold voltage drift, and reduce the short channel effect. It is beneficial to realize the reduction of leakage, improve the signal abnormality, thereby improve the overall signal output capability of the gate driving circuit, further, the range of gate-on voltage can be improved, thereby ensuring the normal work of outdoor display products and improving the service life of display products.

[0160] It should be noted that, according to the above description, the conductive pattern 1072 is connected with the gate control line GK, and the conductive pattern 1072 overlaps with the active layer pattern 1042 of the second transistor T2, which can improve the degree of the second transistor T2 to withstand characteristic degradation. According to the analysis of the inventors of the present application, under harsh outdoor use environment, such as high temperature, high brightness and other environmental conditions, the characteristics of the second transistor T2 will deteriorate. For example, the threshold voltage of the second transistor T2 will increase. Due to the increase of the threshold voltage of the second transistor T2, the second transistor will be in a state of insufficient charging for a long time, which will further cause the opening voltage of the sub-pixel output by the second transistor to the display area to decrease, that is, the gate opening voltage decreases. That is, due to the characteristic degradation of the second transistor T2, the output gate opening voltage VGH cannot guarantee the normal opening of the first transistor T1, and since the gate opening voltage VGH is also related to the initial gate opening voltage, if the gate opening voltage VGH can guarantee the normal opening of the first transistor T1, the working voltage range of the initial gate opening voltage needs to be improved.

[0161] The above working voltage range refers to that the initial gate opening voltage VGH' is within a certain range, which can guarantee that the gate opening voltage can control the normal opening of the first transistor T1. For example, when the second transistor T2 is a bottom gate transistor, the initial gate opening voltage VGH' is 25V-32V, and the first transistor T1 can work normally, that is, the working voltage range of the initial gate opening voltage VGH' is adjusted within 7V, which can meet the requirement of the normal opening of the first transistor T1. In the case of the second transistor T2 being a double-gate transistor, according to the above content, the current can be increased, that is, under the same conditions, the required initial gate opening voltage VGH' is reduced. For example, when the initial gate opening voltage VGH' is 22V, the gate opening voltage output by the second transistor T2 can meet the requirement of the normal opening of the first transistor T1. At this time, the first transistor T1 can work normally when the initial gate opening voltage VGH' is 20V-32V, that is, the working voltage range of the initial gate opening voltage VGH' is adjusted within 12V, which can meet the requirement of the normal opening of the first transistor T1. Therefore, the working voltage range of the initial gate opening voltage VGH' is expanded to a certain extent when the second transistor T2 is a double-gate transistor compared with the working voltage range when the second transistor T2 is a bottom gate transistor.

[0162] In some embodiments, for example, display products for outdoor use, the requirement for the initial gate-on voltage VGH' is higher, the initial gate-on voltage VGH' needs to be controlled within a certain range, therefore, in order to achieve accurate control of the initial gate-on voltage VGH', the inventors judge the initial gate-on voltage VGH' through long-term reliability evaluation, for example, by observing the initial gate-on voltage VGH' under the condition of turning on the first transistor T1, recording the critical voltage value of the initial gate-on voltage VGH' at which the display device starts to show display abnormalities, and then comparing the difference with the set initial gate-on voltage value, the larger the difference, the larger the working voltage range of the initial gate-on voltage VGH', that is, the adjustment of the working voltage range is improved to a certain extent. Specifically, accelerate the degradation of the characteristics of the second transistor T2 in the first time, for example, factors such as light and temperature, and observe the initial gate-on voltage VGH' at which the display device starts to show abnormalities in the second time, and compare the difference with the set initial gate-on voltage VGH', the larger the difference, the larger the working voltage range of the initial gate-on voltage VGH', the adjustment of the working voltage range is expanded to a certain extent. The above long-term reliability evaluation method can observe the change of the initial gate-on voltage VGH' under the corresponding conditions by changing the characteristics of the transistor, and the better the characteristics of the transistor, the better the performance of the initial gate-on voltage VGH', that is, when the characteristic parameters of the transistor are controlled within a certain range, the change range of the initial gate-on voltage VGH' can better meet the outdoor conditions. This evaluation method shows that in more severe use environments such as outdoors, the voltage value of the initial gate-on voltage VGH' is within the adjusted working voltage range, which can still ensure the normal operation of outdoor products.

[0163] For the structure of the second transistor T2 being a double-gate transistor, the inventors found through testing that the second transistor T2 being a double-gate transistor can be improved, and thus the service life of the display device can be extended and the reliability of the display device can be improved.

[0164] For the structure of the second transistor, the inventors have conducted experimental verification, and tested the on-state current and off-state leakage current of the second transistor in the case of a double-gate structure, and the on-state current and off-state leakage current of the second transistor in the case of the original bottom-gate structure, and the results are shown in Table 2.

[0165] As shown in Table 2 below, the experimental data comparison results of the second transistor being a double-gate transistor and a bottom-gate transistor.

[0166] Table 2

[0167] According to the above table, in the case that the second transistor is a double-gate transistor, the on-state current is higher, and the off-state leakage current can be reduced, that is, in harsh environmental conditions, the second transistor as a double-gate transistor can reduce the performance degradation of the second transistor compared to the case that the second transistor is a bottom-gate transistor. For example, at this time, the working voltage range of the initial gate-on voltage VGH' can be expanded. For example, when the second transistor is a bottom-gate transistor, the initial gate-on voltage VGH' is 25V-32V, which can make the first transistor normally open. Setting the second transistor as a double-gate transistor can increase the on-state current. According to the characteristic curve of the transistor, the greater the current, the higher the corresponding voltage, that is, the on-state current increases, and the initial gate-on voltage VGH' decreases. For example, at this time, the initial gate-on voltage VGH' is 20V-32V, that is, the working voltage range of the initial gate-on voltage VGH' is expanded by 5V. Similarly, setting the second transistor as a double-gate transistor can reduce the off-state leakage current, that is, reduce the current loss. According to the characteristic curve of the transistor, the smaller the current, the lower the corresponding voltage, that is, the working voltage of the initial gate-on voltage VGH' corresponding to the normal working of the first transistor is reduced, that is, the working voltage range of the initial gate-on voltage VGH' is larger, which is a certain improvement compared to the original normal working voltage range.

[0168] According to the above analysis, since the conductive pattern 1072 is connected with the gate control line GK, and the conductive pattern 1072 overlaps the active layer pattern 1042 of the second transistor T2, the double-gate design of the second transistor can increase the carrier mobility of the second transistor, so that the second transistor has a higher current density, that is, the on-state current of the second transistor is improved, the leakage current is reduced, the threshold voltage offset of the second transistor T2 is improved, the performance degradation of the second transistor T2 is reduced, and the performance of the second transistor is improved, so that the working voltage range of the initial gate-on voltage VGH' is improved.

[0169] In some embodiments, referring to FIG. 9B, the distance D1 between the first plate pattern C1 of the storage capacitor C and the conductive pattern 1072 is equal to the distance D2 between the first plate pattern C1 of the storage capacitor C and the gate control line GK.

[0170] Exemplarily, since the conductive pattern 1072 overlaps with the active layer pattern 1042 of the second transistor T2, and also overlaps with the first plate pattern C1 of the storage capacitor C, that is, the portion C21 where the conductive pattern 1072 overlaps with the active layer pattern 1042 of the second transistor T2 can be used as a part of the second plate pattern C2 of the storage capacitor C, in addition, the gate control line GK overlaps with the first plate pattern C1 of the storage capacitor C, that is, the portion C22 where the gate control line GK overlaps with the first plate pattern C1 of the storage capacitor C can also be used as a part of the second plate pattern C2 of the storage capacitor C, thus, the second plate pattern C2 of the storage capacitor C includes two parts, compared with the embodiment where the second plate pattern C2 is only arranged on the gate layer 102, the above arrangement can increase the storage capacitance of the storage capacitor C. In addition, the distance between the first plate pattern C1 of the storage capacitor C and the conductive pattern 1072 is equal to the distance between the first plate pattern C1 of the storage capacitor C and the gate control line GK, that is, the storage capacitor C' at this time is composed of two parts, and the sizes of the two parts of the storage capacitor C are equal, so the storage capacitor C' becomes twice the original storage capacitor C, therefore, under the premise of ensuring the capacitance value of the storage capacitor C, the area of the first plate pattern C1 of the storage capacitor C can be halved, by such arrangement, in addition to ensuring the use of normal storage capacitors, the storage capacitor C in the gate drive circuit can also occupy less space, and thus the overall area of the gate drive circuit can be reduced, so as to realize the narrow frame of the display device.

[0171] The following verifies the change of the conduction band and the valence band of the transistor under the action of the voltage, and illustrates the difference between the double-gate transistor and the bottom-gate transistor.

[0172] As shown in FIG. 10A, in the case where the transistor is not powered on, the conduction band (EC) and the valence band (EV) in the band diagram shown in FIG. 10A do not bend, where EFis a Fermi level between the conduction band (EC) and the valence band (EV). When the gate-on voltage VGHis 15 V, the transistor can normally be turned on. Referring to FIG. 10B, in the case where the transistor is a dual-gate transistor, the active layer pattern 1042 of the transistor is affected by the gate-on voltage VGHnear the surface of the first insulating layer 103 and near the surface of the second insulating layer 106, and there is electron accumulation near the surface of the first insulating layer 103 and near the surface of the second insulating layer 106, so that the conduction band bends downward. As shown in FIG. 10C, the transistor shown in FIG. 10C is a bottom-gate transistor, and the active layer pattern 1042 of the transistor is affected by the gate-on voltage VGHnear the surface of the first insulating layer 103, and there is electron accumulation near the surface of the first insulating layer 103, so that the conduction band bends downward. Compared to the case where the transistor shown in FIG. 10C is a bottom-gate transistor, in the case where the transistor is a dual-gate transistor and in the on-state, the central energy level of the mobility gap between the conduction band (EC) and the valence band (EV) is lower, so that the electron density of the active layer pattern of the dual-gate transistor is greater than that of the bottom-gate transistor, thereby increasing the current. Higher current can make the display product have more current reduction space, and can improve the phenomenon that the picture display of the transistor is abnormal due to insufficient charging rate.

[0173] When the gate-off voltage VGLis -8 V, the transistor can normally be turned off. Referring to FIG. 10D, in the case where the transistor is a dual-gate transistor, the active layer 104 pattern of the transistor is affected by the gate-off voltage VGLnear the surface of the first insulating layer 103 and near the surface of the second insulating layer 106, and there is hole accumulation near the surface of the first insulating layer 103 and near the surface of the second insulating layer 106, so that the conduction band bends upward. As shown in FIG. 10E, the transistor shown in FIG. 10E is a bottom-gate transistor, and the active layer pattern 1042 of the transistor is affected by the gate-on voltage VGHnear the surface of the first insulating layer 103, and there is electron accumulation near the surface of the first insulating layer 103, so that the conduction band bends upward. Compared to the case where the transistor shown in FIG. 10E is a bottom-gate transistor, in the case where the transistor is a dual-gate transistor and in the off-state, the central energy level of the mobility gap between the conduction band (EC) and the valence band (EV) is higher, so that the hole density of the active layer pattern of the dual-gate transistor is less than that of the bottom-gate transistor, thereby reducing the leakage current. This can improve the phenomenon that the output signal of the transistor is abnormal due to excessive leakage current.

[0174] The above is an analysis of the beneficial effects of the transistor being configured as a double-gate transistor relative to the transistor being configured as a bottom-gate transistor. In the above, the transistor is applicable to the first transistor and the second transistor, that is, the first transistor and the second transistor configured as a double-gate transistor also have the above effects of improving current and reducing leakage current.

[0175] Referring to FIGS. 11A, 11B, 12A, and 12B, the embodiments of the present disclosure further provide a display panel 100 comprising the array substrate 10 provided by any of the above embodiments. Therefore, the display panel 100 provided by the present disclosure has all the beneficial effects of the array substrate 10 provided by any of the above embodiments, which will not be repeated here.

[0176] In some embodiments, referring to FIGS. 11A and 11B, the display panel 100 further comprises a color filter substrate 20 disposed on the array substrate 10, and at least one spacer 30 disposed between the array substrate 10 and the color filter substrate 20; the spacer 30 comprises a first spacer 31 disposed on one side of the second pattern 1071b and in contact with the second pattern 1071b.

[0177] For example, referring to FIGS. 11A and 11B, the first spacer 31 can be a red color blocking block, a green color blocking block, and a blue color blocking block, wherein the first spacer 31 can be stacked by two layers of color blocking blocks. It should be noted that the spacer formed by the color blocking block can reduce the light brightness in the dark state and improve the light contrast during dark state display.

[0178] For example, referring to FIGS. 11B and 12B, the color filter substrate 20 can further comprise a color blocking layer 108 disposed on the spacer 30, and a black matrix layer 109 disposed on the side of the color blocking layer 108 away from the spacer 30. The black matrix layer 109 has a light shielding effect to prevent light leakage of the display panel 100, and the color blocking layer 108 is used to shield part of the color light and has an adjusting effect on light.

[0179] It should be noted that, referring to FIGS. 11B and 12B, the surface of the spacer 30 away from the array substrate 10 is connected to the surface of the color blocking layer 108 close to the array substrate 10. In the case that the spacer 30 is offset from the color blocking layer 108, the spacer 30 will be offset together with the color blocking layer 108.

[0180] Exemplarily, referring to FIG. 13A and FIG. 13B, FIG. 13A is a structural diagram of the spacer 30 being offset under the action of an external force without the second pattern 1071b, and FIG. 13B is a structural diagram of the spacer 30 being offset under the action of an external force with the second pattern 1071b. In the figures, the arrow shown in the figure is the offset direction Z of the spacer 30. As can be seen from the figure, when the first spacer 31 in FIG. 13A is offset under the action of an external force, since the side surface of the first spacer 31 away from the array substrate 10 is connected to the surface of the color resist layer 108 close to the array substrate 10, the first spacer 31 will be offset together with the color resist layer 108 in the case of the color resist layer 108 being offset, that is, the first spacer 31 will be offset to the region corresponding to the opening of the sub-pixel, and the opening of the sub-pixel is provided with liquid crystal between the array substrate 10 and the color film substrate 20, and the side surface of the array substrate 10 close to the liquid crystal and the side surface of the color film substrate 20 close to the liquid crystal are both provided with a resin layer for protecting the liquid crystal. In the process of the first spacer 31 being offset and rebounding under the action of pressure, the side surface of the first spacer 31 close to the array substrate 10 is closer to the array substrate 10 when rebounding, and is easy to scratch the resin layer of the side surface of the array substrate 10 close to the liquid crystal, thereby causing the liquid crystal to be misaligned and causing the blue spot defect. In FIG. 13B, the first spacer 31 is arranged on the side of the second pattern 1071b, and the second pattern 1071b can raise the first spacer 31, that is, the height of the first spacer 31 can be reduced, that is, the side surface of the first spacer 31 close to the array substrate 10 is farther away from the array substrate 10 when rebounding in the process of the first spacer 31 being offset and rebounding under the action of pressure, that is, the side surface of the first spacer 31 close to the array substrate 10 will not scratch the resin layer of the side surface of the array substrate 10 close to the liquid crystal in the process of the first spacer 31 being offset and rebounding under the action of pressure, and the problem of the liquid crystal being misaligned can be avoided, thereby avoiding the blue spot defect. Since the first spacer 31 is arranged on the side of the second pattern 1071b, the second pattern 1071b can raise the first spacer 31, that is, the height of the first spacer 31 can be reduced compared with the height of the spacer in the related art, and the width of the black matrix layer 109 arranged above the first spacer 31 can be reduced, referring to FIG. 13A and FIG. 13B, the width of the black matrix layer 109 in FIG. 13B is shorter than the width of the black matrix layer 109 in FIG. 13A, thereby the aperture ratio of the sub-pixel can be improved, and the aperture ratio can be improved by 4% exemplarily. At the same time, the liquid crystal arrangement at the position of the first spacer 31 is disordered, and the light leakage defect is easy to occur, and the black matrix layer 109 can avoid the light leakage defect at the position corresponding to the first spacer 31, and affect the display of the display panel.

[0181] In some embodiments, referring to FIG. 14, the spacers 30 include second spacers 32, and the height H1 of the first spacers 31 is higher than the height H2 of the second spacers 32; the second spacers 32 are arranged on one side of the second pattern 1071b.

[0182] For example, referring to FIG. 14, the spacers 30 include the first spacers 31 and the second spacers 32, wherein, referring to FIGS. 12A and 12B, the second spacers 32 can be any one of the red color resist blocks, the green color resist blocks and the blue color resist blocks, and referring to FIGS. 11A and 11B, the first spacers 31 can be stacked by two layers of color resist blocks. The light brightness in the dark state can be reduced, and the light contrast during the display in the dark state can be improved.

[0183] It should be noted that the first spacers 31 and the second spacers 32 arranged between the array substrate 10 and the color film substrate 20 can be arranged in an array, for example, the first spacers 31 and the second spacers 32 are arranged in the same sub-pixel region, or the first spacers 31 and the second spacers 32 are arranged in two adjacent sub-pixel regions respectively, and are arranged on the side of the second pattern in the respective sub-pixels, and the two adjacent sub-pixels are, for example, green sub-pixels and blue sub-pixels, which are not limited here.

[0184] For example, referring to FIG. 14, the materials of the first spacers 31 and the second spacers 32 are the same as the material of the second pattern 1071b, which can be formed synchronously when the second pattern 1071b is manufactured, so as to simplify the process. In addition, since the first spacers 31 and the second spacers 32 are arranged in an array on the array substrate 10, the height H1 of the first spacers 31 is set to be higher than the height H2 of the second spacers 32, so that the first spacers 31 play a main supporting role, and when the pressure is large, the second spacers 32 play a supporting role together with the first spacers 31, so as to prevent the liquid crystal from being affected in the deflection process, and to prevent the display device from having a display problem.

[0185] For example, referring to FIGS. 11B and 12B, wherein FIG. 11B is a sectional structure diagram of the first spacer, and FIG. 12B is a sectional structure diagram of the second spacer, since the height H1 of the first spacers 31 is higher than the height H2 of the second spacers 32, and the first spacers 31 play a main supporting role, the first spacers 31 are arranged to be in contact with the second pattern 1071b, and the second spacers 32 are not in contact with the second pattern 1071b, that is, when the pressure on the first spacers 31 is large, the height H1 of the first spacers 31 is compressed to the height H2 of the second spacers 32, and the second spacers 32 play a supporting role together with the first spacers 31.

[0186] Exemplarily, referring to FIG. 14, the first and second spacers 31 and 32 can ensure that the display panel 100 can maintain a certain cell gap when the display panel 100 is pressed by an external force. The present inventors have found that the transistor will have abnormal characteristics when the cell gap is pressed, and the greater the pressure, the more obvious the abnormal phenomenon. During the manufacturing process, the display panel 100 will inevitably be subjected to suction and transportation or support after being boxed. The first and second spacers 31 and 32 will squeeze the transistor too hard after being pressed, which will cause the transistor to have a risk of performance degradation. The material of the first and second spacers 31 and 32 is the same as that of the second pattern 1071b. Since the material of the second pattern 1071b can be an organic polymer material, it has strong adhesion, that is, it can make the first and second spacers 31 and 32 more firmly adhere to the array substrate, and can prevent the first and second spacers 31 and 32 from falling off or shifting during use.

[0187] Some embodiments of the present disclosure provide a display device 1000, as shown in FIG. 15, which can be a mobile phone, a tablet computer, a personal digital assistant (PDA), a vehicle-mounted computer, a wearable display device, etc. The specific form of the display device is not specially limited in the embodiments of the present disclosure. As shown in FIG. 16, the display device 1000 includes the display panel 100 provided by any of the above embodiments, and the display panel 100 includes a display side 100a and a non-display side 100b. Therefore, the display device 1000 provided by the present disclosure has all the beneficial effects of the display panel 100 provided by any of the above embodiments, which will not be described here.

[0188] Exemplarily, as shown in FIG. 16, the display device 1000 in the embodiments of the present disclosure is exemplified by a liquid crystal display device. Referring to FIG. 10, in some embodiments, the main structure of the liquid crystal display device 1000 includes a frame 200, a cover plate 300, a display panel 100, a backlight module 400, a circuit board 500, and other electronic accessories.

[0189] The frame 200 surrounds a receiving space, and the display panel 100, the backlight module 400, the circuit board 500, and other electronic accessories are arranged in the receiving space. The cover plate 300 is arranged on the open side of the frame 200. The display panel 100 is arranged close to the cover plate 300 relative to the backlight module 400 and the circuit board 500. The circuit board 500 is arranged away from the cover plate 300 relative to the display panel 100 and the backlight module 400. The backlight module 400 is arranged on the non-display side 100b of the display panel 100 and between the display panel 100 and the circuit board 500. The backlight module 400 is used to provide a backlight source for the display device 1000.

[0190] Exemplarily, referring to FIG. 16, the display panel 100 includes a liquid crystal layer 50 between an array substrate 10 and a color film substrate 20, and the array substrate 10 and the color film substrate 20 can be pasted together by a frame sealant 40, so as to define the liquid crystal layer 50 in an area surrounded by the frame sealant 40.

[0191] Exemplarily, a plurality of liquid crystal molecules are contained in the liquid crystal layer 50, and since the display panel 100 itself cannot emit light, it is necessary to set a backlight module 400, and the backlight source provided by the backlight module 400 passes through the liquid crystal layer in the display panel. Since the liquid crystal molecules have optical rotation characteristics on polarized light, a specific arrangement direction of the molecules can change the polarization direction of the polarized light. When the arrangement direction of the liquid crystal molecules is rotated under the control of the electric field generated between the pixel electrode and the common electrode, the polarization direction of the polarized light passing through the liquid crystal molecules is also changed, so that the light passing through the liquid crystal layer can be controlled to be emitted, that is, the light is deflected by a plurality of liquid crystal molecules to realize the emission of the light from the display panel, that is, the display panel 100 can display a to-be-displayed picture. The to-be-displayed picture is a picture that the display panel 100 needs to present, for example, the to-be-displayed picture is a black, white, gray or color picture, etc. The opposite sides of the backlight module 400 are an out-light side and a non-out-light side, respectively, and the light emitted by the backlight module 400 is emitted from the out-light side. The opposite sides of the display panel 100 are a display side 100a and a non-display side 100b, respectively, and the non-display side 100b of the display panel 100 faces the out-light side of the backlight module 400.

[0192] In some embodiments, the display device 1000 described above is a liquid crystal display device, and the backlight module 400 adopts a Mini LED chip or a Micro LED chip.

[0193] In the display device 1000 provided by the application, the light-emitting backboard 1 in the backlight module 400 adopts a Mini LED or a Micro LED as a light-emitting device to provide backlight for the display panel 100, and the backlight module 400 is designed as a direct type backlight source, which can be made into a region dimming (Local Dimming) and has better light transmission uniformity, higher contrast ratio (Contrast Ratio) and more bright-dark details compared with a general side-in type backlight source. Compared with an OLED display device, the display device 1000 adopting a Mini LED backlight design has better color rendering.

[0194] As shown in FIG. 16, some embodiments of the present disclosure provide a display device. The display device provided by the embodiments of the present disclosure can be any device that displays whether motion (e.g., video) or fixation (e.g., still image) and whether text or image. More specifically, it is contemplated that the embodiments can be implemented in or in association with a variety of electronic devices such as, but not limited to, mobile phones, wireless devices, personal data assistants (PDAs), hand-held or portable computers, GPS receivers / navigators, cameras, MP4 video players, camcorders, game consoles, watches, clocks, calculators, television monitors, flat panel displays, computer monitors, auto displays (e.g., odometer display, etc.), cockpit controls and / or displays, display of camera views (e.g., display of rear view camera views of a vehicle), electronic photographs, electronic billboards or signs, projectors, architectural structures, packaging, and aesthetic structures (e.g., display of images on a piece of jewelry), and the like.

[0195] In the description of the present specification, specific features, structures, materials or characteristics can be combined in any one or more embodiments or examples in a suitable manner.

[0196] The above description is merely illustrative of the disclosure and not limiting thereof. Any person skilled in the art should understand that changes or substitutions can be made to the technical scope disclosed in the present disclosure, and should be encompassed within the scope of the present disclosure. Therefore, the scope of the present disclosure should be subject to the scope of protection of the claims.

Claims

1. An array substrate, comprising a plurality of sub-pixels, at least one of the plurality of sub-pixels comprising a first transistor; a substrate substrate; a gate layer disposed on one side of the substrate substrate, the gate layer comprising a gate pattern of the first transistor; an active layer disposed on a side of the gate layer away from the substrate substrate, the active layer comprising an active layer pattern of the first transistor; a light-shielding conductive layer disposed on a side of the active layer away from the substrate substrate, the light-shielding conductive layer comprising a light-shielding conductive pattern, the light-shielding conductive pattern comprising a first pattern and a second pattern, a normal projection of the active layer pattern of the first transistor on the substrate substrate being located within a normal projection of the first pattern on the substrate substrate, a distance between a boundary of the normal projection of the first pattern on the substrate substrate and a boundary of the normal projection of the active layer pattern of the first transistor on the substrate substrate being within a set distance range; a transmittance of the first pattern being less than or equal to a transmittance of the second pattern; the second pattern being connected with the gate pattern of the first transistor.

2. The array substrate according to claim 1, wherein, the light-shielding conductive layer comprising a first sub-layer, the first pattern and the second pattern being located in the first sub-layer; a material of the second pattern being a transparent conductive oxide, a material of the first pattern being a blackened transparent conductive oxide; the blackened transparent conductive oxide being obtained by blackening treatment of the transparent conductive oxide, wherein the process condition in which the light transmittance is weakened is that a source power ranges from 5 kW to 7 kW, a hydrogen flow rate ranges from 70000 sccm to 80000 sccm, a working pressure ranges from 900 mt to 1200 mt, and a processing time ranges from 10 S to 20 S.

3. The array substrate of claim 1, wherein, the light-shielding conductive layer comprising a first sub-layer, the first pattern and the second pattern being located in the first sub-layer, and a material of the first pattern and the second pattern being metal, the transmittance of the first pattern being equal to the transmittance of the second pattern.

4. The array substrate of claim 1, wherein, the light-shielding conductive layer comprising a first sub-layer, the first pattern and the second pattern being located in the first sub-layer, and a material of the second pattern being a transparent conductive oxide, a material of the first pattern being metal or an organic light-shielding material.

5. The array substrate of claim 1, wherein, the light-shielding conductive layer comprising a first sub-layer and a second sub-layer, the second sub-layer being located on a side of the first sub-layer away from the substrate substrate, and a transmittance of the second sub-layer being less than a transmittance of the first sub-layer; the first pattern comprising a first sub-pattern located in the first sub-layer and a second sub-pattern located in the second sub-layer, and the second pattern being located in the first sub-layer.

6. The array substrate according to claim 5, wherein, a material of the first sub-layer being a transparent conductive oxide, and a material of the second sub-layer being metal or an organic light-shielding material.

7. The array substrate of claim 1, wherein, the set distance range being from 1 μm to 2.5 μm.

8. The array substrate according to any one of claims 1 to 7, wherein, the sub-pixel further comprising a pixel electrode and a common electrode; the light-shielding conductive layer comprising a first sub-layer, the first sub-layer further comprising a pixel electrode pattern; the gate layer further comprising a common electrode pattern and a common signal line, a material of the common electrode pattern being transparent conductive material, and the common signal line being connected with the common electrode pattern; the pixel electrode pattern and the common signal line having an overlap.

9. The array substrate according to any one of claims 1 to 8, wherein, The gate layer comprises gate lines, and a gate pattern of the first transistor is a part of the gate lines which overlaps with an active layer pattern of the first transistor; The second pattern is connected with the gate lines.

10. The array substrate according to any one of claims 1 to 9, wherein, The array substrate comprises a gate driving circuit, and the gate driving circuit comprises at least one second transistor and a storage capacitor; The gate layer further comprises a gate control line, and the gate control line comprises a gate pattern of the second transistor; The active layer further comprises an active layer pattern of the second transistor; The array substrate further comprises a source-drain metal layer which is arranged on a side of the active layer away from the substrate, and the source-drain metal layer is in contact with the active layer, and the source-drain metal layer comprises a first plate pattern of the storage capacitor; The light-shielding conductive layer further comprises a conductive pattern, and the conductive pattern overlaps with the active layer pattern of the second transistor and overlaps with the first plate pattern of the storage capacitor; and the conductive pattern is connected with the gate control line; The gate control line overlaps with the first plate pattern of the storage capacitor.

11. The array substrate according to claim 10, wherein, A distance between the first plate pattern of the storage capacitor and the conductive pattern is equal to a distance between the first plate pattern of the storage capacitor and the gate control line.

12. A display panel, comprising the array substrate according to any one of claims 1 to 11.

13. The display panel of claim 12, wherein, The display panel further comprises: a color filter substrate arranged on the array substrate; at least one spacer arranged between the array substrate and the color filter substrate; the spacer comprises a first spacer which is arranged on a side of the second pattern and is in contact with the second pattern.

14. The display panel of claim 13, wherein, The spacer comprises a second spacer, and a height of the first spacer is higher than a height of the second spacer; and the second spacer is arranged on a side of the second pattern.

15. A display device, comprising: the display panel according to any one of claims 12 to 14, the display panel comprising a display side and a non-display side; a backlight module arranged on the non-display side of the display panel, and the backlight module is configured to provide a backlight source.

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