Lateral device

Abstract

The present application relates to a lateral device, comprising: a source region (134) having a first conductivity type; a drain region (132) having the first conductivity type; a drift region (110) having the first conductivity type and at least partially located between the source region (134) and the drain region (132); a buried region (112) of a second conductivity type located in the drift region (110) between the source region (134) and the drain region (132); a field oxide layer (150) located on the drift region (110); a top-doped region (120) located in the drift region (110) that is above the buried region (112) of the second conductivity type and below the field oxide layer (150), the top-doped region comprising at least one doped layer of the first conductivity type, and the doped layer of the first conductivity type having a doping concentration greater than that of the drift region (110); and field plates (140) located on the field oxide layer (150).

Description

Lateral device

[0001] Related applications

[0002] The present application claims priority to the Chinese patent application No. 2024112304374, filed on September 3, 2024, entitled “Lateral device”, the contents of which are hereby incorporated by reference in its entirety. TECHNICAL FIELD

[0003] The present application relates to the field of semiconductor manufacturing, and in particular, to a lateral device. BACKGROUND

[0004] The statements herein are provided only to enhance understanding of the present application and are not necessarily intended to constitute the prior art.

[0005] As a core device in BCD (Bipolar-CMOS-DMOS) technology, the mitigation of the contradiction between specific on-resistance and breakdown voltage (breakdown voltage) of high-voltage LDMOS (Lateral Diffused Metal Oxide Semiconductor Field Effect Transistor) has always been the main way to save chip cost. The development of RESURF (Reduced Surface Field) technology, D (Double)-RESURF and T (Triple)-RESURF technology has continuously reduced the specific on-resistance of the device.

[0006] The industry expects a RESURF structure that further improves the breakdown voltage and reduces the on-resistance. SUMMARY

[0007] According to various embodiments of the present application, a lateral device is provided.

[0008] A lateral device, comprising: a source region having a first conductivity type; a drain region having the first conductivity type; a drift region having the first conductivity type and at least partially located between the source region and the drain region; a second conductivity type buried region located in the drift region between the source region and the drain region; the first conductivity type and the second conductivity type being opposite conductivity types; a field oxide layer located on the drift region; a top doping located in the drift region above the second conductivity type buried region and below the field oxide layer, comprising at least one first conductivity type doping layer, the doping concentration of the first conductivity type doping layer being greater than the doping concentration of the drift region; a field plate located on the field oxide layer.

[0009] In one embodiment, the field plate is used to assist in depleting the top doping.

[0010] In one embodiment, the top doping includes at least two layers of first conductivity type doping layers with different doping depths, and the doping concentration of the top layer of the first conductivity type doping layers in the top doping is greater than the doping concentration of the rest of the first conductivity type doping layers, and the adjacent first conductivity type doping layers are separated by a part of the drift region.

[0011] In one embodiment, the doping concentration of the top layer of the first conductivity type doping layers is 1e15-5e17 / cm 3 .

[0012] In one embodiment, the field plate is a floating field plate.

[0013] In one embodiment, the field plate includes an outer ring and a spiral part inside the outer ring, the spiral part is connected to the outer ring, and the ring width of the outer ring is greater than the strip width of the spiral part.

[0014] In one embodiment, the field plate includes an outer ring, a plurality of annular structures inside the outer ring, and a plurality of strip parts, each strip part is located between two adjacent annular structures, and the ring width of the outer ring is greater than the strip width of each annular structure and the strip width of each strip part.

[0015] In one embodiment, each strip part is located on both sides of the long axis of the field plate, and no strip part is arranged on both sides of the short axis of the field plate.

[0016] In one embodiment, the field plate is a polysilicon field plate.

[0017] In one embodiment, the field plate is a hole field plate, the bottom of the hole field plate penetrates into the field oxide layer, the hole field plate includes conductive material arranged in a plurality of contact holes, and the lateral device further includes a metal wiring layer on the hole field plate, the metal wiring layer connects at least part of the contact holes of the hole field plate into at least one group, and the conductive material in each group of contact holes is electrically connected together by the metal wiring layer.

[0018] In one embodiment, the lateral device further includes a gate arranged above the region between the source region and the drain region and extending from the edge of the source region to the field oxide layer; an interlayer dielectric layer covering the source region, the drain region, the gate, and the field oxide layer; wherein the metal wiring layer is arranged on the interlayer dielectric layer, and each contact hole of the hole field plate penetrates through the interlayer dielectric layer and penetrates into the field oxide layer downward.

[0019] In one embodiment, the lateral device is a silicon-on-insulator lateral device; the silicon-on-insulator lateral device includes a substrate and an insulating buried layer on the substrate, and the drift region is located on the insulating buried layer.

[0020] In one of the embodiments, the substrate is a silicon substrate, and the material of the insulating buried layer is an oxide of silicon.

[0021] In one of the embodiments, the lateral device is a lateral diffused metal oxide semiconductor field effect transistor, and the lateral device further comprises a first-conductivity-type well region and a second-conductivity-type well region, the drain region is disposed in the first-conductivity-type well region, and the source region is disposed in the second-conductivity-type well region.

[0022] In one of the embodiments, the first conductivity type is N type, and the second conductivity type is P type.

[0023] In one of the embodiments, a top surface of the first-conductivity-type doped layer of the top layer directly contacts a bottom surface of the field oxide layer.

[0024] The details of one or more embodiments of the application are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the application will be apparent from the description and drawings, and from the claims. BRIEF DESCRIPTION OF DRAWINGS

[0025] In order to more clearly illustrate the technical solutions in the embodiments of the application or in the prior art, the accompanying drawings needed to be used in the embodiments or the description of the prior art will be briefly introduced. Obviously, the accompanying drawings in the following description only represent some embodiments of the application, and for those ordinary skilled in the field, other drawings can be obtained from the disclosed drawings without any creative effort.

[0026] FIG. 1 is a structural schematic diagram of a lateral device in an embodiment of the application.

[0027] FIG. 2 is a partial layout of the field plate 140 in an embodiment of the application.

[0028] FIG. 3 is a layout of the field plate 140 in another embodiment of the application.

[0029] FIG. 4 is a structural schematic diagram of a lateral device in another embodiment of the application.

[0030] FIG. 5 is a top view of the hole field plate 142 in an embodiment of the application. DETAILED DESCRIPTION

[0031] The technical solutions in the embodiments of the application will be described clearly and completely in the following description of the technical solutions in the embodiments of the application with reference to the accompanying drawings in the embodiments of the application. Obviously, the described embodiments only represent some of the embodiments of the application, rather than all the embodiments. Based on the embodiments in the application, all other embodiments obtained by those ordinary skilled in the field without any creative effort fall within the protection scope of the application.

[0032] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the description herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0033] It will be understood that when an element or layer is referred to as being "on" or "connected to" or "coupled to" another element or layer, it can be directly on, connected or coupled to the other element or layer or intervening elements or layers can be present. In contrast, when an element is referred to as being "directly on," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present application.

[0034] Spatially relative terms, such as "beneath", "below", "lower", "under", "above", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" or "over" the other elements or features. Thus, the exemplary term "below" can encompass both an orientation of above and below. The device can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0035] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0036] Embodiments of the application are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the application. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Thus, embodiments of the application should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an implanted region illustrated as a rectangle will, typically, have rounded or curved features and / or a gradient of implant concentration at its edges rather than a binary change between implanted and non-implanted regions. Similarly, a buried region formed by implantation can result in some implantation in a region between the buried region and a surface through which the implant was performed. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the precise shape of a region of a device and are not intended to limit the scope of the application.

[0037] The substrate termination and Ntop structure proposed by the Qiao Ming group of the University of Electronic Science and Technology of China on the basis of the T-RESURF structure solves the terminal withstand voltage and low specific on-resistance problems of the interdigital structure, and Ntop is an N-type doped region close to the top of the drift region. However, the interdigital structure avoids high-voltage cross-line, but the terminal area of the source package leakage is too large and the isolation is inconvenient. The conventional Ntop structure is only assisted by Pbury (P-type buried layer) for depletion, and the doping concentration of Ntop is difficult to further improve, so the on-resistance is limited. At present, there is no suitable technology to increase the surface concentration of the drift region in addition to Ntop. Although the surface super-junction can improve the doping concentration, the requirement for charge balance is too harsh. In the special lateral integrated device, under the condition of high-energy implantation Gaussian distribution and substrate assisted depletion effect, there is no suitable solution to increase the surface concentration of the drift region.

[0038] The present application provides an innovative lateral device with RESURF structure using field plate to assist the depletion of Ntop. FIG. 1 is a schematic diagram of a lateral device in an embodiment of the present application, which includes a source region 134, a drain region 132, a drift region 110, a buried region of second conductivity type 112, a top doping 120, a field oxide layer 150, and a field plate 140. The source region 134, the drain region 132, and the drift region 110 have a first conductivity type. In the embodiment shown in FIG. 1, the first conductivity type is N-type, and the second conductivity type is P-type. Therefore, the buried region of second conductivity type 112 is a P-bury in the N-type drift region 110, and the top doping 120 is Ntop. In other embodiments, the first conductivity type can be P-type, and the second conductivity type can be N-type.

[0039] The drift region 110 is located at least partially between the source region 134 and the drain region 132. The buried region of second conductivity type 112 is located in the drift region 110 between the source region 134 and the drain region 132. The field oxide layer 150 is located on the drift region 110. The top doping 120 is located in the drift region 110 above the buried region of second conductivity type 112 and below the field oxide layer 150, and the top doping 120 includes at least one layer of first conductivity type doping layer. In the embodiment shown in FIG. 1, the top doping 120 includes two layers of first conductivity type doping layer, i.e., N-type layer 122 and N-type layer 124. The doping concentration of the first conductivity type doping layer is greater than the doping concentration of the drift region 110. The field plate 140 is located on the field oxide layer 150 to assist the depletion of the top doping 120.

[0040] The above-mentioned lateral device uses the field plate 140 to assist the depletion of the first conductivity type doping layer above the buried region of second conductivity type 112. Therefore, the first conductivity type doping layer can have a higher doping concentration, thereby further reducing the on-resistance of the device.

[0041] In an embodiment of the present application, the top doping 120 includes at least two layers of first conductivity type doping layer with different junction depths, i.e., one layer of first conductivity type doping layer is located above another layer of first conductivity type doping layer, and these layers of first conductivity type doping layer are arranged from top to bottom in the drift region 110 above the buried region of second conductivity type 112. The doping concentration of the top layer of first conductivity type doping layer in the top doping 120 is greater than the doping concentration of the remaining first conductivity type doping layers, for example, the doping concentration of the N-type layer 122 is greater than the doping concentration of the N-type layer 124 in FIG. 1, and the adjacent first conductivity type doping layers are separated by a portion of the drift region 110. In the embodiment shown in FIG. 1, the top surface of the top layer of first conductivity type doping layer, i.e., the N-type layer 122, in the top doping 120 directly contacts the bottom surface of the field oxide layer 150. In the embodiment shown in FIG. 1, the doping concentration of the N-type layer 122 is 1e15-5e17 / cm3, and the doping concentration of the N-type layer 124 is 1e15-5e17 / cm3. 3The implant dose of the N-type ion implantation forming the N-type layer 122 is 0.5e12-3e12 / cm 2 Since the present application uses the field plate 140 to assist in depleting the N-type layer 122, the doping concentration of the N-type layer 122 can be increased by 2-3 times compared with the conventional Ntop, thereby making the device obtain a lower on-resistance.

[0042] In the embodiment shown in FIG. 1, the field plate 140 is a floating field plate, i.e., a field plate not connected with an electrode. In one embodiment of the present application, the floating field plate is a floating polysilicon field plate; in other embodiments, the floating field plate can also be made of other materials.

[0043] FIG. 2 is a partial layout of the field plate 140 in one embodiment of the present application. In the embodiment shown in FIG. 2, the field plate 140 includes an outer ring 242, a plurality of ring structures 244 inside the outer ring 242, and a plurality of strip-shaped portions 246, each of which is located between two adjacent ring structures 244. The ring width of the outer ring 242 is greater than the strip width of each ring structure 244 and the strip width of each strip-shaped portion 246. Since the field plate 140 shown in FIG. 2 is an axisymmetric pattern, it is symmetric about the left-right direction and the up-down direction, and therefore FIG. 2 omits the lower part structure which is symmetric to the upper part structure. In the embodiment shown in FIG. 2, the strip-shaped portions 246 are located on both sides of the long axis of the field plate 140, and no strip-shaped portion 246 is provided on both sides of the short axis of the field plate 140. In the embodiment shown in FIG. 2, a strip-shaped portion 246 is provided between each two adjacent ring structures 244, a strip-shaped portion 246 is also provided between the outer ring 242 and the outermost ring structure 244, and a strip-shaped portion 246 is also provided inside the innermost ring structure 244.

[0044] FIG. 3 is a layout of the field plate 140 in another embodiment of the present application. In the embodiment shown in FIG. 3, the field plate 140 includes an outer ring 342 and a spiral portion 344 inside the outer ring 342. The spiral portion 344 is connected with the outer ring 342, and the ring width of the outer ring 342 is greater than the strip width of the spiral portion 344.

[0045] It should be noted that FIGS. 2 and 3 only show two structural shapes of the field plate 140, and in other embodiments, the field plate 140 can also have other shapes.

[0046] In the embodiment shown in FIG. 1, the lateral device is a silicon-on-insulator (SOI) device. The device includes a substrate 10 and an insulating buried layer 20 on the substrate 10. The drift region 110 is located on the insulating buried layer 20. In the embodiment shown in FIG. 1, the substrate 10 is a P-type silicon substrate, and the material of the insulating buried layer 20 is an oxide of silicon, such as silicon dioxide.

[0047] In one embodiment of the application, the lateral device further includes a gate 138. The gate 138 is disposed over the region between the source region 134 and the drain region 132 and extends from the edge of the source region 134 onto the field oxide layer 150. In one embodiment of the application, the gate 138 is formed of polysilicon material, although in other embodiments, metal, metal nitride, metal silicide, or similar compounds can be used as the material for the gate 138. The lateral device shown in Figure 1 is an LDMOSFET.

[0048] In one embodiment of the application, the gate 138 and the field plate 140 are formed in the same step by depositing polysilicon and then photolithographing and etching the polysilicon in the same step.

[0049] In one embodiment of the application, a gate dielectric layer is also disposed under the gate 138. The gate dielectric layer can include conventional dielectric materials such as oxides, nitrides, and oxynitrides of silicon having dielectric constants from about 4 to about 20 (measured in vacuum), or the gate dielectric layer can include higher dielectric constant dielectric materials having dielectric constants from about 20 to at least about 100. Such higher dielectric constant dielectric materials can include, but are not limited to, hafnium oxide, hafnium silicates, titanium oxide, barium strontium titanates (BSTs), and lead zirconium titanates (PZTs).

[0050] Figure 4 is a schematic diagram of the structure of a lateral device in another embodiment of the application. The lateral device includes a source region 134, a drain region 132, a drift region 110, a buried region 112 of a second conductivity type, a top doping 120 including an N-type layer 122 and an N-type layer 124, and a field oxide layer 150. The source region 134, the drain region 132, and the drift region 110 have a first conductivity type. The drift region 110 is at least partially located between the source region 134 and the drain region 132. The buried region 112 of the second conductivity type is located in the drift region 110 between the source region 134 and the drain region 132. The field oxide layer 150 is located on the drift region 110. The top doping 120 is located in the drift region 110 above the buried region 112 of the second conductivity type and below the field oxide layer 150 and includes at least one layer of a first conductivity type doping. In the embodiment shown in Figure 4, the top doping 120 includes two layers of the first conductivity type doping, namely the N-type layer 122 and the N-type layer 124. The doping concentration of the first conductivity type doping layer is greater than the doping concentration of the drift region 110. A field plate 140 is located on the field oxide layer 150 to assist in depleting the top doping 120.

[0051] In contrast to the field plate 140 of FIG. 1, the field plate of the embodiment of FIG. 4 is a via field plate 142. The via field plate 142 has a bottom portion that penetrates down into the field oxide layer 150, and includes conductive material disposed in a plurality of contact vias. The lateral device also includes a metal interconnect layer 160 disposed on the via field plate 142. The metal interconnect layer 160 connects at least some of the contact vias of the via field plate 142 into one or more groups, with the conductive material in each group of contact vias being electrically connected together by the metal interconnect layer 160. For example, the contact vias can be arranged in columns, with the odd-numbered columns of contact vias connected to the metal interconnect layer 160 and the even-numbered columns of contact vias not connected to the metal interconnect layer 160, or vice versa. In one embodiment of the application, the conductive material of the via field plate 142 can be a metal or an alloy, and in other embodiments, other conductive materials can be used for the via field plate 142.

[0052] In the embodiment of FIG. 4, the lateral device also includes an interlayer dielectric layer 154 disposed on the source region 134, the drain region 132, the gate 138, and the field oxide layer 150. The metal interconnect layer 160 is disposed on the interlayer dielectric layer 154, and the contact vias of the via field plate 142 penetrate through the interlayer dielectric layer 154 and down into the field oxide layer 150.

[0053] FIG. 5 is a top view of the via field plate 142 of one embodiment of the application. The metal interconnect layer 160 is transparentized in FIG. 5 to facilitate showing the location of the via field plate 142. It is noted that FIG. 5 shows only one arrangement of the via field plate 142, and other embodiments of the via field plate 142 can have other shapes and configurations.

[0054] In the embodiment of FIG. 4, the lateral device also includes an etch stop layer 152 disposed between the field oxide layer 150 and the N-type layer 122, and used as an etch stop layer when etching the interlayer dielectric layer 154 to form the contact vias of the via field plate 142. The etch stop layer 152 can be a silicon nitride layer, or other material that can be used as an etch stop layer when etching silicon dioxide.

[0055] In the embodiments shown in FIG. 1 and FIG. 4, the lateral device further comprises a first-conductivity-type well region 114 and a second-conductivity-type well region 116. The drain region 132 is located in the first-conductivity-type well region 114, and the source region 134 is located in the second-conductivity-type well region 116. The drift region 110 is at least partially located between the first-conductivity-type well region 114 and the second-conductivity-type well region 116. The second-conductivity-type buried region 112 is located between the first-conductivity-type well region 114 and the second-conductivity-type well region 116. The doping concentration of the source region 134 and the drain region 132 is greater than the doping concentration of the first-conductivity-type well region 114. In an embodiment of the present application, the doping concentration of the first-conductivity-type well region 114 is greater than the doping concentration of the drift region 110. In the embodiments shown in FIG. 1 and FIG. 4, the source region 134 and the drain region 132 are N+ regions.

[0056] In the embodiments shown in FIG. 1 and FIG. 4, the lateral device further comprises a body tap region 136 located in the second-conductivity-type well region 116. The doping concentration of the body tap region 136 is greater than the doping concentration of the second-conductivity-type well region 116. In the embodiments shown in FIG. 1 and FIG. 4, the body tap region 136 is a P+ region.

[0057] In the embodiments shown in FIG. 4, the lateral device is further provided with a contact hole penetrating through the interlayer dielectric layer 154 and electrically connecting the source region 134, the drain region 132, the gate 138 and the body tap region 136 to the metal wiring layer 160.

[0058] Based on all the above embodiments, the present application has the effect of one more RESURF field plate than the conventional P-bury auxiliary depletion, and the top layer of the first-conductivity-type doped layer, i.e. the N-type layer 122, in the top doping 120 can have 2-3 times higher doping concentration than the conventional Ntop. And the conventional field plate is only used in high-voltage lateral devices to shield high-voltage cross lines, and for the first time in the present application, the field plate is used to assist the depletion of the surface Ntop, so that the implantation dose and doping concentration of the Ntop can be significantly improved.

[0059] The technical features of the above embodiments can be combined in any manner. To make the description concise, not all possible combinations of the technical features in the above embodiments are described, but as long as the combinations of the technical features do not contradict, they should be considered within the scope of the present application.

[0060] The above embodiments only express several implementation manners of the present application, and the description is relatively specific and detailed, but it should not be understood as a limitation on the patent scope of the present application. It should be noted that for ordinary skilled persons in the art, several modifications and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the patent protection scope of the present application should be subject to the appended claims.

Claims

1. A lateral device, comprising: a source region having a first conductivity type; a drain region having the first conductivity type; a drift region having the first conductivity type and at least partially located between the source region and the drain region; a buried region of a second conductivity type located in the drift region between the source region and the drain region; the first conductivity type and the second conductivity type being opposite conductivity types; a field oxide layer located on the drift region; a top doping located in the drift region above the buried region of the second conductivity type and below the field oxide layer, the top doping comprising at least one layer of a first conductivity type doping layer having a doping concentration greater than a doping concentration of the drift region; and a field plate located on the field oxide layer. The field plate is configured to assist in depleting the top doping.

2. The lateral device according to claim 1, wherein The top doping comprises at least two layers of the first conductivity type doping layer having different junction depths, and a top layer of the first conductivity type doping layer in the top doping has a doping concentration greater than a doping concentration of the remaining first conductivity type doping layers, and the top layer of the first conductivity type doping layer is separated from the remaining first conductivity type doping layers by a portion of the drift region.

3. The lateral device of claim 1, wherein, A top surface of the top layer of the first conductivity type doping layer is in direct contact with a bottom surface of the field oxide layer.

4. The lateral device according to claim 3, wherein The field plate is a floating field plate.

5. The lateral device of claim 1, wherein, The field plate comprises an outer ring and a spiral located inside the outer ring, the spiral is connected to the outer ring, and a ring width of the outer ring is greater than a strip width of the spiral.

6. The lateral device according to claim 5, wherein The field plate comprises an outer ring, a plurality of ring structures located inside the outer ring, and a plurality of strip portions, each of the strip portions is located between two adjacent ring structures, a ring width of the outer ring is greater than a strip width of each of the ring structures and a strip width of each of the strip portions.

7. The lateral device of claim 5, wherein, Each of the strip portions is located on both sides of a long axis of the field plate, and no strip portion is located on both sides of a short axis of the field plate.

8. The lateral device according to claim 7, wherein The field plate is a polysilicon field plate.

9. The lateral device of claim 5, wherein, The field plate is a hole field plate, a bottom of the hole field plate penetrates into the field oxide layer, the hole field plate comprises a conductive material located in a plurality of contact holes, the lateral device further comprises a metal wiring layer located on the hole field plate, the metal wiring layer connects at least a portion of the contact holes of the hole field plate into at least one group, and the conductive material in each group of the contact holes is electrically connected together by the metal wiring layer.

10. The lateral device of claim 1, wherein, Further comprising:

11. The lateral device according to claim 10, wherein a gate located above a region between the source region and the drain region and extending from an edge of the source region to the field oxide layer; and an interlayer dielectric layer covering the source region, the drain region, the gate and the field oxide layer; wherein the metal wiring layer is located on the interlayer dielectric layer, and each of the contact holes of the hole field plate penetrates through the interlayer dielectric layer and penetrates into the field oxide layer. The lateral device is a silicon-on-insulator lateral device. The silicon-on-insulator lateral device comprises a substrate and an insulating buried layer on the substrate, and the drift region is located on the insulating buried layer; the substrate is a silicon substrate, and a material of the insulating buried layer is an oxide of silicon.

12. The lateral device of claim 1, wherein, The lateral device is a lateral diffusion metal oxide semiconductor field effect transistor, and the lateral device further comprises a first conductivity type well region and a second conductivity type well region, the drain region is located in the first conductivity type well region, and the source region is located in the second conductivity type well region.

13. The lateral device of claim 1, wherein, ​ 14. The lateral device of claim 1, wherein, ​ 15. The lateral device of claim 1, wherein, The first conductivity type is N type and the second conductivity type is P type. The first conductivity type is N type and the second conductivity type is P type.

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