Techniques for improving utilization of a GPU

Abstract

The method and system for acceleration of artificial intelligence (Al) computation is presented. The system includes: a barycentric rasterizer; a processing circuitry including a plurality of architectural registers; a first memory accessible by the barycentric rasterizer and the processing circuitry; and a second memory, the second memory containing instructions that, when executed by the processing circuitry, configure the system to: trigger a pre-fetch memory operation performed by the barycentric rasterizer, wherein the pre-fetch memory operation includes reading from the first memory a value common to a plurality of computational threads; configure the barycentric rasterizer to write the value to an architectural register of the plurality of architectural registers; spawn each of the plurality of computational threads, each computational thread programmed to utilize at least the value; and process the spawned plurality of computational threads.

Description

f’Cl / GR2024 / 000025TECHNIQUES FOR IMPROVING UTILIZATION OF A GPUTECHNICAL FIELD

[0001] The present disclosure A relates generally to acceleration of artificial intelligence computations and more specifically to acceleration of computation of a deep neural network with an output tensor having an input that impacts a plurality of output values.

[0002] The present disclosure B relates generally to an acceleration of artificial intelligence computations and more specifically to acceleration of computation of a convolutional neural network with an output tensor having an input vector that impacts a plurality of output values.

[0003] The present disclosure C relates generally to the field of anti-aliasing for minimizing visual artifacts in rendering three-dimensional (3D} graphics.BACKGROUND

[0004] Barycentric rasterization techniques represent a fundamental aspect of computer graphics, facilitating the rendering of complex scenes in real-time applications such as video games, simulations, and augmented reality systems. Rasterization involves the process of converting geometric primitives, such as polygons, into pixels on a display or image plane. Among the various rasterization methods, barycentric rasterization stands out for its efficiency and accuracy in determining pixel coverage within polygons.

[0005] Traditionally, rasterization algorithms compute the coverage of pixels within polygons by evaluating the positions of vertices and interpolating attributes across the polygon surface. Barycentric rasterization calculates the barycentric coordinates of each pixel relative to the vertices of the polygon. These coordinates define the weights of the vertices contributing to the pixel's position and attribute interpolation. By utilizing barycentric coordinates, this technique enables efficient determination of pixel coverage, facilitating the rendering of smooth and detailed images.

[0006] However, despite its advantages, barycentric rasterization methods encounter challenges related to memory access and computational efficiency, particularly when processing large and complex scenes. In rasterization pipelines, memory access patterns play a crucial role in overalls .A 0 A v 9PCT / GR 2024 / 000025 performance, as certain memory operations, such as non-consecutive addresses, can lead to bottlenecks and degrade rendering speed.

[0007] Optimizing memory access in barycentric rasterization involves addressing issues such as cache utilization, memory bandwidth constraints, and data locality. Efficient memory access strategies aim to minimize latency and maximize throughput, thereby enhancing the performance of rasterization pipelines.

[0008] Moreover, with the proliferation of artificial intelligence and machine learning algorithms, many parallel processor architectures, such as those utilized by a graphics processing unit {GPU) are repurposed to perform the computations required by these applications. (0009] It would therefore be advantageous to provide a solution that would overcome the challenges noted above.

[0010] When it is necessary to calculate an output value of an output volume, for example, the output value 120-1,1 of output volume 120 shown in Fig. 1A, it is performed using an input volume 110 comprising the input data 112 and padding data that completes the input volume 110. As shown, the padding is all zeros, however, other values may be used. In the prior art, the computation of the out value 120-1,1 is typically performed by computing offsets and then loading data from memory into registers of a kernel code. However, this method involves mul tiple memory reads which reduce the performance of the system, i.e., providing the output volume 120 requires more time, more compute power, or both. (0011] It would be therefore advantageous to provide a solution that reduces the memory access demands of computation of values of an output volume that depends on a padded input volume.

[0012] Anti-aliasing is a fundamental technique in computer graphics aimed at reducing visual artifacts, commonly referred to as "jaggies” that occur when displaying images, text, or 3D graphics on digital screens. These jagged edges are particularly noticeable when rendering high- resolution images, text, or 3D graphics on digital screens, and specifically on lower-resolution displays. The primary goal of anti-aliasing is to smooth out these jagged edges to create a more visually pleasing and natural appearance.

[0013] The concept of anti-aliasing dates back to the early days of computer graphics when rasterbased displays became prevalent. Initially, graphics were displayed using a process known as"nearest-neighbor interpolation," which simply rounded each pixel to the nearest color value from the source image. However, this approach resulted in noticeable stair-stepping along diagonal lines and curved edges. To address this issue, anti-aliasing techniques were developed to intelligently blend colors along the edges of objects, effectively simulating higher resolutions and reducing the appearance of "jaggies". Different anti-aliasing methods have been devised over the years, each with its own trade-offs in terms of performance impact and visual quality.

[0014] Some common anti-aliasing techniques include multisample anti-aliasing (MSAA), which selectively applies anti-aliasing to specific edges or surfaces, and supersample anti-aliasing (SSAA), which renders the scene at high resolution before downscaling it to the display resolution. Additionally, post processing anti-aliasing techniques like FXAA (Fast Approximate Anti-Aliasing) and SMAA (Subpixel Morphological Anti-Aliasing) are applied after rendering to smooth out edges in the final image.

[0015] Overall, anti-aliasing plays a crucial role in enhancing the visual quality of computer graphics by minimizing jagged edges and improving the overall realism of rendered scenes. (0016] In the field of anti-aliasing, there are several ongoing challenges and problems that developers face in areas such as performance impact, required memory bandwidth, edge detection, and integration.

[0017] Many anti-aliasing techniques can significantly Impact system performance, particularly in real-time applications such as video games. Techniques, like supersample anti-aliasing (SSAA), require rendering the scene at a higher resolution before downsampling, which can be computationally intensive and may not be feasible for real-time applications on lower-end graphics processing units. Balancing a trade-off between visual quality and performance remains a challenge, especially as display resolutions and graphics complexity continue to increase.

[0018] Anti-aliasing techniques aim to smooth out jagged edges and reduce visual artifacts but they may inadvertently introduce new artifacts or blur the image excessively. Edge detection algorithms play a crucial role in identifying where anti-aliasing should be applied, but accurately detecting edges in complex scenes with varying lighting conditions and textures can be challenging.0 0 ^ 2 0 2 4PCT / GR2024 / 000025

[0019] Integrating anti-aliasing techniques into existing rendering pipelines and graphics Application Programming Interfaces (APIs) can be complex, particularly in heterogenous environments with diverse hardware configurations. Ensuring compatibility across different hardware systems while maintaining performance and visual consistency poses a significant challenge for developers.(0020] Therefore, it would be advantageous to provide a solution that would overcome the challenges noted above.SUMMARY

[0021] A summary of disclosure A follows. This summary is provided for the convenience of the reader to provide a basic understanding of such embodiments and does not wholly define the breadth of the disclosure. This summary Is not an extensive overview of all contemplated embodiments, and is intended to neither identify key or critical elements of all embodiments nor to delineate the scope of any or all aspects. Its sole purpose is to present some concepts of one or more embodiments in a simplified form as a prelude to the more detailed description that is presented later. For convenience, the term "some embodiments" or "certain embodiments" may be used herein to refer to a single embodiment or multiple embodiments of the disclosure.

[0022] A system of one or more computers can be configured to perform particular operations or actions by virtue of having software, firmware, hardware, or a combination of them installed on the system that in operation causes or cause the system to perform the actions. One or more computer programs can be configured to perform particular operations or actions by virtue of including instructions that, when executed by data processing apparatus, cause the apparatus to perform the actions.

[0023] In one general aspect, the system may include a barycentric rasterizer; a processing circuitry including a plurality of architectural registers; a first memory accessible by the barycentric rasterizer and the processing circuitry; a second memory, the second memory containing instructions that, when executed by the processing circuitry, configure the system to; trigger a pre-fetch memory operation performed by the barycentric rasterizer, where the pre-fetch memory operation includes reading from the first memory a value common to a plurality of computational threads; configure the barycentric rasterizer to write the value to an architecturalregister of the plurality of architectural registers; spawn each of the plurality of computational threads, each computational thread programmed to utilize at least the value; and process the spawned plurality of computational threads. Other embodiments of this aspect include corresponding computer systems, apparatus, and computer programs recorded on one or more computer storage devices, each configured to perform the actions of the methods,

[0024] Implementations may include one or more of the following features. A system where the second memory contains further instructions that, when executed by the processing circuitry, further configure the system to: detect a plurality of threads, each thread utilizing a plurality of common values; and trigger the pre-fetch memory operation based on detecting that the plurality of threads utilizes the plurality of common values. A system where the second memory contains further instructions that, when executed by the processing circuitry, further configure the system to: write a plurality of values to a portion of the plurality of architectural registers. A system where the second memory contains further instructions that, when executed by the processing circuitry, further configure the system to: process the spawned plurality of computational threads on a parallel processing circuitry, A system where the second memory contains further instructions that, when executed by the processing circuitry, further configure the system to: configure the processing circuitry to read the value from the architectural register; and process the spawned plurality of computational threads based at least on the read value, where each computational thread corresponds to a kernel code. A system where the value is utilized in any one of: a filter, a kernel, a weight, and a combination thereof. Implementations of the described techniques may include hardware, a method or process, or a computer tangible medium.

[0025] in one general aspect, a non-transltory computer-readable medium may include one or more instructions that, when executed by one or more processors of a device, cause the device to: trigger a pre-fetch memory operation performed by a barycentric rasterizer of the one or more processors, where the pre-fetch memory operation includes reading from a first memory of the device a value common to a plurality of computational threads; configure the barycentric rasterizer to write the value to an architectural register of a plurality of architectural registers of the one or more processors; spawn each of the plurality of computational threads, each computational thread programmed to utilize at least the value; and process the spawned pluralityof computational threads. Other embodiments of this aspect include corresponding computer systems, apparatus, and computer programs recorded on one or more computer storage devices, each configured to perform the actions of the methods.

[0026] Implementations may include one or more of the following features. A non-transitory computer-readable medium where the one or more instructions further cause the device to: detect a plurality of threads, each thread utilizing a plurality of common values; and trigger the pre-fetch memory operation based on detecting that the plurality of threads utilizes the plurality of common values. A non-transitory computer-readable medium where the one or more instructions further cause the device to: write a plurality of values to a portion of the plurality of architectural registers. A non-transitory computer-readable medium where the one or more instructions further cause the device to: process the spawned plurality of computational threads on a parallel processing circuitry. A non-transitory computer-readable medium where the one or more instructions further cause the device to: configure the one or more processors to read the value from the architectural register; and process the spawned plurality of computational threads based at least on the read value, where each computational thread corresponds to a kernel code.A non-transitory computer-readable medium where the value is utilized in any one of: a filter, a kernel, a weight, and a combination thereof, implementations of the described techniques may include hardware, a method or process, or a computer tangible medium,

[0027] A summary of disclosure B follows. This summary is provided for the convenience of the reader to provide a basic understanding of such embodiments and does not wholly define the breadth of the disclosure. This summary is not an extensive overview of all contemplated embodiments, and is intended to neither identify key or critical elements of all embodiments nor to delineate the scope of any or all aspects, its sole purpose is to present some concepts of one or more embodiments in a simplified form as a prelude to the more detailed description that is presented later. For convenience, the term "some embodiments" or "certain embodiments" may be used herein to refer to a single embodiment or multiple embodiments of the disclosure.

[0028] A system of one or more computers can be configured to perform particular operations or actions by virtue of having software, firmware, hardware, or a combination of them installed on the system that in operation causes or cause the system to perform the actions. One or morecomputer programs can be configured to perform particular operations or actions by virtue of including instructions that, when executed by a data processing apparatus, cause the apparatus to perform the actions.

[0029] In one general aspect, a non-transitory computer-readable medium may include one or more instructions that, when executed by one or more processors of a device, cause the device to: determine a plurality of output dimensions of the output generated by a processing circuitry, the output including a plurality of output values arranged according to the plurality of output dimensions; configure a barycentric rasterizer to generate a shuffle vector for each output value; initiate a vectorized load memory operation based on the shuffle vector and an input into a register of the processing circuitry; and configure the processing circuitry to initiate an operation including reading a portion of the input from the register. Other embodiments of this aspect include corresponding computer systems, apparatus, and computer programs recorded on one or more computer storage devices, each configured to perform the actions of the methods.

[0030] Implementations may include one or more of the following features. A non-transitory computer-readable medium where the one or more instructions further cause the device to: receive an input matrix; and compute an output value of the plurality of output values based on a value of the input value, the initiated operation, and the shuffle vector. A non-transitory computer-readable medium where the one or more instructions further cause the device to: initiate a new vectorized load memory operation based on a new shuffle vector and another input into the register. A non-transitory computer-readable medium where the one or more instructions further cause the device to: configure the barycentric rasterizer to initiate the vectorized load memory operation. A non-transitory computer-readable medium where the output is an output tensor. A non-transitory computer-readable medium where the input is an input tensor. A non-transitory computer-readable medium where the device includes a barycentric rasterizer. A non-transitory computer-readable medium where the device further comprises a plurality of registers, including the register. A non-transitory computer-readable medium where the one or more instructions further cause the device to: generate padding values for the input. A non-transitory computer-readable medium where the padding values of a portion of the input are read from the register. A non-transitory computer-readable medium where theone or more instructions further cause the device to: configure the barycentric rasterizer to generate at least a value of the shuffle vector; and load the generated at least a value of the shuffle vector into the register. Implementations of the described techniques may include hardware, a method or process, or a computer tangible medium.

[0031] ln one general aspect, a system may include a processing circuitry. The system may also include a memory, the memory containing instructions that, when executed by the processing circuitry, configure the system to: determine a plurality of output dimensions of the output generated by a processing circuitry, the output including a plurality of output values arranged according to the plurality of output dimensions, The system may in addition configure a barycentric rasterizer to generate a shuffle vector for each output value. The system may moreover initiate a vectorized load memory operation based on the shuffle vector and an input into a register of the processing circuitry. The system may also configure the processing circuitry to initiate an operation including reading a portion of the input from the register. Other embodiments of this aspect include corresponding computer The systems, apparatus, and computer programs recorded on one or more computer storage devices, each configured to perform the actions of the methods.

[0032] Implementations may include one or more of the following features. A system where the memory contains further instructions which when executed by the processing circuitry further configure the system to: receive an input matrix; and compute an output value of the plurality of output values based on a value of the input value, the initiated operation, and the shuffle vector.A system where the memory contains further instructions which when executed by the processing circuitry further configure the system to: initiate a new vectorized load memory operation based on a new shuffle vector and another input into the register. A system where the memory contains further instructions which when executed by the processing circuitry further configure the system to: configure the barycentric rasterizer to initiate the vectorized load memory operation. A system where the output is an output tensor. A system where the input is an input tensor. A system where the processing circuitry further includes a barycentric rasterizer. A system where the processing circuitry further comprises a plurality of registers, including the register. A system where the memory contains further instructions which when executed by thew s.>CT / GR2024 / 000025 processing circuitry further configure the system to: generate padding values for the input. A system where the padding values of a portion of the input are read from the register. A system where the memory contains further instructions which when executed by the processing circuitry further configure the system to: configure the barycentric rasterizer to generate at least a value of the shuffle vector; and load the generated at least a value of the shuffle vector into the register.Implementations of the described techniques may include hardware, a method or process, or a computer tangible medium.

[0033] A summary of disclosure C follows. This summary is provided for the convenience of the reader to provide a basic understanding of such embodiments and does not wholly define the breadth of the disclosure. This summary is not an extensive overview of all contemplated embodiments, and is intended to neither identify key or critical elements of all embodiments nor to delineate the scope of any or all aspects. Its sole purpose is to present some concepts of one or more embodiments in a simplified form as a prelude to the more detailed description that is presented later. For convenience, the term "some embodiments” or "certain embodiments'' may be used herein to refer to a single embodiment or multiple embodiments of the disclosure.

[0034] A system of one or more computers can be configured to perform particular operations or actions by virtue of having software, firmware, hardware, or a combination of them installed on the system that in operation causes or cause the system to perform the actions. Gne or more computer programs can be configured to perform particular operations or actions by virtue of including instructions that, when executed by data processing apparatus, cause the apparatus to perform the actions.

[0035] In one general aspect, a non-transitory computer readable medium may include one or more instructions that, when executed by one or more processors of a device, cause the device to: render a graphic for display, the graphic including a depth map as a plurality of values, each value corresponding to a pixel of the rendered graphic; store the rendered graphic in a framebuffer; detect an edge based on the depth map; generate a color value for a pixel corresponding to the detected edge based on at least a neighboring pixel; and update the rendered graphic in the framebuffer with the generated color value. Other embodiments of this aspect includecorresponding computer systems, apparatus, and computer programs recorded on one or more computer storage devices, each configured to perform the actions of the methods.

[0036] Implementations may indude one or more of the following features. A non-transitory computer-readable medium where the one or more instructions further cause the device to: select a pixel group from the depth map, each pixel in the pixel group including a value of the plurality of values; and generate a first difference value and a second difference value based on the values of the pixel group, A non-transitory computer-readable medium where the one or more instructions further cause the device to: generate a comparison between the first difference value and a threshold value; and detect the edge in response to determining that the first difference value exceeds the threshold value. A non-transitory computer-readable medium where the one or more instructions further cause the device to: generate a comparison between the second difference value and a threshold value and; and detect the edge in response to determining that the second difference value exceeds the threshold value. A non-transitory computer-readable medium where the one or more instructions further cause the device to: detect the edge further based on color values of the pixel group. A non-transitory computer- readable medium where the one or more instructions further cause the device to: generate a third difference value and a fourth difference value based on the color values of the pixel group. A non-transitory computer-readable medium where the one or more instructions further cause the device to: generate the color value based on an average of the values of the pixel group. A non-transitory computer-readable medium where the one or more instructions further cause the device to: generate a new pixel group from the depth map in response to generating the color value, where the new pixel group includes at least one pixel of the pixel group. A non-transitory computer-readable medium where the one or more instructions further cause the device to: generate a new pixel group from the depth map if the first difference value is greater than a threshold value. A non-transitory computer-readable medium where the one or more instructions further cause the device to: generate a new pixel group from the depth map if the second difference value is greater than a threshold value. Implementations of the described techniques may include hardware, a method or process, or a computer tangible medium.

[0037] In one general aspect, a system may include a processing circuitry. A system may also include a memory, the memory containing instructions that, when executed by the processing circuitry, configure the system to: render a graphic for display, a graphic including a depth map as a plurality of values, each value corresponding to a pixel of the rendered graphic, A system may in addition store the rendered graphic In a framebuffer. A system may moreover detect an edge based on the depth map. A system may also generate a color value for a pixel corresponding to the detected edge based on at least a neighboring pixel, A system may furthermore update the rendered graphic in the framebuffer with the generated color value. Other embodiments of this aspect include corresponding computer systems, apparatus, and computer programs recorded on one or more computer storage devices, each configured to perform the actions of the methods,

[0038] Implementations may include one or more of the following features. A system where the memory contains further instructions which when executed by the processing circuitry further configure the system to: select a pixel group from the depth map, each pixel in the pixel group including a value of the plurality of values; and generate a first difference value and a second difference value based on the values of the pixel group. A system where the memory contains further instructions which when executed by the processing circuitry further configure the system to: generate a comparison between the first difference value and a threshold value; and detect the edge in response to determining that the first difference value exceeds the threshold value. A system where the memory contains further instructions which when executed by the processing circuitry further configure the system to: generate a comparison between the second difference value and a threshold value and; and detect the edge in response to determining that the second difference value exceeds the threshold value. A system where the memory contains further instructions which when executed by the processing circuitry further configure the system to: detect the edge further based on color values of the pixel group. A system where the memory contains further instructions which when executed by the processing circuitry further configure the system to: generate a third difference value and a fourth difference value based on the color values of the pixel group. A system where the memory contains further instructions which when executed by the processing circuitry further configure the system to: generate the color value based on an average of the values of the pixel group. A system where the memory contains" O " o 0 2 oPCT / GR2024 / 000025 further instructions which when executed by the processing circuitry further configure the system to: generate a new pixel group from the depth map in response to generating the color value, where the new pixel group includes at least one pixel of the pixel group. A system where the memory contains further instructions which when executed by the processing circuitry further configure the system to: generate a new pixel group from the depth map if the first difference value is greater than a threshold value. A system where the memory contains further instructions which when executed by the processing circuitry further configure the system to: generate a new pixel group from the depth map if the second difference value is greater than a threshold value, implementations of the described techniques may include hardware, a method or process., or a computer tangible medium.

[0039] In one general aspect, a method may include rendering a graphic for display, the graphic including a depth map as a plurality of values, each value corresponding to a pixel of the rendered graphic, A method may also include storing the rendered graphic in a framebuffer. A method may furthermore include detecting an edge based on the depth map. A method may in addition include generating a color value for a pixel corresponding to the detected edge based on at least a neighboring pixel. A method may moreover include updating the rendered graphic in the framebuffer with the generated color value. Other embodiments of this aspect include corresponding computer systems, apparatus, and computer programs recorded on one or more computer storage devices, each configured to perform the actions of the methods.BRIEF DESCRIPTION OF THE DRAWINGS

[0040] The subject matter disclosed for disclosure A, 8, and C herein are particularly pointed out and distinctly claimed in the claims at the conclusion of the specification. The foregoing and other objects, features, and advantages of the disclosed embodiments will be apparent from the following detailed description taken in conjunction with the accompanying drawings.

[0041] Figure 1A is an example schematic diagram of a barycentric system, utilized to describe an embodiment.pCT / GR2Q24 / 000025

[0042] Figure 2A is an example flowchart of a method for using a barycentric rasterizer for processing acceleration of computation, implemented according to an embodiment.

[0043] Figure 3A is an example schematic diagram of a system according to an embodiment.

[0044] Figure 1A1 is an example of using a shuffle vector for determination of a first value of an output volume based on an input volume utilized to describe an embodiment.

[0045] Figure IB is an example of using a shuffle vector for determination of a second value of an output volume based on an input volume according to an embodiment.

[0046] Figure 2B is an example of a barycentric rasterization system for determination of an output value of an output volume based on an input volume Implemented according to an embodiment.

[0047] Figure 3B is an example schematic diagram of a processing circuitry of the barycentric system according to an embodiment.

[0048] Figure 4B is an example flowchart of a method implemented by a barycentric rasterizer for using a shuffle vector for determination of a first value of an output tensor based on an input tensor according to an embodiment.

[0049] Figure 1C is a schematic diagram illustrating stages of a graphics rendering pipeline, utilized to describe an embodiment.

[0050] Figure 2C is a schematic diagram of a graphics processing pipeline, utilized to describe another embodiment.

[0051] Figure 3C is a flowchart illustrating a method for depth based anti-aliasing according to an embodiment.

[0052] Figure 4C is a diagram illustrating sample pixel groups of a pixel array, according to an embodiment.

[0053] Figure 5C is a schematic diagram of a system for reducing memory access in rendering antialiasing for depth-based graphics, according to an embodiment.DETAILED DESCRIPTION

[0054] It is important to note that the embodiments disclosed for disclosure A herein are only examples of the many advantageous uses of the innovative teachings herein. In general.PCT / GR2O24 / OOOO25 statements made in the specification of the present application do not necessarily limit any of the various claimed embodiments. Moreover, some statements may apply to some inventive features but not to others. In general, unless otherwise indicated, singular elements may be in plural and vice versa with no loss of generality, in the drawings, like numerals refer to like parts through several views.

[0055] Throughout this disclosure, the term 'kernel' is utilized in different contexts. In some embodiments, reference is made to a computational kernel, which is a routine, computer code, and the like, compiled for accelerator processors, such as graphics processing units (GPUs), field- programmable arrays (FPGAs), and the like.

[0056] In certain embodiments, a kernel is used to refer to a convolutional matrix, mask, and the like. In such embodiments, a kernel is a matrix, tensor, etc., of values, which are used in a convolutional computation, for example.

[0057] Fig. 1 shows an example schematic diagram of a barycentric, system 100, utilized to describe an embodiment. In an embodiment, the barycentric system 100 is configured to receive at least an input vector, such as input vectors110-m, where 'm' is an integer having a value of greater than '1', In some embodiments, an input vector 110 is an input matrix, where a matrix is a vector having a plurality of dimensions.

[0058] in another embodiment, the barycentric system 100 is further configured to access data of a kernel 120, for processing by the processor 130, In certain embodiments, the kernel 120 includes therein bias values, weight values, and the like. In some embodiments, such values are used in conjunction with one or more of the input vectors 110 and as further explained herein. In an embodiment, a filter includes a plurality of kernels, such as kernel 120.

[0059] ln certain embodiments, a processor 130 is configured to generate an output tensor 150. In some embodiments, the processor 130 includes field programmable gate arrays (FPGAs), application -specific integrated circuits (ASICs), Application-specific standard products (ASSPs), system-on-a-chip systems (SOCs), graphics processing units (GPUs), general purpose GPUs (GPGPUs), tensor processing units (TPUs), general-purpose microprocessors, microcontrollers, digital signal processors (DSPs), a combination thereof, and the like.PCT / GR2O24 / OOOO2S

[0060] In an embodiment, the output tensor 150 is implemented as a data structure having 'N' dimensions, where 'N' has a value of '2' or greater. For example, in an embodiment, the output tensor 150 includes 'N' matrices of values, each matrix implemented as an array of values, arranged as an 'x' by 'x’ matrix, where 'x' has a value of '2' or greater. In some embodiments, the output tensor 150 includes a matrix of 'x' by 'y', where V is an integer having a value of '2' or greater. According to an embodiment the output tensor 150 comprises data of a plurality of convolution layers. According to certain embodiments, the processor 130 is configured to activate the barycentric rasterizer 140.

[0061] ln some embodiments, the processor 130 includes a plurality of processor cores. In certain embodiments, the processor 130 is implemented utilizing a single instruction multiple data (SIMD) architecture. In an embodiment, the processor 130 is configured to process multiple threads, multiple threads in parallel, multiple threads serially, etc.

[0062] In an embodiment, it is advantageous to split the output tensor 150 into tiles and process each tile individually. This allows better memory utilization, and beter use of processing 130 lanes (i.e., individual SIMD lanes). For example, parallelizing processing of a tensor by splitting into tiles allows to beter utilize a parallel processor, a multithreaded processor, such as a graphical processor unit (GPU), and the like.

[0063] in an embodiment, a plurality of threads are generated, each thread based on a tile and an operation. In an embodiment, a plurality of methods can be used to generate tiles for the same output tensor 150. In an embodiment, selecting a method, schema, and the like, for tile generation results in different generated tiles, in some embodiments, a first tiling schema is preferable over a second tiling schema.

[0064] For example, preference is determined, according to an embodiment, based on a dimension of the output tensor 150, based on a symmetry of the output tensor 150, based on a number of SIMD lanes of the processor 130, based on a dimension of the output tensor 150, based on a processor architecture (e.g., 8-bit architecture, 32-bit architecture, 64-bit architecture, etc.), based on the number of available number of cores, based on the number of available hardware threads per core, and the like, as well as any permissible combination thereof.

[0065] In an embodiment, the processor 130 is configured to determine when an input vector, for exampie input vector Vi 110-1, is shared by a plurality of, for example, tiles 155 of output tensor 150. it should be noted that the plurality of tiles 155 are merely an example, and that the tile 155 of the output tensor 150, can represent other kinds of data without departing from the scope of the disclosure.

[0066] Accordingly, the processor 130 is configured to cause the barycentric rasterizer 140 to propagate such input vector Vi 110-1, kernel 120, a combination thereof, and the like, to reside in at least a register of the register bank 145 of the processor which are accessible to the processor 130 and the barycentric rasterizer 140.

[0067] In an embodiment, configuring the barycentric rasterizer 140 to populate a common value of an input vector 110, a kernel 120, and the like, into an architectural register of the processor 130 allows the processor 130 to perform less memory access operations. For example, in an embodiment, each thread processed by the processor 130 would otherwise include a memory read instruction to read a value, a plurality of values, etc., which are common to each thread. This tends to occur for example in convolutional neu ral networks, where a plurality of values, such as a kernel of a convolutional neural network, are applied to a plurality of inputs (e.g., an input matrix representing pixel values).

[0068] According to an embodiment, rather than reading the kernel matrix values for each computation, it is advantageous to have the barycentric rasterizer 140 write the values into the register bank 145 which is a single memory access, and configure the processor 130 to read the values from the register bank 145 for each kernel 120. In an embodiment, where the register bank 145 is implemented as a circuitry of the processor 130, this accelerates processing and reduces external memory access, for example, such as accessing a scratchpad memory.

[0069] Fig. 2 is an example flowchart 200 of a method for using a barycentric rasterizer for processing acceleration, implemented according to an embodiment. In an embodiment, use of a barycentric rasterizer provides for acceleration of the generation of an output tensor, for example, output tensor 150 of Fig. 1, by identifying computations where input vector values, kernels, permissible combinations thereof, and the like, are common to a tile of an output tensor.

[0070] At S21O, a common value is detected. In an embodiment, the common value is detected in a plurality of computational kernels, a plurality of input vectors, etc. In some embodiments, a plurality of common values are detected. In certain embodiments, the common values are arranged as a vector, a matrix, a tensor, and the like.

[0071] in an embodiment, a common value is a value utilized by a plurality of computational threads, a plurality of computational cores, a plurality of computational kernels, and the like. For example, according to an embodiment, a plurality of common values correspond to a convolution matrix, also known as a mask, which is utilized in a convolutional neural network.

[0072] In some embodiments, the convolution matrix is utilized in a computation with a plurality of different input, where a computation (i.e., a convolution) is performed between the convolution matrix and each different input. Therefore, the convolution matrix is a common value to each of the plurality of the computations which are performed with respect to the different inputs,

[0073] At S22O, a pre-fetch memory operation is initiated, In an embodiment, a barycentric rasterizer is configured to pre-fetch the detected common values, in an embodiment, the pre-fetch memory operation is initiated prior to processing of a computational kernel utilizing a value targeted by the pre-fetch memory operation.

[0074] In an embodiment, a barycentric rasterizer is configured to determine an address in a memory from which to perform the pre-fetch memory operation. In certain embodiments, the pre -fetch memory operation is a memory read operation. (0075] At S230, the pre-fetched value is written to a register. In an embodiment, a barycentric rasterizer is utilized to write the value to the register. In some embodiments, a barycentric rasterizer is utilized where the barycentric rasterizer is configured to access a memory, such as a scratchpad memory, of a processor.(0076] In some embodiments, the barycentric rasterizer is configured to write the pre-fetched value to an architectural register of the processor. In an embodiment, by pre-fetching common values and writing them to a register (i.e., internal memory) of the processor, there is a reduced memory access, as each computational kernel which would otherwise include a fetch operation is reduced only to the computational instructions which are required for the actual computation (e.g., fetching the input, and performing a computation between the input and the pre-fetched values).4 V *»PCT / GR2024 / 000025Additionally, access by the processor into an interna! memory is faster than access by the processor of other memory types.

[0077] At $240, a computational thread is executed. In an embodiment, a computational thread is executed by processing a computational kerne!. In some embodiments, a computational kernel which is generated utilizing the teachings herein is smaller in size, as the computational kerne! does not require a fetch instruction.

[0078] Therefore, according to an embodiment, a plurality of computational kernels, which each utilize a common value, do not require a fetch (i.e,, read from memory) of the common value each time a computational kernel is processed. This reduces the size of the computational kernels overall, and therefore accelerates processing through a GPU pipeline.

[0079] Furthermore, by configuring the barycentric rasterizer to perform a fetch from a first memory and write to a second memory, this reduces the number of times the first memory is accessed for the same common value. This reduction in memory usage is translated, in an embodiment, to a reduction of power consumption by the processing circuitry. (0080] In some embodiments, reducing memory access allows to use narrower memory bandwidth, which reduces the physical size of the processing circuitry, allowing for a smaller processing circuit.

[0081] Fig. 3 is an example schematic diagram of a system 300 according to an embodiment. In an embodiment of system 100, the processor 130 may be implemented as system 300. The system 300 includes a processing circuitry 310 coupled to a memory 320, a storage 330, and a network interface 340. In an embodiment, the components of the system 300 may be communicatively connected via a bus 350.

[0082] The processing circuitry 310 may be realized as one or more hardware logic components and circuits. For example, and without limitation, illustrative types of hardware logic components that can be used include FPGAs, ASICs, ASSPs, SOCs, GPUs, TPUs, general-purpose microprocessors, microcontrollers, DSPs, and the like, or any other hardware logic components that can perform calculations or other manipulations of information, as well as any permissible combinations thereof.

[0083] The memory 320 may be volatile (e.g., random access memory, etc,), non-volatile (e.g., readonly memory, flash memory, etc.}, or any combination thereof. In an embodiment, the memory 320 is an on-chip memory, an off-chip memory, a combination thereof, and the like. In certain embodiments, the memory 320 is a scratchpad memory for the processing circuitry 310. In yet other embodiments the memory 320 may further provide cache memory functionality.

[0084] In one configuration, software for implementing one or more embodiments disclosed herein may be stored in the storage 330, in the memory 320, in a combination thereof, and the like. Software shall be construed broadly to mean any type of instructions, whether referred to as software, firmware, middleware, microcode, hardware description language, or otherwise. Instructions may include code (e.g., in source code format, binary code format, executable code format, or any other suitable format of code). The instructions, when executed by the processing circuitry 310, cause the processing circuitry 310 to perform the various processes described herein. Memory 320 may further include therein a code memory 325 where instructions are stored . Such instructions may be executed by the processing circuitry 310. More specifically, in an embodiment, such instructions may be used to control the operations described in Fig. 2 and / or the operation of the barycentric rasterizer 140.

[0085] The storage 330 is a magnetic storage, an optical storage, a solid-state storage, a combination thereof, and the like, and is realized, according to an embodiment, as a flash memory, as a harddisk drive, or other memory technology, or any other medium which can be used to store the desired information. In an embodiment, the storage 330 may contain therein one or more kernels 120 used as described herein. When such a kernel 120 is to be used by the barycentric rasterizer, for example, the kernel 120 is provided from the storage 330. lo an embodiment the one or more input vectors 110 are stored in the storage 330 and loaded to the barycentric rasterizer therefrom. One of ordinary skill in the art would readily appreciate that in an embodiment the kernel 120 and the input vectors 110 may be loaded first into memory 320 prior to loading into the barycentric rasterizer.

[0086] The bus 350 communicatively connecting between the components of system 300 may include serial and / or parallel busses, and permissible combinations thereof. The bus 350 may be a proprietary bus or a standard bus such as, but not limited to, peripheral componentinterconnect (PCS), Advanced Microcontroller Bus Architecture (AMBA), small computer system interface (SCSI), universal serial bus (USB), IEEE 1394 (aka FireWire), and the like, as well as any permissible combinations thereof.(0087] Typically, a barycentric rasterizer may be implemented by, but not by way of limitation, certain graphics hardware such as a GPU, configured to perform the barycentric rasterization process.This may include one or more of: vertex processing, edge functions, scan conversion, attribute interpolation, and fragment shading; Fundamentally, barycentric rasterization involves rendering triangles efficiently in computer graphics.

[0088] The various embodiments disclosed herein can be implemented as hardware, firmware, software, or any combination thereof. Moreover, the software is preferably implemented as an application program tangibly embodied on a program storage unit or computer- read able medium consisting of parts, or of certain devices and / or a combination of devices. The application program may be uploaded to, and executed by, a machine comprising any suitable architecture. Preferably, the machine is implemented on a computer platform having hardware such as one or more processing units ("PUs"), a memory, and input / output interfaces. The computer platform may also include an operating system and microinstruction code. The various processes and functions described herein may be either part of the microinstruction code or part of the application program, or any combination thereof, which may be executed by a PU, whether or not such a computer or processor is explicitly shown. In addition, various other peripheral units may be connected to the computer platform such as an additional data storage unit and a printing unit. Furthermore, a non-transitory computer-readable medium is any computer-readable medium except for a transitory propagating signal.

[0089] All examples and conditional language recited herein are intended for pedagogical purposes to aid the reader in understanding the principles of the disclosed embodiment and the concepts contributed by the inventor to furthering the art, and are to be construed as being without limitation to such specifically recited examples and conditions. Moreover, all statements herein reciting principles, aspects, and embodiments of the disclosed embodiments, as well as specific examples thereof, are intended to encompass both structural and functional equivalents thereof. Additionally, it is intended that such equivalents include both currently known equivalents as wellas equivalents developed in the future, i.e., any elements developed that perform the same function, regardless of structure.

[0090] It should be Understood that any reference to an element herein using a designation such as "first," "second," and so forth does not generally limit the quantity or order of those elements. Rather, these designations are generally used herein as a convenient method of distinguishing between two or more elements or instances of an element. Thus, a reference to first and second elements does not mean that only two elements may be employed there or that the first element must precede the second element in some manner. Also, unless stated otherwise, a set of elements comprises one or more elements.

[0091] As used herein, the phrase "at least one of" followed by a listing of items means that any of the listed items can be utilized individually, or any combination of two or more of the listed items can be utilized. For example, if a system is described as including "at least one of A, 8, and C," the system can include A alone; B alone; C alone; 2A; 28; 2C; 3A; A and B in combination; B and C in combination; A and C in combination; A, B, and C in combination; 2A and C in combination; A, 3B, and 2C in combination; and the like.

[0092] It is important to note that the embodiments disclosed for disclosure B herein are only examples of the many advantageous uses of the innovative teachings herein. In general, statements made In the specification of the present application do not necessarily limit any of the various claimed embodiments. Moreover, some statements may apply to some inventive features but not to others. In general, unless otherwise indicated, singular elements may be in plural and vice versa with no loss of generality. In the drawings, like numerals refer to like parts through several views.

[0093] Fig. 1A is a schematic diagram of utilizing a shuffle vector for determination of a first value 120-1,1 of an output volume 120 (also referred to as an output tensor 120} based on an input volume 110 (also referred to as an input tensor 110) according to an embodiment. In an embodiment, an input volume 110 Includes input data 112 that is surrounded with padding values.

[0094] According to an embodiment, the padding is all '0fvalues, however, this is merely for example purposes and other values are utilized in other embodiments, including utilizing the same valuefor al! the padding or, different padding values as the case requires. Therefore, such cases are specifically included in the scope of the disclosure.

[0095] in an embodiment, a shuffle vector used on the input volume 110 (e.g., assuming a 32-bit implementation) is: {0x09090909, 0x09010009, 0x09010009}. In certain embodiments, the input volume 110 is 7-by-7-by-3 (see Fig. 3 for the depth), of which an input volume 110-1 (as discussed in Fig. 3) 7-by-7 matrix is shown. In an embodiment, the output value 120-1,1 is a floating point value, a fixed point value, an integer value, and the like. In some embodiments, the output volume 120 is a feature map,

[0096] In some embodiments, the shuffle vector is applied on a portion 110-1,1 of the input volume 110. In an embodiment, applying the shuffle vector on a portion results in an output value, such as output value 120-1,1, i.e., '-3'.

[0097] Accords ng to an embodiment, and as further explained herein, the padding values 114, are preloaded into registers of a processing circuitry accessible by a barycentric rasterizer thereof, thereby reducing memory access overhead when computation is performed, in an embodiment, the output volume 120, 0[:,:,0], is one of two output volumes, the second being output volume 130,

[0098] That is, in an embodiment, the 7-by-7-by-3 input volume, e.g., input volumes 110-1, 110-2, and 110-3 (see Fig, 3), have been convoluted, utilizing the shuffle vector, into a 3-by-3-by-2 output volume, represented as 120 and 130. In other words, an input tensor having a depth of three (7- by-7-by 3), has been transformed into an output tensor having a depth of two (3-by-3-by-2). As noted, in an embodiment, each element of the output tensor, i.e., the combination of output volume 120 and output volume 130, is a value of a layer of a convolutional neural network.

[0099] Similarly, in an embodiment, the output value of 120-1,3 of Fig. IB is computed by the processing circuitry from portion 110-1,3 shown in Fig. IB, using the shuffle vector: {0x09090909, 0x09090100, 0x09090100}. That is, the shuffle vector is applied on portion 110-1,3 of the input volume 110 thereby resulting in the output value 120-1,3, i.e., '-3'.

[0100] In certain embodiments, a barycentric rasterizer is configured to generate values for preloading into the register. For example, in some embodiments, a preloaded value is generatedbased on a value, a plurality of values, etc., that are read by the barycentric rasterizer, which is configured to then generate a value for preloading based on the read value.

[0101] According to an embodiment, and as further explained herein, the padding values 116, are preloaded into registers (also referred to as architectural registers) of a processing circuitry accessible by a barycentric rasterizer, thereby reducing memory access overhead when a calculation is performed.

[0102] In an embodiment, the output volume 120, 0[:,:,0], is one of two output volu mes, the second being output volume 130,. That is, the 7-by-7-by-3 input volume, e.g., input volumes 110-1, 110-2, and 110-3 (see Fig. 3), have been transformed, using the shuffle vector into a 3-by-3-by- 2 output volume, represented as 120 and 130,

[0103] Fig. 2 shows an example schematic diagram of a barycentric system 200 for processing convolutional neural networks, utilized to describe an embodiment. In an embodiment, the barycentric system 200 is configured to receive at least an input volume, such as input volume 110-1, where an input volume may also be referred to as an input tensor. In some embodiments, the input tensor 110 is a vector having a plurality of dimensions, for example, UO-lm 110-2, and 110-3. In certain embodiments, a processor 230 is configured to generate an output tensor, for example, output tensor 120 or output tensor 130, In some embodiments, the processor 230 includes field programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), system-on-a-chip systems (SOCs), graphics processing units (GPUs), general purpose GPUs (GPGPUs), tensor processing units (TPUs), general-purpose microprocessors, microcontrollers, digital signal processors (DSPs), a combination thereof, and the like. According to certain embodiments, the processor 230 is configured to activate the barycentric rasterizer 240.

[0104] In an embodiment, the input tensor 110 is implemented as a data structure having 'N' dimensions, where 'N' has a value of '2' or greater. For example, in an embodiment, the input tensor 110 includes 'N' matrices of values, e.g., 110-1, 110-2, and 110-3 (in N=3) each matrix implemented as an array of values, arranged as an 'x' by 'x' matrix, where 'x' has a value of '2' or greater.

[0105] in an embodiment, the output tensor 120 and output tensor 130 are each a matrix implemented as an array of values, arranged as an 'x' by 'x' matrix, where 'x' has a value of '2' or greater. According to an embodiment each of output tensor 120 and output tensor 130 comprises data of a plurality of pixels. In some embodiments, the output tensor 120, the output tensor 130, etc., include a plurality of matrices of 'x' by 'y', where 'x' and y are each integers having a value of '2' or greater.

[0106] In some embodiments, the processor 230 includes a plurality of processor cores. In certain embodiments, the processor 230 is implemented utilizing a single instruction multiple data (SIMD) architecture. In an embodiment, the processor 230 is configured to process multiple threads, multiple threads in parallel, multiple threads serially, etc. In some embodiments, the processor 230 is implemented for processing vector instructions. In an embodiment, the processor 230 is implemented utilizing a hybrid architecture, e.g,, using SIMD and vector processing, alternatively.

[0107] In certain embodiments, the barycentric system 200 further includes a barycentric rasterizer 240 operating under the control of the processor 230. In an embodiment, the barycentric rasterizer 240 is configured to access a register bank 245 of the processor 230. In some embodiments, the barycentric rasterizer 240 is configured to load the register bank 245, a plurality of register banks, etc., with padding data so that when the operation on the input volume 110 is performed, it is not necessary to read the padding data each for each computation, thereby saving on loading data from memory to perform the computation described with respect of Figs.1A and IB, In an embodiment, a plurality of register banks are accessed by the barycentric rasterizer 240 and load values therein.

[0108] As is understood from Figs. 1A and 18 it is necessary to repeat the convolution process (i.e., computation) nine times to achieve a 3-by-3 output tensor, for example, output tensor 120, as each of its nine elements, for example, element 120-1,1 is computed by the processor 230. Saving on memory access is therefore paramount for performance considerations as well as compute power savings.

[0109] In an embodiment, a barycentric rasterizer 240 is implemented by, but not by way of limitation, certain graphics hardware circuitry such as a GPU, configured to perform thebarycentric rasterization process. In an embodiment, such a processing circuitry includes any one of: a vertex processing circuitry, edge functions, scan conversion, attribute interpolation, fragment shading, a combination thereof, and the like.

[0110] In an embodiment, the barycentric rasterizer 240 is configured to write to the register bank 245, a plurality of register banks, etc., a value, a plurality of values, and the like, utilized as a padding value. In an embodiment, a convolutional neural network utilizes padding values to perform a computation which includes an edge of a matrix. In some embodiments, it is advantageous for the barycentric rasterizer 240 to perform a pre-fetch memory operation and write the padding value to the register bank 245. in such embodiments, a computation kernel which utilizes the padding value is generated which includes reading the padding value from the register bank 245, rather than perform a memory access operation as part of the computation kernel.

[0111] Fig. 3 is an example schematic diagram of a system 300 according to an embodiment. In an embodiment of system 200, the processor 230 is implemented as a processing circuitry 310 of system 300. The system 300 includes a processing circuitry 310 coupled to a memory 320, a storage 330, and a network interface 340, In an embodiment, the components of the system 300 may be communicatively connected via a bus 350.

[0112] The processing circuitry 310 may be realized as one or more hardware logic components and circuits. For example, and without limitation, illustrative types of hardware logic components that can be used include FPGAs, ASICs, ASSPs, SOCs, GPUs, TPUs, general-purpose microprocessors, microcontrollers, DSPs, and the like, or any other hardware logic components that can perform calculations or other manipulations of information, as well as any permissible combinations thereof.

[0113] The memory 320 is volatile (e.g., random access memory, etc.), non-volatile (e.g., read only memory, flash memory, etc.), or any permissible combination thereof. In an embodiment, the memory 320 is an on-chip memory, an off-chip memory, a combination thereof, and the like. In certain embodiments, the memory 320 is a scratch-pad memory for the processing circuitry 310. In yet other embodiments the memory 320 may further provide cache memory functionality.

[0114] In one configuration, software for implementing one or more embodiments disclosed herein may be stored in the storage 330, in the memory 320, in a combination thereof, and the like. Software shall be construed broadly to mean any type of instructions, whether referred to as software, firmware, middleware, microcode, hardware description language, or otherwise. Instructions may include code (e.g„ in source code format, binary code format, executable code format, or any other suitable format of code). The instructions, when executed by the processing circuitry 310, cause the processing circuitry 310 to perform the various processes described herein. Memory 320 may further include therein a code memory 325 where instructions are stored. Such instructions may be executed by the processing circuitry 310. More specifically, in an embodiment, such instructions may be used to control the operations described in Figs. 1A, IB, or 4, as well as the operation of the barycentric rasterizer 240.[0115JThe storage 330 is a magnetic storage, an optical storage, a solid-state storage, a combination thereof, and the like, and is realized, according to an embodiment, as a flash memory, as a harddisk drive, or other memory technology, or any other medium which can be used to store the desired information. In an embodiment the one or more input tensors 110 are stored in the storage 330 and loaded to the barycentric rasterizer therefrom. In an embodiment any of the output tensors, for example output tensor 120 and output tensor 130 are stored in storage 330 subsequent to being generated by the barycentric rasterizer 240,

[0116] The bus 350 communicatively connects between the components of system 300 and may include serial and / or parallel busses, and permissible combinations thereof. In an embodiment, the bus 350 is a proprietary bus or a standard bus such as, but not limited to, peripheral component interconnect (PCI), Advanced Microcontroller Bus Architecture (AMBA), small computer system interface (SCSI), universal serial bus (USB), IEEE 1394 (aka FireWire), and the like, as well as any permissible combinations thereof. (0117] In an embodiment the barycentric rasterizer 240 is implemented as part of the system 300. In such an embodiment the barycentric rasterizer 240 is implemented in hardware, software, firmware, and any permissible combination thereof.

[0118] In an embodiment a barycentric system, such as barycentric system 200 of Fig. 2, may implement finite state machine (FSM) logic or mathematical equations to compute the shufflevectors, In another embodiment the shuffle vectors may be loaded from lookup tables (LUTs) that may be stored in memory 320 or storage 330.

[0119] Fig. 4 is an example flowchart 400 of a method for using a shuffle vector for determination of a first value of an output tensor based on an input tensor, implemented utilizing a barycentric rasterizer according to an embodiment.

[0120] At S410, a plurality of output dimensions of an output is determined. For example, referring to the example shown in Figs. 1A and IB, the determination is of a 3-by-3-by-2 which means that two output tensors 120 and 130 are to be used each being a 3-by-3 matrix.

[0121] At S420, a shuffle mask is generated. In an embodiment, the shuffle mask includes a plurality of memory addresses which are accessible. In some embodiments, a barycentric rasterizer, for example, barycentric rasterizer 240, is configured to generate a shuffle vector (which may also be referred to as a shuffle mask} for each output value. In an embodiment, the number of output values is determined at S410. In an embodiment a single shuffle vector is generated for each output tensor, for example a first shuffle vector for output tensor 120 and a second shuffle vector for output tensor 130.

[0122] In some embodiments, a single shuffle vector is generated for all output tensors. For example, a first shuffle vector for output tensor 120, and the first shuffle vector for output tensor 130. In certain embodiments, a combination of shuffle vectors are utilized, such that a portion of output tensors utilize a first shuffle vector, and another portion of output tensors utilize a second shuffle vector. In an embodiment, the configuration of the barycentric rasterizer involves the use of lookup tables (LUTs).

[0123] At S430, a portion of an input tensor is accessed. In an embodiment, a processing circuitry, for example, processing circuitry 310, is configured to read at least a portion of an input tensor. In an embodiment, reading a portion of an input tensor includes configuring processing circuitry 310 to read, for example, portion 110-1,1 of the input tensor 110 from a memory.

[0124] At S440, a value is stored in a register. In an embodiment, a barycentric rasterizer is configured to detect memory addresses of values of an input vector. In some embodiments, the barycentric rasterizer is configured to detect that a value of an input vector is a padding value, for example,based on the shuffle mask, and store, for each detected padding value, the padding value in a register of a processing circuitry,

[0125] In some embodiments, a vectorized load memory operation is initiated. In an embodiment, the vectorized load memory operation is initiated by applying the shuffle vector on the at least a portion of the input tensor. In an embodiment the method repeats until all elements of the one or more output tensors have been processed and loaded.

[0126] The method allows configuring a processing circuitry to reduce memory accesses when determining values of an output based on an inpu t and a shuffle vector, and includes: determining a plurality of output dimensions of the output generated by a processing circuitry, the output including a plurality of output values arranged according to the plurality of output dimensions; configuring a barycentric rasterizer to generate a shuffle vector for each output value; initiating a vectorized load memory operation based on the shuffle vector and an input into an architectural register; and, configuring the processing circuitry to initiate an operation including reading a portion of the input from the architectural register.

[0127] In an embodiment the input may be an input tensor have a plurality of dimensions. Furthermore, the output may be an output tensor. In an embodiment, the plurality of output dimensions of the output are equal to or lesser than a plurality of dimensions of the input.

[0128] The various embodiments disclosed herein can be implemented as hardware, firmware, software, or any combination thereof. Moreover, the software is preferably implemented as an application program tangibly embodied on a program storage unit or computer-readable medium consisting of parts, or of certain devices and / or a combination of devices. The application program may be uploaded to, and executed by, a machine comprising any suitable architecture. Preferably, the machine is implemented on a computer platform having hardware such as one or more processing units ("PUs"), a memory, and input / output interfaces. The computer platform may also include an operating system and microinstruction code. The various processes and functions described herein may be either part of the microinstruction code or part of the application program, or any combination thereof, which may be executed by a PU, whether or not such a computer or processor is explicitly shown. In addition, various other peripheral units may be connected to the computer platform such as an additional data storage unit and a printingf’CT / GR2O24 / 00oO25 unit. Furthermore, a non-transitory computer-readable medium is any computer-readable medium except for a transitory propagating signal,(0129] All examples and conditional language recited herein are intended for pedagogical purposes to aid the reader in understanding the principles of the disclosed embodiment and the concepts contributed by the inventor to furthering the art, and are to be construed as being without limitation to such specifically recited examples and conditions. Moreover, all statements herein reciting principles, aspects, and embodiments of the disclosed embodiments, as well as specific examples thereof, are intended to encompass both structural and functional equivalents thereof. Additionally, it is intended that such equivalents include both currently known equivalents as well as equivalents developed in the future, i.e., any elements developed that perform the same function, regardless of structure.

[0130] It should be understood that any reference to an element herein using a designation such as "first," "second / ' and so forth does not generally limit the quantity or order of those elements. Rather, these designations are generally used herein as a convenient method of distinguishing between two or more elements or instances of an element. Thus, a reference to first and second elements does not mean that only two elements may be employed there or that the first element must precede the second element in some manner. Also, unless stated otherwise, a set of elements comprises one or more elements.

[0131] As used herein, the phrase "at least one of" followed by a listing of items means that any of the listed items can be utilized individually, or any combination of two or more of the listed items can be utilized. For example, if a system is described as including "at least one of A, B, and C," the system can include A alone; 8 alone; C alone; 2A; 2B; 2C; 3A; A and B in combination; B and C in combination; A and C in combination; A, B, and C in combination; 2A and C in combination; A, 38, and 2C in combination; and the like. (0132] It is important to note that the embodiments disclosed for disclosure C herein are only examples of the many advantageous uses of the innovative teachings herein. In general, statements made in the specification of the present application do not necessarily limit any of the various claimed embodiments. Moreover, some statements may apply to some inventive features but not to others. In general, unless otherwise indicated, singular elements may be inF / G R2024 / 000025 plural and vice versa with no loss of generality. In the drawings, like numerals refer to like parts through several views,

[0133] The various disclosed embodiments include a method and system for reducing memory access in rendering anti-aliasing for depth-based graphics.

[0134] Fig. 1C is a schematic diagram 100 illustrating stages of a graphics rendering pipeline, utilized to describe an embodiment. In an embodiment, the graphic rendering pipeline comports with the OpenGL graphics pipeline. However, it should be understood graphics rendering pipelines may be implemented in alternative manners and some stages may be omited or performed in an order that differs from that illustrated in Fig. 1, according to some embodiments. (0135] In an embodiment, the first stage of the graphics rendering pipeline includes a geometry stage 130 and a second stage includes a rasterization stage 140.(0136] In an embodiment, data 120 for generating an image includes a plurality of objects 110. In Certain embodiments, an object includes a geometric model. For example, according to an embodiment, a geometric model Includes a plurality of vectors, each vector defined by at least a first point and a second point.

[0137] In some embodiments, the plurality of objects 110 of an image data 120 are projected onto a two-dimensional (2D) plane at the geometry stage 130. In an embodiment, the objects 110 are transformed by translating, rotating, scaling, a combination thereof, and the like, position vertices of a model of an object of the plurality of objects 110. (0138] In certain embodiments, the geometry stage 130 further includes generating a plurality of primitives based, for example, on a projection of a 3D model onto a 2D plane. In an embodiment, a primitive is, for example, a triangle.

[0139] In an embodiment, at the rasterization stage 140, objects 110 of the image data 120 that were processed into primitives such as triangles at the geometry stage 130 are assigned to fragments. In an embodiment, a rasterizer Is configured to generate an axis aligned bounding box that encompasses a triangle. In an embodiment, the rasterizer is further configured to perform scanline conversion, to determine which pixel(s) of a display are assigned to an individual triangle encompassed by the axis aligned bounding box.0 9 - Z 0 2PCT / GR2024 / 00002S[0140J In some embodiments, the rasterizer is configured to interpolate color, texture coordinates, depth information, a combination thereof, and the like, for each triangle. In certain embodiments, the rasterizer is configured to assign a color value to a fragment based on the interpolated color, texture coordinates, depth information, combination thereof, and the like. [0141 J According to an embodiment, the color value of a fragment is writen to a memory, such as a framebuffer, which is then read by a display 150 (for example via a display controller) and rendered on a screen for viewing.

[0142] Fig. 2C is a schematic diagram of a graphics processing pipeline 200, utilized to describe another embodiment, in an embodiment, the graphics rendering pipeline 200 comports with the OpenGL graphics pipeline. According to some embodiments, graphics rendering pipelines are implemented in alternative manners, and some stages are omitted, performed in an order that differs, and the like, from that illustrated in Fig. 2.

[0143] In an embodiment, the stages of the graphics rendering pipeline include projection 210, tessellation 220, depth shading 230, rasterization 240, and fragment shading 250. The projection 210, tessellation 220, and depth shading 230 stages are substages of the geometry phase 130 of the broader graphics rendering pipeline.

[0144] In certain embodiments, at the projection stage 210, a shader is configured to transform a 30 geometric model into a 2D image representative of that 3D model portrayed from the perspective of a camera utilizing orthographic projection. In an embodiment, each point of the 3D model is projected onto a 2D plane from the viewpoint of a camera. In some embodiments, coordinate points of the 3D model are converted in 2D coordinate points of a projection plane.

[0145] In an embodiment, at the tessellation 220 stage a shader is configured to modify an image, such as images 120 of Fig. 1 to create a smoother effect for the objects 110 and edges of the image 120. In an embodiment, a shader is configured to generate a smoothening effect by subdividing objects (e.g., objects 110 of the image 120) into primitives, or smaller geometric shapes, such as smaller triangles.

[0146] According to some embodiments, these smaller triangles result in a greater amount of vertices in the image. In an embodiment, vertex values for the vertices are computed for thecolor, texture, and position coordinates. In an embodiment, the smoothening effect is generated based on the computed values, to reduce jagged edges of an image.

[0147] tn an embodiment, at the depth testing 230, a rasterizer is configured perform a depth test on an image, for example to generate shading. In some embodiments, the rasterizer Is configured to perform depth testing in order to render spatial relationships of objects within a scene.

[0148] For example, when an object is projected onto a display the depth of the generated pixel on the projected display is compared to a depth value stored in a depth buffer (e.g., a z-buffer), according to an embodiment. In an embodiment, a depth buffer is configured to store depth values of an object as the object is rendered onto a display. Specifically, a depth buffer is configured to store z-coordinates of pixels in an image which are representative of the pixel's distance from the camera also referred to as a viewport.

[0149] Accord! ng to an embodiment, a depth value is stored as a floating point value, a fixed point value, an integer, and the like. In some embodiments, the depth value is represented with a plurality of bits. For example, in an embodiment, 8 bits, 16 bits, 32 bits, and the like, are utilized to represent a depth value.

[0150] In an embodiment, at the rasterization stage 240, a rasterizer is configured to assign geometric primitives of an image to a plurality of pixels. In some embodiments, the a rasterizer is configured to assign textures, colors, a combination thereof, and the like, to a triangle primitive of an image.

[0151] According to an embodiment, a rasterizer is configured to project triangle primitives onto a display using projection, in an embodiment, this process converts a 3D representation of the triangles of the image into a 2D representation of the triangles. The 2D representation of triangles is fitted over a pixel grid of the image to determine which pixels are covered by the resulting triangles, in an embodiment.

[0152] For each pixel covered by a primitive, a rasterizer is configured to generate a fragment and is further configured to fill a pixel with the triangle's color, in an embodiment. In an embodiment, this process is referred to as fragment shading 250. In some embodiments, fragment shading 250 occurs after the rasterization stage 240. In an embodiment, a rasterizer is configured to determine a color of a fragment based on illumination, a texture of the triangle primitive, a combinationthereof, and the like. It is important to note that in an embodiment, colors of an image are altered based on lighting information.

[0153] Fig. 3C is a flowchart 300 illustrating a method for depth based anti-aliasing according to an embodiment. According to an embodiment, anti-aliasing is performed by detecting edges based on a depth map of an image, and determining a color for pixels of an edge based on the detected edges and a color value (or in some embodiments a plurality of color values) of adjacent pixels.

[0154] At S310, a pixel group is selected. In an embodiment, the pixel group includes a plurality of pixels and corresponding pixel values, including color values and depth values. In some embodiments, pixel values includes depth values selected from a depth map of an image. In an embodiment pixel values are stored as floating point values, fixed point values, integer values, a combination thereof, and the like, in certain embodiments, a plurality of bits are utilized to represent a pixel value, such as 8 bits for representing a value of a red channel, 8 bits for representing a value of a green channel, 8 bits for representing a value of a blue channel, 8 bits for representing a value of an alpha channel, 8 bits for representing a depth value, a combination thereof, and the like.

[0155] In an embodiment, the pixel group includes a number of pixels arranged as an array. In certain embodiments, the pixel group includes pixels which form a spatial array in a display. In an embodiment, the spatial array is arranged as a matrix array such as a two row by two column [2x2] matrix, a three row by three column [3x3] matrix, and the like. (0156] In some embodiments, the depth map is stored as a visual representation of the distance of a pixel from a perspective in the scene of an image. For example, according to an embodiment, a distant pixel (pixel that is farthest from the viewpoint) has a minimum value (e.g., ‘0’), while a close pixel (closest to the viewpoint) has a maximum value (e.g., '100'). In an embodiment, the pixel group is selected based on a scanline. For example, in an embodiment, a scanline begins at the top left pixel and progresses pixel by pixel from there towards the right.

[0157] In certain embodiments, a first pixel group includes a first number of pixels arranged in a first array, and a second pixel group includes a second number of pixels arranged in a second array. For example, in an embodiment, pixel groups of the first type are utilized to perform edge detection at a physical edge of the image (e.g., a pixel which borders with less than four otherpixels is a physical edge pixel), and pixel groups of the second type are utilized to perform edge detection in every other section of the image.

[0158] According to some embodiments, a number of pixels in a pixel group is determined based on a distance of depth values of the pixels in a first group of pixels. In certain embodiments, the number of pixels in a pixel group is determined based on a test of color values. For example, in an embodiment, where a depth value exceeds a predetermined threshold value, a first pixel group size is selected, and where the depth value is below the predetermined threshold value a second pixel group size is selected.

[0159] In some embodiments, a pixel group size includes a number of pixels in the group, and an arrangement of the pixels (e.g., 6 pixels arranged as 2 by 3, 6 pixels arranged as 3 by 2, 6 pixels arranged as 4 by 2, etc.). The example presented in one embodiment herein refers to a group of4 pixels having a 2 by 2 pixel arrangement, however other geometries are utilized in various embodiments Without departing from the scope of this disclosure.

[0160] At S320, a first difference value is generated. In an embodiment, the first difference value is generated from the depth values of the pixel group which correspond to the depth map.According to an embodiment, the first difference value is generated by determining a difference of a first set of diagonal pixel values of the selected pixel group. For example, assuming the following selected pixel group is a 2x2 matrix in an embodiment, the first difference valueis the difference of the pixel value d and pixel value a. In some embodiments, the first difference value is an absolute value (e.g., the value of 'd' subtracted from the value of 'a' is equal to the value of 'a' subtracted from the value of 'd')

[0161] In an embodiment, the first difference value is generated based on a first value of a first pixel and a second value of a second pixel (which is not the first pixel). In certain embodiments, the first difference value, is generated based on a plurality of pixel values. For example, in an embodiment, the pixel group includes 9 pixels arranged in a 3 by 3 matrix. In an embodiment, the first difference value is generated by subtracting a first pixel value from a second value to determine a first result, subtracting a third pixel value from the second pixel value to determine a second result, and generating the first difference value as an average of the first result and the second result.

[0162] At S330, a second difference value is generated. In an embodiment, the second difference value is generated from the depth values of the pixel group which correspond to the depth map. The second difference value is generated by determining a difference of a second set of diagonal pixel values of the selected pixel group. For example, assuming the following selected pixel group is a 2x2 matrix ^.1 in an embodiment, the second difference value is the difference of thedl pixel value c and pixel value b. In some embodiments, the second difference value is an absolute value {e.g., the value of 'c' subtracted from the value of 'b' is equal to the value ofzb' subtracted from the value of 'c') ,

[0163] At S340, a comparison Is generated, in an embodiment, the comparison is generated between the first difference value and a threshold value. According to an embodiment, the first difference value is determined to exceed the threshold value based on a result of the generated comparison. In some embodiments, the first difference value is determined to be less than the threshold value based on a result of the generated comparison.

[0164] According to an embodiment, a threshold value (of a color value, of a depth value, etc.) is generated as a dynamic value, as an adaptive value, as a predetermined value, a combination thereof, and the like. In some embodiments, the threshold value is generated based on a minimum value of the depth map and a maximum value of the depth map, a local minimum value, a local maximum value, a global minimum value, a global maximum value, a combination thereof, and the like. For example, in an embodiment, the threshold is an average value based on a global maximum value and a global minimum value of the depth values.

[0165] At S350, a comparison is generated. In an embodiment, the comparison is generated between the second difference value and a threshold value. In certain embodiments, the second difference value is determined to exceed the threshold value based on a result of the generated comparison. In some embodiments, the second difference value is determined to be less than the threshold value based on a result of the generated comparison.

[0166] At 5360, an edge is detected. According to some embodiments, an edge is detected based on a comparison. In some embodiments, the first difference value is determined to exceed the threshold value based on a result of the generated comparison, and this will determine that an edge is detected. In certain embodiments, the second difference value is determined to exceedthe threshold value based on a result of the generated comparison, and this will determine that an edge is detected.

[0167] in an embodiment, an edge is detected based on performing the method above with a first group of pixels, and performing the method again with a second group of pixels which includes therein the first group of pixels. For example, in an embodiment., an edge is detected when edge detecting of a group of 2 by 2 pixels yields a first result, which triggers edge detection of a 3 by 3 group of pixels which includes therein the group of 2 by 2 pixels.

[0168] In some embodiments, detection of an edge is based on performing the above steps on a depth map and on a corresponding channel value (e.g., red channel, green channel, etc.) of a group of pixels. For example, in an embodiment, steps S310 through S350 are performed for a group of pixels in a depth map, and the corresponding group of pixels on a red channel of an image. In some embodiments, a first difference threshold is utilized for a depth map and a second difference threshold is utilized for a color value. In an embodiment, both the first threshold and the second threshold are exceeded when detecting an edge. In some embodiments, exceeding the first threshold, the second threshold, or both thresholds, indicates an edge.

[0169] At S370, a color value is generated. In some embodiments, a color value is generated based off the detection of an edge. The color value assigned will be the mathematical average of all the color values of the pixel group, according to some embodiments, For example, assuming the an embodiment, the color value assignedis the average of the color values of pixel value a, pixel value b, pixel value c, and pixel value d.In some embodiments, an average is an arithmetic average, a geometric average, a harmonic average, a median, a mid-range average, a combination thereof, and the like. In an embodiment, a subgroup of pixels is selected for generating an average value. For example, in certain embodiments, where the group includes 6 pixels arranged as 2 by 3, the four comer pixels are selected and the color value is generated based on the values of the four corner pixels.

[0170] Fig. 4C is a diagram 400 illustrating sample pixel groups of a pixel array, according to an embodiment.

[0171] According to an embodiment, a pixel group is selected from a matrix of a plurality of pixels and pixels values. In certain embodiments, the selected pixel group will be a matrix of a groupingof pixels and pixel values of any size. For example, in some embodiments, the size of pixel group 1, in Fig. 4. is a 2x2 matrix that contains four pixel values. For example, in another embodiment, the size of pixel group 2 in Fig. 4, is a 3x3 matrix and contains nine pixel values.

[0172] According to an embodiment, a processing circuitry, a rasterizer, and the like, is configured to determine whether an edge is detected based on the first difference value of a selected pixel group. In an embodiment, the first difference value is the difference between a first diagonal group of pixel values in the pixel group. For example, in some embodiments, in pixel group 1, in Fig. 4, the first difference value is the difference between al and b2. According to an embodiment, the second difference value is the difference between a second diagonal group of pixels. For example, in an embodiment, in pixel group 1, in Fig. 4, the second difference value would be the difference between a2 and bl.

[0173] ln an embodiment, the first difference value and the second difference vaiue are compared to a threshold value. In some embodiments, the first difference value is determined to exceed the threshold value based on a result of a generated comparison, and this will determine that an edge is detected. In certain embodiments, the second difference value is determined to exceed the threshold value based on a result of the generated comparison, and this will determine that an edge is detected.

[0174] According to an embodiment, if an edge is detected, an average of the color values of each pixel in the pixel group is assigned to the pixel associated with the edge. For example, according to an embodiment, in pixel group 1 in Fig. 4, if an edge is detected for pixel al, the average color values of pixel value al, pixel value, a2, pixel value bl, pixel value b2 would be assigned to the edge. More specifically, in certain embodiments, the average color value for pixel value al would be mathematically calculated

[0175] In an embodiment, after a determination for edge detection is made for a pixel group, other groupings of pixel groups may be selected in an iterative manner to continuously smooth the edge coloring of an image. For example, according to an embodiment in Fig. 4, after an edge is detected for pixel al, another pixel group will be selected, such as pixel group 2 from Fig. 4, In an embodiment, pixel group 2 from Fig.4 is selected to determine whether pixel value bl constitutes an edge and if it is determined that pixel vaiue bl constitutes an edge an updated color value willbe assigned to pixel value bl. In some embodiments, pixels from different pixel groups may overlap. For example, according to an embodiment in Fig. 4, pixel value bl and pixel value b2 were included in both pixel group 1 and pixel group 2.

[0176] Fig. 5C. is an example schematic diagram of a system 500 for reducing memory access in rendering anti-aliasing for depth based graphics according to an embodiment. The system 500 for reducing memory access in rendering anti-aliasing for depth based graphics includes, according to an embodiment, a processing circuitry 510 coupled to a memory 520, a storage 530, and a network interface 540. In an embodiment, the components of the system 500 are communicatively connected via a bus 550.

[0177] In certain embodiments, the processing circuitry 510 is realized as one or more hardware logic components and circuits. For example, according to an embodiment, illustrative types of hardware logic components include field programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), Application-specific standard products (ASSPs), system-on-a-chip systems (SOCs), graphics processing units (GPUs), tensor processing units (TPUs), Artificial Intelligence (Al) accelerators, general-purpose microprocessors, microcontrollers, digital signal processors (DSPs), and the like, or any other hardware logic components that are configured to perform calculations or other manipulations of information.

[0178] in an embodiment, the memory 520 is a volatile memory (e.g., random access memory, etc.), a non-volatile memory (e.g., read only memory, flash memory, etc.), a combination thereof, and the like. In some embodiments, the memory 520 is an on-chip memory, an off-chip memory, a combination thereof, and the like. In certain embodiments, the memory 520 is a scratch-pad memory for the processing circuitry 510.

[0179] In one configuration, software for implementing one or more embodiments disclosed herein is stored in the storage 530, in the memory 520, in a combination thereof, and the like. Software shall be construed broadly to mean any type of instructions, whether referred to as software, firmware, middleware, microcode, hardware description language, or otherwise. Instructions include, according to an embodiment, code (e.g., in source code format, binary code format, executable code format, or any other suitable format of code). The instructions, when executedby the processing circuitry 510, cause the processing circuitry 510 to perform the various processes described herein, in accordance with an embodiment,

[0180] In some embodiments, the storage 530 is a magnetic storage, an optical storage, a solid-state storage, a combination thereof, and the like, and is realized, according to an embodiment, as a flash memory, as a hard-disk drive, another memory technology, various combinations thereof, or any other medium which can be used to store the desired information.[0i81]The network interface 540 is configured to provide the system for reducing memory access in rendering anti-aliasing for depth based graphics with communication with, for example, a network, according to an embodiment.

[0182] It should be understood that the embodiments described herein are not limited to the specific architecture illustrated in Fig. 5, and other architectures may be equally used without departing from the scope of the disclosed embodiments.

[0183] The various embodiments disclosed herein can be implemented as hardware, firmware, software, or any combination thereof. Moreover, the software is preferably implemented as an application program tangibly embodied on a program storage unit or computer readable medium consisting of parts, or of certain devices and / or a combination of devices. The application program may be uploaded to, and executed by, a machine comprising any suitable architecture. Preferably, the machine is implemented on a computer platform having hardware such as one or more processing units ("PUs"), a memory, and input / outpui interfaces. The computer platform may also include an operating system and microinstruction code. The various processes and functions described herein may be either part of the microinstruction code or part of the application program, or any combination thereof, which may be executed by a PU, whether or not such a computer or processor is explicitly shown. In addition, various other peripheral units may be connected to the computer platform such as an additional data storage unit and a printing unit. Furthermore, a non-transitory computer readable medium is any computer readable medium except for a transitory propagating signal.

[0184] All examples and conditional language recited herein are intended for pedagogical purposes to aid the reader in understanding the principles of the disclosed embodiment and the concepts contributed by the inventor to furthering the art, and are to be construed as being withoutlimitation to such specifically recited examples and conditions. Moreover, all statements herein reciting principles, aspects, and embodiments of the disclosed embodiments, as well as specific exampies thereof, are intended to encompass both structural and functional equivalents thereof. Additionally, it is intended that such equivalents include both currently known equivalents as well as equivalents developed in the future, i.e„ any elements developed that perform the same function, regardless of structure,

[0185] It should be understood that any reference to an element herein using a designation such as "first," ''second,'' and so forth does not generally limit the quantity or order of those elements. Rather, these designations are generally used herein as a convenient method of distinguishing between two or more elements or instances of an element. Thus, a reference to first and second elements does not mean that only two elements may be employed there or that the first element must precede the second element in some manner. Also, unless stated otherwise, a set of elements comprises one or more elements.

[0186] As used herein, the phrase "at least one of" followed by a listing of items means that any of the listed items can be utilized individually, or any combination of two or more of the listed items can be utilized. For example, if a system is described as including "at least one of A, B, and C," the system can include A alone; B alone; C alone; 2A; 2B; 2C; 3A; A and B in combination; B and C in combination; A and C in combination; A, B, and C in combination; 2Aand Gin combination; A, 3B, and 2C in combination; and the like.

Claims

1. 9 4PCT / GR2024 / 000025CLAIMSWhat is claimed is:

1. A system for acceleration of artificial intelligence (Al) computation, comprising: a barycentric rasterizer; a processing circuitry including a plurality of architectural registers; a first memory accessible by the barycentric rasterizer and the processing circuitry; a second memory,, the second memory containing instructions that, when executed by the processing circuitry, configure the system to: trigger a pre-fetch memory operation performed by the barycentric rasterizer, wherein the pre-fetch memory operation includes reading from the first memory a value common to a plurality of computational threads; configure the barycentric rasterizer to write the value to an architectural register of the plurality of architectural registers; spawn each of the plurality of computational threads, each computational thread programmed to utilize at least the value; and process the spawned plurality of computational threads.

2. A non-transitory computer-readable medium storing a set of instructions for acceleration of artificial intelligence (Al) computation, the set of instructions comprising: one or more instructions that, when executed by one or more processors of a device, cause the device to: trigger a pre-fetch memory operation performed by a barycentric rasterizer of the one or more processors, wherein the pre-fetch memory operation includes reading from a first memory of the device a value common to a plurality of computational threads; configure the barycentric rasterizer to write the value to an architectural register of a plurality of architectural registers of the one or more processors;spawn each of the plurality of computational threads, each computational thread programmed to utilize at least the value; and process the spawned plurality of computational threads.

3. A non-transitory computer'readable medium storing a set of instructions for reduction in memory access when determining values of an output based on an input and a shuffle vector, the set of instructions comprising: one or more instructions that, when executed by one or more processors of a device, cause the device to: determine a plurality of output dimensions of the output generated by a processing circuitry, the output including a plurality of output values arranged according to the plurality of output dimensions; configure a barycentric rasterizer to generate a shuffle vector for each output value; initiate a vectorized load memory operation based on the shuffle vector and an input into a register of the processing circuitry; and configure the processing circuitry to initiate an operation including reading a portion of the input from the register.

4. A system for reduction in memory access when determining values of an output based on an input and a shuffle vector comprising: a processing circuitry; a memory, the memory containing instructions that, when executed by the processing circuitry, configure the system to: determine a plurality of output dimensions of the output generated by a processing circuitry, the output including a plurality of output values arranged according to the plurality of output dimensions; configure a barycentric rasterizer to generate a shuffle vector for each output value; initiate a vectorized load memory operation based on the shuffle vector and an input into a register of the processing circuitry; andconfigure the processing circuitry to initiate an operation including reading a portion of the input from the register.

5. A non -transitory computer-readable medium storing a set of instructions for reducing memory access in rendering depth-based anti-aliasing for graphics, the set of instructions comprising: one or more instructions that, when executed by one or more processors of a device, cause the device to: render a graphic for display, the graphic including a depth map as a plurality of values, each value corresponding to a pixel of the rendered graphic; store the rendered gra phic in a framebuffer; detect an edge based on the depth map; generate a color value for a pixel corresponding to the detected edge based on at least a neighboring pixel; and update the rendered graphic in the framebuffer with the generated color value.

6. A system for reducing memory access in rendering depth-based anti-aliasing for graphics comprising: a processing circuitry; a memory, the memory containing instructions that, when executed by the processing circuitry, configure the system to: render a graphic for display, the graphic including a depth map as a plurality of values, each value corresponding to a pixel of the rendered graphic; store the rendered graphic in a framebuffer; detect an edge based on the depth map; generate a color value for a pixel corresponding to the detected edge based on at least a neighboring pixel; and update the rendered graphic in the framebuffer with the generated color value.7, A method for reducing memory access in rendering depth-based anti-aliasing for graphics, comprising: rendering a graphic for display, the graphic including a depth map as a plurality of values, each value corresponding to a pixel of the rendered graphic; storing the rendered graphic in a framebuffer; detecting an edge based on the depth map; generating a color value for a pixel corresponding to the detected edge based on at least a neighboring pixel; and updating the rendered graphic in the framebuffer with the generated color value.4

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