Circuit board and semiconductor package comprising same

Abstract

Disclosed in an embodiment of the present invention is a method for manufacturing a circuit board, the method comprising the steps of: preparing an organic layer; exposing the organic layer to a plasma gas including N2; forming a metal layer on at least one of the upper surface and the lower surface of the exposed organic layer; forming, on the metal layer, a core layer formed of glass; separating the core layer and the metal layer from the organic layer; and forming a build-up layer and an electrode portion on the core layer.

Description

Circuit boards and semiconductor packages including the same

[0001] Embodiments according to the present invention relate to circuit boards and semiconductor packages.

[0002] As the performance of electrical and electronic products continues to improve, technologies are being proposed and researched to attach a greater number of packages to a limited-size substrate. However, because typical packages are based on mounting a single semiconductor chip, achieving the desired performance is limited.

[0003] A typical circuit board or package substrate consists of a processor package, which houses the processor chip, and a memory package, which houses the memory chips, all connected together. These package substrates integrate the processor and memory chips into a single package, reducing the chip footprint and enabling high-speed signal transmission through short paths. Due to these advantages, these package substrates are widely used in mobile devices and other devices.

[0004] Meanwhile, the recent advancements in electronic devices, such as mobile devices, and the adoption of High Bandwidth Memory (HBM) have led to larger package sizes. Furthermore, as the number of functions required for application processors increases, there is a growing demand for separate processor chips for each function, along with circuit boards capable of mounting these processor chips. Even when the application processor is split into two processor chips, the number of terminals (input / output) provided on each processor chip is increasing.

[0005] In addition, due to recent trends such as 5G, the Internet of Things (IoT), increased image quality, and increased communication speed, the number of terminals on processor chips is gradually increasing due to the increase in power and signal quantities. Accordingly, the area, thickness, and circuit pattern density of circuit boards are also increasing. When the area and thickness of circuit boards increase, it becomes difficult to miniaturize products, and there are problems such as reliability issues such as warpage of the circuit board, and product price increases. Therefore, increasing the density of circuit patterns is more advantageous in terms of product price, reliability issues such as warpage, and product miniaturization than increasing the area and thickness of the circuit board. Therefore, miniaturization of circuit patterns and through-holes is required.

[0006] In particular, as circuit boards become increasingly thinner, deformations such as warping and twisting that occur during circuit board manufacturing are increasing. To prevent this, a glass core structure, in which a glass plate is formed in the core portion of the circuit board, has been proposed.

[0007] In addition, there is a difficulty in reducing reliability due to a decrease in bonding strength between the bump and the protective layer as the bump is formed on the protective layer covering a fine line width or small circuit pattern.

[0008] An embodiment of the present invention implements a circuit board and a semiconductor package including the same with improved ease of manufacture by forming the bonding force between the glass layer and the metal layer to be greater than the bonding force between the organic layer for separation and the metal layer when the glass layer is manufactured as a separation core.

[0009] In addition, the embodiment can implement a circuit board and a semiconductor package including the same, in which warpage is suppressed and electrical characteristics are improved through a glass layer having high package rigidity and a small coefficient of thermal expansion.

[0010] In addition, the embodiment can implement a circuit board and a semiconductor package including the same with improved performance by reducing signal loss by maintaining the roughness of a metal layer through an organic layer of an amide bond.

[0011] The embodiment provides a circuit board having improved bonding strength between a protective layer and a bump portion by having a metal oxide structure at the interface between the bump portion and the protective layer, and a semiconductor package including the same.

[0012] In addition, the embodiment can provide a circuit board and a semiconductor package including the same in which signal loss is prevented by bonding between a protective layer and a bump portion without improving illumination by plasma.

[0013] The problem to be solved in the embodiment is not limited to this, and it can be said that the purpose or effect that can be understood from the solution or implementation form of the problem described below is also included.

[0014] A method for manufacturing a circuit board according to an embodiment of the present invention comprises the steps of: providing an organic layer; exposing the organic layer to a plasma gas including N2; forming a metal layer on at least one of an upper surface and a lower surface of the exposed organic layer; forming a core layer made of glass on the metal layer; separating the core layer and the metal layer from the organic layer; and forming a build-up layer and an electrode portion on the core layer.

[0015] In the step of exposing the organic layer to plasma gas including N2, the vacuum level may be set to 0.1 to 0.5 Torr and the temperature may be set to 20 to 30°C.

[0016] In the step of exposing the organic layer to plasma gas including N2, the total flow rate of the plasma gas may be controlled to 1500 sccm or less, and the exposure time may be less than 500 seconds.

[0017] In the step of exposing the organic layer to the plasma gas including the N2, the plasma gas may further include at least one of Ar, O2, and CF4 in addition to the N2.

[0018] The above exposed organic layer may have an amide bond structure.

[0019] The above exposed organic layer may have a structure of HNC=O.

[0020] The step of separating the core layer and the metal layer from the organic layer may include a step in which a sub-organic layer, which is a part of the organic layer, remains on the metal layer.

[0021] The peel strength between the organic layer and the metal layer may be less than 0.1 kgf / cm2.

[0022] A circuit board according to an embodiment of the present invention includes a core layer; a first wiring portion disposed on an upper surface and a lower surface of the core layer; and an organic layer disposed on one of the upper surface and the lower surface of the core layer among the first wiring portions, wherein the organic layer has an amide bond structure.

[0023] The above organic layer may have a structure of HNC=O.

[0024] A circuit board according to an embodiment includes a build-up structure; a protective layer disposed on the build-up structure; and a bump portion disposed on the protective layer, and when analyzed by XPS at an interface between the protective layer and the bump portion, the circuit board has a first peak having the highest intensity in a range of 400 (eV) to 600 (eV) among a range of binding energies of 200 (eV) to 1200 (eV).

[0025] It may have a second peak with the greatest intensity at binding energy 400 (eV) to 500 (eV).

[0026] The first peak may be greater than the second peak.

[0027] It may have a third peak with the greatest intensity at the binding energy of 200 (eV) to 400 (eV).

[0028] The second peak may be larger than the third peak.

[0029] The second peak may be smaller than the third peak.

[0030] The above bump portion includes a first sub-layer in contact with the protective layer and a second sub-layer disposed on the first sub-layer; and the first sub-layer may include a transition metal.

[0031] When XPS analysis is performed on the surface of the bump portion exposed after removal of the protective layer by etching at the interface between the protective layer and the bump portion, the fourth peak having the greatest intensity may be present at a binding energy of 400 (eV) to 600 (eV) among 200 (eV) to 1200 (eV).

[0032] When the above XPS analysis is performed on the surface of the bump portion exposed after removal of the protective layer by etching, the fifth peak has the highest intensity at a binding energy of 400 (eV) to 500 (eV), and the fourth peak may be greater than the fifth peak.

[0033] When XPS analysis is performed on the surface of the bump portion exposed after removal of the protective layer by etching, the sixth peak has the highest intensity at 200 (eV) to 400 (eV), and the fifth peak may be greater than the sixth peak.

[0034] When XPS analysis is performed on the surface of the protective layer exposed after removal of the bump portion by etching at the interface between the protective layer and the bump portion, the seventh peak having the greatest intensity may be present at a binding energy of 200 (eV) to 400 (eV) among 200 (eV) to 1200 (eV).

[0035] When the above XPS analysis is performed on the surface of the protective layer exposed after removal of the bump portion by etching, the eighth peak has the highest intensity at a binding energy of 400 (eV) to 600 (eV), and the seventh peak may be greater than the eighth peak.

[0036] When XPS analysis is performed on the surface of the protective layer exposed after removal of the bump portion by etching, the ninth peak has the highest intensity at 400 (eV) to 500 (eV), and the eighth peak may be greater than the ninth peak.

[0037] The above protective layer may include a resin and a plurality of fillers spaced apart from each other.

[0038] An embodiment of the present invention provides a circuit board and a semiconductor package including the same with improved ease of manufacture by forming the bonding force between a glass layer and a metal layer to be greater than the bonding force between an organic layer and a metal layer for separation when the glass layer is manufactured as a separation core.

[0039] In addition, the embodiment can provide a circuit board and a semiconductor package including the same, in which warpage is suppressed and electrical characteristics are improved through a glass layer having high rigidity and a small coefficient of thermal expansion.

[0040] In addition, the embodiment can provide a circuit board and a semiconductor package including the same with improved performance by maintaining the roughness of a metal layer through an organic layer of an amide bond and reducing signal loss.

[0041] In addition, the embodiment implements a circuit board and a semiconductor package including the same, which improves bonding strength between a protective layer and a bump portion by having a metal oxide structure at the interface between the bump portion and the protective layer.

[0042] In addition, the embodiment can implement a circuit board and a semiconductor package including the same in which signal loss is prevented by bonding between a protective layer and a bump portion without improving illumination by plasma.

[0043] The various advantageous and beneficial effects of the present invention are not limited to the above-described contents, and will be more easily understood in the course of explaining specific embodiments of the present invention.

[0044] Figure 1 is a cross-sectional view of a circuit board according to an embodiment of the present invention;

[0045] Figure 2 is an enlarged view of part K1 in Figure 1,

[0046] Figure 3 is an enlarged view of part K2 in Figure 1,

[0047] FIGS. 4A to 4F are drawings explaining a method for manufacturing a circuit board according to an embodiment.

[0048] Figure 5 is an image of the surface of an organic layer according to a comparative example and an embodiment.

[0049] Figure 6 is a graph of the contact angle on the surface of the organic layer for each comparative example and example.

[0050] Figures 7(a) to 7(c) are drawings showing the 1D, 2D, and 3D surface roughness of the organic layer according to a comparative example.

[0051] Figures 8(a) to 8(c) are drawings showing the 1D, 2D, and 3D surface roughness of the organic layer according to Example 1.

[0052] Figures 9(a) to 9(c) are drawings showing the 1D, 2D, and 3D surface roughness of the organic layer according to Example 2.

[0053] Figure 10 is a SEM (Scanning Electron Microscopy) photograph of the insulating layer and electrode portion.

[0054] Figure 11 is a drawing showing the peel strength according to comparative examples, examples 1 and 2,

[0055] Figure 12 is an XPS (X-ray Photoelectron Spectroscopy) result for a metal layer and an organic layer in a circuit board according to an embodiment.

[0056] Fig. 13 is a cross-sectional view of a circuit board according to another embodiment;

[0057] Figure 14 is an enlarged view of part K3 in Figure 13,

[0058] FIG. 15 is a graph of an XPS (X-ray Photoelectron Spectroscopy) spectrum for another surface between a protective layer and a bump portion in a circuit board according to an embodiment;

[0059] Fig. 16 is a graph of the XPS spectrum for the interface between the protective layer and the bump portion in the circuit board according to the embodiment.

[0060] Fig. 17 is a graph of the XPS narrow spectrum and depth profile for Ti2P3 of the bump portion after removal of the protective layer in the circuit board according to the embodiment.

[0061] Figure 18 is a graph of the XPS narrow spectrum and depth profile for Ti2P3 of the protective layer after removal of the bump portion in the circuit board according to the embodiment.

[0062] Fig. 19 is a drawing explaining the improvement of the peel strength of a circuit board according to an embodiment.

[0063] Fig. 20 is an EDS (Energy Dispersive X-ray Spectroscopy) mapping image for each element on the upper surface of the protective layer and the lower surface of the bump portion in a circuit board according to an embodiment.

[0064] Fig. 21 is a drawing explaining a method for manufacturing a protective layer and a bump portion in a circuit board according to an embodiment.

[0065] Fig. 22 is a cross-sectional view showing a semiconductor package according to the first embodiment.

[0066] Fig. 23 is a cross-sectional view showing a semiconductor package according to the second embodiment.

[0067] Fig. 24 is a cross-sectional view showing a semiconductor package according to the third embodiment.

[0068] Fig. 25 is a cross-sectional view showing a semiconductor package according to the fourth embodiment.

[0069] The present invention can be modified in various ways and has various embodiments, and specific embodiments are illustrated and described in the drawings. However, this is not to be construed as a specific embodiment of the present invention.

[0070] It should be understood that the present invention is not intended to be limited to the embodiments, but includes all modifications, equivalents, and alternatives that fall within the spirit and technical scope of the present invention. In other words, expressions such as “for example” or “by way of example” used herein are intended to describe specific embodiments and should not be construed as limiting the scope of the present invention.

[0071] The technical idea of ​​the present invention is not limited to some of the embodiments described, and can be implemented in various different forms. Within the scope of the technical idea of ​​the present invention, one or more of the components between the embodiments can be selectively combined or substituted for use, and it should be understood that new embodiments in which various embodiments are combined are also included in the present disclosure. Each component described as an integral part may be implemented by being separated into multiple elements, and similarly, components described as multiple elements may also be implemented in an integral form.

[0072] Please note that the drawings are schematic and not drawn to scale. The relative dimensions and proportions of parts in the drawings may be exaggerated or reduced for clarity and convenience, and any dimensions are for illustrative purposes only and are not limiting. Wherever possible, identical structures, elements, or components appearing in more than one drawing are given the same reference numerals to indicate similar features.

[0073] In addition, terms (including technical and scientific terms) used in the embodiments of the present invention should be interpreted as having a meaning that can be generally understood by a person of ordinary skill in the technical field to which the present invention belongs, unless explicitly and specifically defined and described, and commonly used terms, such as terms defined in a dictionary, should be interpreted in consideration of the meaning in the context described in the present invention. If a term defined in a commonly used dictionary does not match the meaning it has in the context according to the description of the present invention, it should be interpreted as having the meaning it has in the context according to the description of the present invention, and even if it is not explicitly defined in this application, it should not be interpreted in an overly formal meaning based on the description of the present invention.

[0074] Additionally, the terminology used in the embodiments of the present invention is for the purpose of describing the embodiments and is not intended to limit the present invention. In some embodiments, well-known process steps, well-known device structures, or well-known techniques are not specifically described to avoid ambiguity in the interpretation of the present invention. Furthermore, in this specification, the singular form may also include the plural form, unless specifically stated otherwise.

[0075] Terms that include ordinal numbers, such as "first" and "second," may be used to describe various components, but the components are not limited in meaning by their ordinal numbers. Terms that include ordinal numbers are used solely to distinguish one component from another, and are not limited in nature, order, or sequence of the components. For example, a second component may be referred to as a "first component," and similarly, a first component may be referred to as a "second component," without departing from the scope of the present invention. Furthermore, even without ordinal numbers such as "first" and "second," components may be referred to without ordinal numbers, as long as the meaning of the component does not depart from the scope of the present invention.

[0076] The expression “and / or” is to be interpreted to mean that one or more or all of the listed components may be included, for example, “A and / or B” should be understood to include all instances where A alone, B alone, or both A and B are included.

[0077] In this application, terms such as “include,” “provided,” “having,” “comprises,” etc., are intended to specify the presence of a feature, number, step, operation, component, part, or combination thereof described in the specification, and should not be construed as excluding in advance the possibility of the presence or addition of one or more other features, numbers, steps, operations, components, parts, or combinations thereof.

[0078] When referring to directions, vertical direction and horizontal direction are used for convenience of explanation. In addition, the horizontal direction may include a first horizontal direction perpendicular to the vertical direction, a second horizontal direction perpendicular to the first horizontal direction and the vertical direction. In addition, when the vertical direction and the horizontal direction follow the Cartesian coordinate system, they may correspond to the first horizontal direction (X-axis), the second horizontal direction (Y-axis), and the vertical direction (Z-axis), respectively, and when following the cylindrical coordinate system, the first horizontal direction may mean the azimuth (Φ) direction (or circumferential direction), and the second horizontal direction may mean the radius (ρ) direction (or centrifugal direction) away from a specific configuration, and when following the spherical coordinate system, the first horizontal direction may mean the azimuth (Φ) direction (or circumferential direction), and the second horizontal direction may mean the radius (r) direction (or centrifugal direction) away from a specific configuration, and in particular, the vertical direction may mean the polar angle (θ) direction formed by the second horizontal direction and the Z-axis. For convenience of explanation, the first horizontal direction, the second horizontal direction, and the vertical direction may be used as some or a combination of the above-described Cartesian coordinate system, cylindrical coordinate system, and spherical coordinate system. However, unless otherwise specified, the vertical direction means the Z-axis according to the Cartesian coordinate system, and the horizontal direction means all directions that can be defined on the XY plane of the Cartesian coordinate system. For example, when referring to the first horizontal direction and the second horizontal direction perpendicular to the first horizontal direction, the first horizontal direction means the X-axis, and the second horizontal direction means the Y-axis.

[0079] Additionally, when it is described as being formed or arranged "above or below" each component, "above" or "below" includes not only cases where the two components are in direct contact with each other, but also cases where one or more other components are formed or arranged between the two components. Furthermore, when it is expressed as "above" or "below", it can include the meaning of not only the upward direction but also the downward direction based on one component.

[0080] Furthermore, the meaning that configuration A is disposed between configurations B and C may mean that configuration A is located in a horizontal space between configurations B and C, and / or a vertical space between configurations B and C. Furthermore, the meaning that configuration A is disposed between configurations B and C may include the meaning that configuration A is disposed such that at least a portion of configuration A overlaps configurations B and C in the vertical and / or horizontal directions. Unless otherwise specified, configuration C may also be included in the meaning that configuration C is disposed between configurations A and B even if configuration C is located between an imaginary line extending vertically and / or horizontally based on configuration A and an imaginary line extending vertically and / or horizontally based on configuration B.

[0081] In addition, the meaning that the A component is exposed from the B component is not limited to the meaning that the A component is exposed from the entire product, but should be understood to mean that the A component is exposed from the B component, and unless there are special circumstances, it should not necessarily be understood that the entire A component is covered by the B component. In other words, when it is described that the A component is exposed from the B component, it should be understood to include the case where another C component other than the A component and the B component covers the A component exposed from the B component.

[0082] Additionally, when a component is described as being "connected," "coupled," "connected," or "in contact with" another component, it may include not only cases where the component is directly connected, coupled, or connected to that other component, but also cases where the component is "connected," "coupled," "connected," or "in contact with" another component between the component and that other component. Thus, if component A is to be understood only as being directly "connected," "coupled," "connected," or "in contact with" component B, it is described as being "directly connected," "directly coupled," "directly connected," or "directly in contact."

[0083] In addition, when it is described that configuration A is 'fixed' to configuration B, it should be understood that configuration A is fixed not only by being directly combined with configuration B, but also indirectly fixed to configuration B through configuration C and / or configuration D, etc., unless otherwise specified, taking into account the function and purpose to be solved, and when configuration A is to be understood only as being 'directly fixed' to configuration B, it is described as being 'directly fixed'.

[0084] In addition, when it is described as “flat” or “located on the same plane,” it should be understood to be at a level that takes into account process deviations by a person with ordinary knowledge in the relevant technical field, not according to the dictionary meaning.

[0085] Additionally, throughout the specification, “planar” or “when viewed in plan” may mean when the target portion is viewed from above or below, and “cross-sectional” or “when viewed in cross-section” may mean when the target portion is viewed from the side in a cross-section cut vertically.

[0086] Before describing the embodiments, an electronic device to which the circuit board and semiconductor package of the embodiments are applied will be briefly described. The electronic device includes a main board (not shown). The main board may be physically and / or electrically connected to various components. For example, the main board may be connected to the semiconductor package of the embodiments. Various connecting members (e.g., semiconductor elements) may be mounted on the semiconductor package.

[0087] A connecting member can connect different dies (e.g., a central processor (CPU), a graphics processor (GPU), a digital signal processor, an application processor (AP), etc.). The connecting member can also be located within an interposer or a package substrate.

[0088] The memory chip may be a stacked memory such as HBM. Additionally, the memory chip may include a memory chip such as a volatile memory (e.g., DRAM), a non-volatile memory (e.g., ROM), or a flash memory.

[0089] Meanwhile, the product group to which the semiconductor package of the embodiment is applied may be any one of CSP (Chip Scale Package), FC-CSP (Flip Chip-Chip Scale Package), FC-BGA (Flip Chip Ball Grid Array), POP (Package On Package), and SIP (System In Package), but is not limited thereto.

[0090] Additionally, the electronic device may be a smart phone, a personal digital assistant, a digital video camera, a digital still camera, a vehicle, a high-performance server, a network system, a computer, a monitor, a tablet, a laptop, a netbook, a television, a video game, a smart watch, an automotive device, etc. However, the present invention is not limited thereto, and it is to be understood that the electronic device may be any other electronic device that processes data.

[0091] In the circuit board according to the embodiment of the present invention, the insulating layer may be formed of a plurality of insulating layers. The insulating layer may include a first insulating layer (a glass layer described below) and an insulating layer.

[0092] In particular, as the integration density of semiconductor devices increases and multi-pin and miniaturization are promoted, a circuit board according to an embodiment, on which a semiconductor device having an increased number of pins and miniaturization is mounted, may be a multilayer printed circuit board using a built-up method. For example, the circuit board may be a multilayer circuit board having a build-up layer formed on the surface and back surface of a first organic layer.

[0093] In such a multilayer circuit board, the first insulating layer is, as described above, a resin substrate (such as a glass epoxy substrate) in which reinforcing fibers are impregnated with resin. In addition, by utilizing the rigidity of the core substrate, a plurality of build-up layers can be formed by alternately laminating resin insulating layers and conductor layers on the front and back surfaces of the core substrate. Accordingly, at least a portion of the insulating layer (110) can correspond to a 'build-up layer'. For example, a build-up layer disposed on top of the first insulating layer, which is the core layer, can be an 'upper build-up layer', and a build-up layer disposed below the first insulating layer can be a 'lower build-up layer'.

[0094] The build-up layer serves as an internal insulating layer of the circuit board where circuit patterns, etc. are formed, and an insulating material is used as the forming material. As the insulating material, as described below, a thermosetting resin and / or a photocurable resin may be used, and an Ajinomoto build-up film may also be used, but is not particularly limited thereto.

[0095] Additionally, when forming dummy grooves and / or via holes in the build-up layer, laser processing and / or photolithography may be used depending on the insulating material.

[0096] Alternatively, a material with a high modulus can be used as the insulating material, and in addition, a material with a small curing shrinkage itself can be used, or an anisotropic material with a dominant vertical shrinkage can be used.

[0097] These build-up layers may be multiple layers and may be formed using the same materials or may be formed using different materials.

[0098] FIG. 1 is a cross-sectional view of a circuit board according to an embodiment of the present invention, FIG. 2 is an enlarged view of part K 1 in FIG. 1, and FIG. 3 is an enlarged view of part K2 in FIG. 1.

[0099] Referring to FIG. 1, a circuit board (100) according to an embodiment may include an insulating layer (110), an electrode portion (120), and a protective layer (130). The circuit board (100) may further include an organic layer (FIGS. 2, 3 OL). In addition, the circuit board (100) according to an embodiment may include a semiconductor element (not shown) and a conductive member (not shown) positioned on one side (e.g., an upper portion). There may be a plurality of chips such as semiconductor elements (not shown). Furthermore, the circuit board (100) may include a cavity formed therein, and a bridge, a chip, etc. may be mounted in this cavity.

[0100] The first insulating layer (111) may be a 'core layer' or a 'substrate layer'. The first insulating layer (111) can suppress warpage that occurs due to thinning of the circuit board. In other words, warpage can be reduced by placing a glass layer (or glass core) with high rigidity and a low coefficient of thermal expansion (CTE) at the center or core of the circuit board. For example, the first insulating layer (111) may have high rigidity and a low coefficient of thermal expansion compared to other insulating layers or protective layers.

[0101] And the first insulating layer (111) can be made of a glass material. For example, the first insulating layer (111) can include pure silicon dioxide (about 100% SiO2), soda-lime glass, borosilicate glass, alumino-silicate glass, etc., and is not limited to silicon-based glass compositions, and alternative glass materials, such as fluorine glass, phosphate glass, chalcogen glass, etc., can also be used. In addition, the first insulating layer (111) can further include other additives to form glass having specific physical properties. These additives can include not only calcium carbonate (e.g., lime) and sodium carbonate (e.g., soda), but also magnesium, calcium, manganese, aluminum, lead, boron, iron, chromium, potassium, sulfur, and antimony, and carbonates and / or oxides of these elements and other elements. In addition, the first insulating layer (111) can include an insulating material.

[0102] In addition, the first insulating layer (111) may be arranged at the center of the insulating layer (110). In addition, the first insulating layer (111) may include a first through hole (FIG. 3, IS) as described below. The first through hole (FIG. 3, IS) may have various shapes and be formed at various locations, different from the number and structure illustrated in the drawing.

[0103] And the insulating layer (110) may include an insulating layer other than the first insulating layer (111). For example, the insulating layer (110) may include a second insulating layer (112) and a third insulating layer (113). The second insulating layer (112) and the third insulating layer (113) may be made of an insulating material.

[0104] And the second insulating layer (112) and the third insulating layer (113) may be positioned above and below the first insulating layer (111), respectively. For example, the second insulating layer (112) may be positioned above the first insulating layer (111). And the third insulating layer (113) may be positioned below the first insulating layer (111). For example, the second insulating layer (112) may be in contact with the upper surface of the first insulating layer (111). And the third insulating layer (113) may be in contact with the lower surface or bottom surface of the first insulating layer (111).

[0105] And in the embodiment, the second insulating layer (112) and / or the third insulating layer (113) may be formed of multiple insulating layers. The multiple insulating layers may be formed of the same insulating material or different insulating materials. For example, the second insulating layer (112) may be formed of multiple layers according to the structure or design of the circuit board (100) as described above. For example, the second insulating layer (112) may be formed of multiple insulating layers. And the third insulating layer (113) may be formed of multiple insulating layers.

[0106] Additionally, a plurality of circuit patterns, via holes, etc. may be positioned in the second insulating layer (112) and / or the third insulating layer (113). For example, the via hole of the second insulating layer (112) and / or the third insulating layer (113) may be connected to the first through hole of the first insulating layer (111). In other words, the via electrode positioned in the via hole of the second insulating layer (112) may be electrically connected to the via electrode positioned in the first through hole of the first insulating layer (111).

[0107] The second insulating layer (112) and / or the third insulating layer (113) may include a thermosetting resin such as an epoxy resin or a thermoplastic resin such as a polyimide. In addition, the second insulating layer (112) and / or the third insulating layer (113) may further include a reinforcing material in the resin. The reinforcing material may be, for example, a fabric reinforcing material, an inorganic filler, etc. The fabric reinforcing material may be glass fiber, and the glass fiber may be impregnated into the resin to form a prepreg (PPG).

[0108] For example, the second insulating layer (112) and / or the third insulating layer (113) may be formed of any insulating resin, such as a thermosetting and / or photocurable resin. As the thermosetting resin, ABF (Ajinomoto Build-up Film), a product released by Ajinomoto Co., Ltd., may be used, and a material such as prepreg (PPG) containing glass fiber may be used. As the photocurable resin, any insulating resin, such as PID (Photo Imageable Dielectric) resin, may be used. The above-described arbitrary insulating resin may be, for example, an epoxy resin, a bismaleimide triazine resin (BT resin), a phenol resin, etc., and may include an inorganic filler such as silica. When the insulating resin is used as a core, it may include a reinforcing material formed of glass fiber or aramid fiber. For example, the second insulating layer (112) may use ABF (Ajinomoto Build-up Film), a product released by Ajinomoto Co., Ltd., as an example, and FR-4, BT (Bismaleimide Triazine), PID (Photo Imageable Dielectric resin), BT, etc. may be used. For example, the second insulating layer (112) and / or the third insulating layer (113) may include a plurality of layers composed of ABF.

[0109] In an embodiment, the electrode portion (120) may be arranged for electrical connection between a main board, etc., and a chip (or semiconductor element (not shown), die). In addition, the electrode portion (120) may include a wiring portion (circuit pattern (or circuit pattern layer) or pad), a via portion (or via electrode). Here, the wiring portion of the electrode portion (120) may include the aforementioned pad and circuit pattern.

[0110] In the electrode portion (120), the circuit pattern can be designed in various forms for transmitting signals and / or power to the semiconductor element and can be placed on a laminated insulating layer.

[0111] In the electrode section (120), via electrodes are arranged to penetrate a portion of each insulating layer for vertical connection between each vertically stacked insulating layer and the circuit patterns arranged on the insulating layers. That is, the insulating layer may include a via hole for arrangement of the via electrode. In addition, the via electrode may have a wider width than the circuit pattern for impedance optimization or heat dissipation, but is not limited thereto and may be freely designed.

[0112] In the electrode portion (120), pads may be arranged on each insulating layer. The pads may be electrically connected to circuit patterns. In addition, the pads may be electrically connected to semiconductor elements and / or main boards or substrates, etc. For example, the pads may vertically overlap with or contact the semiconductor elements and / or main boards or substrates, etc. In addition, the pads may be electrically connected to via electrodes. The pads may vertically overlap with or contact the via electrodes.

[0113] The electrode portion (120) may include a first electrode portion (121), a second electrode portion (122), and a third electrode portion (123). The first electrode portion (121) to the third electrode portion (123) may function as a circuit connected to a semiconductor element.

[0114] The first electrode portion (121) may be located in the first insulating layer (111). The second electrode portion (122) may be located in the second insulating layer (112). The third electrode portion (123) may be located in the third insulating layer (113).

[0115] The first electrode portion (121) may include a first via electrode (121a) and a first wiring portion (121b). The first via electrode (121a) may be located in a first through hole (FIG. 3, IS) of the first insulating layer (111). The via (Vertical Interconnect Access, VIA) electrode penetrates the insulating layer to perform electrical connection in a vertical direction or a stacking direction. The first wiring portion (121b) may be disposed on the upper and lower surfaces of the first insulating layer (111). For example, the first wiring portion (121b) may include a first sub-wiring portion disposed on the upper surface of the first insulating layer (111) and a second sub-wiring portion disposed on the lower surface of the first insulating layer (111).

[0116] The second electrode portion (122) may include a second via electrode (122a) and a second wiring portion (122b). The second via electrode (122a) may be positioned in a through hole penetrating the second insulating layer (112). The second wiring portion (122b) may be positioned on one surface (e.g., the upper surface) of the second insulating layer (112).

[0117] The third electrode portion (123) may include a third via electrode (123a) and a third wiring portion (123b). The third via electrode (123a) may be positioned in a through hole penetrating the third insulating layer (113). The third wiring portion (123b) may be positioned on one surface (e.g., the lower surface) of the third insulating layer (113).

[0118] In particular, pads positioned on the outer side of the pads can be bonded to semiconductor elements, substrates, boards, etc. using solder, wires, conductive adhesives, etc., and may be positioned with a width greater than the width of the circuit pattern to solve problems such as securing yield. However, this is not limited to this, and may have a width equal to the width of the circuit pattern depending on the technical limitations of the bonding process.

[0119] And the pads arranged on the inside have the function of connecting the via electrodes and the circuit patterns. When the via electrodes are arranged with a wider width than the circuit patterns, pads having a wider width than the circuit patterns are provided for positional alignment during the manufacturing process of the via electrodes to be arranged on each circuit pattern. Therefore, each via electrode may have an upper surface that is positioned on the same plane as the lower surface of the upper pad that is in direct contact with the via electrode, and a lower surface that is positioned on the same plane as the upper surface of the lower pad that is in direct contact with the lower surface of the via electrode. Here, the lower surface of the upper pad and the upper surface of the lower pad do not necessarily mean flat surfaces, and it should be understood that even concave or convex surfaces that may appear depending on various processes may be present.

[0120] The protective layer (130) may be positioned on top or bottom of the second insulating layer (112) and / or the third insulating layer (113). For example, the protective layer (130) may include a first protective layer (131) positioned on top of the second insulating layer (112) and a second protective layer (132) positioned on bottom of the third insulating layer (113).

[0121] The protective layer (130) can have the function of protecting the pad from external moisture or contaminants, and to prevent short circuit problems caused by the occurrence of solder bridges, etc. during solder bonding between the semiconductor element and / or the main board and the circuit board, the protective layer (130) may be provided with a solder resist that does not have good solder and wettability, for example. Specifically, the semiconductor element and / or the main board, etc. have a plurality of terminals for connecting the circuit board. In addition, the plurality of terminals may be arranged at a high density. When the plurality of terminals and the pads of the circuit board are joined, solder may be used, for example. When solder is used, a solder short circuit problem may occur between terminals having a high density, and thus, a solder resist that does not have good solder and wettability may be arranged to solve this short circuit problem. In addition, the protective layer (130) may be formed of a material that has insulating properties for electrical connection. The protective layer (130) may include a resin, a curing agent, a photoinitiator, a pigment, a solvent, a filler, an additive, an acrylic monomer, etc. Additionally, the protective layer may include any one of a photo solder resist layer, a cover-lay, and a polymer material.

[0122] And the protective layer (130) on the circuit board may have an opening. Through the opening, it may be electrically connected to other semiconductor elements, the circuit board, etc. The outermost insulating layer may have an opening or be connected to a chip, etc. through a pad.

[0123] And for the electrical connection described above, a conductive member (not shown) may be located on the upper or lower side of the circuit board (100).

[0124] Furthermore, the electrode part (120) may include a fourth electrode part (124) disposed on the first protective layer (131) and a fifth electrode part (125) disposed on the second protective layer (132).

[0125] The fourth electrode portion (124) may include a first via portion (124a) and a first pad portion (124b). The first via portion (124a) may be positioned in a through hole penetrating the first protective layer (131). The first pad portion (124b) may be positioned on one surface (e.g., the upper surface) of the first protective layer (131). The first pad portion (124b) may be electrically connected to a component or substrate on a circuit board.

[0126] The fifth electrode portion (125) may include a second via portion (125a) and a second pad portion (125b). The second via portion (125a) may be positioned in a through hole penetrating the second protective layer (132). The second pad portion (125b) may be positioned on one surface (e.g., the lower surface) of the second protective layer (132). The second pad portion (125b) may be electrically connected to a substrate, etc., located below the circuit board.

[0127] The organic layer (see FIG. 3, OL) may be disposed on either the upper or lower surface of an insulating layer of one of the wiring portions. For example, the organic layer may be disposed on either the upper or lower surface of the first insulating layer (111) of the first wiring portion (121b). A detailed description thereof will be provided later.

[0128] A semiconductor device (not shown) may be mounted on the upper portion of the circuit board (100). The semiconductor device (not shown) may be a logic chip, a memory chip, or the like. The logic chip may be a central processor (CPU), a graphics processor (GPU), or the like. For example, the logic chip may be an AP including at least one of a central processor (CPU), a graphics processor (GPU), a digital signal processor, an encryption processor, a microprocessor, and a microcontroller, or an analog-to-digital converter, an application-specific IC (ASIC), or the like, or a chip set including a specific combination of those listed so far. And the memory chip may be a stacked memory such as HBM. In addition, the memory chip may include a memory chip such as a volatile memory (e.g., DRAM), a non-volatile memory (e.g., ROM), or a flash memory. The semiconductor device (not shown) may be electrically connected to the electrode unit (120) through the conductive member (CB2) described above.

[0129] Furthermore, the circuit board illustrated may be a BGA board. However, the circuit board and package board described in the embodiments are not limited to such BGAs. For example, the circuit board and package board described in the embodiments may be applied to various circuit boards (bridge boards, packages, interposers, etc.) in which a bonding layer is disposed on a first insulating layer, which is a glass layer.

[0130] In addition, circuit boards can be divided into package substrates and interposers according to their function. The package substrate functions to mount semiconductor devices and / or interposers. As data increases, the circuit board area increases or the number of laminated insulating layers increases, which can significantly reduce the yield of the circuit board. Therefore, in order to improve the yield of circuit boards with a high number of laminated layers, the yield of the circuit board can be improved by separating them into an interposer and a package substrate. In addition, as the terminal density of semiconductor devices increases, it may be difficult to implement pads on the package substrate with an area corresponding to the terminals of the semiconductor devices. Therefore, the pad size of the package substrate and the fine pattern size of the terminals of the semiconductor devices can act as a buffer.

[0131] The package substrate and interposer described above can be classified into core substrates and coreless substrates, respectively, depending on the composition of the insulating layer. In an embodiment according to the present invention, a circuit substrate having a first insulating layer including glass is described.

[0132] Referring further to FIGS. 2 and 3, the first insulating layer (111) according to the embodiment may include a bottom surface (BS) and an upper surface (US). The bottom surface (BS) and the upper surface (US) may be outer surfaces facing each other in the lamination direction or the vertical direction in the first insulating layer (111).

[0133] For example, the second insulating layer (112) may be positioned on top of the first insulating layer (111) in the vertical direction or stacking direction (Y-axis direction). And the second insulating layer (112) may be adjacent to the first insulating layer (111). That is, the bottom surface of the second insulating layer (112) may be adjacent to the top surface (US) of the first insulating layer (111).

[0134] And the third insulating layer (113) can be adjacent to the bottom surface (BS) of the first insulating layer (111). The upper surface of the third insulating layer (113) can be in contact with the bottom surface (BS) of the first insulating layer (111). In addition, the upper surface (US) of the first insulating layer (111) can face the bottom surface of the second insulating layer (112), and the bottom surface (BS) of the first insulating layer (111) can face the top surface of the third insulating layer (113).

[0135] The first insulating layer (111) may be a ‘glass layer’, a ‘glass core’, or a ‘glass insulating layer’ as described above, and may be made of glass material.

[0136] Additionally, the electrode portion may have multiple layers depending on the formation method (deposition, plating, etc.). For example, the electrode portion may be composed of a first layer (L1) of chemical copper and a second layer (L2) of electrolytic copper. In an embodiment, the first wiring portion (121b) may or may not include an organic layer (OL) depending on its location.

[0137] The first wiring section (121b) may include a first-first wiring section (121ba) arranged on the upper surface (US) of the first insulating layer (111) and a first-second wiring section (121bb) arranged on the lower surface of the 21st insulating layer (111).

[0138] Either the first-first wiring section (121ba) or the first-second wiring section (121bb) may include an organic layer (OL). Hereinafter, the first-first wiring section (121ba) is described as including an organic layer (OL).

[0139] And the first-first wiring section (121ba) may include a first layer (L1) and a second layer (L2). The first layer (L1) may be a layer in contact with the upper surface (US) of the first insulating layer (111). And the first layer (L1) may be, for example, a chemical layer. The second layer (L2) may be a layer spaced apart from the upper surface (US) of the first insulating layer (111) and positioned on the upper surface of the first layer (L1). The second layer (L2) may be, for example, an electrical layer.

[0140] Furthermore, the first-second wiring section (121bb) may include a third layer (L3) and a fourth layer (L4). The third layer (L3) may be a layer in contact with the lower surface or bottom surface (BS) of the first insulating layer (111). And the third layer (L3) may be, for example, chemical copper. The fourth layer (L4) may be a layer spaced apart from the lower surface (BS) of the first insulating layer (111) and positioned below the third layer (L3). The fourth layer (L4) may be, for example, electrical copper.

[0141] According to the present embodiment, an organic layer (OL) may be positioned on the first layer (L1). The organic layer (OL) may be positioned between the first layer (L1) and the second layer (L2). Alternatively, no organic layer may be present between the third layer (L3) and the fourth layer (L4). For example, when the first layer (L1) and the third layer (L3) have the same area, the bonding area between the second layer (L2) and the first layer (L1) may be smaller than the bonding area between the third layer (L3) and the fourth layer (L4).

[0142] Furthermore, the organic layer (OL) may be adjacent to the first layer (L1) and the second layer (L2), and may be spaced apart from the first layer (L1) and the second layer (L2) by a third layer (L3) and a fourth layer (L4). That is, the organic layer (OL) may be positioned adjacent to the first layer (L1) and the second layer (L2) by a third layer (L3) and a fourth layer (L4).

[0143] This organic layer (OL) may be made of the same material as the insulating layer (110) or the protective layer (130). For example, the organic layer (OL) may include a solder resist. In addition, the organic layer (OL) may be made of a material having insulating properties for electrical connection. The organic layer (OL) may include a resin, a curing agent, a photoinitiator, a pigment, a solvent, a filler, an additive, an acrylic monomer, etc. In addition, the organic layer (OL) may include any one of a photo solder resist layer, a cover-lay, and a polymer material. In addition, the organic layer (OL) may be made of any insulating resin, such as a thermosetting and / or photocurable resin.

[0144] In addition, the organic layer (OL) may have an amide bond structure. As described below, the organic layer (OL) may have this bond structure by being exposed to a plasma gas containing N2. For example, the organic layer (OL) may have a structure of HNC=O. By this configuration, the bonding force between the first layer (L1) and the organic layer (OL) may be smaller than the bonding force between the first insulating layer (111) and the organic layer (OL). Accordingly, the organic layer (OL) can be more easily separated from the first layer (L1), and the fabrication of a structure in which the first layer (L1) is formed on the first insulating layer (111) can be more easily implemented. That is, the ease of fabrication can be improved.

[0145] In addition, the organic layer (OL) may overlap with a second layer (L2) covering the organic layer (OL) in the horizontal direction (X-axis direction). The organic layer (OL) may be misaligned with the first insulating layer (111) and the first-second wiring portion (121bb) in the horizontal direction (X-axis direction). That is, the organic layer (OL) may not overlap with the first insulating layer (111) and the first-second wiring portion (121bb) in the horizontal direction (X-axis direction).

[0146] Furthermore, the organic layer (OL) may be spaced apart from the first via electrode (121a) in the first-1 wiring portion (121ba). For example, the organic layer (OL) may be spaced apart from the first via electrode (121a) in the vertical direction (Y-axis direction) so as not to overlap with the first via electrode (121a) in the vertical direction (Y-axis direction).

[0147] Specifically, compared to the 1-1 wiring portion (121ba), the first via electrode (121a) may include a first inner layer (L1') and a second inner layer (L2') arranged on the inner wall of the through hole (IS). In manufacturing, the organic layer (OL) may be positioned on the first layer (L1) of the 1-1 wiring portion (121ba). In particular, the organic layer (OL) may be misaligned with the first via electrode (121a) in the lamination direction or the vertical direction (Y-axis direction). That is, the organic layer (OL) may not overlap with the first via electrode (121a) in the lamination direction or the vertical direction (Y-axis direction). In addition, at least a portion of the organic layer (OL) may be positioned on the outer side of the inner wall of the through hole (IS). Therefore, the organic layer (OL) may not be positioned on the inner side of the through hole (IS) of the first insulating layer (111). Specifically, the organic layer (OL) may not be positioned on the first layer (L1) and may not be positioned in an area that overlaps the through hole (IS) of the first insulating layer (111) in the vertical direction or the stacking direction (Y-axis direction). That is, the organic layer (OL) may be positioned to be misaligned with the first via electrode (121a). By this configuration, the first layer (L1) and the first insulating layer (111) are in a bonded state by the organic layer (OL), and separation during manufacturing is easily performed, while the phenomenon of electrical connection being disconnected through the via electrode due to a decrease in reliability according to the organic material of the organic layer can be suppressed. In other words, a decrease in the electrical reliability of the circuit board can be prevented.

[0148] FIGS. 4A to 4F are drawings explaining a method for manufacturing a circuit board according to an embodiment.

[0149] The same components described above are given the same drawing reference numerals, and duplicate descriptions of the same components are omitted, with only the differences described.

[0150] A method for manufacturing a circuit board according to an embodiment may include a step of providing an organic layer, a step of exposing the organic layer to plasma gas, a step of forming a metal layer, a step of forming a core layer, a step of separating the metal layer and the core layer from the organic layer, and a step of forming an insulating layer or a build-up layer and an electrode portion on the core layer.

[0151] Referring to Fig. 4a, an organic layer (OL') can be first prepared. The organic layer (OL') can be formed of a material such as an insulating layer or a protective layer, as described above. For example, the organic layer (OL') can be formed of solder resist, ABF, PPG, etc.

[0152] Thereafter, the prepared organic layer (OL') can be exposed to a plasma gas. For example, the organic layer can be exposed to a plasma gas containing N2 in a low vacuum state. Here, the low vacuum state can have a vacuum level of 0.1 Torr to 0.5 Torr. In addition, the temperature can be set to 20°C to 30°C.

[0153] And when the plasma gas is exposed to the organic layer (OL'), the total flow rate of the plasma gas can be controlled to 1500 sccm or less. And the exposure time to the plasma gas can be less than 500 seconds. Furthermore, when the organic layer (OL') is exposed to the plasma gas, a processing energy of 3 kW to 5 kW can be applied. kW is Kilo-Watt and can be a unit of processing energy during plasma processing.

[0154] For example, in the embodiment, plasma treatment can be performed under the conditions that the vacuum is 0.22 Torr, the temperature is 25°C, the treatment energy is 4 kW, the exposure time is 200 seconds, N2 is 1000 sccm, CF4 is 100 sccm, and O2 is 300 sccm to 1000 sccm.

[0155] In addition, in the step of exposing the organic layer (OL') to the plasma gas containing N2, the plasma gas may further contain at least one of Ar, O2, and CF4 in addition to N2. For example, the plasma gas may contain N2. In addition, the plasma gas may contain N2, Ar, and O2. In addition, the plasma gas may contain N2 and CF4.

[0156] The plasma gas can be exposed to at least one surface (upper surface or lower surface) of the organic layer (OL'). For example, the plasma gas can be exposed to both the upper surface and lower surface of the organic layer (OL').

[0157] Referring to Fig. 4b, upon exposure to such plasma gas, the exposed organic layer (OL') may have an amide bond structure. For example, the exposed organic layer (OL') may have a structure of HNC=O. That is, an amide bond structure may exist on both the upper and lower surfaces of the organic layer (OL').

[0158] By this configuration, the exposed organic layer (OL') may not experience any change in illuminance regardless of exposure to the plasma gas. For example, the illuminance of the organic layer (OL') may have a change of 10% or less depending on whether or not it is exposed to the plasma gas. In addition, since the organic layer (OL') exposed to the plasma gas has an amide bond structure, for example, the first layer can be easily manufactured without an interface void during etching. For example, by performing a wet method, voids at the interface of the first layer can be minimized, thereby improving the reliability of the circuit board.

[0159] Referring to FIGS. 4C and 4D , a metal layer may be formed on at least one of the upper and lower surfaces of the exposed organic layer. For example, a first layer (L1), which is a metal layer, may be formed on an organic layer (OL') treated with a plasma gas. For example, a first layer (L1), which is a metal layer, may be formed on the upper and lower surfaces of the exposed organic layer (OL'). The first layer (L1) may be formed according to various forming methods (deposition, plating, etc.) as described above. For example, the first layer (L1) may be chemical copper or electrolytic copper.

[0160] And, a first insulating layer (111), which is a core layer, can be laminated on the first layer (L1), which is a metal layer. That is, a first insulating layer (111) made of glass can be formed on the metal layer. For example, a first insulating layer (111) can be laminated on the upper and lower portions of the first layer (L1) above and below the organic layer (OL').

[0161] Next, the first insulating layer (111), which is a core layer, and the first layer (L1), which is a metal layer, can be separated from the organic layer (OL'). As described above, the exposed organic layer (OL') may have an amide bond structure without increasing roughness on the surface in contact with the first layer (L1), which is a metal layer. Accordingly, the bonding force between the organic layer (OL') and the first layer (L1), which is a metal layer, may be lower than the bonding force between the first insulating layer (111), which is glass, and the first layer (L1). Accordingly, the separation can be performed more easily.

[0162] Referring to FIG. 4e, a first electrode portion (121) may be formed on a first insulating layer (111), which is a core layer. At this time, a first layer (L1) exists on one surface of the first insulating layer (111), and a part of the exposed organic layer (OL') may remain on a part of the first layer (L1). For example, a sub-organic layer (OL), which is a part of the exposed organic layer (O''), may remain on the first layer (L1), which is a metal layer. The sub-organic layer may correspond to the organic layer described above in FIGS. 2 and 3. In addition, as described above, the first wiring portion (121b) of the first electrode portion (121) may or may not include the organic layer (OL) depending on the position. In addition, the organic layer (OL2) may be positioned between the second layer (L2) and the first layer (L1).

[0163] Additionally, a through hole in the first insulating layer may be formed, and a first via electrode may be formed. Such a through hole may be formed by a photolithography process using a photomask or by various etching methods, such as a laser method.

[0164] Referring to FIG. 4F, a build-up layer and an electrode portion may be formed on the core layer. Specifically, a build-up layer (a second insulating layer or a third insulating layer) may be laminated on a first insulating layer (111). Furthermore, an electrode portion (a second electrode portion, a third electrode portion) may be formed on the build-up layer (a second insulating layer or a third insulating layer). The electrode portion (e.g., a wiring portion) may be formed by a manufacturing process of a printed circuit board, such as an additive process, a subtractive process, a modified semi-additive process (MSAP), or a semi-additive process (SAP).

[0165] Furthermore, a protective layer (131, 132) may also be formed on the upper or lower portion of the build-up layer. Additionally, a fourth electrode portion and a fifth electrode portion may also be formed on the protective layer (131, 132).

[0166] FIG. 5 is an image of the surface of the organic layer according to the comparative example and the embodiment, FIG. 6 is a graph of the contact angle on the surface of the organic layer according to the comparative example and the embodiment, FIGS. 7(a) to 7(c) are drawings showing the surface roughness of the organic layer according to the comparative example in 1D, 2D, and 3D, FIGS. 8(a) to 8(c) are drawings showing the surface roughness of the organic layer according to the embodiment 1 in 1D, 2D, and 3D, FIGS. 9(a) to 9(c) are drawings showing the surface roughness of the organic layer according to the embodiment 2 in 1D, 2D, and 3D, and FIG. 10 is an SEM (Scanning Electron Microscopy) photograph of the insulating layer and the electrode portion. As described above, the organic layer may have the same material as the insulating layer. Therefore, the treatment for the organic layer may correspond to the treatment for the insulating layer.

[0167] Referring to FIG. 5, FIG. 5(a) is the surface of an organic layer when plasma treatment is not applied to the organic layer (comparative example), FIG. 5(b) is the surface of an organic layer when plasma treatment (N2) is applied to the organic layer (Example 1), and FIG. 5(c) is the surface of an organic layer when plasma treatment (CF4+N2) is applied to the organic layer (Example 2).

[0168] And Table 1 below is a table showing the average contact angles of each of Comparative Examples, Example 1, and Example 2, which are FIGS. 5(a) to 5(c).

[0169] Comparison Example Example 1 (N2) Example 2 (CF4+N2) Average contact angle 79.47.15.9

[0170] Referring to FIGS. 5 and 6 and Table 1, it can be seen that when plasma treatment is performed, the surface contact angle of the organic layer decreases from about 80º to about 10º or less. This can suppress the generation of uneven residues or opaque layers on the surface during the surface treatment or coating process. In other words, the clouding phenomenon can be suppressed, thereby preventing deterioration of surface uniformity or induction of bonding defects. In addition, the contact angle is lowered, so that the wettability of the surface increases, allowing a liquid (e.g., solder paste, adhesive, etc.) to spread evenly on the surface of the organic layer. This can improve the bonding quality for the metal layer or the first layer on the organic layer. Table 2 shows Ra (average roughness) and Rz (maximum roughness) in Comparative Example, Example 1, and Example 2, respectively.

[0171] Comparison Example Example 1 (N2) Example 2 (CF4+N2) Ra0.03um0.03um0.03umRz0.67um0.70um0.66um

[0172] Here, Ra (Arithmetic Average Roughness) may be a value calculated by averaging the absolute values ​​of the roughness height of the surface of the organic layer. For example, the average value of the height difference may be the average roughness by comparing the height of the surface in the organic layer with a horizontal line. For example, the average roughness may be the average of the absolute values ​​of the difference between the height of each point and the reference line (average line) within the measured length. Rz (Maximum Height Roughness) may be a value based on the distance between the highest point and the lowest point of the surface among the roughness of the surface of the organic layer. For example, the maximum roughness is calculated by dividing the surface into a predetermined number (e.g., 5) equal parts, measuring the difference between the highest point and the lowest point in each part, and then calculating the average of these values. The average roughness may be used to evaluate the overall roughness of the surface of the organic layer. And the surface quality of the organic layer can be strictly controlled through the maximum roughness. Referring to FIGS. 7 to 9 and Table 2, it can be seen that there is no or very little change in the average roughness in Examples 1 and 2 compared to the comparative example. In addition, it can be seen that there is also very little change in the maximum roughness in Examples 1 and 2 compared to the comparative example. Accordingly, it can be seen that there is no or very little change in the surface roughness of the organic layer after the plasma treatment. Therefore, even if the plasma treatment is performed, the change in the surface roughness of the organic layer can be at the same level as before the plasma treatment. Accordingly, the roughness of the first layer, which is a metal layer on the organic layer, can also be lowered. Therefore, since the roughness of the first layer, which is an electrode part, is low, loss is reduced during signal transmission, so that an improved signal transmission rate can be implemented.

[0173] In addition, Fig. 10(a) is an SEM (Scanning Electron Microscopy) photograph of the insulating layer (organic layer) and the electrode portion in the first embodiment, and Fig. 10(b) is an SEM photograph of the insulating layer (organic layer) and the electrode portion in the second embodiment. As described above, the organic layer is made of the same material as the insulating layer (110) (or protective layer (130)), and therefore, it is described below as the insulating layer.

[0174] As described above, in the first and second embodiments, the electrode portion can be smoothly and uniformly applied or formed on the surface of the insulating layer (110) corresponding to the organic layer without increasing or significantly changing the roughness at the interface between the insulating layer and the electrode portion (120). In other words, the quality can be improved and uniformity can be secured in the surface treatment or plating process.

[0175] Figure 11 is a drawing showing the peel strength according to comparative examples, examples 1 and 2.

[0176] Referring further to Fig. 11, Examples 1 and 2 have a peel strength of 0.1 kgf / cm between the organic layer and the metal layer. 2 It can be seen that the value for the adhesion between the organic layer and the metal layer is less than 0.1 kgf / cm. 2 By forming a lower layer, separation between the organic layer and the metal layer can be achieved more easily. In other words, separation between the first insulating layer, which is glass, and the metal layer (first layer) can be effectively prevented.

[0177] Figure 12 shows the XPS (X-ray Photoelectron Spectroscopy) results for the metal layer and organic layer in the circuit board according to the embodiment.

[0178] That is, in the first layer, which is a metal layer, X-rays are used as a light source for the nanoparticle and circuit pattern layer, and the binding energy through the kinetic energy of photoelectrons emitted from the surface of the nanoparticle and circuit pattern layer, which is a sample, can be measured.

[0179] Referring to Figure 12, the XPS results (A) are from one side of the first layer, which is a metal layer (the side not in contact with the first insulating layer), and the XPS results (B) are from one side of the organic layer (OL) separated from the first layer, which is a metal layer.

[0180] Furthermore, Table 3 shows the results of XPS Quantitative Analysis for Comparative Examples, Examples 1 and 2, respectively. In Fig. 12, the Y-axis represents “c / s”, which stands for “counts per second,” which may be the number of photoelectrons detected in the XPS measurement calculated per second. Accordingly, atomic% may be calculated through correction values ​​such as sensitivity factors. In addition, the x-axis represents bonding energy or electron binding energy, and the unit may generally be electron volts (eV).

[0181] Atomic% Classification C 1sO 1sN 1sF 1sNa 1sSi 2pP 2pS 2pBa 3d Comparative Example 48.6 32.2 2.16.5 4.7 1.4 2.6 1.3 0.7 Example 1 (N2) 52.6 26.7 2.7 9.9 4.30.8 2.0 0.6 0.4 Example 2 (CF4+N2) 56.1 23.9 2.9 10.6 4.7 0.30.6 0.5 0.4 C Increase O Decrease N Increase

[0182] Referring to Table 12 and Table 3, Examples 1 and 2 (plasma treatment) may increase the amounts of C, O, and N compared to the comparative example (non-plasma treatment). For example, in some areas of the first layer, the organic layer may remain so that the atomic ratio (or percentage, amount) of C may be 1.8 to 3 times less than the atomic ratio of O. In other areas, the atomic ratio of C may be 1 to 1.8 times less than the atomic ratio of O. In addition, in some areas, the atomic ratio of O may be 12 times less than the atomic ratio of N. And in other areas, the atomic ratio of O may exceed 12 times the atomic ratio of N. For example, in other areas, the atomic ratio of O may be 15 times or more less than the atomic ratio of N. By this, it can be seen that the ease of manufacturing the circuit board is improved and the signal transmission efficiency is improved by confirming that the amide bond remains in the metal layer, and the easy separation of the insulating layer and the organic layer. The structure of the various embodiments described above can be equally applied to the circuit board according to the present embodiment. In addition, the circuit board according to the various embodiments described above can be positioned in some areas or correspond to one substrate in various semiconductor packages. FIG. 13 is a plan view of a circuit board according to another embodiment of the present invention, and FIG. 14 is an enlarged view of part K3 in FIG. 13.

[0183] Referring to FIGS. 13 and 14, a circuit board (100A) according to an embodiment may include a build-up structure (110) and an electrode portion (120). In the following embodiment of the present invention, the build-up structure (110) may include a plurality of insulating layers and may be provided in a structure in which a plurality of insulating layers are laminated. The wiring or electrode portion (120) may be disposed by being embedded in each layer (e.g., an insulating layer) of the build-up structure (110), thereby performing a function of transmitting signals and / or power from a main board (not shown) to a semiconductor element.

[0184] In addition, such a circuit board may include a core layer disposed within a build-up structure (110). Accordingly, the circuit board may be divided into an outer laminated region and an inner laminated region, and the inner laminated region may correspond to the core layer. When the circuit board includes the core layer, the outer laminated region disposed above the core layer may be referred to as an upper build-up layer, and the outer laminated region disposed below the core layer may be referred to as a lower build-up layer. As described above, the upper build-up layer and / or the lower build-up layer may be formed by a structure in which a plurality of insulating layers are laminated.

[0185] As an example, the build-up structure (110) may be formed of a plurality of insulating layers laminated between the upper surface of the upper build-up layer and the lower surface of the lower build-up layer. For example, the build-up structure (110) may include a core layer (111), an upper build-up layer (112), and a lower build-up layer (113). In addition, a protective layer (SR) described later may be further disposed on the build-up structure (110). Furthermore, when the circuit board is coreless, an insulating layer may be positioned between the upper surface of the upper build-up layer (112) and the lower surface of the lower build-up layer (113) without the aforementioned core layer (111). In this case, the upper build-up layer (112) and the lower build-up layer (113) are not distinguished, but are described separately for convenience of explanation.

[0186] In addition, the build-up structure (110) of the circuit board (100A) may be rigid or flexible. For example, the build-up structure (110) of the circuit board (100A) may include glass or plastic. For example, the build-up structure (110) of the circuit board or each insulating layer forming the build-up structure (110) may include chemically strengthened / semi-strengthened glass such as soda lime glass or aluminosilicate glass. For example, the build-up structure (110) of the circuit board may include a strengthened or flexible plastic such as polyimide (PI), polyethylene terephthalate (PET), propylene glycol (PPG), or polycarbonate (PC). For example, the build-up structure (110) of the circuit board may include sapphire. For example, the build-up structure (110) of the circuit board may include an optically isotropic film. For example, the build-up structure (110) of the circuit board may include a cyclic olefin copolymer (COC), a cyclic olefin polymer (COP), optically isotropic polycarbonate (PC), or optically isotropic polymethyl methacrylate (PMMA). For example, the build-up structure (110) of the circuit board may be formed of a material including a filler and an insulating resin. For example, the build-up structure (110) of the circuit board may have a structure in which a filler such as silica or alumina is arranged in a thermosetting resin or a thermoplastic resin. In addition, the build-up structure (110) may have a structure in which a plurality of different insulating materials are laminated, and an exemplary arrangement structure will be described in more detail as follows.

[0187] In one embodiment, the build-up structure (110) may include a core layer including a reinforcing member. Here, the core layer may mean an insulating layer including the reinforcing member and having a thickness exceeding several tens (e.g., 30) μm in the vertical direction (Y-axis direction or lamination direction) thereof. Preferably, the core layer may have a thickness of 100 μm or more in the vertical direction. In addition, the upper build-up layer (112) and the lower build-up layer (113) may include a plurality of layers that are respectively disposed above and below the core layer and do not include a reinforcing member. In this case, the circuit board may be the core board. The reinforcing member may also be referred to as a reinforcing fiber or glass fiber embedded in the core layer. Hereinafter, the upper build-up layer (112) will be described as being based on the upper build-up layer. In addition, although the upper build-up layer is illustrated in the drawing as including only a 'first insulating layer', it may be composed of a plurality of insulating layers, and the upper build-up layer may be used interchangeably with the first insulating layer hereinafter.

[0188] Reinforcing member may mean a glass fiber material extending along a direction perpendicular to the vertical direction of the insulation layer (e.g., horizontal direction (X-axis direction)) and may have a different meaning from the spaced apart fillers.

[0189] The core layer (111) may be made of various insulating materials. In addition, the core layer (111) may be made of multiple layers, and the multiple layers may be made of the same or different materials. Furthermore, the core layer (111) may include via electrodes penetrating the upper and lower surfaces of the core layer (111).

[0190] And the upper build-up layer (112) or the lower build-up layer (113) can be provided with any insulating resin such as a thermosetting and / or photocurable resin. As the thermosetting resin, ABF (Ajinomoto Build-up Film), a product released by Ajinomoto Co., Ltd., can be used, and a material such as prepreg (PPG) containing glass fiber can be used. As the photocurable resin, any insulating resin such as PID (Photo Imageable Dielectric) resin can be used. The above-mentioned arbitrary insulating resin may be, for example, an epoxy resin, a bismaleimide triazine resin (BT resin), a phenol resin, etc., and may include an inorganic filler such as silica. When the insulating resin is used as a core, it may include a reinforcing material provided with glass fiber or aramid fiber. For example, when manufacturing a build-up structure (110), ABF (Ajinomoto Build-up Film), a product released by Ajinomoto Co., Ltd., can be used, and FR-4, BT (Bismaleimide Triazine), PID (Photo Imageable Dielectric resin), BT, etc. can be used. For example, when the circuit board (100A) is coreless, the build-up structure (110) can be provided by laminating without a core layer, for example, using ABF. The above-described insulating resins can be freely combined to form the build-up structure (110) by taking into consideration the dielectric constant, insulating properties, warpage of the circuit board, etc.

[0191] Additionally, the circuit board (100A) according to the embodiment may further include a protective layer (SR) and a bump portion (BP). And the circuit board (100A) may further include a metal layer (MP).

[0192] The protective layer (SR) can have the function of protecting the pad from external moisture or contaminants, and to prevent a short circuit problem when joining the semiconductor element and / or the main board and the circuit board, the protective layer (SR) can be provided with a solder resist, for example. Specifically, the semiconductor element and / or the main board, etc. have a plurality of terminals for connecting the circuit board. In addition, the plurality of terminals can be arranged at a high density. When the plurality of terminals and the pads of the circuit board are joined, solder can be used, for example. When solder is used, a solder short circuit problem may occur between terminals with a high density, and thus, a solder resist that does not have good wettability with the solder can be arranged to solve this short circuit problem. In addition, the protective layer (SR) can be formed of a material that has insulating properties for electrical connection. The protective layer (SR) can include a resin, a curing agent, a photoinitiator, a pigment, a solvent, a filler, an additive, an acrylic monomer, etc. Additionally, the protective layer (SR) may include any one of a photo solder resist layer, a cover-lay, and a polymer material. The protective layer (SR) may have at least one opening for connection between a terminal of a semiconductor device and a pad of a circuit board. For example, in an embodiment, the protective layer (SR) may be composed of a resin and a filler, which is a reinforcing member.

[0193] A protective layer (SR) is disposed on a build-up structure (110), and specifically, the protective layer (SR) may include a first protective layer (SR1) disposed on an upper build-up layer (112) and a second protective layer (SR2) disposed under a lower build-up layer (113). The first protective layer (SR1) and the second protective layer (SR2) may be disposed spaced apart from each other along the lamination direction, and may have different thicknesses in consideration of warpage of the circuit board. Hereinafter, the protective layer will be described based on the first protective layer (SR1).

[0194] The first protective layer (SR1) may have a higher coefficient of thermal expansion than the insulating layer constituting the other build-up structure. Therefore, the bump portion (BP) may be peeled off from the first protective layer (SR1) due to heat applied during the process of the circuit board and / or heat generated during the operation of the semiconductor device. In addition, as the horizontal width and / or spacing of the bump portion (BP) narrow, there is a possibility that the bump portion (BP) may be peeled off due to the applied stress. Therefore, the peeling problem can be solved by improving the bonding strength between the bump portion and the protective layer through the structure of the bump portion described below. This will be described later.

[0195] The bump portion (BP) may be disposed on the protective layer (SR). The bump portion (BP) may include a protrusion portion (PP) disposed on the upper surface of the protective layer (SR) and a penetration portion (TP) penetrating the protective layer (SR). The penetration portion (TP) and the protrusion portion (PP) may each include a plurality of protrusions or convex portions protruding toward the adjacent protective layer (SR), thereby suppressing a peeling phenomenon from the protective layer. For example, on the first protective layer (SR1), the penetration portion (TP) and the protrusion portion (PP) may include a plurality of protrusions (or convex portions) protruding toward the first protective layer (SR1).

[0196] A metal layer (not shown) may be disposed on the bump portion (BP). Specifically, the metal layer (not shown) may be disposed on the upper surface of the protrusion portion (PP). The metal layer (not shown) is in contact with the bump portion (BP) and may provide electrical connection and improved durability and reliability.

[0197] The metal layer (not shown) may be formed of at least one metal layer. The metal layer (not shown) may be formed of copper (Cu), gold (Au), nickel (Ni), palladium (Pd), tungsten (W), titanium (Ti), or a combination thereof. As a result, the bonding strength with the bump portion (BP) is improved, the corrosion resistance and durability of the bump portion (BP) are improved, and the loss of electrical signals can be minimized.

[0198] The width of the metal layer (not shown) may be different from the width of the upper surface of the protrusion (PP) of the bump portion (BP). For example, the width of the metal layer (not shown) may be smaller than the width of the upper surface of the protrusion (PP) of the bump portion (BP). The metal layer (not shown) may be formed on the bump portion (BP) by deposition, electroplating, or the like of various metals.

[0199] In addition, the wiring or electrode portion (120) according to the embodiment is arranged for electrical connection between a main board, etc. and a chip (or semiconductor element, die), and includes a wiring portion (circuit pattern or circuit pattern layer, pad) and a via electrode. For example, the wiring portion of the electrode portion (120) may include a circuit pattern and pad on the upper surface of an insulating layer. In addition, the electrode portion (120) may include a via portion (121) penetrating the insulating layer. Accordingly, in the embodiment, the electrode portion (120) may include a via portion (121) and a wiring portion (122).

[0200] In the electrode portion (120), the circuit pattern can be designed in various forms for transmitting signals and / or power to the semiconductor element, and is arranged within each insulating layer of the laminated build-up structure (110).

[0201] In the electrode portion (120), a via portion (121) is arranged to penetrate at least a portion of each insulating layer for vertical connection between circuit patterns arranged in each insulating layer of the build-up structure (110). The via portion (121) can connect a plurality of wiring portions (122) to each other. The via portion (121) can also be formed in multiple pieces like the wiring portion. That is, the insulating layer can include a via hole for arranging the via electrode. In addition, the via electrode can have a wider width than the circuit pattern for impedance optimization or heat dissipation, but is not limited thereto and can be freely designed.

[0202] In the electrode portion (120), a wiring portion (122) may be arranged on each insulating layer. And the wiring portion (122) may be electrically connected to a circuit pattern. In addition, the wiring portion (122) may be connected to each via portion (121). And the wiring portion (122) arranged on the upper and lower surfaces of the build-up structure (110) may be electrically connected to a semiconductor element and / or a main board or substrate, etc. For example, the electrode portion (120) may be located on each layer (insulating layer) of the core layer (111), the upper build-up layer (112), and the lower build-up layer (113).

[0203] According to an embodiment, the circuit pattern of the wiring portion (122) in the electrode portion (120) may include a circuit pattern (or a combination thereof) having a fine pitch and a second pattern having a larger pitch than the first pattern. Referring to FIG. 14, the first pattern may be arranged on the upper build-up layer (112) so as to have a high wiring density for signal connection with the semiconductor elements (CH1, CH2). In addition, the first pattern may be provided to provide a function of a line for signal connection between the semiconductor elements (CH1, CH2), thereby preventing the semiconductor elements from becoming unnecessarily large, thereby improving the yield of the semiconductor elements.

[0204] Also, referring to FIG. 14, the second pattern is illustrated as being placed on the upper build-up layer (112), but is not limited thereto, and the second pattern may also be placed on the lower build-up layer (113) to perform the function of electrically connecting the circuit board and the semiconductor elements (CH1, CH2).

[0205] In addition, according to an embodiment, the first pattern may be connected to the connecting member (SD). The second pattern may be spaced apart from the connecting member (SD) in the horizontal direction (X-axis direction). Here, as described above, the horizontal direction may include both the first horizontal direction and the second horizontal direction perpendicular to the stacking direction. In addition, the width and / or spacing of the second pattern of the wiring portion (122) in the horizontal direction (X-axis direction) is larger than the width and / or spacing of the first pattern in the horizontal direction (X-axis direction). The second pattern may mean a pattern having the same width and spacing as a pattern used in a conventional circuit board, and the first pattern means a microcircuit pattern having a width and spacing of 5 μm or less, for example, narrower than the width and spacing of a pattern used in a conventional circuit board for interconnection between semiconductor elements, impedance matching, or formation of an inductor.

[0206] And the electrode portion (120) may include the aforementioned bump portion (BP). The bump portion (BP) may be electrically connected to the wiring portion (122).

[0207] In addition, the circuit board (100A) may include a cavity (CV) formed therein. The cavity (CV) may be formed in at least one of the core layer (111), the upper build-up layer (112), and the lower build-up layer (113). For example, the cavity (CV) may be formed across the core layer (111) and the upper build-up layer (112), or may be formed only in the core layer (111). The cavity (CV) may be formed of a plurality of cavities spaced apart from each other in the horizontal direction. For example, the cavity (CV) may include a first cavity (CV1) and a second cavity (CV). A connecting member (SD) described below may be arranged in the first cavity (CV1), and the second cavity (CV2) may include not only the connecting member (SD) but also other connecting members (SD) and functional elements (e.g., passive elements). The first cavity (CV1) and the second cavity (CV2) can be positioned to overlap the core layer (111) at least partially in the first horizontal direction (X-axis direction), and are arranged to have different vertical depths and different horizontal widths, thereby preventing warpage of the circuit board and enabling devices having various functions to be embedded within the circuit board. Hereinafter, the first cavity (CV1) in which the connecting member (SD) is arranged will be described as a reference.

[0208] The connecting member (SD) may be mounted in the first cavity (CV1). The connecting member (SD) may be arranged in the first cavity (CV1) and may perform a function of electrically connecting a plurality of other chips (CH1, CH2) arranged on the upper portion of the circuit board (100A) to each other. For example, by interconnecting chiplets that are functionally divided from existing semiconductor chips, the size of the semiconductor chip may be reduced, thereby contributing to improving the yield of the semiconductor chip. The connecting member (SD) is made of, for example, an inorganic material (e.g., Si) or an organic material, and may be referred to as a bridge. In addition, the connecting member (SD) may be used interchangeably with the terms 'semiconductor element', 'chip', 'die', etc.

[0209] In addition, the connecting member (SD) may include a connecting electrode portion on one side and / or on another side spaced apart from the one side in a vertical direction. For example, the connecting electrode portion may be located on the upper portion of the connecting member (SD). By this configuration, the connecting member (SD) may be electrically connected to a plurality of chips (CH1, CH2) arranged on the outer side of the circuit board (100A). For example, the connecting electrode portion may be electrically connected to the electrode portion of the circuit board, and may be electrically connected to other semiconductor elements or chips (CH1, CH2) on the circuit board. In addition, different chips (CH1, CH2) may be electrically connected through the connecting member (SD).

[0210] Furthermore, the wiring portion (122) of the electrode portion (120) may include a pad portion (PD) arranged on the outer surface (e.g., upper surface / lower surface) of the build-up structure (110). For example, in the embodiment, the pad portion (PD) may be arranged on the upper surface of the build-up structure (110) or the upper surface of the upper build-up layer (112). The pad portion (PD) may be

[0211] It can be electrically connected to the penetration portion (TP). Hereinafter, the pad portion (PD) arranged on the upper surface of the upper build-up layer (112) among the build-up structure (110) will be described based on it. In addition, the pad portion (PD) arranged on the outermost side of the build-up structure (110) can be bonded to a semiconductor element, substrate, board, etc. using solder, wire, conductive adhesive, etc., and can be arranged to have a width larger than the width of the circuit pattern in order to solve problems such as securing yield. However, the present invention is not limited thereto, and may have a width equal to or smaller than the width of the circuit pattern depending on the technical limitations of the bonding process.

[0212] And the pad arranged on the inner side (inside the outer surface) of the build-up structure (110) among the electrode portions (120) functions to connect the via electrode and the circuit pattern. When the via electrode is arranged with a wider width than the circuit pattern, a pad having a wider width than the circuit pattern is provided for positional alignment during the manufacturing process of the via electrode to be arranged on each circuit pattern. Accordingly, each via electrode may have an upper surface that is positioned on the same plane as the lower surface of the upper pad that is in direct contact with the via electrode, and a lower surface that is positioned on the same plane as the upper surface of the lower pad that is in direct contact with the lower surface of the via electrode. Here, the lower surface of the upper pad and the upper surface of the lower pad do not necessarily mean a flat surface, and it should be understood that even a concave surface or a convex surface that may appear depending on various processes may be included.

[0213] In addition, the electrode portion (120) may include a conductive member or conductive bonding portion (SB) disposed below the lower build-up layer (113) and the second protective layer (SR2). The conductive member or conductive bonding portion (SB) may perform electrical connection with another substrate, etc. Accordingly, the conductive member or conductive bonding portion (SB) may serve as an intermediate medium for electrical signal transmission. In addition, the conductive member or conductive bonding portion (SB) may release heat from the circuit board or package substrate through heat transfer.

[0214] In addition, circuit boards can be divided into package substrates and interposers according to their function. The package substrate functions to mount semiconductor devices and / or interposers. As data increases, the circuit board area increases or the number of laminated insulating layers increases, which can significantly reduce the yield of the circuit board. Therefore, in order to improve the yield of circuit boards with a high number of laminated layers, the yield of the circuit board can be improved by separating them into an interposer and a package substrate. In addition, as the terminal density of semiconductor devices increases, it may be difficult to implement pads on the package substrate with an area corresponding to the terminals of the semiconductor devices. Therefore, the interposer can act as a buffer between the pad size of the package substrate and the fine pattern size of the terminals of the semiconductor devices.

[0215] The package substrate and interposer described above can be classified into core substrates and coreless substrates, respectively, depending on the composition of the insulating layer. In the case of a core substrate, the insulating layer may include a core layer, and the core layer may refer to a layer among the laminated insulating layers that includes a reinforcing member. The reinforcing member may refer to glass fiber. The core layer may have the function of preventing warpage of the circuit board during the process by being arranged thicker than other insulating layers. However, the core layer may cause problems such as voltage drop and signal loss, or may be difficult to thin. Therefore, depending on the application, the insulating layer of the circuit board may use a coreless substrate that does not include a core layer.

[0216] Specifically, the upper surface (US1) of the first protective layer (SR1) can be in contact with the lower surface (BS) of the bump portion (BP). The bump portion (BP) may be formed of a plurality of layers. For example, the bump portion (BP) may include a first sub-layer (L5), a second sub-layer (L6), and a third sub-layer (L7). The first sub-layer (L5) can be in contact with the first protective layer (SR1). The first sub-layer (L5) may be arranged at the lowest portion of the bump portion (BP). The second sub-layer (L6) may be located between the first sub-layer (L5) and the third sub-layer (L7). In addition, the third sub-layer (L7) may be located at the uppermost portion of the bump portion (BP) and may be in contact with the upper surface of the second sub-layer (L6).

[0217] The first sub-layer (L5) and the second sub-layer (L6) may have a smaller thickness than the third sub-layer (L7). The first sub-layer (L5) and the second sub-layer (L6) may be formed by a deposition process such as sputtering. In addition, the first sub-layer (L5), the second sub-layer (L6), and the third sub-layer (L7) may include a transition metal. In addition, each layer may include different or the same metal. For example, the first sub-layer (L5) and the second sub-layer (L6) may be formed of different metals. In addition, the first sub-layer (L5) and the third sub-layer (L7) may be formed of different metals. The second sub-layer (L6) and the third sub-layer (L7) may include the same metal. For example, the first sub-layer (L5) may include Ti, and the second sub-layer (L6) and the third sub-layer (L7) may include Cu. At this time, the second sub-layer (L6) and the third sub-layer (L7) are made of Cu, but the formation methods (sputtering, electroplating, etc.) are different, so that the crystal grain sizes may be different, or there may be a difference in the etching speed when etching each layer. For example, the first sub-layer (L5) and the second sub-layer (L6) may be formed by sputtering, but the third sub-layer (L7) may be formed by plating. By this configuration, the bonding strength between the bump portion (BP) and the first protective layer (SR1) is improved, so that problems such as peeling can be resolved. Furthermore, the multiple layer structure of the bump portion (BP) can be equally applied to the via hole or through hole of the first protective layer (SR1).

[0218] FIG. 15 is a graph of an XPS (X-ray Photoelectron Spectroscopy) spectrum for another surface between a protective layer and a bump portion in a circuit board according to an embodiment, and FIG. 16 is a graph of an XPS spectrum for a boundary surface between a protective layer and a bump portion in a circuit board according to an embodiment.

[0219] FIG. 15 shows graphs of XPS (X-ray Photoelectron Spectroscopy) spectra for cases where XPS analysis is performed on the surface of a bump portion (BP) or a first sub-layer (L5) exposed after removal of a first protective layer (SR1) by etching or separation (SP1, A) and where XPS analysis is performed on the surface of a first protective layer (SR1) exposed after removal of a bump portion (BP) by etching or separation (SP2, B).

[0220] And Figure 16 shows a graph of an XPS (X-ray Photoelectron Spectroscopy) spectrum for the boundary surface of the first protective layer (SR1) and the bump portion (BP) (the upper surface of the first protective layer (SR1) or the lower surface of the bump portion (BP)).

[0221] First, X-ray photoelectron spectroscopy (XPS) is a technique for analyzing the chemical state of the surface of a target object. Generally, XPS is a technique that measures photoelectrons emitted from the surface of a material to analyze the elemental composition and chemical bonding state of that surface. XPS can analyze a region with a depth of nm on the sample surface. For example, XPS analyzes a region with a depth of 10 to 20 nm. Through XPS analysis, substances adsorbed on the surface, attached contaminants, and oxide layers can be analyzed.

[0222] This XPS is performed by irradiating the surface of a target with high-energy X-rays, and when photoelectrons are emitted from the atoms on the surface, the emitted photoelectrons are detected by an analysis device, and the elements and chemical states (e.g., oxidation states) are analyzed based on the binding energy of each photoelectron. In other words, since each element has a unique binding energy, the elements contained in the sample can be identified by analyzing the binding energy through XPS. In addition, since the energy of the emitted photoelectrons changes depending on the chemical environment of the emitted atoms, the chemical state (e.g., oxidation state) of the elements can be identified by analyzing the subtle changes in binding energy through XPS. In addition, XPS can quantitatively analyze the relative intensity of elements present on the surface. Therefore, the relative intensity difference for each element can be analyzed based on the intensity or density of the 'counts per second, signal intensity (c / s)' described below. In the XPS spectrum graph, the X-axis represents bonding energy or electron binding energy, and the unit can generally be electron volts (eV). The Y-axis in the graph stands for "c / s", which stands for "counts per second", which can be a value calculated per second of the number of photoelectrons detected in the XPS measurement.

[0223] Furthermore, as XPS analysis conditions, a source with an energy of 1 kV to 15 kV can be applied to XPS analysis. In addition, the beam size can be 10 μm to 500 μm. In addition, as sputtering conditions, an ion source may be used with argon ions (Ar+), and the ion energy can be 1 keV to 5 keV. The sputtering rate can be measured in nm / min units. However, these conditions can be modified depending on the adjusted conditions or sample. In this example, the beam size is 120 μm, and the energy of the X-ray source is set to 3 kV.

[0224] First, as illustrated in FIG. 16, when performing XPS analysis at the interface between the first protective layer (SR1) and the bump portion (BP), the circuit board may have a first peak (P1) having the highest intensity at 400 (eV) to 600 (eV) among the binding energy of 200 (eV) to 1200 (eV) in the XPS spectrum. At this time, the binding energy in the XPS spectrum may be 0 (eV) to 1200 (eV). The first peak (P1) may correspond to the intensity for O1s (oxygen atom). The first peak (P1) may be located within 530 (eV) to 535 (eV). That is, the concentration of oxygen may be the highest at the interface between the bump portion and the first protective layer. This means that a large concentration of oxide is formed due to the thermal reaction between the first sub-layer (or bump portion) and the first protective layer. Therefore, it can be seen that the bonding between the bump portion and the first protective layer is strong based on the oxide concentration. In other words, the circuit board according to the embodiment provides bonding strength between the bump portion and the first protective layer.

[0225] And the circuit board may have a second peak (P2) with the highest intensity at a binding energy of 400 (eV) to 500 (eV) during XPS analysis. In addition, the circuit board may have a third peak (P3) with the highest intensity at a binding energy of 200 (eV) to 400 (eV) during XPS analysis. The first peak (P1) may have an intensity greater than the second peak (P2) or the third peak (P3).

[0226] The second peak (P2) may correspond to the intensity of Ti2P3 (titanium atoms). The second peak (P2) may indicate that titanium exists in various chemical states (e.g., Ti0, Ti2+, Ti3+, Ti4+). For example, when titanium (Ti) forms different chemical bonds, the position of the Ti2p3 peak may shift slightly or split. For example, titanium in an oxidized state such as TiO2 (titanium dioxide) is in the Ti4+ state, in which case the Ti2p3 peak may have an intensity of about 458.7 [eV]. In an embodiment, the second peak (P2) of Ti2P3 may have an intensity corresponding to a binding energy of 453.7 [eV]. By this configuration, titanium is present in greater abundance at the interface of the circuit board compared to other elements. Since the intensity of the second peak (P2) is lower than that of the first peak (P1) corresponding to oxygen atoms, it can be seen that a large amount of titanium and oxygen exist at the boundary between the first protective layer and the bump portion. This indicates that the metal (Ti) of the first sublayer is mostly bonded to the resin or filler of the first protective layer.

[0227] And the third peak (P3) may correspond to the intensity of C1s (carbon atoms). The third peak (P3) may indicate the existence of various chemical states of carbon.

[0228] And in an embodiment, the second peak (P2) may be greater or less than the third peak (P3). That is, either the second peak (P2) or the third peak (P3) may have the greatest intensity at a binding energy of 0 (eV) to 1200 (eV) other than the first peak (P1). For example, the second peak (P2) may have the greatest intensity at a binding energy of 0 (eV) to 1200 (eV) other than the first peak (P1).

[0229] Alternatively, the third peak (P3) may have a greater intensity than the second peak (P2), and may have the greatest intensity at a binding energy of 0 (eV) to 1200 (eV) other than the first peak (P1). At this time, the third peak (P3) may have a greater intensity than the second peak (P2) due to surface contamination, etc. At the interface exposed to air, organic compounds or hydrocarbon-based contaminants exist, which may cause the third peak (P3), which is a C1s peak, to have a greater intensity than the second peak (P2). In addition, depending on the area or location according to XPS analysis, carbon atoms of the carbon-based first protective layer may be predominantly analyzed.

[0230] Referring to FIG. 15, when the XPS analysis is performed on the lower surface of the first sub-layer or bump portion exposed after the first protective layer is removed by etching, the circuit board may have a fourth peak (P4) having the highest intensity at a binding energy of 400 (eV) to 600 (eV) in the XPS spectrum. And the circuit board may have a fifth peak (P5) having the highest intensity at a binding energy of 400 (eV) to 500 (eV) in the XPS spectrum. Furthermore, the circuit board may have a sixth peak (P6) having the highest intensity at a binding energy of 200 (eV) to 400 (eV) in the XPS spectrum. The fourth peak (P4) may be greater than the fifth peak (P5). The fourth peak (P4) and the fifth peak (P5) may be larger than the sixth peak (P6). The fourth peak (P4) may correspond to the intensity of O1s (oxygen atoms). The fifth peak (P5) may correspond to the intensity of Ti2P3 (titanium atoms). The sixth peak (P6) may correspond to the intensity of C1s (carbon atoms).

[0231] When the XPS analysis is performed on the surface (top surface) of the first protective layer exposed after removal of the bump portion by separation or etching, the circuit board may have a seventh peak (P7) having the highest intensity at a binding energy of 200 (eV) to 400 (eV) among a binding energy of 200 (eV) to 1200 (eV) in the XPS spectrum. And the circuit board may have an eighth peak (P8) having the highest intensity at a binding energy of 400 (eV) to 600 (eV) among a binding energy of 200 (eV) to 1200 (eV) in the XPS spectrum. The eighth peak (P8) may have the highest intensity excluding the seventh peak (P7) at a binding energy of 0 to 1200 (eV). Additionally, the circuit board may have a ninth peak (P9) having the greatest intensity at a binding energy of 400 eV to 500 eV among a binding energy of 200 eV to 1200 eV. The seventh peak (P7) may be greater than the eighth peak (P8). And the eighth peak (P8) may be greater than the ninth peak (P9). The ninth peak (P9) may have a greater binding energy than the seventh peak (P7) and a lower binding energy than the eighth peak (P8). That is, the ninth peak (9) may be located between the seventh peak (P7) and the eighth peak (P8). The eighth peak (P8) may correspond to an intensity for O1s (oxygen atoms). The ninth peak (P9) may correspond to an intensity for Ti2P3 (titanium atoms). The seventh peak (P7) may correspond to an intensity for C1s (carbon atoms).

[0232] In the embodiment, the fourth peak (P4) may be larger than the fifth peak (P5). And the fifth peak (P5) may be larger than the sixth peak (P6). Therefore, it can be seen that there are many different chemical bonds between titanium and oxygen rather than the protective layer due to the bonding of the bump portion with the first protective layer.

[0233] Table 4 shows the results of XPS Quantitative Analysis on the surface of the bump portion (BP) or the first sub-layer (L5) exposed after the first protective layer (SR1) is removed by etching or separation in a circuit board according to an embodiment. Atomic% can be calculated through correction values ​​such as sensitivity factors based on c / s. Accordingly, the relationship between the sizes of atoms according to c / s and atomic% can be the same or different. In other words, c / s and atomic% are related, but do not form a proportional relationship with each other.

[0234] Atomic% Classification O1sC1sTi2pNa1sCu2p3Example 51.229.617.51.7<0.1

[0235] Referring to Table 4, the atomic percentage of oxygen atoms (Atomic%) may be greater than the atomic percentages of carbon and titanium. In addition, the fifth peak (P5) may be greater than the sixth peak (P6), but the atomic percentage of carbon may be greater than the atomic percentage of titanium. However, the atomic percentage of carbon may be 1 to 2 times the atomic percentage of titanium. Table 5 shows the results of XPS Quantitative Analysis on the surface of the first protective layer (SR1) exposed after the bump portion (BP) is removed by etching or separation in the circuit board according to the embodiment.

[0236] Atomic% Classification O1sC1sTi2pNa1sCu2p3Example 74.224.90.80.1<.1

[0237] Referring to Table 5, the seventh peak (P7) is larger than the eighth peak (P8), but the atomic percentage of oxygen atoms (Atomic%) may be larger than the atomic percentages of carbon and titanium. Furthermore, the atomic percentage of carbon may be larger than the atomic percentage of titanium, and may be at least 15 times the atomic percentage of titanium. Furthermore, the atomic percentage of oxygen may be two to four times the atomic percentage of carbon. Fig. 17 is a graph of an XPS narrow spectrum and a depth profile for Ti2P3 of a bump portion after removal of a protective layer in a circuit board according to an embodiment, Fig. 18 is a graph of an XPS narrow spectrum and a depth profile for Ti2P3 of a protective layer after removal of a bump portion in a circuit board according to an embodiment, and Fig. 19 is a drawing explaining improvement in peel strength of a circuit board according to an embodiment. In particular, signal intensity (c / s) appears at binding energy 452 (eV) to 458 (eV) in the narrow spectrum for Ti2P3. Fig. 17 may be a result of analysis performed corresponding to 'SP1', and Fig. 18 may be a result of analysis performed corresponding to 'SP2'.

[0238] Here, the depth profile graph is a graph that shows how the concentration (or density) of an element changes in the depth direction of a sample or object. Through the depth profile graph, we can analyze how the elements are distributed from the surface to the inside of the sample depending on the sputtering time. In the depth profile graph, the X-axis represents the sputtering time (Sputter Time), which means the time that sputtering was performed. For example, the larger the X-axis, the deeper the layer is exposed on the surface of the sample or object. In other words, the X-axis can correspond to the depth of the sample. In addition, the Y-axis in the depth profile graph represents the density or concentration, which indicates the relative density or concentration of the element. For example, the higher the Y-axis value, the more the corresponding element exists at that depth. Table 6 is a table about chemical bonds and binding energy for Ti2P3.

[0239] Chemical bond Binding energy Ti453.7TiO454.8Ti2O3455.2TiO2457.6

[0240] Referring to Fig. 17, a graph of an XPS narrow spectrum and a depth profile for Ti2P3 of a bump portion after removal of a protective layer from a circuit board is shown. As shown in the graph, it can be seen that the closer to the bottom surface of the bump portion (BP), the more TiO2 among titanium oxides exists, and the closer to the top surface of the bump portion (BP) (the farther from the first protective layer), the more Cu exists. That is, the first region (T1), the second region (T2), and the third region (T3) may be regions that are sequentially farther away from the bottom surface of the bump portion (BP). Accordingly, the concentrations of Ti and O increase as they get closer to the bottom surface of the bump portion (BP) or the first protective layer, and in particular, the oxide of Ti exists in large quantities. Therefore, as described above, a circuit board with improved reliability can be provided due to the bonding strength due to oxidation between the protective layer and the bump portion. Fig. 18 is a graph of the XPS narrow spectrum and depth profile for Ti2P3 of the first protective layer after the removal of the bump portion in the circuit board according to the embodiment. As shown in the graph, it can be seen that the closer to the upper surface of the first protective layer (SR1), the more TiO2 or Ti2O3 among the titanium oxides are present. That is, the fourth region (T4), the second region (T5), and the sixth region (T6) may be regions that are sequentially farther away from the upper surface of the first protective layer. Accordingly, the concentration of Ti and O increases as they approach the upper surface of the first protective layer, and in particular, the oxide of Ti is present in large quantities. Therefore, as described above, a bond due to oxidation between the protective layer and the bump portion is formed in both the first protective layer and the bump portion, so that a circuit board with improved reliability can be provided. Referring to FIG. 19, it can be seen that the peel strength between the first protective layer and the bump portion is 0.3 kgf / cm2 or more compared to Comparative Examples 1, 2, and 3 (each performing plasma etching (CF4 / O2 / N2, MRF / MUP, N2) on the upper surface of the first protective layer).That is, the value for the adhesion between the first protective layer and the bump portion may be greater than the roughness direction through surface treatment on the surface of the first protective layer. Accordingly, separation between the first protective layer and the bump portion may be prevented, thereby improving the reliability of the circuit board.

[0241] Fig. 20 is an EDS (Energy Dispersive X-ray Spectroscopy) mapping image for each element on the upper surface of the protective layer and the lower surface of the bump portion in a circuit board according to an embodiment.

[0242] Energy Dispersive X-ray Spectroscopy (EDS) refers to equipment or technology that distinguishes each atom by utilizing the fact that each substance is composed of an atomic nucleus and electrons. For example, when an electron beam accelerated to several keV or more is irradiated on a magnetic material, electrons (e.g., K-shell electrons) (especially inner-shell electrons) that are orbiting in distinct orbits with principal quantum numbers such as K, L, and M can be knocked out by the electron beam. At this time, since it becomes an unstable excited state in terms of energy, energy can be released when an outer-shell electron (an electron that was in the next orbit (e.g., L-shell) or the orbit after that (e.g., M-shell) of the knocked-out inner-shell electron) enters the orbit (inner-shell electron, e.g., K-shell) that it was previously knocked out of in order to become a stable energy state. EDS detects elements by scanning this emitted energy (e.g., X-rays).

[0243] Referring to Fig. 20, it can be seen through EDS mapping that Ti, O, and Cu exist on the bottom surface (BS) of the bump portion (BP) (or the bottom surface of the first sub-layer (L5)). In particular, due to the presence of Ti and O, it can be seen that the metal (Ti) of the first sub-layer (L5) exists in combination with O of the first protective layer (SR1), as in the XPS analysis. Furthermore, it can be seen through EDS mapping that C, Si, Ba, O, S, and Ti exist on the top surface (US) of the first protective layer (SR1). Specifically, it can be seen that C, Si, Ba, O, S corresponding to the resin and filler, and Ti and O of the oxide exist on the top surface of the first protective layer (SR1). In particular, it can be seen that Ti exists in combination with O on the top surface (US) of the first protective layer (SR1) corresponding to the bottom surface of the bump portion (BP).

[0244] Fig. 21 is a drawing explaining a method for manufacturing a protective layer and a bump portion in a circuit board according to an embodiment.

[0245] First, the circuit board according to the embodiment may include a step of providing a core layer, a step of forming a cavity, a step of mounting a connecting member in the cavity, a step of laminating a build-up layer (insulating layer) and forming an electrode portion, a step of forming a protective layer and an opening in the protective layer, and a step of forming a bump portion and forming a metal layer. Except for the contents described below, the above-described contents may be applied to the description of each component. If there is no core layer, a build-up layer (insulating layer) may be provided and an electrode layer may be formed.

[0246] A build-up layer may be formed, and an electrode layer may be formed on the build-up layer. The electrode portion may be formed using a manufacturing process for printed circuit boards, such as an additive process, a subtractive process, a modified semi-additive process (MSAP), or a semi-additive process (SAP). In addition, the wiring pattern may be formed using a dry film, etc.

[0247] The protective layer can be formed on the upper build-up layer and the lower build-up layer, respectively. The following description will be based on the formation of the first protective layer (SR1) on the upper build-up layer.

[0248] Afterwards, a bump portion (BP) can be formed on the first protective layer (SR1). To form the bump portion (BP), a via hole can be formed in the first protective layer (SR1). The via hole can be formed by various drilling (laser, mechanical) and etching methods.

[0249] A first sub-layer (L5) and a second sub-layer (L6) can be sequentially deposited on the upper surface of the first protective layer (SR1) by sputtering without plasma etching. The first sub-layer (L5) and the second sub-layer (L6) can be a transition metal. As a result, as described above, the bonding strength between the first protective layer (SR1) and the bump portion can be improved. In particular, the bonding strength or adhesion between the first protective layers for a fine bump (a bump portion having a line width or line space of several microns or less) can be improved. The first sub-layer (L5) can be deposited to a thickness of 1 to 20 nm. And the second sub-layer (L6) can be deposited to a thickness of 200 nm or less. For example, the first sub-layer (L5) and the second sub-layer (L6) can be formed on the first protective layer (SR1) in the form of a film. At this time, an amorphous Ti oxide thin film may be formed by moisture adsorbed on the surface of the first protective layer (SR1) or residual oxygen in the vacuum chamber. Accordingly, the Ti seed layer, which is the first sub-layer, may exist in an oxide state and diffuse into the first protective layer (Sr1) and the second sub-layer (L6). Due to the anchoring effect, the reliability of the bump portion and the first protective layer may be improved. In addition, the third sub-layer (L7) may be formed by a method such as plating. As a result, the roughness of the interface on the upper surface of the first protective layer (SR1) due to plasma etching does not increase, so that signal loss can be minimized.

[0250] Fig. 22 is a cross-sectional view showing a semiconductor package according to the first embodiment, Fig. 23 is a cross-sectional view showing a semiconductor package according to the second embodiment, Fig. 24 is a cross-sectional view showing a semiconductor package according to the third embodiment, and Fig. 25 is a cross-sectional view showing a semiconductor package according to the fourth embodiment.

[0251] In the various semiconductor packages described below, the circuit board described above may be located in some area or may correspond to one substrate.

[0252] Referring to FIG. 22, the semiconductor package of the first embodiment may include a first substrate (1100), a second substrate (1200), and a semiconductor element (1300).

[0253] The first substrate (1100) may mean or include a 'package substrate' or a 'circuit substrate'. For example, the first substrate (1100) may provide a space to which at least one external substrate is coupled. The external substrate may mean a second substrate (1200) coupled on the first substrate (1100). In addition, the external substrate may mean a main board included in an electronic device coupled to a lower portion of the first substrate (1100).

[0254] Additionally, although not shown in the drawing, the first substrate (1100) can provide a space in which at least one semiconductor element is mounted.

[0255] The first substrate (1100) may include at least one insulating layer and an electrode portion disposed on at least one insulating layer.

[0256] A second substrate (1200) may be placed on the first substrate (1100).

[0257] The second substrate (1200) may be an interposer. For example, the second substrate (1200) may provide a space in which at least one semiconductor element is mounted. The second substrate (1200) may be connected to at least one semiconductor element (1300). For example, the second substrate (1200) may provide a space in which a first semiconductor element (1310) and a second semiconductor element (1320) are mounted. The second substrate (1200) may electrically connect the first semiconductor element (1310) and the second semiconductor element (1320), and electrically connect the first and second semiconductor elements (1310, 1320) and the first substrate (1100). That is, the second substrate (1200) may perform a horizontal connection function between a plurality of semiconductor elements and a vertical connection function between the semiconductor element and the package substrate.

[0258] In addition, although the above-described example illustrates two semiconductor elements (1310, 1320) being arranged on the second substrate (1200), the present invention is not limited thereto. For example, one semiconductor element may be arranged on the second substrate (1200), or alternatively, three or more semiconductor elements may be arranged.

[0259] A second substrate (1200) may be placed between at least one semiconductor element (1300) and the first substrate (1100).

[0260] In one embodiment, the second substrate (1200) may be an active interposer that functions as a semiconductor device. When the second substrate (1200) functions as a semiconductor device, the semiconductor package of the embodiment may have a vertically stacked structure on the first substrate (1100) and may function as a plurality of logic chips. Having the function of a logic chip may mean having the functions of an active device and a passive device. Unlike passive devices, the characteristics of current and voltage may not be linear in the case of an active device, and the active interposer may have the function of an active device. In addition, the active interposer may perform the function of a corresponding logic chip while performing a signal transmission function between the second logic chip disposed thereon and the first substrate (1100).

[0261] In another embodiment, the second substrate (1200) may be a passive interposer. For example, the second substrate (1200) may function as a signal relay between the semiconductor device (1300) and the first substrate (1100), and may have passive device functions such as a resistor, a capacitor, and an inductor. For example, the number of terminals in the semiconductor device (1300) is gradually increasing due to reasons such as 5G, the Internet of Things (IoT), increased image quality, and increased communication speed. That is, the number of terminals provided in the semiconductor device (1300) is increasing, and as a result, the width of the terminals or the spacing between the plurality of terminals is decreasing. At this time, the first substrate (1100) may be connected to the main board of the electronic device. Accordingly, in order for the electrodes provided on the first substrate (1100) to have a width and spacing for connection with the semiconductor element (1300) and the main board, respectively, there is a problem that the thickness of the first substrate (1100) increases or the layer structure of the first substrate (1100) becomes complicated. Therefore, in the first embodiment, a second substrate (1200) can be placed on the first substrate (1100) and the semiconductor element (1300). In addition, the second substrate (1200) can include electrodes having a micro width and spacing corresponding to the terminals of the semiconductor element (1300).

[0262] The semiconductor device (1300) may be a logic chip, a memory chip, etc. The logic chip may be a central processor (CPU), a graphics processor (GPU), etc. The memory chip may be a stack memory such as HBM.

[0263] Meanwhile, the semiconductor package of the first embodiment may include a connecting portion.

[0264] For example, a semiconductor package may include a first connection portion (1410) disposed between a first substrate (1100) and a second substrate (1200). The first connection portion (1410) may electrically connect the second substrate (1200) to the first substrate (1100) while bonding them thereto.

[0265] For example, the semiconductor package may include a second connection portion (1420) disposed between a second substrate (1200) and a semiconductor element (1300). The second connection portion (1420) may electrically connect the semiconductor element (1300) while bonding them to the second substrate (1200).

[0266] The semiconductor package may include a third connector (1430) disposed on the lower surface of the first substrate (1100). The third connector (1430) may electrically connect the first substrate (1100) to the main board while connecting them therebetween.

[0267] At this time, the first connection portion (1410), the second connection portion (1420), and the third connection portion (1430) can electrically connect the plurality of components using at least one bonding method among wire bonding, solder bonding, and direct metal-to-metal bonding. That is, since the first connection portion (1410), the second connection portion (1420), and the third connection portion (1430) have the function of electrically connecting the plurality of components, when direct metal-to-metal bonding is used, the semiconductor package can be understood as a part that is electrically connected rather than solder or wire.

[0268] The wire bonding method may refer to electrically connecting a plurality of components using a conductor such as gold (Au). In addition, the solder bonding method may electrically connect a plurality of components using a material including at least one of Sn, Ag, and Cu. In addition, the direct metal-to-metal bonding method may refer to directly bonding a plurality of components by applying heat and pressure between the plurality of components to recrystallize them without the use of solder, wires, conductive adhesives, etc. In addition, the direct metal bonding method may refer to a bonding method using a second connection portion (1420). In this case, the second connection portion (1420) may refer to a metal layer formed between the plurality of components by recrystallization.

[0269] Specifically, the first connection portion (1410), the second connection portion (1420), and the third connection portion (1430) can be bonded to each other by a thermal compression bonding method. The thermal compression bonding method may refer to a method of directly bonding the plurality of components by applying heat and pressure to the first connection portion (1410), the second connection portion (1420), and the third connection portion (1430).

[0270] At this time, in at least one of the first substrate (1100) and the second substrate (1200), the electrodes on which the first connection portion (1410), the second connection portion (1420) and the third connection portion (1430) are arranged may be provided with a protrusion that protrudes outward away from the insulating layer of the corresponding substrate. The protrusion may protrude outward from the first substrate (1100) or the second substrate (1200).

[0271] The protrusion may be referred to as a bump. The protrusion may also be referred to as a post. The protrusion may also be referred to as a pillar. Preferably, the protrusion may refer to an electrode on which a second connection portion (1420) for coupling with a semiconductor element (1300) is arranged among the electrodes of the second substrate (1200). That is, as the pitch of the terminals of the semiconductor element (1300) becomes finer, a short circuit may occur between the plurality of second connection portions (1420) that are respectively connected to the plurality of terminals of the semiconductor element (1300) by a conductive adhesive such as solder. Therefore, in the embodiment, thermal compression bonding may be performed to reduce the volume of the second connection portion (1420). Accordingly, the embodiment may include a protrusion in the electrode of the second substrate (1200) on which the second connecting portion (1420) is arranged to secure a degree of alignment, diffusion, and diffusion-preventing ability to prevent an intermetallic compound (IMC) formed between a conductive adhesive such as solder and the protrusion from diffusing into the interposer and / or the substrate.

[0272] Additionally, looking further into FIG. 22, the semiconductor package of the first embodiment may further include a connecting member (1210).

[0273] The connecting member (1210) may be referred to as a bridge substrate. For example, the connecting member (1210) may include a redistribution layer. The connecting member (1210) may have a function of horizontally electrically connecting a plurality of semiconductor devices to each other. For example, since the area that a semiconductor device should have is generally too large, the connecting member (1210) may include a redistribution layer. Since the semiconductor package and the semiconductor device have a large difference in the width or width of the circuit pattern, etc., a buffering function of the circuit pattern for electrical connection is required. The buffering function may mean having a size between the width or width of the circuit pattern of the semiconductor package and the width or width of the circuit pattern of the semiconductor device, and the redistribution layer may have a function of performing a buffering function.

[0274] In an embodiment, the connecting member (1210) may be an organic bridge. For example, the connecting member (1210) may include an organic material. For example, the connecting member (1210) may include an organic substrate instead of a silicon substrate. The connecting member (1210) may be embedded within the second substrate (1200).

[0275] To this end, the second substrate (1200) may include a cavity, and a connecting member (1210) may be placed within the cavity of the second substrate (1200). The connecting member (1210) may horizontally connect a plurality of semiconductor elements placed on the second substrate (1200).

[0276] Referring to FIG. 23, the semiconductor package of the second embodiment may include a second substrate (1200) and a semiconductor element (1300). At this time, the semiconductor package of the second embodiment may have a structure in which the first substrate (1100) is omitted compared to the semiconductor package of the first embodiment.

[0277] That is, the second substrate (1200) of the second embodiment can function as a package substrate while also functioning as an interposer.

[0278] The first connecting portion (1410) arranged on the lower surface of the second substrate (1200) can connect the second substrate (1200) to the main board of the electronic device.

[0279] Referring to FIG. 24, the semiconductor package of the third embodiment may include a first substrate (1100) and a semiconductor element (1300).

[0280] At this time, the semiconductor package of the third embodiment may have a structure in which the second substrate (1200) is omitted compared to the semiconductor package of the first embodiment.

[0281] That is, the first substrate (1100) of the third embodiment can function as a package substrate while also connecting a semiconductor element (1300) and a main board. To this end, the first substrate (1100) can include a connecting member (1110) for connecting a plurality of semiconductor elements. The connecting member (1110) can be an organic bridge connecting a plurality of semiconductor elements.

[0282] Referring to FIG. 25, the semiconductor package of the fourth embodiment may further include a third semiconductor element (1330) compared to the semiconductor package of the fourth embodiment. To this end, a fourth connecting portion may be further arranged on one surface of the first substrate (1100).

[0283] In this way, the semiconductor package of the fourth embodiment may have a structure in which semiconductor elements are mounted on the upper and lower sides, respectively. In this case, the third semiconductor element (1330) may have a structure in which it is placed on the lower surface of the second substrate (1200) in the aforementioned circuit board or semiconductor package.

[0284] And a connecting member (1110) can be embedded in the first substrate (1100). The connecting member (1110) can horizontally connect the first and second semiconductor elements (1310, 1320).

[0285] Additionally, the first substrate (1100) may include a conductive coupling portion (1450). The conductive coupling portion (1450) may further protrude from the first substrate (1100) toward the second semiconductor element (1320). The conductive coupling portion (1450) may be referred to as a bump, or alternatively, as a post. The conductive coupling portion (1450) may be positioned with a protruding structure on an electrode positioned on the uppermost side of the first substrate (1100).

[0286] A third semiconductor element (1330) may be placed on the conductive joint (1450). At this time, the third semiconductor element (1330) may be connected to the first substrate (1100) through the conductive joint (1450). In addition, a second connection (1420) may be placed between the first and second semiconductor elements (1310, 1320) and the third semiconductor element (1330).

[0287] Accordingly, the third semiconductor element (1330) can be electrically connected to the first and second semiconductor elements (1310, 1320) through the second connection portion (1420).

[0288] That is, the third semiconductor element (1330) can be connected to the first substrate (1100) through the conductive joint (1450), and can also be connected to the first and second semiconductor elements (1310, 1320) through the second connection (1420).

[0289] At this time, the third semiconductor element (1330) can receive a power signal and / or electric power through the conductive coupling portion (1450). In addition, the third semiconductor element (1330) can exchange communication signals with the first and second semiconductor elements (1310, 1320) through the second connection portion (1420).

[0290] The semiconductor package of the fourth embodiment can provide sufficient power for driving the third semiconductor element (1330) or enable smooth control of power operation by supplying a power signal and / or power to the third semiconductor element (1330) through the conductive coupling portion (1450).

[0291] Accordingly, the embodiment can improve the driving characteristics of the third semiconductor element (1330). That is, the embodiment can solve the problem of insufficient power provided to the third semiconductor element (1330). Furthermore, the embodiment can provide at least one of the power signal, power, and communication signal of the third semiconductor element (1330) through different paths via the conductive coupling portion (1450) and the second connection portion (1420). Through this, the embodiment can solve the problem of loss of the communication signal caused by the power signal. For example, the embodiment can minimize mutual interference between the power signal and the communication signal.

[0292] Meanwhile, the third semiconductor element (1330) in the fourth embodiment may have a POP (Package On Package) structure in which a plurality of package substrates are stacked and may be placed on the first substrate (1100). For example, the third semiconductor element (1330) may be a memory package including a memory chip. And the memory package may be coupled on the conductive joint (1450). At this time, the memory package may not be connected to the first and second semiconductor elements (1310, 1320).

[0293] Furthermore, the semiconductor package of the modified example may include the first substrate (1100) and first and second semiconductor elements (1310, 1320) arranged on the first substrate (1100) as in the above-described example. Furthermore, the semiconductor package may include a first connection portion (1410) arranged between the first substrate (1100) and the first and second semiconductor elements (1310, 1320). That is, the semiconductor package may have a structure in which the second substrate and the second connection portion are omitted in the above-described example.

[0294] Meanwhile, when a circuit board having the characteristics of the invention described above is used in IT devices such as smartphones, server computers, TVs, or home appliances, it can stably perform functions such as signal transmission or power supply. For example, when a circuit board having the characteristics of the invention performs a semiconductor package function, it can safely protect semiconductor chips from external moisture or contaminants, and can solve problems such as leakage current or electrical shorts between terminals, or electrical open circuits in terminals supplying semiconductor chips. Furthermore, when it performs a signal transmission function, it can solve noise problems. Through this, the circuit board having the characteristics of the invention described above can maintain the stable function of IT devices or home appliances, thereby enabling the entire product and the circuit board to which the invention is applied to achieve functional integration or technical interoperability with each other.

[0295] When a circuit board having the characteristics of the invention described above is used in a transportation device such as a vehicle, it can solve the problem of signal distortion transmitted to the transportation device, safely protect the semiconductor chip controlling the transportation device from external sources, and solve the problem of leakage current or electrical short circuit between terminals, or electrical open of the terminal supplying the semiconductor chip, thereby further improving the stability of the transportation device. Accordingly, the transportation device and the circuit board to which the present invention is applied can achieve functional integration or technical interoperability with each other.

[0296] The features, structures, effects, etc. described in the embodiments above are included in at least one embodiment, and are not necessarily limited to just one embodiment. Furthermore, the features, structures, effects, etc. exemplified in each embodiment can be combined or modified in other embodiments by those skilled in the art to which the embodiments pertain. Therefore, the contents related to such combinations and modifications should be construed as being included within the scope of the embodiments.

[0297] Although the above description focuses on examples, these are merely examples and are not intended to limit the examples. Those skilled in the art will appreciate that various modifications and applications not exemplified above are possible without departing from the essential characteristics of the present examples. For example, each component specifically shown in the examples can be modified and implemented. In addition, differences related to such modifications and applications should be interpreted as being included within the scope of the embodiments set forth in the appended claims.

Claims

1. Step of preparing an organic layer; A step of exposing the organic layer to a plasma gas including N2; A step of forming a metal layer on at least one of the upper and lower surfaces of the exposed organic layer; A step of forming a core layer made of glass on the metal layer; A step of separating the core layer and the metal layer from the organic layer; and A method for manufacturing a circuit board, comprising: forming a build-up layer and an electrode portion on the core layer.

2. In paragraph 1, A method for manufacturing a circuit board, wherein the vacuum level is set to 0.1 to 0.5 Torr and the temperature is set to 20 to 30°C in the step of exposing the organic layer to plasma gas including N2.

3. In paragraph 2, A method for manufacturing a circuit board, wherein in the step of exposing the organic layer to plasma gas including N2, the total flow rate of the plasma gas is controlled to be 1500 sccm or less, and the exposure time is less than 500 seconds.

4. In paragraph 1, A method for manufacturing a circuit board, wherein in the step of exposing the organic layer to the plasma gas including the N2, the plasma gas further includes at least one of Ar, O2, and CF4 in addition to the N2.

5. In paragraph 1, A method for manufacturing a circuit board in which the above-mentioned exposed organic layer has an amide bond structure.

6. In paragraph 5, A method for manufacturing a circuit board in which the above-mentioned exposed organic layer has a structure of HNC=O.

7. In paragraph 1, The step of separating the core layer and the metal layer from the organic layer is: A method for manufacturing a circuit board, comprising: a step in which a sub-organic layer, which is part of the organic layer, remains on the metal layer.

8. In paragraph 1, The peel strength between the organic layer and the metal layer is 0.1 kgf / cm 2 A method for manufacturing a circuit board having a thickness of less than 100 nm.

9. Core layer; A first wiring portion arranged on the upper and lower surfaces of the core layer; and An organic layer disposed on either the upper surface or the lower surface of the first wiring section; The above organic layer is a circuit board having an amide bond structure.

10. In paragraph 9, A circuit board in which the organic layer has a structure of HNC=O.

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