Method for selectively growing vertical two-dimensional material, vertical two-dimensional material layer formed thereby, and application of selectively grown two-dimensional material

Abstract

Provided are a method for selectively growing a vertical two-dimensional material, a vertical two-dimensional material layer formed thereby, and an application of the selectively grown two-dimensional material. A method for selectively growing a vertical two-dimensional material according to an embodiment includes forming a stacked structure in which a selection material layer providing a growth region and a non-selection material layer providing a non-growth region are stacked adjacent to each other on a substrate, wherein at least a portion of a side surface of each of the selection material layer and the non-selection material layer is exposed, and a two-dimensional material layer is selectively grown on the exposed side surface of the selection material layer.

Description

Method for selectively growing vertical two-dimensional materials, vertical two-dimensional material layers formed thereby, and applications of selectively grown two-dimensional materials

[0001] The present invention relates to a method for selectively growing a vertical two-dimensional material, a vertical two-dimensional material layer formed thereby, and applications of the selectively grown two-dimensional material.

[0002] In the semiconductor field, semiconductor miniaturization is progressing to realize high-performance, highly integrated devices. Existing semiconductor devices using silicon as the channel material suffer from the short-channel effect at fine linewidths. To address this, research is underway to structurally improve these devices and explore alternative materials for silicon. Specifically, technologies are being developed to form channels perpendicular to the substrate, such as FIN-FETs and V-FETs, thereby achieving high integration. Furthermore, two-dimensional materials are being studied as alternatives to silicon.

[0003] Two-dimensional materials are being studied for their unique optical and electrical properties in a variety of applications, and various growth and deposition methods are being developed. TMDs, as two-dimensional materials, maintain stability even at nanoscale thicknesses.

[0004] Prior art documents 1 and 2 provide FIN-FET structures that utilize 2D materials grown vertically on a substrate as channels. Prior art document 1 provides a vertical 2D material by growing TMD flakes on a Si step edge, patterning them, and removing the Si to leave only the TMDs formed on the sidewalls, thereby providing a FIN-FET structure that utilizes this vertical 2D material as a channel. However, prior art document 1 has the disadvantage of requiring numerous process steps to leave the vertical 2D material.

[0005] Unlike prior art document 1, prior art document 2 utilizes ledge-guided epitaxial growth, which allows for a shorter process for forming complex structures such as step edges. However, it has the disadvantage of requiring the use of a diamond scraper to form the steps on the substrate.

[0006] For the mass production and industrial application of two-dimensional materials such as TMDs, compatibility with the mass production processes of existing semiconductor devices is necessary, and there is the challenge of improving the crystallinity of TMDs. Conventional techniques for forming TMDs are difficult to grow on a large area, require high processing temperatures, and can cause misalignment due to physical surface treatment and physical transport. Furthermore, they require expensive substrates such as sapphire and are difficult to stack on amorphous layers. In particular, among various growth / deposition methods, techniques such as chemical vapor deposition (CVD), metalorganic chemical vapor deposition (MOCVD), and atomic layer deposition (ALD) have been proposed for industrial applications due to their high compatibility with the mass production processes of existing semiconductor devices. However, improvements in nucleation control and growth control techniques are necessary to form large-area, highly uniform thin films.

[0007] Recently, nucleation / growth control technologies utilizing selective thin film growth based on the substrate material and its shape have been reported. In addition to nucleation and growth control, selective growth offers the advantages of shortening the process, eliminating PR residue (since it does not use photoresist), and eliminating misalignment.

[0008] However, prior art techniques that present selective growth techniques place significant limitations on the types of materials and pattern sizes that can be selectively grown. For example, prior art document 3 uses a mask to form trenches surrounded by all sides, but the maximum horizontal dimension of each trench is limited to 2 µm. Furthermore, the technique of prior art document 3 makes it extremely difficult to form 2D materials vertically on the substrate.

[0009] Prior Literature 1. A FIN-FET with one atomic layer channel (Nature Communications 11, Article number: 1205 (2020))

[0010] Prior literature 2. Integrated 2D multi-fin field-effect transistors (Nature Communications 15, Article number: 3622 (April 29, 2024))

[0011] Prior Document 3. U.S. Patent Application Publication No. US2024 / 0071759 A1 (February 29, 2024)

[0012] The problem to be solved by the present invention is to provide a new method capable of selectively growing a two-dimensional material layer perpendicular to a substrate.

[0013] Another problem that the present invention seeks to solve is to provide a method for forming a vertical two-dimensional material layer that can simplify the process.

[0014] Another problem that the present invention seeks to solve is to provide a method for forming a vertical two-dimensional material layer that can apply a growth process compatible with the mass production process of semiconductor devices.

[0015] Another problem to be solved by the present invention is to provide a vertical two-dimensional material layer formed by the above method and its application.

[0016] According to one embodiment of the present invention, a method for selectively growing a vertical two-dimensional material is provided. The method comprises forming a laminated structure in which a selective material layer providing a growth region and a non-selective material layer providing a non-growth region are laminated adjacent to each other on a substrate, wherein at least a portion of each side surface of the selective material layer and the non-selective material layer is exposed, and selectively growing a two-dimensional material layer on the exposed side surface of the selective material layer.

[0017] In one embodiment, the laminated structure may include a layer of selective material disposed between two layers of non-selective material.

[0018] The above-described laminated structure may have a plurality of selective material layers and a plurality of non-selective material layers alternately laminated with each other, and the two-dimensional material layers may be grown on each sidewall of the plurality of selective material layers.

[0019] In one embodiment, the thickness of the selective material layer may be greater than the thickness of the non-selective material layer.

[0020] The above-described selective material layer and non-selective material layer may each be formed as an oxide film, a nitride film, or an oxynitride film, and at least one of the elements, composition ratio, or deposition method of the selective material layer is different from the elements, composition ratio, or deposition method of the non-selective material layer.

[0021] The above-mentioned selected or non-selected material may be selected from the group consisting of AlOx, SiNx, SiOx, TiNx, TiOx, AlNx, MoOx, SiOxNy, TiOxNy, AlOxNy, HfOx, ZrOx, TaOx, TaNx, TaOxNy, FeOx, LaOx.

[0022] In one embodiment, the selected material may be SiOx SiNx, AlOx, HfOx, or mixtures thereof, and the non-selected material may be SiOx, HfOx, ZrOx, FeOx, or mixtures thereof.

[0023] The above two-dimensional material layer may include a transition metal dichalcogenide (TMD) film.

[0024] The above TMD film can be grown using a chemical vapor deposition technique or an atomic layer deposition technique using a transition metal precursor and a chalcogen precursor.

[0025] The above deposition technique can further utilize a catalyst.

[0026] The above laminated structure may include a cavity penetrating the selective material layer and the non-selective material layer, and the selective material layer may be grown on an inner surface of the selective material layer exposed within the cavity.

[0027] The above two-dimensional material layer may be a single crystal.

[0028] According to one embodiment of the present invention, a vertical two-dimensional material layer is provided. The vertical two-dimensional material layer is selectively grown on at least a portion of a side surface of the selective material layer in a laminated structure in which a selective material layer and a non-selective material layer are laminated adjacent to each other in the thickness direction.

[0029] The above laminated structure may include a selective material layer disposed between two non-selective material layers.

[0030] The above-described laminated structure may have a plurality of selective material layers and a plurality of non-selective material layers that are alternately laminated, and the vertical two-dimensional material layers may be grown on each side wall of the plurality of selective material layers.

[0031] According to one embodiment of the present invention, a semiconductor device including the above-described vertical two-dimensional material layer is provided.

[0032] In one embodiment, the two-dimensional material layer may be a channel layer.

[0033] In one embodiment, the two-dimensional material layer may be a bonding layer, a contact layer, a contact liner, or a diffusion barrier layer.

[0034] In one embodiment, the two-dimensional material layer may be a seed layer or a lattice constant tuning layer.

[0035] In one embodiment, the two-dimensional material layer may be an etching protection layer.

[0036] In one embodiment, the two-dimensional material layer may be a charge trap layer of a CTF (Charge Trap Flash) cell.

[0037] In one embodiment, the semiconductor device may be an optical device that emits light.

[0038] According to embodiments of the present invention, a vertical two-dimensional material layer can be formed through a simple process, and thus, the two-dimensional material layer can be easily applied to various fields such as optical devices and semiconductor devices.

[0039] Figure 1 is a schematic diagram illustrating a two-dimensional material layer growth device according to one embodiment of the present invention.

[0040] FIGS. 2A and 2B are schematic perspective views illustrating a method for selectively growing a vertical two-dimensional material layer according to one embodiment of the present invention.

[0041] FIG. 2c is a schematic cross-sectional view illustrating a method for selectively growing a vertical two-dimensional material layer according to another embodiment of the present invention.

[0042] FIG. 3a is a schematic plan view illustrating a FIN-FET according to one embodiment of the present invention.

[0043] FIGS. 3b to 3d are schematic cross-sectional views illustrating a method for manufacturing a FIN-FET according to one embodiment of the present invention.

[0044] FIGS. 4A to 4C are schematic cross-sectional views illustrating a method for manufacturing a V-FET according to one embodiment of the present invention.

[0045] FIG. 5a is a schematic plan view illustrating a NS-FET (Nanosheet Field-Effect Transistor) according to one embodiment of the present invention.

[0046] FIGS. 5b to 5d are schematic cross-sectional views illustrating a method for manufacturing an NS-FET according to one embodiment of the present invention.

[0047] FIGS. 6A and 6B are schematic cross-sectional views illustrating an anisotropic etching technique using a vertical two-dimensional material layer as an etching protection layer according to one embodiment of the present invention.

[0048] FIGS. 7A and 7B are schematic cross-sectional views illustrating another etching technique using a vertical two-dimensional material layer as an etching protection layer according to one embodiment of the present invention.

[0049] FIGS. 8A and 8B are schematic cross-sectional views illustrating an example of a semiconductor device using a vertical two-dimensional material layer as a contact layer according to one embodiment of the present invention.

[0050] FIGS. 9A and 9B are schematic cross-sectional views illustrating a DG-FET (Double Gate Field-Effect Transistor) using a vertical two-dimensional material layer as a band alignment layer according to one embodiment of the present invention.

[0051] FIGS. 10A to 10E are schematic cross-sectional views (FIGS. 10A to 10D) and plan views (FIG. 10E) for explaining a method of manufacturing a transistor using a vertical two-dimensional material layer as a seed layer according to one embodiment of the present invention.

[0052] FIGS. 11A to 11E are schematic cross-sectional views illustrating a method for manufacturing a CTF (Charge Trap Flash) cell according to one embodiment of the present invention.

[0053] FIG. 11f is a schematic cross-sectional view illustrating a modified example of a CTF (Charge Trap Flash) cell according to one embodiment of the present invention.

[0054] FIGS. 12A to 12D are schematic cross-sectional views illustrating a method for manufacturing a semiconductor device using a vertical two-dimensional material layer as a diffusion barrier layer according to one embodiment of the present invention.

[0055] FIGS. 13A to 13C are schematic cross-sectional views illustrating a method of manufacturing an optical element using a vertical two-dimensional material layer as a seed layer according to one embodiment of the present invention.

[0056] FIGS. 14A to 14C are SEM images showing TMDs grown in various laminated structures according to embodiments of the present invention.

[0057] Hereinafter, embodiments of the present invention will be described in detail with reference to the attached drawings. The embodiments introduced below are provided as examples so that the spirit of the present invention can be sufficiently conveyed to those skilled in the art to which the present invention pertains. Therefore, the present invention is not limited to the embodiments described below and may be embodied in other forms. In addition, in the drawings, the width, length, thickness, etc. of components may be expressed in an exaggerated manner for convenience. In addition, when one component is described as being "over" or "on" another component, it includes not only cases where each part is "directly over" or "directly on" the other part, but also cases where another component is interposed between each component and another component. Like reference numbers represent like components throughout the specification.

[0058] FIG. 1 is a schematic diagram illustrating a growth device (100) according to one embodiment of the present invention. The growth device (100) may be a metalorganic chemical vapor deposition (MOCVD) device, but is not particularly limited thereto, and may also be another chemical vapor deposition device or an atomic layer deposition device. The drawing illustrates the use of a horizontal flow space, but is not particularly limited thereto. For example, it may be a vertical flow space using a showerhead method. Furthermore, the drawing illustrates a single-wafer method, but is not particularly limited thereto. For example, multiple substrates may be processed simultaneously in a batch-type method. An MOCVD device can provide a large quantity of two-dimensional materials, making it suitable for industrial applications. Hereinafter, the growth device (100) will be described using an MOCVD device as an example. In addition, while transition metal dichalcogenide (TMD) is described below as a two-dimensional material, the two-dimensional material in embodiments of the present invention is not limited to TMD, and may include graphene, h-BN, or black phosphorus.

[0059] Referring to FIG. 1, the growth device (100) may include a chamber (11), a gas inlet (13), and a gas outlet (15).

[0060] The chamber (11) provides a sealed space for TMD growth. The interior of the chamber (11) can be evacuated using a vacuum pump. During the reaction, the interior of the chamber (11) can maintain a constant temperature and pressure. The chamber (11) has a mounting platform for placing a wafer (20), and the mounting platform includes a heater to heat the wafer (20).

[0061] A wafer (20) having a growth region defined within a chamber (11) is placed. As illustrated in FIG. 2A, the wafer (20) has a laminated structure in which a non-selective material layer (21) providing a non-growth region and a selective material layer (23) providing a growth region are laminated. The wafer (20) may also include a base substrate supporting the laminated structure, and other layers may be placed between the base substrate and the laminated structure.

[0062] As illustrated in FIG. 2A, a plurality of non-selective material layers (21) and a plurality of selective material layers (23) may be alternately arranged. The order in which the non-selective material layers (21) and the selective material layers (23) are laminated is not particularly limited. In addition, the laminated structure may include only one non-selective material layer (21) and one selective material layer (23), or may be a structure in which one selective material layer (23) is arranged between two non-selective material layers (21). In some embodiments, all of the selective material layers (23) may be arranged between two non-selective material layers (21).

[0063] In embodiments of the present invention, a laminated structure may be formed by laminating a non-selective material layer and a selective material layer on a base substrate using a deposition technique, and then exposing a side surface through a patterning process. The laminated structure may be formed, for example, in an island type within a wafer, and the side surface of the laminated structure may be exposed. A plurality of laminated structures may be provided within the wafer, and these laminated structures may have the same or different shapes. The laminated structure may have a hexahedral shape as illustrated in FIG. 2A, but is not limited thereto, and may have various shapes. For example, it may have a cavity inside, or it may have an uneven surface on the surface. In some embodiments, the side surface of the laminated structure may be entirely exposed, but is not limited thereto, and a portion of the side surface may be exposed.

[0064] The exposed sides of the selective material layer (23) and the non-selective material layer (21) may be arranged parallel to each other on the same surface, but are not necessarily limited thereto, and either the selective material layer (23) or the non-selective material layer (21) may have a shape that is at least partially protruding or recessed.

[0065] In one embodiment, the thickness of the selective material layer may be about 20 nm or more and about 10 μm or less. Preferably, the thickness of the selective material layer may be about 50 nm or more and about 5 μm or less. In one embodiment, the thickness of the selective material layer (23) may be greater than the thickness of the non-selected material layer (21). By making the thickness of the selective material layer (23) greater than the thickness of the non-selected material layer (21), selective growth in the selective material layer (23) can be assisted. However, the present invention is not limited thereto, and the thickness of the non-selected material layer (21) may be greater than the thickness of the non-selected material layer (23).

[0066] Various gas sources (13a, 13b, 13c, 13d) including transition metal precursors are connected to the gas inlet (13). For example, the first gas source (13a) may be a transition metal precursor, the second gas source (13b) may be a chalcogen precursor, the third gas source (13c) may be a carrier gas, and the fourth gas source (13d) may be a promoter and / or an oxidizer. The gas sources are not limited to these, and may further include other gas sources, such as a reducing agent, or the fourth gas source may not be supplied.

[0067] Examples of transition metal precursors include transition metal oxides, transition metal halides, transition metal oxyhalides, and transition metal carbonyls, and chalcogen precursors include at least one of chalcogen elements such as S, Se, and Te, and examples thereof include sulfur powder, selenium powder, tellurium powder, hydrogen sulfide, hydrogen selenide, hydrogen telluride, (C2H5)2S, (CH3)2Se, (CH3)2S2, (CH3)2Se2, and the like. Transition metal precursors and chalcogen precursors may further include precursor materials of doping elements. Meanwhile, the promoter may be an organic metal promoter, an inorganic metal promoter, a halogen gas, or a halide compound. For example, sodium propionate (SP) is preferred as a promoter because it has a high vapor pressure, a low decomposition temperature, and is harmless with no residual byproducts. Meanwhile, Ar, N2, H2, etc. can be used as carrier gases, and O2 can be used as oxidizers, but are not limited to these.

[0068] Gases are introduced into the chamber (11) through the gas inlet (13), and after the gases react within the chamber (11), gases containing reaction by-products are discharged through the gas outlet (15).

[0069] The lower the TMD growth temperature, the more advantageous it is for industrial applications, and in embodiments of the present invention, the growth temperature may be, for example, lower than 750°C. The lower limit of the TMD growth temperature may be limited by the supply method of precursors, decomposition temperature, type of promoter, etc., and may further vary depending on the types of the non-selective material layer (21) and the selective material layer (23) used for selective growth. In embodiments of the present invention, the TMD growth temperature may be, for example, 300°C or higher, and further, 400°C or higher.

[0070] The pressure within the chamber for TMD growth may vary depending on the type of TMD, for example, within the range of 0.1 to 700 torr, further within the range of 1 to 100 torr, and further within the range of 3 to 10 torr.

[0071] FIGS. 2A and 2B are schematic perspective views illustrating a method for selectively growing a vertical two-dimensional material layer according to one embodiment of the present invention.

[0072] Referring to Fig. 2a, first, a laminated structure is formed in which a non-selective material layer (21) and a selective material layer (23) are laminated adjacent to each other. The laminated structure can be formed using deposition and patterning techniques. For example, after laminating a non-selective material layer (21) and a selective material layer (23) on a base substrate, a hexahedral-shaped laminated structure can be formed through a patterning process, as illustrated in Fig. 2a. As described above, the shape of the laminated structure is not limited to a hexahedral shape and may vary.

[0073] In the laminated structure, the side surfaces of each of the selective material layer (23) and the non-selective material layer (21) are at least partially exposed. In particular, the selective material layer (23) may be entirely exposed, but may also be partially exposed. For example, a material layer similar to the non-selective material layer (21) may be additionally formed to partially cover the selective material layer (23), thereby partially covering the side surfaces of the selective material layer (23).

[0074] In one embodiment, the laminated structure can be formed on a base substrate (not shown), and a plurality of laminated structures can be formed together on the base substrate through the same process.

[0075] The non-selective material layer (21) is a material layer on which a two-dimensional material is not grown, and the selective material layer (23) is a material layer on which a two-dimensional material is selectively grown. The selective material layer (23) and the non-selective material layer (21) are set according to the relative difference in selectivity, and a specific material layer may be a selective material layer or a non-selective material layer depending on the relative material layer. The selective material layer (23) and the non-selective material layer (21) may be formed as an oxide film, a nitride film, or an oxynitride film, respectively, and at least one of the elements, composition ratio, or deposition method of the selective material layer (23) may be different from the elements, composition ratio, or deposition method of the non-selective material layer (21). The selected or non-selected material may be selected from the group consisting of AlOx, SiNx, SiOx, TiNx, TiOx, AlNx, MoOx, SiOxNy, TiOxNy, AlOxNy, HfOx, ZrOx, TaOx, TaNx, TaOxNy, FeOx, LaOx.

[0076] For example, the selected material may be SiOx SiNx, AlOx, HfOx, or mixtures thereof, and the non-selected material may be SiOx, HfOx, ZrOx, FeOx, or mixtures thereof.

[0077] Here, x and y are intended to include cases where the stoichiometric ratio is not correct, and can have values ​​within the range of about 0.1 to about 5, respectively. When the stoichiometric ratio is correct, the above materials can be expressed as, for example, SiO2, Si3N4, Al2O3, ZrO2, HfO2, etc.

[0078] Referring to FIG. 2B, a two-dimensional material layer (25), for example, a TMD film, is grown on the exposed surface of the selective material layer (23). Under the growth conditions of the TMD film, the two-dimensional material layer (25) is selectively grown on the selective material layer (23) and is not grown on the non-selected material layer (21). The two-dimensional material layer (25) selectively grown on the side surface of the selective material layer (23) has a shape whose height is greater than its thickness. The side surface of the selective material layer (23) is arranged to be inclined with respect to the base substrate, and therefore, the two-dimensional material layer (23) formed on the side surface of the selective material layer (23) is also formed to be inclined with respect to the base substrate. In the present specification, the two-dimensional material layer (25) grown to be inclined with respect to the base substrate is referred to as a “vertical two-dimensional material layer.” The vertical two-dimensional material layer is not limited to being perfectly perpendicular to the base substrate, and refers to a two-dimensional material layer formed on the side surface of the selective material layer (23). Additionally, in this specification, the “side” of the selection material layer (23) may be a side exposed to the outside of the laminated structure, or, if a cavity is formed in the laminated structure, may be an inner wall surface exposed to the inside of the cavity, i.e., an inner side.

[0079] FIG. 2c is a schematic cross-sectional view illustrating a method for selectively growing a vertical two-dimensional material layer according to another embodiment of the present invention.

[0080] The laminated structure in this specification can be modified in various ways. For example, referring to FIG. 2c, the non-selected material layer (21) can be in contact with the lower side of the selective material layer (23) and cover a portion of the side. For example, the non-selected material layer (21) can surround the lower side of the selective material layer (23). In addition, the non-selected material layer (21') can cover the upper surface of the selective material layer (23). The non-selected material layer (21) and the non-selected material layer (21') can be the same material or different materials.

[0081] The side of the selective material layer (23) is exposed on top of the non-selective material layer (21), and a two-dimensional material layer (25) can be grown on the exposed side of the selective material layer (23).

[0082] A two-dimensional material layer (25) can be grown by supplying a precursor of a two-dimensional material into a chamber of a growth device. To this end, a transition metal and chalcogen precursor are supplied into the chamber of the growth device. For example, a transition metal and chalcogen precursor can be supplied into the chamber to grow a TMD film. In one embodiment, the transition metal and chalcogen precursor may be an organic material. The precursor can be introduced into the chamber of the growth device using a carrier gas. Along with the precursor, a promoter and an oxidizer, etc., can also be introduced into the chamber.

[0083] In embodiments of the present invention, a two-dimensional material layer (25) can be grown on a selective material layer (23) by using a stacked structure of a non-selective material layer (21) and a selective material layer (23) without forming a separate layer such as a seed layer. Therefore, the process can be simplified compared to a selective growth technique that requires a seed layer.

[0084] Furthermore, in embodiments of the present invention, the two-dimensional material layer (25) is selectively grown on the side of the selective material layer (23), and thus is formed in a shape perpendicular to the substrate. That is, according to embodiments of the present invention, since a two-dimensional material layer parallel to the substrate is not formed during the growth step, a process for etching it is not required.

[0085] The grown two-dimensional material layer (25) may be a single layer, a double layer, or a triple layer. In addition, the grown two-dimensional material layer (25) may be a single crystal or a polycrystalline layer. In a specific embodiment, the grown two-dimensional material layer (25) is a single crystal. A multilayer TMD film can be grown by controlling the growth time, and when the TMD film is used as a channel layer of a transistor, the TMD film may be three or fewer layers as a semiconductor.

[0086] Accordingly, a wafer having a TMD film formed thereon that can be applied to various fields can be provided, and semiconductor devices having various structures can be provided using the TMD film on the wafer. Hereinafter, various application examples using a vertical two-dimensional material layer (25) will be described with reference to the drawings.

[0087] FIG. 3A is a schematic plan view illustrating a FIN-FET according to one embodiment of the present invention, and FIGS. 3B to 3D are schematic cross-sectional views illustrating a method of manufacturing a FIN-FET according to one embodiment of the present invention. FIGS. 3B to 3D are drawings corresponding to cross-sections taken along the cutting line A-A' of FIG. 3A.

[0088] First, referring to FIGS. 3A and 3D, a FIN-FET according to an embodiment of the present invention may include a two-dimensional material layer (25), a gate dielectric layer (27), a source (S), a drain (D), and a gate (G). The FIN-FET may be placed on a base substrate, and a detailed description of the base substrate will be omitted.

[0089] A two-dimensional material layer (25) is used as a channel layer. The two-dimensional material layer (25) has a fin shape. That is, the width in one direction (corresponding to the thickness of the two-dimensional material layer (25)) is smaller than the height. The gate dielectric layer (27) covers both sides and the upper surface of the two-dimensional material layer (25). The gate dielectric layer (27) can be formed of a high-k material. For example, HfO2 can be used as the gate dielectric layer (27).

[0090] A source (S) and a drain (D) are in contact with each other at both ends in the longitudinal direction of the two-dimensional material layer (25), and a gate (G) is placed on top of a gate dielectric layer (27) between the source (S) and the drain (D).

[0091] Since the FIN-FET structure is generally well known, further detailed description is omitted, and a FIN-FET manufacturing method according to one embodiment of the present invention is briefly described.

[0092] First, referring to FIG. 3b, a laminated structure is provided in which a non-selective material layer (21) is laminated on a selective material layer (23). The upper surface of the selective material layer (23) is covered with the non-selective material layer (21), and the lower surface of the selective material layer (23) is disposed on a base substrate or another base film. Accordingly, only the side surface of the selective material layer (23) is exposed to the outside. The entire side surface of the selective material layer (23) may be exposed, or may be partially exposed.

[0093] Next, a two-dimensional material layer (25) is grown on the side of the selection material layer (23). The two-dimensional material layer (25) can be grown using the organic chemical vapor phase growth apparatus described above, but the present invention is not limited thereto.

[0094] The two-dimensional material layer (25) is selectively grown on the selective material layer (23). Therefore, the two-dimensional material layer (25) is selectively grown on the side of the selective material layer (23) exposed to the outside, and is not grown on the non-selected material layer (21).

[0095] Referring to FIG. 3C, the non-selected material layer (21) and the selective material layer (23) are removed. The non-selected material layer (21) and the selective material layer (23) can be removed, for example, using a wet etching technique. Accordingly, a vertical two-dimensional material layer (25) remains on the base film. A portion of the grown two-dimensional material layer (25) may be removed through a patterning process before or after removing the non-selected material layer (21) and the selective material layer (23). In another embodiment, the process of removing the grown two-dimensional material layer (25) may be omitted by pre-patterning the selective growth region of the two-dimensional material layer (25).

[0096] In one embodiment, a two-dimensional material layer (25) grown along both sides of the selection material layer (23) may remain. Accordingly, two two-dimensional material layers (25) are arranged parallel to each other in a pin shape.

[0097] Referring to FIG. 3d, a gate dielectric layer (27) covering a two-dimensional material layer (25) is formed. The gate dielectric layer (27) can cover both side surfaces and the upper surface of the two-dimensional material layer (25), except for the area for contacting the source (S) and drain (D).

[0098] Next, a source (S) and a drain (D) connected to both ends of the two-dimensional material layer (25) and a gate (G) crossing the upper portion of the two-dimensional material layer (25) between the source (S) and the drain (D) are formed. The source (S), the drain (D), and the gate (G) may be formed together in the same process or may be formed through different processes.

[0099] At least a portion of the source (S) and drain (D) or a portion of the gate dielectric layer (27) may be pre-formed prior to the wet etching described with reference to FIG. 3c to support the two-dimensional material layer.

[0100] According to this embodiment, a FIN-FET using a vertical two-dimensional material layer (25) as a channel layer can be formed.

[0101] FIGS. 4A to 4C are schematic cross-sectional views illustrating a method for manufacturing a V-FET according to one embodiment of the present invention.

[0102] Referring to FIG. 4a, a layered structure is provided in which a source (S) is first formed on a base substrate or a base film, and a selection material layer (23) and a non-selection material layer (21) are layered thereon. The width of the selection material layer (23) may be smaller than that of the source (S), and an exposed side surface of the selection material layer (23) may be recessed inwardly relative to a side surface of the source (S).

[0103] Next, a two-dimensional material layer (25) is selectively grown on the exposed side of the selective material layer (23). The selectively grown two-dimensional material layer (25) can be connected to the source (S) as illustrated in Fig. 4a. The two-dimensional material layer (25) can be formed on both sides of the selective material layer (23).

[0104] Referring to FIG. 4b, the non-selective material layer (21) and the selective material layer (23) are removed, and a dielectric layer (35) is formed between the two-dimensional material layers (25). The dielectric layer (35) can fill part or all of the area between the two-dimensional material layers (25).

[0105] Next, a drain (D) may be formed on the two-dimensional material layer (25) and the dielectric layer (35). Although the source (S) is described as being formed first and the drain (D) later, the order of these may be reversed. That is, the drain (D) may be formed first and the source (S) may be formed later.

[0106] Referring to FIG. 4c, a dielectric layer (37) covering the exposed side surface including the outer surface of the two-dimensional material layer (25) may be formed, and then a gate (G) may be formed. The gate (G) may be formed inside the dielectric layer (35). In one embodiment, the gate (G) may be formed in a horizontal direction as shown in FIG. 4c and may be arranged close to at least two sides or three sides of the two-dimensional material layer (25). A dielectric layer (35) or a dielectric layer (37) may be arranged between the two-dimensional material layer (25) and the gate (G). In another embodiment, the gate (G) may be formed to have a double gate structure by being arranged inside the dielectric layer (35) and outside the dielectric layer (37), respectively. A dielectric layer (35) may be placed between a gate placed inside the dielectric layer (35) and a two-dimensional material layer (25), and a dielectric layer (37) may be placed between a gate placed outside the dielectric layer (37) and a two-dimensional material layer (25).

[0107] According to the present embodiment, a V-FET can be provided in which a two-dimensional material layer (25) is used as a channel layer. In the present embodiment, the dielectric layer (35) and the dielectric layer (37) can be used as a gate dielectric layer.

[0108] FIG. 5a is a schematic plan view illustrating a NS-FET (Nanosheet Field-Effect Transistor) according to one embodiment of the present invention, and FIGS. 5b to 5d are schematic cross-sectional views illustrating a method of manufacturing an NS-FET according to one embodiment of the present invention. FIGS. 5b to 5d are drawings corresponding to cross-sections taken along the cutting line A-A' of FIG. 5a.

[0109] First, referring to FIGS. 5A and 5D, the NS-FET according to an embodiment of the present invention may include a non-selective material layer (21), a selective material layer (23), a dielectric layer (47), a source (S), a drain (D), and a gate (G). The NS-FET may be disposed on a base substrate, and a detailed description of the base substrate will be omitted.

[0110] A non-selective material layer (21) and a selective material layer (23) are laminated. A plurality of non-selective material layers (21) and a plurality of selective material layers (23) are alternately laminated. In the present embodiment, three non-selective material layers (21) and two selective material layers (23) are illustrated as being laminated, but the present invention is not limited thereto. In addition, the non-selective material layer (21) and the selective material layer (23) may be separated from each other in the horizontal direction.

[0111] Two-dimensional material layers (25) are arranged to overlap each other vertically and are used as channel layers. The two-dimensional material layers (25) are arranged on the outer side of each of the selective material layers (23). The width in one direction of the two-dimensional material layers (25) (corresponding to the thickness of the two-dimensional material layer (25)) is smaller than the height.

[0112] The dielectric layer (47) covers the upper surface of the two-dimensional material layer (25) and covers the side surface of the two-dimensional material layer (25) facing the selective material layer (23). The dielectric layer (47) can be formed of a high-k material. For example, HfO2 can be used as the dielectric layer (47). The dielectric layer (47) can be formed of the same material as the selective material layer (23), but is not necessarily limited thereto. The upper surface, lower surface, and both side surfaces of the two-dimensional material layer (25) are surrounded by the dielectric layer (47) and the selective material layer (23).

[0113] A source (S) and a drain (D) are in contact at both ends of the length direction of the two-dimensional material layer (25), and a gate (G) crossing between the source (S) and the drain (D) is arranged.

[0114] In addition, in this embodiment, the selection material layer (23) is shown and described as remaining on one side of the two-dimensional material layer and being used as a gate dielectric layer, but the selection material layer (23) may be removed after the two-dimensional material layer (25) is grown, and another dielectric layer may replace the selection material layer (23).

[0115] Since the NS-FET structure is generally well known, further detailed description is omitted, and a method for manufacturing an NS-FET according to one embodiment of the present invention is briefly described.

[0116] First, referring to FIG. 5b, a laminated structure is formed in which non-selective material layers (21) and selective material layers (23) are alternately laminated on a base substrate or a base film. In the present embodiment, two or more selective material layers (23) are formed within the laminated structure, and the selective material layers (23) are respectively positioned between non-selective material layers (21). A plurality of laminated structures can be provided together on a single wafer. Thereafter, a two-dimensional material layer (25) is selectively grown on the exposed side surface of the selective material layer (23).

[0117] Referring to FIG. 5c, a dielectric layer (47) covering two-dimensional material layers (25) is formed. The dielectric layer (47) covers the stacked structure formed by the non-selected material layers (21) and the selected material layers (23) and the two-dimensional material layers (25) grown on the side surfaces of the selected material layers (23). The dielectric layer (47) may be formed of, for example, a high-k material, such as HfO2.

[0118] Referring to FIG. 5d, a portion of the stacked structure is removed to divide the stacked structure of non-selective material layers (21) and selective material layers (23) into two regions, and a source (S), a drain (D), and a gate (G) are formed. The source (S) and the drain (D) can each be commonly connected to two-dimensional material layers (25) formed in one stacked structure.

[0119] The gate (G) passes through the region between the source (S) and the drain (D), as shown in Fig. 5a, and passes through the region dividing the stacked structure.

[0120] According to the present embodiment, an NS-FET can be provided in which the upper surface, lower surface, and both side surfaces of a two-dimensional material layer (25) used as a channel layer are surrounded by a gate dielectric layer.

[0121] FIGS. 6A and 6B are schematic cross-sectional views illustrating an anisotropic etching technique using a vertical two-dimensional material layer as an etching protection layer according to one embodiment of the present invention.

[0122] Referring to FIG. 6a, a laminated structure is provided in which a non-selective material layer (21) and a selective material layer (23) are alternately laminated on a base substrate or a base film, and a two-dimensional material layer (25) is selectively grown on the side of the selective material layer (21).

[0123] Referring to Fig. 6b, a side surface of a non-selected material layer (21) is etched using an etching technique to form a recessed layer (21a). A two-dimensional material layer (25) grown on the side surface of the selected material layer (23) can be used as an etching protection layer, thereby preventing the selected material layer (23) from being etched. Accordingly, the anisotropic etching characteristics of the non-selected material layer (21) can be improved.

[0124] FIGS. 7A and 7B are schematic cross-sectional views illustrating another etching technique using a vertical two-dimensional material layer as an etching protection layer according to one embodiment of the present invention.

[0125] Referring to Fig. 7a, a laminated structure of a selective material layer (23) and a non-selective material layer (21) is provided on an etching target layer (53). An etching stop layer (51) may be disposed below the etching target layer (53).

[0126] Meanwhile, a two-dimensional material layer (25) is formed on the side surface of the selection material layer (23). The two-dimensional material layer (25) is selectively grown on the side surface of the selection material layer (23).

[0127] Referring to FIG. 7b, the etching target layer (53) can be etched using the non-selective material layer (23) and the two-dimensional material layer (25) as a hard mask. The etching target layer (53) can be etched until the etching stop layer (51) is exposed.

[0128] In this embodiment, the two-dimensional material layer (25) can be used as an etching protection layer of the selective material layer (23), thereby protecting a material layer that is not resistant to etching and reinforcing the etching resistance of the hard mask.

[0129] FIGS. 8A and 8B are schematic cross-sectional views illustrating an example of a semiconductor device using a vertical two-dimensional material layer as a contact layer according to one embodiment of the present invention.

[0130] Referring to Fig. 8a, a laminated structure is formed in which a selective material layer (23) and a non-selective material layer (21) are laminated on a base substrate or a base film, and a two-dimensional material layer (25) is selectively grown on an exposed side of the selective material layer (23). Here, the selective material layer (23) may be a semiconductor layer. Alternatively, the selective material layer (23) may be removed and part or all of the selective material layer may be filled with a semiconductor material. The two-dimensional material layer (25) may make an ohmic contact with the selective material layer (23).

[0131] Referring to FIG. 8b, a conductive layer (61) electrically connected to a two-dimensional material layer (25) is formed. The conductive layer (61) can be electrically connected to a selective material layer (23) through the two-dimensional material layer (25).

[0132] In this embodiment, the two-dimensional material layer (25) is used as a contact layer to reduce the contact resistance of the conductive layer (61). The two-dimensional material layer (25) may be a contact liner as well as a contact layer. In addition, the two-dimensional material layer (25) may also be used as a diffusion barrier layer.

[0133] FIGS. 9A and 9B are schematic cross-sectional views illustrating a DG-FET (Double Gate Field-Effect Transistor) using a vertical two-dimensional material layer as a band alignment layer according to one embodiment of the present invention.

[0134] Referring to Fig. 9a, a first gate dielectric layer (77a) is formed on a base film on which a back gate (BG) is formed, and a laminated structure is formed in which a selection material layer (23) and a non-selection material layer (21) are laminated on the first gate dielectric layer (23). Thereafter, a two-dimensional material layer (25) is formed on the exposed side of the selection material layer (23).

[0135] Referring to FIG. 9b, contact layers (55) are formed on the side surfaces of the two-dimensional material layer (25). The contact layers (55) may be contact layers for connecting the source and drain. Meanwhile, a top gate (TG) may be formed on the non-selected material layer (21). In the present embodiment, the non-selected material layer (21) may be used as the second gate dielectric layer (77b), and the selective material layer (23) may be used as the channel layer (C). However, the present invention is not limited thereto, and the non-selected material layer (21) and / or the selective material layer (23) may be removed, and the channel layer (C) and / or the second gate dielectric layer (77b) may be formed through a separate process.

[0136] In this embodiment, the two-dimensional material layer (25) can be used as a band alignment layer of the channel layer (C) and the contact layer (55).

[0137] FIGS. 10A to 10E are schematic cross-sectional views (FIGS. 10A to 10D) and plan views (FIG. 10E) for explaining a method of manufacturing a transistor using a vertical two-dimensional material layer as a seed layer according to one embodiment of the present invention.

[0138] Referring to FIG. 10a, a laminated structure is formed in which a non-selective material layer (21) and a selective material layer (23) are alternately laminated on a base substrate or a base film, and two-dimensional material layers (25) are selectively grown on the exposed side of the selective material layer (21).

[0139] Referring to FIG. 10b, an epitaxial layer (81) is formed on each two-dimensional material layer (25) using the two-dimensional material layer (25) as a seed layer. The epitaxial layer (81) may be formed of a two-dimensional material, but is not particularly limited thereto. The epitaxial layer (81) may include one or more of graphene, h-BN, TMD, SiGe, GaN, AlN, AlGaN, InGaN, ZnS, or GaAs.

[0140] Referring to FIG. 10c, a first dielectric layer (83) covering the epitaxial layer (81) is formed. The first dielectric layer (83) may cover all of the epitaxial layer (81), the two-dimensional material layer (25), and the laminated structure.

[0141] Referring to FIG. 10d, the stacked structure of the non-selective material layer (21) and the selective material layer (23) can both be removed, the two-dimensional material layer (25) can also be removed, and the inner surfaces of the epitaxial layers (81) can be exposed. Thereafter, a second dielectric layer (85) can be formed on the exposed side surfaces of the epitaxial layer (81). Alternatively, by using the epitaxial layer (81) as a sacrificial layer, the epitaxial layer (81) can also be removed, and a channel layer can be formed on part or all of the epitaxial layer (81).

[0142] Next, referring to FIGS. 10d and 10e, a source (S), a drain (D), and a gate (G) can be formed to complete a transistor.

[0143] According to the present embodiment, a transistor having a structure similar to the NS-FET described with reference to FIGS. 5A to 5D may be provided. However, the shape and material of the epitaxy layer (81) and the structure of the dielectric layer (85) formed on one side of the epitaxy layer (81) may differ from the previous embodiment.

[0144] FIGS. 11A to 11E are schematic cross-sectional views illustrating a method for manufacturing a CTF (Charge Trap Flash) cell according to one embodiment of the present invention.

[0145] Referring to Fig. 11a, non-selective material layers (21) and selective material layers (23) are alternately laminated on a base substrate or base film. Although three non-selective material layers (21) and two selective material layers (23) are illustrated in the drawing, this is not limited thereto, and each may be laminated in a greater number.

[0146] Referring to Fig. 11b, a cavity is formed that penetrates the non-selected material layer (21) and the selected material layer (23). Accordingly, the inner surfaces of the non-selected material layer (21) and the selected material layer (23) within the cavity are exposed to the outside. Thereafter, a two-dimensional material layer (25) is selectively grown on the exposed inner surface of the selected material layer (23). Each of the two-dimensional material layers (25) can be grown in a ring shape within the cavity.

[0147] In Fig. 11c, a dielectric layer (91) is formed within the cavity. The dielectric layer (91) covers the two-dimensional material layers (25). The dielectric layer (91) is formed within the cavity so that a portion of the cavity remains without completely filling the cavity.

[0148] Referring to FIG. 11d, a channel material fills the cavity to form a channel (95). The channel material may be formed of, for example, polysilicon. Meanwhile, the outer portion of the memory cell may be etched to expose the outer surface of the laminated structure, and further, the selective material layers (23) may be removed. Accordingly, the surface of the two-dimensional material layer (25) may be exposed, and a dielectric layer (93) may be formed on the exposed two-dimensional material layer (25). In another embodiment, a portion of the selective material layer (25) may remain and function as the dielectric layer (93).

[0149] Referring to FIG. 11e, a gate (G) may be formed on a dielectric layer (93), thereby providing a CTF cell. In the present embodiment, the two-dimensional material layer (25) may be used as a charge trap layer or as a barrier material.

[0150] FIG. 11f is a schematic cross-sectional view illustrating a modified example of a CTF (Charge Trap Flash) cell according to one embodiment of the present invention.

[0151] Referring to FIG. 11f, a second two-dimensional material layer (25a) may be disposed on each of the two-dimensional material layers (25). The second two-dimensional material layers (25a) may be grown from a different material than the two-dimensional material layer (25), for example, after the two-dimensional material layer (25) is grown and before the dielectric layer (91) is formed.

[0152] The two-dimensional material layer (25) and the two-dimensional material layer (25a) can be used as a charge trap layer and a barrier material, respectively.

[0153] FIGS. 12A to 12D are schematic cross-sectional views illustrating a method for manufacturing a semiconductor device using a vertical two-dimensional material layer as a diffusion barrier layer according to one embodiment of the present invention.

[0154] Referring to Fig. 12a, a selective material layer (23) and a non-selective material layer (21) are laminated on a base film (101).

[0155] Referring to Fig. 12b, a cavity is formed by partially removing the selective material layer (23) and the non-selective material layer (21) to expose the base film (101). The inner surfaces of the selective material layer (23) and the non-selective material layer (21) are also exposed within the cavity.

[0156] Referring to Fig. 12c, a two-dimensional material layer (25) is selectively grown on the exposed surface of the selective material layer (23). The two-dimensional material layer (25) is not grown on the surface of the non-selected material layer (21). The two-dimensional material layer (25) may or may not be grown on the surface of the base film (101).

[0157] Referring to FIG. 12d, a filling metal (103) is formed to fill the cavity. The filling metal (103) can fill an area surrounded by a two-dimensional material layer (25) and an area surrounded by a non-selective material layer (21). The filling metal (103) can also cover the non-selective material layer (21). The filling metal (103) is electrically connected to the base film (101).

[0158] In the present embodiment, the two-dimensional material layer (25) may be disposed between the filling metal (103) and the selection material layer (23) to prevent diffusion of metal materials, etc. Furthermore, the two-dimensional material layer (25) may also be disposed between the base film (101) and the filling metal (103), and may function as a bonding layer, a contact layer, a contact liner, and / or a diffusion prevention layer between the base film (101) and the filling metal (103).

[0159] FIGS. 13A to 13C are schematic cross-sectional views illustrating a method of manufacturing an optical element using a vertical two-dimensional material layer as a seed layer according to one embodiment of the present invention.

[0160] Referring to Fig. 13a, a laminated structure is formed in which a non-selective material layer (21) and a selective material layer (23) are laminated on a base film (111). The selective material layer (23) may be placed between the non-selective material layers (21).

[0161] Next, a two-dimensional material layer (25) is selectively grown on the exposed side of the selective material layer (23), and compound semiconductor layers of a buffer layer (112), an n-GaN layer (113), an active layer (114), and a p-GaN layer (115) are grown using the two-dimensional material layer (25) as a seed layer, thereby forming a light-emitting diode (110).

[0162] Referring to FIG. 13b, an insulating layer (116) surrounding a light-emitting diode (110) is formed, and a p-electrode (117a) in ohmic contact with the p-GaN layer (115) is formed.

[0163] Referring to FIG. 13c, the non-selective material layer (21) and the selective material layer (23) are removed, and an n-electrode (117b) electrically connected to the two-dimensional material layer (25) is formed, thereby providing a light-emitting element. The light-emitting element may include a reflector (119), and light emitted from the light-emitting element in various directions toward the reflector (119) may be reflected by the reflector (119) and emitted upward. In the present embodiment, the base film (111) may be formed of a reflective material to become the reflector (119), or a reflector (119) separate from the base film (111) may be mounted on the light-emitting element.

[0164] According to the present embodiment, an optical element can be provided using a selectively grown two-dimensional material layer (25).

[0165] Figures 14a to 14c are SEM images showing TMDs grown in various laminated structures according to embodiments of the present invention. In each embodiment, a laminated structure in which a non-selected material layer and a selected material layer are laminated on a Si substrate was formed, and TMDs were grown.

[0166] (Example 1)

[0167] As a non-selective material layer, HfO2 with a thickness of approximately 50 nm was formed using electron beam deposition technology, and as a selective material layer, Al2O3 with a thickness of approximately 100 nm was formed using electron beam deposition technology.

[0168] TMD was performed at a chamber temperature of 650℃ using a flow controller, with 1 sccm of MHC (Molybdenum hexacarbonyl) as a transition metal precursor and DES (diethyl sulfide) as a chalcogen precursor.

[0169] was introduced into the chamber at a flow rate of 0.4 sccm, SP was introduced as a promoter at a flow rate of 0.2 sccm, Ar was introduced as a carrier gas at a flow rate of 395 sccm, H2 was introduced as a reducing agent at a flow rate of 10 sccm, and a 99% Ar / 1% O2 mixed gas was introduced as an oxidizing agent at a flow rate of 5 sccm.

[0170] As shown in Fig. 14a, TMD was not grown on the non-selective material layer HfO2, and it was confirmed that TMD was grown on the Al2O3 layer.

[0171] (Example 2)

[0172] As a non-selective material layer, HfO2 with a thickness of approximately 90 nm was formed using electron beam deposition technology, and as a selective material layer, Si3N4 with a thickness of approximately 270 nm was formed using electron beam deposition technology.

[0173] At a chamber temperature of 650°C, MHC as a transition metal precursor, DES as a chalcogen precursor, and SP as a promoter were introduced into the chamber at 1 sccm, 0.4 sccm, and 0.2 sccm using a flow rate controller, respectively. Ar was introduced as a carrier gas at 390 sccm, H2 as a reducing agent at 10 sccm, and a 99% Ar / 1% O2 mixed gas as an oxidizing agent was introduced into the chamber at a flow rate of 10 sccm.

[0174] As shown in Fig. 14b, TMD was not grown on the non-selective material layer HfO2, and it was confirmed that TMD was grown on the Si3N4 layer.

[0175] (Example 3)

[0176] As a selective material layer, SiO2 with a thickness of about 300 nm was formed by thermal oxidation of the substrate, and as a non-selective material layer, SiO2 with a thickness of about 500 nm was formed using electron beam deposition technology.

[0177] At a chamber temperature of 650°C, MHC as a transition metal precursor, DES as a chalcogen precursor, and SP as a promoter were introduced into the chamber at a flow rate of 1 sccm, 0.4 sccm, and 0.2 sccm, respectively, using a flow rate controller. Ar as a carrier gas, 10 sccm of H2 as a reducing agent, and O2 as an oxidizing agent were introduced into the chamber at a flow rate of 400 sccm, 10 sccm, and 0.05 sccm, respectively.

[0178] As shown in Fig. 14c, TMD was not grown on the EBD SiO2 layer, which is a non-selective material layer, and it was confirmed that TMD was grown on the SiO2 layer by thermal oxidation.

[0179] In Examples 1 and 2, the thickness of the selective material layer was greater than that of the non-selected material layer, and in Example 3, the thickness of the selective material layer was less than that of the non-selected material layer. The greater the thickness of the selective material layer than that of the non-selected material layer, the more advantageous it is for selective growth. However, it was also confirmed that TMDs were selectively grown on the selective material layer even when the non-selected material layer was thicker than the selective material layer.

[0180] According to embodiments of the present invention, a two-dimensional material layer perpendicular to a substrate can be provided by selectively growing a two-dimensional material layer on a side surface of a laminated structure in which a non-selective material layer and a selective material layer are laminated, and various semiconductor devices, including various optical devices, can be provided using the two-dimensional material layer.

[0181] Although the above has described methods for manufacturing several transistors and several application examples using two-dimensional material layers according to embodiments of the present invention, the present invention is not limited to these embodiments or applications. For example, the two-dimensional material layer according to the present invention can be used as a channel layer in a vertical multi-bridge channel GAA-FET.

[0182] In addition, the two-dimensional material layer according to embodiments of the present invention can be used primarily as a channel layer in a field effect transistor, but is not limited thereto, and can also be used as a fin gate in a transistor such as a Fin-Gate FET, for example.

[0183] Furthermore, a two-dimensional material layer can be used as a seed layer to grow various layers, and a sacrificial layer can also be grown to form a cavity inside.

[0184] While various embodiments of the present invention have been described above, the present invention is not limited to the various embodiments and features described above. Furthermore, matters or components described for one embodiment may be applied to other embodiments as long as they do not depart from the technical spirit of the present invention.

Claims

1. A laminated structure is formed in which a selective material layer providing a growth region on a substrate and a non-selective material layer providing a non-growth region are laminated adjacent to each other, and at least a portion of each side of the selective material layer and the non-selective material layer is exposed. A method for selectively growing a two-dimensional material layer on a vertical surface of a substrate, comprising: selectively growing a two-dimensional material layer on an exposed side of the substrate; 2. In claim 1, A method for selectively growing a vertical two-dimensional material, wherein the laminated structure comprises a selective material layer disposed between two non-selective material layers.

3. In claim 1, The above laminated structure has a plurality of selective material layers and a plurality of non-selective material layers that are alternately laminated, A method for selectively growing a vertical two-dimensional material, wherein the two-dimensional material layer is grown on each side wall of the plurality of selective material layers.

4. In claim 1, A method for selectively growing a vertical two-dimensional material, wherein the thickness of the selective material layer is greater than the thickness of the non-selected material layer.

5. In claim 1, A method for selectively growing a vertical two-dimensional material, wherein the selective material layer and the non-selective material layer are each formed as an oxide film, a nitride film, or an oxynitride film, and at least one of the elements, composition ratio, or deposition method of the selective material layer is different from the elements, composition ratio, or deposition method of the non-selective material layer.

6. In claim 5, A method for selectively growing a vertical two-dimensional material, wherein the above-mentioned selective or non-selective material is selected from the group consisting of AlOx, SiNx, SiOx, TiNx, TiOx, AlNx, MoOx, SiOxNy, TiOxNy, AlOxNy, HfOx, ZrOx, TaOx, TaNx, TaOxNy, FeOx, and LaOx.

7. In claim 5, A method for selectively growing a vertical two-dimensional material, wherein the selected material may be SiOx SiNx, AlOx, HfOx, or a mixture thereof, and the non-selected material may be SiOx, HfOx, ZrOx, FeOx, or a mixture thereof.

8. In claim 1, A method for selectively growing a vertical two-dimensional material, wherein the two-dimensional material layer comprises a transition metal dichalcogenide (TMD) film.

9. A method for selectively growing a vertical two-dimensional material, wherein the TMD film is grown using a chemical vapor deposition technique or an atomic layer deposition technique using a transition metal precursor and a chalcogen precursor, according to claim 8.

10. In claim 9, The above deposition technique is a selective growth method of vertical two-dimensional materials that further utilizes a promoter.

11. In claim 1, The above laminated structure includes a cavity penetrating the selective material layer and the non-selective material layer, A method for selectively growing a vertical two-dimensional material, wherein the selective material layer is grown on the inner surface of the selective material layer exposed within the cavity.

12. In claim 1, A method for selectively growing a vertical two-dimensional material, wherein the two-dimensional material layer is a single crystal.

13. A vertical two-dimensional material layer selectively grown on at least a portion of the side surface of the selective material layer among a laminated structure in which a selective material layer and a non-selective material layer are laminated adjacent to each other in the thickness direction.

14. In claim 13, The above laminated structure is a vertical two-dimensional material layer comprising a selective material layer disposed between two non-selective material layers.

15. In claim 13, The above laminated structure has a plurality of selective material layers and a plurality of non-selective material layers that are alternately laminated, A vertical two-dimensional material layer grown on each side wall of the plurality of selected material layers.

16. A semiconductor device comprising a vertical two-dimensional material layer formed by a selective growth method of any one of claims 1 to 12 or a vertical two-dimensional material layer of any one of claims 13 to 15.

17. In claim 16, A semiconductor device in which the above two-dimensional material layer is a channel layer.

18. In claim 16, A semiconductor device wherein the two-dimensional material layer is a bonding layer, a contact layer, a contact liner or a diffusion barrier layer.

19. In claim 16, A semiconductor device in which the above two-dimensional material layer is a seed layer or a lattice constant adjustment layer.

20. In claim 16, A semiconductor device in which the above two-dimensional material layer is an etching protection layer.

21. In claim 16, The above two-dimensional material layer is a semiconductor device that is a charge trap layer of a CTF (Charge Trap Flash) cell.

22. In claim 16, A semiconductor device that is an optical element that emits light.

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