Transistor, method for manufacturing same, and electronic device including transistor

Abstract

This transistor comprises a single-crystal silicon film, a gate insulating film on the single-crystal silicon film, a gate electrode on the gate insulating film, an interlayer insulating film on the gate electrode, and a pair of terminals. The single-crystal silicon film is positioned on an amorphous glass substrate and has a (100) crystal plane. The pair of terminals are located on the interlayer insulating film and electrically connected to the single-crystal silicon film. The length direction of the channel of the transistor is inclined at an angle of more than 0° and no more than 45° from the [001] crystal axis or the [010] crystal axis of the single-crystal silicon film.

Description

Transistors, methods for fabricating them, and electronic devices containing transistors

[0001] One embodiment of the present invention relates to a transistor and a method for manufacturing the same. Alternatively, one embodiment of the present invention relates to an electronic device including the transistor.

[0002] In recent years, a technique has been developed for forming a single-crystal silicon film on an amorphous glass substrate. In this method, an embrittlement layer is formed by implanting ions such as hydrogen ions into the single-crystal silicon substrate, and after bonding the single-crystal silicon substrate to the glass substrate, the single-crystal silicon film on the embrittlement layer can be transferred to the glass substrate by peeling off the single-crystal silicon substrate (see Patent Document 1). By applying this technique, it is possible to form transistors on a glass substrate that have extremely high mobility compared to transistors with polycrystalline silicon films or amorphous silicon films in the channel.

[0003] Patent No. 6070954

[0004] One embodiment of the present invention aims to provide a transistor having a novel structure and a method for fabricating the same. Alternatively, one embodiment of the present invention aims to provide a high-mobility transistor having a single-crystal silicon film as a channel and a method for fabricating this transistor on a glass substrate. Alternatively, one embodiment of the present invention aims to provide an electronic device having the above-mentioned transistor.

[0005] One embodiment of the present invention is a transistor. This transistor comprises a single-crystal silicon film, a gate insulating film on the single-crystal silicon film, a gate electrode on the gate insulating film, an interlayer insulating film on the gate electrode, and a pair of terminals. The single-crystal silicon film is located on an amorphous glass substrate and has a (100) crystal plane. The pair of terminals are located on the interlayer insulating film and are electrically connected to the single-crystal silicon film. The longitudinal direction of the transistor channel is tilted from the

[001] crystal axis or

[010] crystal axis of the single-crystal silicon film at an angle greater than 0° and less than or equal to 45°.

[0006] One embodiment of the present invention is an electronic device having the above-mentioned transistor.

[0007] One embodiment of the present invention is a method for manufacturing a transistor. This manufacturing method includes forming a single-crystal silicon film between the upper surface and the embrittlement layer by implanting ions from the upper surface of a single-crystal silicon substrate having a (100) crystal plane; joining the single-crystal silicon substrate and an amorphous glass substrate so as to sandwich the single-crystal silicon film; peeling the single-crystal silicon substrate from the amorphous glass substrate to transfer the single-crystal silicon film onto the amorphous glass substrate; forming a gate insulating film on the single-crystal silicon film; forming a gate electrode on the gate insulating film; forming an interlayer insulating film on the gate electrode; and forming a pair of terminals located on the interlayer insulating film and electrically connected to the single-crystal silicon film. The gate electrode and the pair of terminals are formed such that the longitudinal direction of the transistor channel is tilted at an angle greater than 0° and 45° or less from the

[001] crystal axis or

[010] crystal axis of the single-crystal silicon film.

[0008] A schematic end view of a transistor according to one embodiment of the present invention. A schematic end view of a transistor according to one embodiment of the present invention. A schematic end view of a transistor according to one embodiment of the present invention. A schematic top view of a transistor according to one embodiment of the present invention. A schematic end view showing a method for manufacturing a transistor according to one embodiment of the present invention. A schematic end view showing a method for manufacturing a transistor according to one embodiment of the present invention. A schematic end view showing a method for manufacturing a transistor according to one embodiment of the present invention. A schematic end view showing a method for manufacturing a transistor according to one embodiment of the present invention. A schematic top view showing a method for manufacturing a transistor according to one embodiment of the present invention. A schematic top view showing a method for manufacturing a transistor according to one embodiment of the present invention. A schematic end view showing a method for manufacturing a transistor according to one embodiment of the present invention. A schematic end view showing a method for manufacturing a transistor according to one embodiment of the present invention. A schematic top view showing a method for manufacturing a transistor according to one embodiment of the present invention. A schematic end view showing a method for manufacturing a transistor according to one embodiment of the present invention. A schematic end view showing a method for manufacturing a transistor according to one embodiment of the present invention. A schematic end view showing a method for manufacturing a transistor according to one embodiment of the present invention. A schematic end view showing a method for manufacturing a transistor according to one embodiment of the present invention. A schematic end view showing a method for manufacturing a transistor according to one embodiment of the present invention. A schematic end view showing a method for manufacturing a transistor according to one embodiment of the present invention. A schematic end view showing a method for manufacturing a transistor according to one embodiment of the present invention. A schematic end view showing a method for manufacturing a transistor according to one embodiment of the present invention. A schematic end view showing a method for manufacturing a transistor according to one embodiment of the present invention. A schematic end view showing a method for manufacturing a transistor according to one embodiment of the present invention. A schematic end view showing a method for manufacturing a transistor according to one embodiment of the present invention. A schematic end view showing a method for manufacturing a transistor according to one embodiment of the present invention. A schematic top view of an electronic device according to one embodiment of the present invention. Equivalent circuit diagram of a pixel in an electronic device according to one embodiment of the present invention.An equivalent circuit diagram of a pixel in an electronic device according to one embodiment of the present invention.

[0009] The embodiments of the present invention will be described below with reference to the drawings and other materials. However, the present invention can be implemented in various forms without departing from its spirit, and is not to be interpreted as being limited to the embodiments described below.

[0010] While drawings may schematically represent the width, thickness, shape, etc., of each part compared to the actual embodiment in order to clarify the explanation, these are merely examples and do not limit the interpretation of the present invention. In this specification and each figure, elements having the same function as those described in previously shown figures are denoted by the same reference numeral, and redundant explanations may be omitted. This reference numeral is used to represent multiple identical or similar structures collectively, and when representing them individually, a hyphen and a natural number are added after the reference numeral.

[0011] In this specification and claims, when describing a manner in which one structure is placed on top of another structure, unless otherwise specified, the term "on top of" includes both cases: when one structure is placed directly on top of another structure so as to be in contact with it, and when another structure is placed above another structure via yet another structure.

[0012] In this specification and claims, the expression "a structure is exposed from another structure" means a portion of a structure that is not covered by another structure, and this portion that is not covered by another structure may also be covered by yet another structure. Furthermore, the expression also includes a portion of a structure that is not in contact with another structure.

[0013] In this invention, when a single film is processed to form multiple films, these multiple films may have different functions and roles. However, these multiple films originate from a film formed as the same layer in the same process, and have substantially the same layer structure, the same material, and the same morphology. Therefore, these multiple films are defined as existing in the same layer.

[0014] The following describes a transistor according to one embodiment of the present invention and a method for manufacturing the same.

[0015] 1. Transistor Configuration 1-1. Overall Structure Figure 1 shows a schematic end view of a transistor 100 according to one embodiment of the present invention. The transistor 100 is provided on an amorphous glass substrate 120. Preferably, the transistor 100 is provided on the amorphous glass substrate 120 via a protective insulating film (hereinafter referred to as an undercoat) 122 to prevent impurities, such as metal ions including sodium contained in the amorphous glass substrate 120, from diffusing into the transistor 100. The transistor 100 is a so-called top-gate type transistor and includes a semiconductor film 102, a gate insulating film 104 on the semiconductor film 102, a gate electrode 106 provided on the gate insulating film 104 and overlapping with the semiconductor film 102 via the gate insulating film 104, an interlayer insulating film 108 provided on the gate electrode 106 and covering the gate electrode 106, and a pair of terminals 110, 112 provided on the interlayer insulating film 108 and electrically connected to the semiconductor film 102. One of the pair of terminals 110, 112 functions as a source electrode, and the other functions as a drain electrode. The following details these components.

[0016] (1) Amorphous glass substrate As the amorphous glass substrate 120, for example, a glass substrate containing silicon oxide, alumina, and alkaline earth metal oxides, called an alkaline earth aluminoborosilicate glass substrate, a glass substrate containing silicon oxide, sodium oxide, alumina, and boron oxide, called a borosilicate glass substrate, a glass substrate containing silicon oxide, potassium oxide, and lead oxide, also called a lead glass substrate, or a glass substrate containing silicon oxide, alumina, lithium oxide, titanium oxide, and zirconium oxide can be used. Preferably, the coefficient of thermal expansion is 3.5 × 10 －６ K －１ The above 4.0 x 10 －６ K －１The following glass substrates are used. There are no restrictions on the size of the amorphous glass substrate 120; for example, a small substrate of about 120 mm x 120 mm may be used, or glass substrates of a size of 600 mm x 720 mm (called 3.5th generation glass), 730 mm x 920 mm (called 4.5th generation glass), 1500 mm x 1850 mm (called 6th generation glass), or larger may be used. Therefore, multiple transistors 100 may be arranged on a single amorphous glass substrate 120.

[0017] (2) Undercoat The undercoat 122 is configured to include one or more layers containing silicon-containing inorganic compounds such as silicon oxide or silicon nitride. The undercoat 122 is applied to the entire surface of the amorphous glass substrate 120 using chemical vapor deposition (CVD) or sputtering. By providing the undercoat 122, it is possible to prevent impurities in the amorphous glass substrate 120 from entering the transistor 100 and to prevent degradation of the characteristics of the transistor 100.

[0018] (3) Semiconductor film The semiconductor film 102 is a single-crystal silicon film containing silicon and having the morphology of a single crystal. Therefore, compared to transistors containing amorphous silicon or polycrystalline silicon, a large on-current and extremely high carrier mobility can be realized in the transistor 100. This contributes to the high-speed operation of electronic devices including the transistor 100. The semiconductor film 102 is provided such that the (100) crystal plane of single-crystal silicon constitutes its upper surface. There are no restrictions on the thickness of the semiconductor film 102, but the thickness of the semiconductor film 102 is, for example, 10 nm to 70 nm. As will be described later, the semiconductor film 102 is formed by transferring a part of the (100) single-crystal semiconductor substrate onto the amorphous glass substrate 120.

[0019] At least a portion of the semiconductor film 102 is doped with a dopant, thereby forming a channel 102a that overlaps with the gate electrode 106 and has intrinsic or substantially intrinsic electrical properties, as well as a pair of source / drain regions 102b that are exposed from the gate electrode 106 and have p-type or n-type conductivity. The channel 102a is sandwiched between the pair of source / drain regions 102b, and the length of the channel 102a along the shortest straight line connecting the pair of source / drain regions 102b is the channel length, and this direction is called the channel length direction. The direction perpendicular to the channel length direction and parallel to the main surface of the channel 102a is the channel width direction.

[0020] (4) Gate insulating film The gate insulating film 104 can be configured to contain a silicon-containing inorganic compound, or an inorganic compound known as a high-k material, such as hafnium silicate, hafnium oxide, or zirconium oxide. The gate insulating film 104 is provided with a relatively small thickness such that the oxide film thickness (EOT) is 40 nm or more and 100 nm or less. The oxide film thickness is the thickness obtained by converting the thickness of the film to an equivalent electrical film thickness of a film made of silicon oxide, and is the thickness of the silicon oxide film when the same capacitance value as a capacitive element having the film as a dielectric film is achieved using a film made of silicon oxide as the dielectric film. The gate insulating film 104 can also be provided so as to cover the semiconductor film 102 by applying a CVD method or a sputtering method. By forming the gate insulating film 104 thinly, the acceleration voltage of the dopant can be reduced in the doping of the semiconductor film 102 via the gate insulating film 104 performed when the transistor 100 is manufactured, and as a result, the degradation of the gate insulating film 104 can be prevented. Furthermore, since the deterioration of the resist mask applied during doping can be suppressed, the resist mask can be easily removed, and as a result, the generation of etching residue during etching of the resist mask can be prevented.

[0021] (5) Gate Socket The gate electrode 106 overlaps with the channel 102a of the semiconductor film 102 via the gate insulating film 104. The gate electrode 106 is configured to contain a metal (zero-valent metal) such as molybdenum, tungsten, tantalum, or titanium. The gate electrode 106 is provided such that its thickness is five times or more the oxide film thickness of the gate insulating film 104. There is no upper limit to the thickness of the gate electrode 106, but for example, the upper limit may be six times, eight times, or ten times the oxide film thickness of the gate insulating film 104. For example, the thickness of the gate electrode 106 can be set in the range of 200 nm to 400 nm. By forming a relatively thick gate electrode 106 in this way, the resistance of the gate electrode 106 and the wiring connected to it (gate wiring) can be reduced, thereby preventing problems such as signal delay caused by wiring resistance. Furthermore, by forming the gate insulating film 104 with a relatively small oxide film thickness and the gate electrode 106 with a large thickness, the gate electrode 106, which has a larger coefficient of thermal expansion than the semiconductor film 102, deforms significantly during the heat treatment (for example, the heat treatment for dopant activation described later) and subsequent cooling process in the manufacturing process of the transistor 100. As a result, greater tensile strain can be generated in the semiconductor film 102 due to the deformation of the gate electrode 106. This contributes to further improving the mobility of the transistor 100.

[0022] (6) Interlayer insulating film The interlayer insulating film 108 is provided so as to cover the gate electrode 106 and, like the undercoat 122, is configured to include one or more layers containing a silicon-containing inorganic compound. The interlayer insulating film 108 is also formed by applying a CVD method or a sputtering method.

[0023] (7) Terminals The pair of terminals 110 and 112 are provided on the interlayer insulating film 108 and are electrically connected to a pair of source / drain regions 102b of the semiconductor film 102 via a gate insulating film 104 and a pair of openings provided in the interlayer insulating film 108. Similar to the gate electrode 106, the pair of terminals 110 and 112 are configured to contain a zero-valent metal, but preferably they are formed to have a lower electrical resistance than the gate electrode 106. Specifically, it is preferable that the pair of terminals 110 and 112 contain molybdenum, tungsten, tantalum, titanium, as well as aluminum or an alloy thereof. For example, each of the pair of terminals 110 and 112 may have a laminated structure of an aluminum-containing film and a titanium-containing film, or a laminated structure of an aluminum-containing film and a molybdenum-containing film, preferably a structure in which an aluminum-containing film is sandwiched between titanium-containing films, or a structure in which an aluminum-containing film is sandwiched between molybdenum-containing films. Examples of aluminum alloys include aluminum-neodymium alloys. Therefore, each of the pair of terminals 110 and 112 may have a laminated structure of a film containing an aluminum-neodymium alloy and a titanium-containing film, or a laminated structure of a film containing an aluminum-neodymium alloy and a molybdenum-containing film. Preferably, a structure in which a film containing an aluminum-neodymium alloy is sandwiched between titanium-containing films, or a structure in which a film containing an aluminum-neodymium alloy is sandwiched between molybdenum-containing films is employed.

[0024] (8) Other structures (not shown in the diagram) When the transistor 100 is used as a switching element, a planar film covering the transistor 100 may be provided. By providing an opening in the planar film that exposes one or both of the pair of terminals 110 and 112, electrical connections between various elements and the transistor 100 can be made using this opening.

[0025] There are no restrictions on the polarity of transistor 100; transistor 100 may be a p-type transistor or an n-type transistor. When functioning as an n-type transistor, as shown in Figure 2, the semiconductor film 102 of transistor 100 may be configured to have a low-concentration doped (LDD) region 102c between the channel 102a and the source / drain region 102b. The LDD region 102c is a region with a lower dopant concentration compared to the source / drain region 102b, and by providing it, electric field concentration can be avoided and the drain electric field can be mitigated.

[0026] Alternatively, as shown in Figure 3, each of the pair of source / drain regions 102b may have a titanium silicide-containing layer 114 in contact with terminals 110 or 112. The titanium silicide-containing layer 114 is a layer containing or composed of titanium silicide, and its thickness is smaller than the thickness of the semiconductor film 102. By forming a titanium silicide-containing layer 114 with low electrical resistance, the resistance of the source / drain region 102b can be further reduced, and the contact resistance between the source / drain region 102b and terminals 110 and 112 can be reduced. Furthermore, as will be described later, the heating and subsequent cooling processes during the formation of the titanium silicide-containing layer 114 can generate greater tensile strain in the semiconductor film 102.

[0027] 1-2. Crystal axis of the semiconductor film A schematic top view of the transistor 100 is shown in Figure 4. The gate insulating film 104 and interlayer insulating film 108 are not shown here. As described above, the semiconductor film 102 of the transistor 100 is provided such that its top surface is the (100) crystal plane of a silicon single crystal. Therefore, as shown in Figure 4, the

[100] crystal axis is in the direction normal to the semiconductor film 102. On the other hand, the

[001] crystal axis and the

[010] crystal axis of the semiconductor film 102 are not parallel to the channel length direction (CLD in the figure) of the transistor 100, but are tilted at an angle θ. The angle θ can be appropriately selected from the range of greater than 0° and 45° or less, 10° or more and 30° or less, or 15° or more and 30° or less. In other words, the gate electrode 106 and the pair of terminals 110 and 112 are arranged such that the channel length direction of the semiconductor film 102 is tilted at an angle θ from the

[001] crystal axis or the

[010] crystal axis.

[0028] As will be described later, the fabrication of transistor 100 involves several stages of heat treatment. The various components included in transistor 100 have different coefficients of thermal expansion; for example, the coefficient of thermal expansion of single-crystal silicon is 3.9 × 10⁻⁶. －６ K －１ The coefficient of thermal expansion of amorphous glass is 3.5 × 10⁻⁶. －６ K －１ Furthermore, the thermal expansion coefficients of the metals constituting the gate electrode 106 and the pair of terminals 110 and 112 are even larger. Also, the thermal expansion coefficient of single-crystal silicon differs depending on the crystal axis. For this reason, by forming the transistor 100 such that the

[001] crystal axis and the

[010] crystal axis of the semiconductor film 102 are tilted with respect to the channel length direction, tensile strain is generated in the semiconductor film 102 along the two crystal axes due to the difference in thermal expansion coefficients during the cooling process after heat treatment. As a result, the transistor 100 acts as a so-called strain transistor, achieving higher mobility.

[0029] 2. Method for fabricating a transistor In the method for fabricating the transistor 100, a technique called so-called smart cut is applied, and a part of the single-crystalline semiconductor substrate is transferred onto the amorphous glass substrate 120 as the semiconductor film 102 through the bonding and peeling between the amorphous glass substrate 120 and the single-crystalline semiconductor substrate. Hereinafter, a method for fabricating p-type and n-type transistors 100 on one amorphous glass substrate 120 will be described as an example.

[0030] (1) Formation of semiconductor film First, the amorphous glass substrate 120 is appropriately cleaned, and then the undercoat 122 is formed by applying the CVD method or the sputtering method (Fig. 5). The undercoat 122 may be provided only on one surface of the amorphous glass substrate 120, and although not shown, it may be provided on both surfaces. In addition, when the undercoat 122 is not provided, this step may be omitted.

[0031] As the single-crystalline semiconductor substrate 130 bonded to the amorphous glass substrate 120, a (110) single-crystalline silicon substrate whose upper surface is the (100)-plane of a single-crystalline silicon is used, Prior to bonding with the amorphous glass substrate 120, ion implantation is performed on the single-crystalline semiconductor substrate 130 (Fig. 6). Examples of the ions include hydrogen ions, and helium ions or argon ions may be further implanted. In ion implantation, a single type of ion obtained by mass separation may be implanted, or multiple types of ions may be implanted simultaneously without performing mass separation.

[0032] By ion implantation, a layer containing minute voids is formed inside the single-crystalline semiconductor substrate 130. This layer is called the embrittlement layer 132 and is formed inside the single-crystalline semiconductor substrate 130 substantially parallel to the ion-implanted surface 130a (Figs, land 7). The portion between the embrittlement layer 132 and the surface 130a becomes the semiconductor film 102. The depth of the embrittlement layer 132 (the distance from the ion-implanted surface 130a) can be adjusted by appropriately controlling the acceleration voltage of the ions. The depth of the embrittlement layer 132 may be appropriately set according to the thickness of the semiconductor film l02 of the transistor 100, and for example, it is set to 40 nm or more and 100 nm or less. The ion dose is, for example, 3 x 10 １６ ions / cm ２ or more and 1 x 10 １７ ions / cm２ The following is correct.

[0033] Subsequently, the amorphous glass substrate 120 and the single-crystal semiconductor substrate 130 are bonded together (Figure 8). The bonding involves joining the ion-implanted surface 130a of the single-crystal semiconductor substrate 130 to the amorphous glass substrate 120. That is, the bonding is performed such that the portion corresponding to the semiconductor film 102 is sandwiched between the amorphous glass substrate 120 and the single-crystal semiconductor substrate 130. When forming the undercoat 122, the portion corresponding to the semiconductor film 102 and the undercoat 122 are bonded together such that they are sandwiched between the single-crystal semiconductor substrate 130 and the amorphous glass substrate 120.

[0034] As described above, in transistor 100, the

[100] crystal axis of the semiconductor film 102 is in the direction normal to the semiconductor film 102, and the

[001] crystal axis and the

[010] crystal axis are tilted from the channel length direction. For this reason, when the amorphous glass substrate 120 is rectangular and multiple transistors are arranged in a matrix in a rectangular region having four sides parallel to the sides of the amorphous glass substrate 120, it is preferable to arrange and bond the single crystal semiconductor substrate 130 to the amorphous glass substrate 120 such that the

[001] crystal axis and the

[010] crystal axis are tilted from the sides of the amorphous glass substrate 120, as shown in Figure 9. By forming the transistor 100 so that the channel length direction is parallel to the sides of the amorphous glass substrate 120, the

[001] crystal axis and the

[010] crystal axis can be tilted from the channel length direction. Furthermore, if the single-crystal semiconductor substrate 130 and the amorphous glass substrate 120 are rectangular, and the crystal axis

[001] and the crystal axis

[010] are parallel to the sides of the single-crystal semiconductor substrate 130, then, as shown in Figure 10, the single-crystal semiconductor substrate 130 can be positioned and bonded to the amorphous glass substrate 120 such that the sides of the single-crystal semiconductor substrate 130 are inclined relative to the sides of the amorphous glass substrate 120.

[0035] There are no restrictions on the number of single-crystal semiconductor substrates 130 bonded to a single amorphous glass substrate 120. Depending on the size relationship between the amorphous glass substrate 120 and the single-crystal semiconductor substrates 130, and the arrangement of the transistors 100, multiple single-crystal semiconductor substrates 130 may be bonded to a single amorphous glass substrate 120 (see Figure 11). Although not shown, the shape of the single-crystal semiconductor substrate 130 is not limited to a rectangle, and may also be a circle (including a circle with a portion of its outer circumference cut off).

[0036] During bonding, the amorphous glass substrate 120 and the single-crystal semiconductor substrate 130 may be subjected to appropriate pressurization and heat treatment. The pressure in the pressurization treatment is appropriately selected within the range of 7 Pa to 35 Pa. The heat treatment is performed below the strain point of the amorphous glass substrate 120, for example, at a temperature selected from the range of 50°C to 200°C. By performing heat treatment on the amorphous glass substrate 120 and the single-crystal semiconductor substrate 130, tensile strain can be applied to the semiconductor film 102 along the

[001] crystal axis and the

[010] crystal axis due to the difference in thermal expansion coefficients between amorphous glass and single-crystal silicon, and the crystal axis dependence of the thermal expansion coefficient of single-crystal silicon.

[0037] In bonding, anode bonding may be further utilized. Specifically, as shown in Figure 12, electrodes 134 and 136 are connected to the single-crystal semiconductor substrate 130 and the amorphous glass substrate 120, respectively, and a voltage is applied between electrodes 134 and 136. At this time, the voltage is applied so that electrodes 134 and 136 function as the positive and negative electrodes, respectively. The voltage is, for example, 30V to 1000V. Heat may also be applied at the same time. By performing anode bonding, a strong electrostatic attraction acts between the amorphous glass substrate 120 and the single-crystal semiconductor substrate 130, and as a result, the amorphous glass substrate 120 and the single-crystal semiconductor substrate 130 can be bonded more firmly.

[0038] Thereafter, the single-crystalline semiconductor substrate 130 is peeled off from the amorphous glass substrate 120. The peeling may be performed physically. As a result, the single-crystalline semiconductor above the embrittlement layer 132 is peeled off with the embrittlement layer 132 as a cleavage plane, and a semiconductor film 102 having a single-crystalline morphology is transferred onto the amorphous glass substrate 120 (FIG. 13). Thereafter, the semiconductor film 102 is appropriately etched, and a plurality of semiconductor films 102 are formed on the amorphous glass substrate 120 according to the number, structure, and arrangement of the transistors 100 (FIG. 14).

[0039] (2) Fabrication of a Transistor Including a Semiconductor Film Thereafter, a structure constituting the transistor 100 is formed on the semiconductor film 102. As an optional step, a dopant may be implanted into the semiconductor film 102 (FIG. 15). This step is for making the semiconductor film 102 intrinsic or substantially intrinsic, and dopants such as phosphorus, arsenic, boron, etc. are used.

[0040] First, a gate insulating film 104 is formed on the semiconductor film 102, and then a gate electrode 106 overlapping the semiconductor film 102 is formed on the gate insulating film 104 (FIG. 16). As described above, these structures may be formed by appropriately using the CVD method or the sputtering method. The thicknesses of these structures are as described above.

[0041] Subsequently, doping is performed on the semiconductor film 102. Specifically, a resist mask 138 covering one semiconductor film 102 (the right semiconductor film 102 providing an n-type transistor in FIG. 17) is formed, and p-doping is performed on the other semiconductor film 102 (the left semiconductor film 102 providing a p-type transistor) through the gate insulating film 104 using the gate electrode 106 as a mask. Boron is exemplified as the dopant. As a result, a source / drain region 102b doped with the dopant is formed, and a channel 102a is formed as a region sandwiched therebetween (FIG. 18).

[0042] Subsequently, after removing the resist mask 138, a resist mask 140 is formed to cover the other semiconductor film 102. In this state, doping (n-doping) is performed on the exposed semiconductor film 102 through the gate insulating film 104 using the gate electrode 106 as a mask (FIG. 19). Examples of the dopant include phosphorus and arsenic. The dose amount at this time is determined so as to be suitable for forming the LDD region 102c. By this process, together with a pair of n-doped regions 102d, a channel 102a sandwiched therebetween is formed (FIG. 20).

[0043] Then, a resist mask 142 is formed to cover the side surface of the gate electrode 106 and expose a part of the n-doped region 102d (FIG. 21). The resist mask 142 can be self-alignedly formed by the step formed by the gate electrode 106 by forming a resist to cover the semiconductor film 102 exposed from the resist mask 140 and the gate electrode 106 and dry-etching this. In this state, by doping the semiconductor film 102 exposed from the resist mask 140 with a dopant that gives n-type conductivity such as phosphorus and arsenic, the portions of the semiconductor film 102 exposed from the resist masks 140 and 14 are converted into source / drain regions 102b, and the portion overlapping with the resist mask 142 can be converted into an LDD region 102c (FIG. 22). After this, the resist masks 140 and 142 are removed. In the above-described example, p-doping is performed on one semiconductor film 102 and then n-doping is performed on the other semiconductor film 102, but there is no restriction on the order of doping, and n-doping and p-doping may be performed in the reverse order.

[0044] As described above, the transistor 100 is provided with a gate insulating film 104 having a relatively small thickness. Therefore, in these series of doping processes, the voltage for accelerating the dopant can be suppressed low, whereby the deterioration of the gate insulating film 104 is suppressed. Also, since the alteration of the resist masks 140 and 142 due to the injection of the dopant is suppressed, the resist masks 140 and 14 can be easily peeled off, and the generation of etching residues can be effectively prevented.

[0045] After this, a heat treatment may be performed to activate the dopant. The heat treatment can be performed, for example, at a temperature of 450°C to 580°C for 5 to 60 minutes. During this heat treatment and the subsequent cooling process, a large tensile strain is generated in the semiconductor film 102 due to the large difference in the coefficient of thermal expansion between the gate electrode 106 and the semiconductor film 102. This can improve the mobility of the transistor 100.

[0046] Next, the gate insulating film 104 and the interlayer insulating film 108 are etched to form an opening that exposes the source / drain region 102b, and a metal film 144 is formed to fill this opening by CVD or sputtering (Figure 23). The configuration of the metal film 144 is the same as the configuration of the pair of terminals 110 and 112. Subsequently, the pair of terminals 110 and 112 are formed by etching the metal film 144 (Figure 24). Through the above process, a p-type transistor 100-1 and an n-type transistor 100-2 can be formed.

[0047] When forming the titanium silicide-containing layer 114, a metal film 146 containing or made of metallic titanium is formed using a CVD method or sputtering method, etc., to fill the opening that exposes the source / drain region 102b (Figure 25). After this, a heat treatment is performed to silicide a part of the source / drain region 102b, thereby forming the titanium silicide-containing layer 114 (Figure 26). After this, the metal film 146 is removed by etching, and a pair of terminals 110 and 112 are formed by forming a metal film 144 as described above and etching it (Figure 27). Alternatively, the metal film 146 may not be removed, a metal film 144 containing the metal film 146 may be formed, and the pair of terminals 110 and 112 may be formed by etching the metal film 144. During the heat treatment for forming the titanium silicide-containing layer 114 and the subsequent cooling process, strain can be applied to the semiconductor film 102 due to the difference in thermal expansion coefficients between the metal film 144, gate electrode 106, the pair of terminals 110 and 121 and the semiconductor film 102. Therefore, the mobility of transistor 100 can be improved.

[0048] Although not shown in the diagram, a planarization film is then formed on the p-type transistor 100-1 and the n-type transistor 100-2 to absorb the irregularities caused by the p-type transistor 100-1 and the n-type transistor 100-2. By forming an opening that exposes one or both of the terminals 110 and 112, the p-type transistor 100-1 and the n-type transistor 100-2 can be electrically connected to other wiring or elements. The planarization film may be formed to contain a polymer such as polyimide, epoxy resin, or acrylic resin.

[0049] By the method described above, a transistor 100 having a semiconductor film 102 with single-crystal morphology can be fabricated. Furthermore, by tilting the channel length direction of the transistor 100 from the

[001] crystal axis and the

[010] crystal axis, and then performing a heat treatment after forming a thin gate insulating film 104 and a thick gate electrode 106, tensile strain can be generated in the semiconductor film 102 along the

[001] crystal axis and the

[010] crystal axis. As a result, the transistor 100 can achieve extremely high on-current and mobility. Therefore, by constructing an electronic device using the transistor 100, it is possible to provide a high-performance electronic device capable of high-speed operation.

[0050] 3. Electronic Devices There are no restrictions on the type or function of electronic devices, including the transistor 100, and the transistor 100 can be used in various electronic devices such as display devices, lighting devices, radio wave reflectors, electrowetting devices, and sensors. As an example of an electronic device, a schematic top view of a display device 150 is shown in Figure 28. The display device 150 includes an array substrate 152 corresponding to an amorphous glass substrate 120, and multiple pixels 154, drive circuits for driving the multiple pixels 154 (scan line drive circuit 156, signal line drive circuit 158), and multiple terminals 160 are formed on the array substrate 152. The terminals 160 are electrically connected to the scan line drive circuit 156 and the signal line drive circuit 158. In addition to the power supply, control signals for driving the display device 150 are input to the scan line drive circuit 156 and the signal line drive circuit 158 ​​from an external circuit (not shown) via the terminals 160. The scan line drive circuit 156 and the signal line drive circuit 158 ​​generate various signals (gate signal, video signal, reset signal, initialization signal, etc.) for driving the pixels 154 based on the control signal and supply them to the pixels 154. This allows multiple pixels 154 to reproduce an image corresponding to the control signal.

[0051] The transistor 100 may be incorporated into the drive circuit, or / or into each pixel 154. For example, if the display device 150 is a liquid crystal display device, as shown in the equivalent circuit diagram of Figure 29, each pixel 154 is configured to have a switching transistor 176, a capacitive element 178, and a liquid crystal element 180. The gate electrode of the switching transistor 176 is electrically connected to the gate line 172 extending from the scan line drive circuit 156. One terminal of the switching transistor 176 is electrically connected to the signal line 170 extending from the signal line drive circuit 158, and the other terminal is electrically connected to one electrode of the capacitive element 178 and one electrode of the liquid crystal element 180 (pixel electrode). The other electrode of the capacitive element 178 and the other electrode of the liquid crystal element 180 (common electrode) are electrically connected to a common wiring 174 to which a constant potential is supplied. The transistor 100 can be incorporated into each pixel 154 as this switching transistor 176. This makes it possible to provide a display device 150 capable of high-speed response.

[0052] When the display device 150 is an electroluminescent display device, as shown in the equivalent circuit diagram of Figure 30, each pixel 154 is configured to have a switching transistor 198, a driving transistor 200, a capacitive element 202, and a light-emitting element 204. The gate electrode of the switching transistor 198 is electrically connected to the gate line 192 extending from the scan line driving circuit 156. One terminal of the switching transistor 198 is electrically connected to the signal line 190 extending from the signal line driving circuit 158, and the other terminal is electrically connected to one electrode of the capacitive element 202 and the gate electrode of the driving transistor 200. One terminal of the driving transistor 200 is connected to the current supply line 196 to which a constant potential is supplied via terminal 160, and the other terminal is electrically connected to the other electrode of the capacitive element 202 and one electrode (pixel electrode) of the light-emitting element 204. The other electrode (counter electrode) of the light-emitting element 204 is electrically connected to the common wiring 194 to which a constant potential lower than the potential applied to the current supply line 196 is supplied. The transistor 100 can be incorporated into each pixel 154 as either or both of the switching transistor 176 and the driving transistor 200. This makes it possible to provide a display device 150 that is capable of high-speed response and high-brightness display.

[0053] The configuration of each pixel 154 is not limited to the above configuration, and may further include one or more transistors or one or more capacitive elements. In addition, one or all of the additionally arranged transistors may be configured using transistor 100.

[0054] The embodiments described above as embodiments of the present invention can be combined and implemented as appropriate, insofar as they do not contradict each other. Furthermore, any additions, deletions, or design changes to components, or additions, omissions, or changes to processes based on these embodiments, made by those skilled in the art, are also included within the scope of the present invention, as long as they retain the essence of the present invention.

[0055] Any effects or benefits other than those brought about by the embodiments described above, if they are clear from the description herein or easily predictable to a person skilled in the art, are naturally considered to be brought about by the present invention.

[0056] 100: Transistor, 100-1: p-type transistor, 100-2: n-type transistor, 102: Semiconductor film, 102a: Channel, 102b: Drain region, 102c: Low-concentration doped (LDD) region, 102d: Doped region, 104: Gate insulating film, 106: Gate electrode, 108: Interlayer insulating film, 110: Terminal, 112: Terminal, 114: Titanium silicide-containing layer, 120: Amorphous glass substrate, 122: Undercoat, 130: Single crystal semiconductor substrate, 130a: Ion-implanted surface, 132: Embrittlement layer, 134: Electrode, 136: Electrode, 138: Resist 140: Resist mask, 142: Resist mask, 144: Metal film, 146: Metal film, 150: Display device, 152: Array substrate, 154: Pixel, 156: Scan line driving circuit, 158: Signal line driving circuit, 160: Terminal, 170: Signal line, 172: Gate line, 174: Common wiring, 176: Switching transistor, 178: Capacitive element, 180: Liquid crystal element, 190: Signal line, 192: Gate line, 194: Common wiring, 196: Current supply line, 198: Switching transistor, 200: Driving transistor, 202: Capacitive element, 204: Light-emitting element

Claims

1. A transistor comprising: a single-crystal silicon film located on an amorphous glass substrate and having a (100) crystal plane; a gate insulating film on the single-crystal silicon film; a gate electrode on the gate insulating film; an interlayer insulating film on the gate electrode; and a pair of terminals located on the interlayer insulating film and electrically connected to the single-crystal silicon film, wherein the channel length direction is tilted from the [001] crystal axis or [010] crystal axis of the single-crystal silicon film at an angle greater than 0° and 45° or less.

2. The transistor according to claim 1, wherein the oxide film thickness of the gate insulating film is 40 nm or more and 100 nm or less.

3. The transistor according to claim 2, wherein the thickness of the gate electrode is 5 to 10 times the oxide film thickness of the gate insulating film.

4. The transistor according to claim 1, wherein the gate electrode comprises a metal selected from molybdenum, tungsten, tantalum, and titanium.

5. The transistor according to claim 1, wherein each of the pair of terminals comprises a metal selected from titanium, aluminum, molybdenum, and neodymium.

6. The transistor according to claim 1, wherein each of the pair of terminals has a structure in which a film containing aluminum and a film containing titanium are stacked, or a structure in which the film containing aluminum and a film containing molybdenum are stacked.

7. The transistor according to claim 1, wherein each of the pair of terminals has a structure in which a film containing an alloy of aluminum and neodymium and a film containing titanium are laminated, or a structure in which the film containing the alloy of aluminum and neodymium and a film containing molybdenum are laminated.

8. The transistor according to claim 1, further comprising a protective insulating film between the amorphous glass substrate and the single-crystal silicon film.

9. The transistor according to claim 1, wherein the single-crystal silicon film has a titanium silicide-containing layer in contact with the pair of terminals.

10. An electronic device having a transistor as described in claim 1.

11. A method for manufacturing a transistor, comprising: (100) implanting ions from the upper surface of a single-crystal silicon substrate having a crystal plane to form an embrittlement layer, thereby forming a single-crystal silicon film between the upper surface and the embrittlement layer; joining the single-crystal silicon substrate and an amorphous glass substrate so as to sandwich the single-crystal silicon film; peeling the single-crystal silicon substrate from the amorphous glass substrate to transfer the single-crystal silicon film onto the amorphous glass substrate; forming a gate insulating film on the single-crystal silicon film; forming a gate electrode on the gate insulating film; forming an interlayer insulating film on the gate electrode; and forming a pair of terminals located on the interlayer insulating film and electrically connected to the single-crystal silicon film, wherein the gate electrode and the pair of terminals are formed such that the channel length direction is tilted at an angle greater than 0° and 45° or less from the [001] crystal axis or [010] crystal axis of the single-crystal silicon film.

12. The manufacturing method according to claim 11, wherein the oxide film thickness of the gate insulating film is 40 nm or more and 100 nm or less.

13. The manufacturing method according to claim 12, wherein the thickness of the gate electrode is 3 to 10 times the oxide film thickness of the gate insulating film.

14. The method for manufacturing according to claim 11, wherein the gate electrode comprises a metal selected from molybdenum, tungsten, tantalum, and titanium.

15. The manufacturing method according to claim 11, wherein each of the pair of terminals comprises a metal selected from titanium, aluminum, molybdenum, and neodymium.

16. The manufacturing method according to claim 11, wherein each of the pair of terminals has a structure in which a film containing aluminum and a film containing titanium are laminated, or a structure in which the film containing aluminum and a film containing molybdenum are laminated.

17. The manufacturing method according to claim 11, wherein each of the pair of terminals has a structure in which a film containing an alloy of aluminum and neodymium and a film containing titanium are laminated, or a structure in which the film containing the alloy of aluminum and neodymium and a film containing molybdenum are laminated.

18. The manufacturing method according to claim 11, further comprising forming a protective insulating film on the amorphous glass substrate before bonding the single crystal silicon substrate and the amorphous glass substrate, wherein the bonding of the single crystal silicon substrate and the amorphous glass substrate is performed such that the protective insulating film and the single crystal silicon film are sandwiched between the single crystal silicon substrate and the amorphous glass substrate.

19. The method for producing according to claim 11, wherein the ions include hydrogen ions.

20. The manufacturing method according to claim 11, further comprising: forming a pair of openings in the gate insulating film and the interlayer insulating film that expose the single crystal silicon film before forming the pair of terminals; forming a titanium-containing film in contact with the single crystal silicon film at the pair of openings; and performing a heat treatment on the titanium-containing film to silicide a portion of the single crystal silicon film.

Images