Two-dimensional heterostructure graphene field effect transistors with hexagonal boron nitride

Abstract

Two-dimensional atomically thin heterostructure graphene field effect transistors (2D-HGFETs) are described in which a graphene conductive channel is encapsulated within highly insulating hexagonal boron nitride (hBN) layers with one dimensional metal edge contacts. The hBN layers comprise 10B or 11B that is isotopically pure. The 2D-HGFETS have demonstrated effects of remote interfacial phonons at the graphene / hBN interfaces when operated at elevated temperatures that impacts positively the transistor's performance including 1 / ƒnoise.

Description

TWO-DIMENSIONAL HETEROSTRUCTURE GRAPHENE FIELD EFFECT TRANSISTORS WITH HEXAGONAL BORON NITRIDE STATEMENT REGARDING FEDERALLY FUNDED RESEARCH AND DEVELOPMENT

[0001] This invention was made with government support under ECCS CAREER Grant No. 2145962 awarded by the National Science Foundation and DE-NA003525 awarded by the Department of Energy. The government has certain rights in the invention. CROSS-REFERENCE TO RELATED APPLICATION

[0002] This application claims the priority benefit under 35 U.S.C. § 119(e) of U.S. Provisional Patent Application Serial No.63 / 693,060 entitled “TWO-DIMENSIONAL HETEROSTRUCTURE GRAPHENE FIELD EFFECT TRANSISTORS WITH HEXAGONAL BORON NITRIDE” filed September 10, 2024, the entire disclosure of which is incorporated herein by reference. BACKGROUND OF THE INVENTION Field of the Invention

[0003] Embodiments according to the present invention pertain to atomically thin two- dimensional heterostructure graphene field effect transistors (2D-HGFETs) encapsulated in hexagonal boron nitride (hBN). These transistors, which have shown high electronic mobility values with significantly lower electronic noise, can be used in high sensitivity sensors and radio frequency applications. In specific embodiments, 2D-HGFETs with single layer graphene transistor channel and isotopically pure hBN (h10BN, h11BN) as well as natural hBN have been fabricated with edge-contacted (called, one-dimensional (1D)) metal contacts and show low noise and high mobility transistors. The use of natural and isotopic hBN provides noise and mobility engineering in these devices.Discussion of Prior Art

[0004] Field Effect Transistors (FETs) form the basis for modern integrated circuits (ICs), that are the building blocks of every computing and communication devices, where semiconducting materials form the basis for transistor devices. The need for faster and energy efficient microprocessors has enabled continuous development of novel device architectures with the state-of-the art micro / nano-fabrication technologies achieving a node size of ≈3 nm and beyond. However, scaling the device dimensions below 3nm brings added challenges due to various fundamental physical limits, thus demanding a paradigm shift in materials and device fabrication techniques. Two-dimensional (2D) atomically thin materials along with their heterostructures have shown exceptional electrical, optical, mechanical, and thermal properties that provide avenues to innovate newer and smaller devices with promise for delivering higher performance and energy efficiency. However, fundamental understanding of carrier transport in terms of their microscopic origin and their scattering mechanisms are necessary to elucidate the device physics of such 2D transistors. SUMMARY OF THE INVENTION

[0005] The design and fabrication of 2D heterostructure graphene field effect transistor (HGFET) devices are described herein.

[0006] According to one embodiment of the invention there is provided a transistor having a substrate layer comprising a first hexagonal boron nitride (hBN) in which the boron is isotopically pure. The transistor further includes a channel layer comprising a monoatomic graphene layer, and an encapsulation layer that comprises a second hBN in which the boron is isotopically pure.

[0007] According to another embodiment, there is provided a method of producing a transistor. The method comprises providing an encapsulation layer that comprises a first hBN in which the boron is isotopically pure. A monoatomic graphene layer is placed on the encapsulation layer, and a substrate layer comprising a second hBN in which the boron is isotopically pure is placed onto the monoatomic graphene layer.BRIEF OF THE DRAWINGS

[0008] Figure 1 is a schematic representation of an HFETs with graphene encapsulated within hBN and having one-dimensional edge contacts;

[0009] Fig.2 is a high magnification (inset: low magnification) microscope image of the fabricated HFET with hBN as the encapsulating material;

[0010] Figs.3A and 3B show the extracted contribution of RIP scattering as a function of operating temperature in the three graphene HFETs at gate overdrive voltages of 5V and 10V, respectively;

[0011] Fig.4A depicts RIP contribution as a function of temperature in the natural hBN, h11BN, h10BN, and hybrid hBN HFETs; and

[0012] Fig.4B is a schematic model showing the relative contribution of RIP phonons in monoisotopic and natural hBN and the effect on the charge carriers in graphene. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

[0013] Turning initially to Fig.1, according to one embodiment of the present invention there is provided a fabricated 2D-HGFET device 10, where a monoatomic layer graphene layer 16 (called a “channel” layer) is sandwiched between a bottom hBN dielectric layer 14 (called a “substrate” layer) and top hBN layer 12 (called an “encapsulation” layer). In certain embodiments, the hBN comprises natural hBN, hBN that is enriched in10B or11B isotopes, and / or isotopically pure hBN comprising10B or 11B isotopes. As used herein, the term “monoisotopic” or “isotopically pure” means that the element described comprises at least 90%, at least 95%, at least 99%, or substantially all of a single isotope. For example, “isotopically pure boron” means that at least 90%, at least 95%, at least 99%, or substantially all boron present in the compound is made up of the same boron isotope, e.g.,10B or11B.

[0014] In one or more embodiments described herein, any hBN species described in International Patent Application No. PCT / US2024 / 34488, filed June 18, 2024, incorporated by reference herein in its entirety, can be used as the substrate 14 and / or encapsulation layer 12. In particular, the isotopes of boron in the substrate layer 14 and the encapsulation layer 16 may be the same or different in each hBN layer. Additionally, the isotope of nitrogen in each hBN layer in the substrate layer 14 andencapsulation layer 16 may be pure but the invention is not limited to such an embodiment.

[0015] In one or more embodiments, the substrate 14 and encapsulation 16 layers can have a thickness that is individually selected ranging from 10 to 100 nm, 20-50 nm, and preferably about 30 nm thick.

[0016] In one or more embodiments, the device further comprises a source 20 and a drain 18 , each placed at opposed ends of the graphene / hBN stack. The source 20 and drain 18 can be formed from at least one of titanium and gold, and preferably from a metal stack comprising both titanium and gold. The thickness of the titanium may be from 1 to 10 nm, 3 to 8 nm, or 4 to 6 nm. The thickness of the gold may be from 50 to 100 nm, 60 to 90 nm, or 70 to 80 nm. In a particularly preferred embodiment, the metal stack comprises 5 nm of titanium and 80 nm of gold. The composition of the source 20 and drain 18 can be the same, or they can be different.

[0017] In certain embodiments, the graphene / hBN stack, source, and drain are placed on a layer of silicon dioxide 22 having a thickness of from 100-500 nm, 200-400 nm, or preferably about 300 nm. The silicon dioxide 22 layer is itself placed on a heavily doped silicon chip. The heavily doped silicon is called a “gate” electrode and both the silicon dioxide and hBN substrates form the gate dielectrics layer. The gate dielectrics layer may have a thickness of from 230 – 430 nm, 250 – 410 nm, 270 – 390 nm, or 290 – 410 nm. In a preferred embodiment, the gate dielectrics layer has a thickness of about 330 nm.

[0018] In one or more embodiments, the atomic layer stacks of graphene and hBN can be used to fabricate low noise and high performance 2D-HGFETs that can be used in an electronic device, for example, in precision sensing and radio-frequency communication. Any suitable method of fabrication known in the art can be used to fabricate a 2D-HGFETs. However, one preferable method of fabricating device 10 includes providing an encapsulation layer that comprises a first hBN in which the boron is isotopically pure. In particular embodiments, this providing of the encapsulation layer 12 comprises depositing the encapsulation layer onto a support. This support may be comprised of silicon, silicon dioxide, doped silicon, or a mixture thereof. A transfer material is then used to adhere to the encapsulation layer and lift it from the support.The monoatomic graphene layer 16 is laid on the support material. Afterwards the encapsulation layer 12 is then adhered to the monoatomic graphene layer 16 and then lifted off of the support. The substrate layer 14 is then laid onto the support and the combined encapsulation 12 and monoatomic graphene 16 layers are adhered to the encapsulation layer 12 so that the monoatomic graphene layer 16 is disposed between the encapsulation 12 and substrate layers 16.

[0019] Methods of fabricating such devices can also include encapsulating a monoatomic graphene layer between top and bottom hBN layers. The bottom hBN layer is in contact with a silicon dioxide layer located on a heavily doped silicon chip. Electrical leads comprising one dimensional edge contacts are affixed to opposite ends of the graphene / hBN stack using, for example, standard electron beam lithography (EBL) and / or reactive ion etching (RIE). The fabricated device can then be annealed in an H2 / Ar environment at 300°C for 3 hours.

[0020] Variations in electrical mobility in graphene field effect transistors have been traced down to different scattering phenomena that carriers experience while traversing the graphene channel. Recent developments in electrical measurements on two dimensional (2D) heterostructure devices have shown that graphene encapsulated in hexagonal boron nitride (hBN) show enhanced carrier mobility values. Here, graphene heterostructure field effect transistors (HFETs) encapsulated in different isotopically pure hBN (h10BN, h11BN and natural hBN) were fabricated and systematic temperature dependent electrical transport and (1 / f) low frequency noise measurements were performed to study the substrate effect of isotopically pure hBN when used as the encapsulating material for graphene channels. It is observed that monoisotopic hBN with10B and11B isotopes show 4 to 5 × weaker electron – surface polar phonon coupling as compared to natural hBN counterparts. This leads to lower resistivity of graphene channel at elevated temperatures when encapsulated by monoisotopic hBN as compared to graphene channels encapsulated in hBN with natural boron isotopic abundance. Furthermore, 1 / f low frequency measurement (LFN) measurements were performed and the Hooge parameters for the fabricated devices were extracted for the fabricated devices. Lowest noise levels were obtained for devices fabricated forgraphene channel encapsulated by hBN with10B isotope while the highest noise was observed for11B isotope.

[0021] Graphene has been the focus of numerous studies due to its exceptional electrical properties making it a prime candidate for future electronic devices for radio frequency and sensor technologies. Recent developments in 2D heterostructure fabrication measurements have shown improved carrier mobility values when graphene is encapsulated in hexagonal boron nitride (hBN). The observed enhancements primarily arise due to hBN’s atomically flat nature, reduced trapped charges, absence of dangling bonds and an isomorphic lattice structure to graphene. Due to graphene / hBN heterostructures’ promising applications in the fields of electronics, photonics, spintronics, etc., it is important to understand the dynamics of charge carriers in the above-mentioned material systems. Early studies in Si MOSFETs show that channel resistivity and carrier mobility in the Si inversion layer is highly susceptible to surface polar phonon modes at the interface of the oxide and the semiconductor at room temperature. Similar studies on graphene channels fabricated on conventional and high - k dielectrics show that the scattering mechanisms of charge carriers in the channel originate from atomic defects, mechanical imperfections, grain boundaries, electron- phonon couplings, etc. These scattering phenomena have also been observed in graphene and have been broadly classified into short range and long-range scattering effects. Theoretical studies on the above-mentioned scattering mechanisms have been performed detailing the different phonon modes coupling to carriers in the graphene channel and their observable effect on channel conductivity when placed on different substrates (e.g., SiO2, hBN, etc.). Moreover, experimental studies have also confirmed the existence of coupling in between electrons and longitudinal acoustic (LA) phonons of graphene and surface polar phonons in the underlying substrates. In a study performed by Sonntag et.al., the authors performed Hall transport measurements on graphene devices encapsulated in monoisotopic hBN showing higher mobility values for graphene encapsulated with h10BN as compared to h11BN and natural hBN, however, a complete picture about the carrier-phonon coupling in such devices is still missing and needs further investigation.

[0022] Boron in its naturally occurring has a mixture of two isotopes with relative proportions of 20%10B and 80%11B, respectively. Consequently, hBN can be obtained with varying levels of boron abundance where isotopically rich hBN constitutes of ≈ 100% of either10B or11B in hBN. Monoisotopic hBN has a higher thermal conductivity that hBN with the natural distribution of boron isotopes due to reduced phonon scattering caused by isotope disorder. Furthermore, phonons show a faster decay at the interface between graphene and natural hBN as compared to monoisotopic hBN. A recent work on monoisotopic hBN using first principal calculations shows a shift in optical phonon dispersion and density of states between h10BN and h11BN whereas the acoustic modes’ dispersion remains relatively unchanged. Thus, it is important to understand the effects of these changes that stem from isotopic mixing in hBN on device conductivity and mobility when semiconducting channels are fabricated with monoisotopic and natural hBN as substrate and encapsulating materials. Below is described a systematic temperature dependent cryogenic electrical transport study on graphene HFETs fabricated by encapsulating the graphene channel in different isotopically rich hBN and fabricating one dimensional (1D) edge contacts to understand the effect of optical phonon modes at hBN / graphene interface on charge transport in graphene. Additionally, 1 / f low frequency noise measurements were performed on the fabricated devices to investigate the potential effect of monoisotopic hBN on low frequency noise. To measure the low frequency noise in the graphene channel, a measurement technique developed by Barone et al., by incorporating a 2-wire, 4-wire, and a zero-bias noise measurement technique to truly measure the noise originating from the graphene channel.

[0023] Three different hBN–graphene–hBN heterostructure field effect transistors were fabricated using a viscoelastic dry stamping technique with different isotopically pure hBN (natural hBN, h10BN and h11BN). The top and bottom hBN layers encapsulating the single layer graphene (SLG) were both ≈ 30 nm in all the devices. Standard electron beam lithography (EBL) and reactive ion etching (RIE) methods were used to fabricate one dimensional edge contacts after the heterostructure assembly. EBL and RIE were followed by electron–beam metal evaporation and standard liftoff techniques to fabricate metal leads consisting of Ti (5nm) and Au (80nm). FIG.1 shows a schematicdiagram of the fabricated HFETs. All devices were fabricated on thermally grown 300 nm SiO2on top of highly p-doped Si substrate. FIG.2 shows a microscope image of a fabricated HFET using natural hBN as the substrate and the encapsulating material (inset shows low magnification microscope image). Prior to any electrical measurements, all the devices were annealed in H2 / Ar environment at 300◦C for 3 hours.

[0024] To confirm the presence of a single layer of graphene and the encapsulation by appropriate isotopically pure hBN in the heterostructures, Raman spectroscopy measurements were performed using a WiTEC Raman spectrometer with a laser power of 200µW at 100× magnification at a set wavelength of 532 nm. The Raman spectra from h11BN, natural hBN, and h10BN samples show that as the abundance of11B increases, the Raman peak shifts to a lower energy (red shift) with h11BN showing the characteristic E2g peak at 1356.3 cm−1, h10BN at 1393.5 cm−1, and natural hBN at an intermediary location of This shift in line positions in the hBNsamples with different boronconcentration can be attributed to the energy of the vibrating lattice where the frequency or energy of vibration can be approximated as E ∝ω ∝mkwhere k is the bond strength and m are the reduced mass. Additionally, Raman spectrum of an example hBN / graphene / hBN channel, highlighted the E2gpeak of natural hBN, G and 2D peaks of graphene. Notably, the intensity of the G band was significantly lower than the 2D band (IG< I2D) confirming the presence of a single layer graphene.

[0025] Cryogenic electrical transport and low frequency noise measurements were performed at operating temperatures between 10K–300K in a dry He cryostat. The electrical measurement setup was built as per the measurement scheme detailed by Barone et al., to measure both 2-wire and 4-wire transport, and low frequency noise in the electrical channel with a global back gate aided by highly doped Si. Two Keithley 2400 source meters were used to source the required current / voltage for the drain and gate terminals. The source meters were accompanied by low pass RC filters (3dB cutoff frequency fc= 0.3 Hz) to filter out any unwanted spurious noise from the source meters that may cause complications in noise measurements. For the 4-wire measurements,two sense leads were fed to the inputs SRS 560 voltage preamplifier in differential mode with the gain set to ×10 and filter settings set to DC. The voltage difference from the sense leads were read out by an HP 34401 digital multimeter. The voltage output from the preamplifier was also fed into an SR770 network analyzer to record the low frequency power spectral density from the connected device. A separate 2–wire noise measurement was also performed in the similar temperature range by using the drain current signal accompanied by a DL1211 transimpedance amplifier.

[0026] Cryogenic transport measurements of the three fabricated devicesshowed the electrical resistances at different charge neutrality point (CNP) corrected gate voltages in semi–log plots at different operating temperatures for graphene FETs fabricated by encapsulation of natural hBN, h11BN, and h10BN, respectively. The 2–wire resistances are roughly an order of magnitude higher than the measured 4–wire measurements due to added contact resistances. The measured 4–terminal resistance in charge saturation regime is in the range of 200Ω –400Ω for our devices. Characteristics of diffusive transport are observed in the charge saturation regime where the electrical resistivity reduces with the reduction of operating temperature. However, the trend was opposite in the charge residual region where the measured electrical resistance increased with decrease in temperature. This behavior is due to the presence of electron–hole puddles in graphene where the chemical potential in the channel is close to the Dirac point. To understand the effect of temperature on the scattering mechanisms affecting the carrier transport away from the Dirac point, the data in the transport regime away from the Dirac point was further analyzed.

[0027] The field effect mobility in the fabricated devices were calculated by:

[0028] where R is a constant drain-source current (Ids) is sourced in the channel. L and W in equation (1) are the length and width of the graphene channel, respectively. Coxis the gate capacitance per unit area given by (εox / dox) where εoxis the dielectric constant of dielectric and doxis the dielectricthickness. Studies have shown that dielectric capacitance is set by SiO2when an hBN layer is placed in between SiO2and graphene. For a SiO2dielectric of thickness dox = 300 nm and εox = 3×10−11F / m, the obtained Cox is 1×10−4F / m2. The extracted field effect mobility for the fabricated HFETs encapsulated by natural hBN, h11BN, and h10BN, respectively as a function of gate overdrive voltage at different operating temperatures was also found. In the charge saturation region, it was observed that the mobility in the three devices increases with reduction of operating temperature further validating diffusive transport in the graphene channels. Mobility values (µFE) in Natural hBN, h11BN, and h10BN encapsulated devices are ≈ 100,000 cm2 / V.s at 10 K. The mobility values drop to ≈ 40,000 cm2 / V.s, ≈ 60,000 cm2 / V.s, and ≈ 80,000 cm2 / V.s at 300K, respectively. This lowered mobility values at 300K and at higher operating temperatures can be attributed to charge carriers experiencing scattering from different thermally activated phonons. These phonons can be present within the electrical channel (graphene in our case) and at channel / substrate interfaces (graphene / hBN interface in our case). Temperature dependent electrical transport measurement allowed for the study of the thermal population of phonons in and around graphene that contribute towards carrier scattering in the channel thus permitting study of the effects of these electron-phonon interactions between charge carriers in graphene and hBN substrates with different boron isotopic concentrations by performing electrical transport and LFN measurements.

[0029] The sheet resistance of the graphene channel was calculated by:

[0030] where ρ is the resistivity, t is thickness of the electrical channel, W is the width, L is the length, and R is the 4-wire resistance of the graphene channel. The sheet resistance of a graphene channel can be further elaborated as a function of operating temperature as:

[0031] where R0is temperature residual sheet resistance due to defects, imperfections, carrier-carrier scattering, carrier-lattice scattering etc. RL.Arepresents the resistance from the electron-phonon coupling between the electrons in graphene and longitudinal acoustic (L.A) phonons in graphene. RRIPrepresents the resistance arising from electron-phonon coupling between the electrons in graphene and surface polar phonons at the interface between graphene and the substrate and encapsulating hBN. Since we have three different types of hBN we are particularly interested in studying and analyzing RRIPin the fabricated devices to differentiate the effects of surface modes in different isotopically rich hBN. Equation 3 can be further written as:h is the Plank’s constant, ρsis the 2D mass density of graphene ≈ 7.6×10−7kg / m2, vsis the velocity of sound in graphene ≈ 2.1×104m / s, and vfis the fermi velocity of the carriers ≈ 106m / s. In the next section we will discuss about RRIPin detail.

[0033] The surface polar phonon modes in the dielectric medium that couple with electrons / holes in semiconducting channel are different from bulk phonon modes and their characteristic mode frequencies are given by:

[0034] where ωsis theoptical (T.O) phonon mode, ε0and ε∞are the static and optical dielectric permittivities, respectively. The Hamiltonian for carrier-phonon coupling between carriers in graphene and surface phonons in hBN is given by:

[0035] Where q is the momentum vector phonons, M⃗qis the interaction matrix element, ρ⃗qis the operator for 2D electron density in graphene, and b⃗qand b⃗†q are creation and annihilation operators for surface phonons. The interaction element, M⃗q, that defines the strength of interaction between electrons and surface phonons is given as:

[0036] Eq.7 shows that the reduce in z (distance between substrate and graphene) and ⃗q ase−q2qz, which eliminates the possibility for inter-valley scattering induced by RIP scattering. Due to this exponential decay in scattering at larger phonon momenta, we select zone center optical phonon energy values for our further analysis. Acoustic modes are neglected as they possess zero energy at the zone center. The dimensionless coupling parameter g can be defined as:

[0037] where β is proportionality parameter given by the static and optical dielectric permittivity of the phonon mode:

[0038] and a is the C-C bond distance. One can easily deduce from Eq 8 that:

[0039] where the fraction from two polar surface phone modes, used SiO2the relative contribution for the surface polar modes (given by Eq 10) is 1:6.5 for phonon modes of ωs1= 59 meV and ωs2= 155 meV. On the other hand, other commonly used substrate like SiC has a single surface mode of ωs=116 meV. We have performed a similar analysis on bulk and surface hBN phonon properties to get a ratio of 1:1 for hBN for surface modes of 101.6 meV (ZO mode) and 195.7 meV (TO mode), where the experimental values are taken from the following sources.

[0040] Thus, the RIP contribution for hBN in graphene HFETs can be written as:

[0041] RIPscattering. Due to exponentially decaying nature of each of the terms in equation (11), we find the second term has at least an order of magnitude lower contribution in resistance at 300K and can be safely dropped for further analysis). The total temperature dependence of Rshcan now be rewritten as:

[0042] An important inference from the data is that vibrations modes with higher frequencies have lower contribution towards RIP scattering and thus induce lower relative rise in resistance at higher operating temperatures. Another important inferenceis that the resistivity contribution RIP scattering increases exponentially as temperature increases above ≈ 150K. Furthermore, the temperature range below 150K sees LA scattering dominate the resistance contribution. The extracted Rsh in graphene FETs encapsulated by natural hBN, h11BN, and h10BN, respectively was determined as a function of operating temperature at multiple gate overdrive voltages (VG-VCNP). A few important observations can be inferred in the above mentioned Rshvs. temperature plots. The sheet resistance increases as a function of temperature in all the devices confirming diffusive transport at gate overdrive voltages away from the charge neutrality point. Furthermore, an exponential rise in Rshis observed at operating temperatures > 150K which can be attributed to remote interfacial phonon (RIP) scattering. This exponential rise in Rshis more prominent in HFETs encapsulated in hBN of natural type, as compared to monoisotopic hBN, suggesting heavy suppression of RIP scattering in HFETs with monoisotopic hBN. To quantify and extract the RIP scattering in all our devices, we fit our sheet resistance data at gate overdrive voltages away from the charge neutrality point to Eq.13. Furthermore, the data shows Rshvs. temperature for the three types of devices as gate overdrive voltages of 5V and 10V, respectively. The fitted function as per Eq.13 was confirmed to be a good fit to the scattering model. To further investigate the effects of RIP scattering, the RIP scattering contribution in Rshas a function of operating temperature at gate overdrive voltage of 5V and 10V, respectively, were plotted. The data confirmed that ≈ 4-5 × stronger RIP contribution in graphene HFETs encapsulated in natural hBN as compared to isotopically pure hBN. The reduction of RIP scattering contribution from 5 V to 10 V confirms gate overdrive dependence of RIP scattering (B ∝ Vg−1).

[0043] A phenomenological picture to explain the observed RIP scattering behavior in HFETs encapsulated in natural hBN and monoisotopic hBN is presented below. As the reduced mass of natural hBN lies between the reduced mass of h10BN and h11BN, one would expect the RIP contribution from natural hBN to lie between the isotopically pure counterparts. However, the results show a significant deviation in natural hBN’s RIP contribution as compared to monoisotopic counterparts. This large difference in RIP contribution observed between natural hBN and isotopically pure hBN is observed for the first time in this study. This observation implies greater degree of coupling ofelectrons to surface phonons in hBN type, suggesting greater number of low energy surface phonons in natural hBN, which can be explained through band broadening theory. Isotopic mass mixing of10B and11B in natural hBN (typically ≈ 80%11B and 20%10B) leads to broadening of the phonon dispersion compared to individual isotopically pure hBN, thereby distributing available phonon energies in a wider available energy range at fixed phonon momenta. This broadening of the phonon bands can be quantified by adding an energy perturbation (∆) in Bose-Einstein (B.E) population function (for two states separated by ±∆) and can be written as:

[0044] where g = 1, energy constant. A simple mathematical expansion and comparison with B.E statistics for non-broadened case (n) shows: (15)

[0045] Hence, from equation (15) can be observed that larger magnitude of broadening (∆), leads to higher number of phonons in natural hBN and the effect is more prominent with phonons at lower energy (E). Different effects of this phonon broadening like higher phonon decay in natural hBN has previously been studied. These higher number of low energy surface phonons lead to higher RIP scattering of channel electrons in the HFETs encapsulated in natural hBN.

[0046] To further strengthen this understanding, an HFET was fabricated using both natural and an isotopically pure hBN (natural hBN as the substrate to SLG channel and h11BN as top encapsulation), called as a hybrid HFET. Cryogenic transport measurements were studied and the resistivity contribution to RIP scattering was extracted. FIG.4 (a) shows RIP scattering comparison of graphene HFETs with natural hBN, h11BN, and hybrid hBN operated at VG-VCNPof 5V. The RIP contribution of the hybrid HFET is close to that of natural hBN with h11BN showing more than 4 × lowerRIP contribution. This observation that even though the presence of h11BN provides lesser number of low energy phonons in the system, natural hBN on the other side acts as the scattering bottleneck by providing greater number of low energy polar phonons to the graphene channel leading to higher degree of RIP scattering. This observation agrees with phonon broadening phenomena explained above. FIG. 4 (b) shows the phenomenological model of electrons (in the graphene channel) and RIP phonons (in hBN) scattering in both natural and monoisotopic hBN.

[0047] Next, 1 / f low frequency noise (LFN) were measured in the fabricated graphene HFETs using h10BN, h11BN, and natural hBN films as the substrate and as the encapsulant. Noise measurements were performed in both 2-wire and 4-wire device configuration to extract the true channel noise in the above HFET channels. Current noise spectral density (SI) and voltage noise spectral density (SV) were measured in all the devices at a frequency range of 0.4 Hz to 490 Hz to record the three-terminal and five-terminal noise, respectively. One needs to keep in mind that unlike resistance measurement, where a standard combination of 4-terminal measurements gets rid of contact resistance (Rc) during measurement, performing LFN measurements in a 4- terminal measurement does not eradicate the noise from the contacts. A Thevenin equivalent noise analysis as detailed by Barone et al., was used to extract the channel noise in the HFET devices. The obtained channel noise can be represented by: (16)

[0048] where SV, SI, and SRare measured or extracted voltage, current and resistance noise spectral density, respectively. Voltage channel noise (or the noise amplitude) normalized with the device area, given for the three devices by:

[0049] where V is the voltageoperated atdifferent temperatures. Spectra gate overdrive voltage (VG-VCNP) of 9.9V showing the inverse scaling of noise amplitude with respect to frequency (1 / f behavior). The normalized noise amplitude shows reasonable scaling with temperature where the noise levels increase with increasing temperature. This suggests thermally activated traps leading to higher noise according to Hooge’s noise model.

[0050] The noise amplitude for both electron and hole transport can be visualized with respect to the applied gate overdrive voltage (VG-VCNP) by setting a fixed frequency and normalizing the noise amplitude by frequency. It further shows the obtained area and frequency normalized noise spectra for the three graphene HFET devices as a function of VG-VCNPat various operating temperatures and at a set frequency of 30 Hz. The rise in overall noise levels with the increase in device operating temperature can also be observed, further confirming the thermally activated interface traps present in all three types of devices contributing towards the electrical channel noise.

[0051] The net noise in the devices can be quantified by using Hooge’s relation to calculate the Hooge paramater (αH). Hooge’s parameter for the three devices were calculated by:

[0052] where n is the charge density in the graphene channel. Hooge’s parameter is a net noise figure of merit in the device. The data gathered showed the extracted Hooge parameter with respect to obtained carrier mobility for the three HFETs at 80K, 200K, and 300K, respectively for the graphene channels encapsulated by h10BN, h11BN, natural hBN, and hybrid hBN (natural and h11BN. The obtained values for Hooge parameter are between 10−5and 10−2at 80 K and between 10−5and 10−1at 300K showing ultralow levels of low frequency noise in the fabricated HFETs. Furthermore, the inverse power dependence of Hooge parameter with respect to extracted mobility indicates mobility fluctuations originating from thermally activated charge traps for the studied devices. Furthermore, the αHvalues obtained for h11BN encapsulated devices are roughly an order of magnitude higher as compared to h10BN and natural hBN encapsulated devices. This suggests the presence of higher density of traps in h11BNcrystals as compared to h10BN allows future avenues for defect studies in transistor devices using engineered hBN crystals.

[0053] In sum, graphene HFETs encapsulated within hBN with different isotopic concentrations of boron (h10BN, h11BN, and natural hBN) with one dimensional edge contacts were fabricated. By performing temperature dependent cryogenic electrical transport measurements, the profound effects of remote interfacial phonons at graphene / hBN interfaces when HFETs are operated at elevated temperatures have been shown. The effect of remote interfacial phonons on the scattering of charge carriers in the graphene channel is observed to be 4 to 5× higher in HFETs using natural hBN while the lowest RIP scattering was observed in graphene HFETs encapsulated by h10BN. Low frequency measurements on the respective devices also show low Hooge parameter values for graphene HFETs encapsulated within h10BN. Thus, monoisotopic hBN (specifically h10BN) can be used for encapsulating graphene and other 2D materials for electronics due to reduced scattering processes and enhanced electrical performance.

Claims

We claim:

1. A transistor comprising: a substrate layer comprising a first hexagonal boron nitride (hBN) in which the boron is isotopically pure; a channel layer comprising a monoatomic graphene layer; and an encapsulation layer comprising a second hBN in which the boron is isotopically pure.

2. The transistor according to claim 1, further comprising: a source lead in contact with a contact edge of at least the monoatomic graphene layer; and a drain lead in contact with an opposed contact edge of at least the monoatomic graphene layer.

3. The transistor according to claim 2, wherein the source lead and the drain lead comprise a stack including layers of at least gold and / or titanium.

4. The transistor according to claim 2, wherein the stack comprising the source lead and the drain lead comprise both titanium and gold layers, wherein the thickness of the titanium layer is from about 1 to about 10 nm, and wherein the thickness of the gold layer is from about 50 to about 100 nm.

5. The transistor according to claim 1, wherein the substrate layer is from 10 nanometers (nm) and 100 nm thick.

6. The transistor according to claim 1, wherein the encapsulation layer is from 10 nanometers (nm) and 100 nm thick.

7. The transistor according to claim 1, wherein the first hBN and the second hBN comprise the same isotope of boron.

8. The transistor according to claim 1, wherein the first hBN and the second hBN comprise different isotopes of boron.

9. The transistor according to claim 1, wherein the nitrogen of either of the first hBN or the second hBN is isotopically pure.

10. The transistor according to claim 1, wherein the transistor is affixed to a layer of silicon dioxide having a thickness from about 100 nm to about 500 nm.

11. The transistor according to claim 10, wherein the total thickness of the silicon dioxide layer and the substrate layer is from about 230 nm to about 430 nm.

12. An electronic device comprising the transistor of any of claims 1 to 11.

13. A method of producing a transistor comprising: providing an encapsulation layer comprising a first hexagonal boron nitride (hBN) in which the boron is isotopically pure; placing a monoatomic graphene layer on the encapsulation layer; and placing a substrate layer on the monoatomic graphene layer, the substrate layer comprising a second hBN in which the boron is isotopically pure.

14. The method of producing a transistor according to claim 13, wherein the step of providing the encapsulation layer comprises: depositing the encapsulation layer onto a support, and subsequently adhering the encapsulation layer to a transfer material.

15. The method of producing a transistor according to claim 14, wherein the step of placing the monoatomic graphene layer on the encapsulation layer comprises: lifting the encapsulation layer from the support using the transfer material, depositing the monoatomic graphene layer on the support, andadhering the encapsulation layer the monoatomic graphene layer.

16. The method of producing a transistor according to claim 15, wherein the step of placing the substrate layer comprises: lifting the combined encapsulation and monoatomic graphene layers from the support using the transfer material, depositing the substrate layer on the support, and adhering the combined encapsulation and monoatomic graphene layers to the substrate layer so that the monoatomic graphene layer is disposed between the encapsulation layer and the substrate layer.

17. The method of producing a transistor according to claim 16, wherein the support comprises at least one of silicon dioxide and silicon.

18. The method of producing a transistor according to claim 17, wherein the support comprises doped silicon.

19. The method of producing a transistor according to claim 13, wherein the monoatomic graphene layer comprises a one-dimensional edge contact.

20. The method of producing a transistor according to claim 19, wherein the one-dimensional edge contact is formed using electron beam lithography and reactive ion etching.

21. The method of producing a transistor according to claim 13, further comprising: placing a source lead in contact with a contact edge of at least the monoatomic graphene layer; and placing a drain lead in contact with an opposed contact edge of at least the monoatomic graphene layer.

22. The method of producing according to claim 21, wherein the source lead and the drain lead comprise a stack including layers of at least gold and / or titanium.

23. The method of producing a transistor according to claim 22, wherein the stack comprising the source lead and the drain lead comprise both titanium and gold layers, wherein the titanium layer has a thickness of from about 1 to about 10 nm, and wherein the gold layer has a thickness of from about 50 to about 100 nm.

24. The method of producing a transistor according to claim 13, wherein the substrate layer is from 10 nanometers (nm) and 100 nm thick.

25. The method of producing a transistor according to claim 13, wherein the encapsulation layer is from 10 nanometers (nm) and 100 nm thick.

26. The method of producing a transistor according to claim 13, wherein the first hBN and the second hBN comprise the same isotope of boron.

27. The method of producing a transistor according to claim 13, wherein the first hBN and the second hBN comprise different isotopes of boron.

28. The method of producing a transistor according to claim 13, wherein the nitrogen of either or both of the first hBN and the second hBN is isotopically pure.

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