Power semiconductor device, power supply circuit, and electronic device

Abstract

The present application relates to a power semiconductor device, a power supply circuit, and an electronic device. The power semiconductor device comprises a power semiconductor device body, a signal processing circuit and a gate port, wherein the power semiconductor device body comprises a first gate structure and a second gate structure independent of each other, the first gate structure comprising a first gate electrode, the second gate structure comprising a second gate electrode, the first gate electrode being connected to the gate port, and the second gate electrode being connected to the gate port by means of the signal processing circuit; the gate port is used for connecting to an external circuit and loading for the first gate electrode and the second gate electrode a control signal provided by the external circuit; the signal processing circuit is used for processing the control signal and then loading the processed control signal onto the second gate electrode; and under the control of the control signal, the first gate electrode and the second gate electrode are used for controlling the state of the power semiconductor device body and reducing the switching loss of the power semiconductor device body. The power semiconductor device provided in the present application has fewer ports and exhibits low loss.

Description

Power semiconductor device, power supply circuit, and electronic device

[0001] This application claims priority to the Chinese patent application No. 202411322177.3, filed on September 20, 2024, entitled “Power semiconductor device, power supply circuit, and electronic device”, the entire content of which is incorporated herein by reference. TECHNICAL FIELD

[0002] The present application relates to a power semiconductor device, in particular to a power semiconductor device, a power supply circuit, and an electronic device. BACKGROUND

[0003] In a power semiconductor device, a double-gate power semiconductor device is widely used in new energy vehicles, rail transit, charging piles, power grids, home appliances, rail transit, data storage, photovoltaic, industrial control, energy storage, and consumer electronics, etc. due to its high efficiency, high reliability, and long life. However, the double-gate power semiconductor device has more ports, which increases the design difficulty of the control circuit, and the switching loss needs to be reduced. SUMMARY

[0004] Embodiments of the present application provide a power semiconductor device, a power supply circuit, and an electronic device to further reduce the loss of the double-gate power semiconductor device.

[0005] In a first aspect, embodiments of the present application provide a power semiconductor device. The device can be a Lateral Double-diffused Metal Oxide Semiconductor (LDMOS), an Insulated Gate Bipolar Transistor (IGBT), a Shield Gate Trench MOSFET (SGT), a MOSFET in a Driver and MOSFET (DrMOS), etc. The device can include a power semiconductor device body, a signal processing circuit, and a gate port. The power semiconductor device body includes a first gate structure and a second gate structure that are independent of each other. The first gate structure includes a first gate electrode, and the second gate structure includes a second gate electrode. The first gate electrode is connected to the gate port, and the second gate electrode is connected to the gate port through the signal processing circuit. The gate port is used to connect to an external circuit, and load a control signal provided by the external circuit to the first gate electrode and the second gate electrode. The signal processing circuit is used to load a processed control signal to the second gate electrode. The first gate electrode and the second gate electrode are used to control the state of the power semiconductor device body under the control of the control signal, and reduce the switching loss of the power semiconductor device body. In the power semiconductor device provided by the embodiments of the present application, the second gate electrode is connected to the gate port through the signal processing circuit, so that both gate structures can be connected to the external circuit through one gate port and can be controlled individually without increasing additional ports. This not only realizes the same number of ports for the power semiconductor device with multiple gates as for the power semiconductor device with single gate, but also reduces the design difficulty of the control circuit of the power semiconductor device, optimizes the dynamic characteristics of the power semiconductor device with multiple gates, and reduces the switching loss thereof.

[0006] In a possible implementation, the signal processing circuit includes a first delay circuit, and the second gate electrode is connected to the gate port through the first delay circuit. The first delay circuit is used to load a processed control signal to the second gate electrode. The first gate electrode generates a first voltage signal under the action of the control signal, and the second gate electrode generates a second voltage signal under the action of the signal loaded by the first delay circuit. In the on stage of the above device, the second voltage signal rises to a high level when the first voltage signal reaches the Miller platform, which can reduce the on loss of the device.

[0007] In a possible implementation, the signal processing circuit further includes a first chopper circuit, the second gate electrode is connected to the first delay circuit through the first chopper circuit, the first chopper circuit is configured to load the signal loaded by the first delay circuit on the second gate electrode after chopping processing, and the second voltage signal is generated by the second gate electrode under the action of the signal loaded by the first chopper circuit. In the off stage of the device, the second voltage signal drops to a low level when the first voltage signal ends the Miller platform, so that the turn-on loss of the device can be reduced while the turn-off loss of the device is reduced.

[0008] In a possible implementation, the signal processing circuit further includes a level shift circuit, the second gate electrode is connected to the first chopper circuit through the level shift circuit, the level shift circuit is configured to load the signal loaded by the first chopper circuit on the second gate electrode after level shift processing, and the second voltage signal is generated by the second gate electrode under the action of the signal loaded by the level shift circuit. Moreover, the low level is a negative voltage, so that the turn-on loss of the device can be reduced while the turn-off loss of the device is further reduced.

[0009] In a possible implementation, the signal processing circuit further includes a second chopper circuit, the second gate electrode is connected to the level shift circuit through the second chopper circuit, the second chopper circuit is configured to load the signal loaded by the level shift circuit on the second gate electrode after chopping processing, and the second voltage signal is generated by the second gate electrode under the action of the signal loaded by the second chopper circuit. The second voltage signal rises to 0 volts after the duration of the low level reaches a preset length. In this implementation, the duration of the low level of the second voltage signal is controlled by the second chopper circuit, so that the minimum voltage of the second voltage signal in the on stage of the device is 0 volts, thereby further reducing the turn-off loss of the device while avoiding increasing the turn-on loss of the device.

[0010] In a possible implementation, the signal processing circuit further includes a third chopper circuit, the second gate electrode is connected to the level shift circuit through the third chopper circuit, the third chopper circuit is configured to load the signal loaded by the level shift circuit on the second gate electrode after chopping processing, and the second voltage signal is generated by the second gate electrode under the action of the signal loaded by the third chopper circuit. The second voltage signal drops to 0 volts after the duration of the high level reaches a preset length, so that the turn-off loss of the device can be further reduced while avoiding using too many passive devices to maintain the high level, thereby reducing the area of the device and further improving the performance of the device.

[0011] In a possible implementation, the first gate electrode is connected to the gate port through the signal processing circuit, and the signal processing circuit further includes a second delay circuit, the first gate electrode is connected to the gate port through the second delay circuit, the second delay circuit is configured to perform delay processing on the control signal and load the processed signal on the first gate electrode, and the first voltage signal is generated by the first gate electrode under the action of the signal loaded by the second delay circuit. In the turn-off stage of the device, the second voltage signal is lowered to a low level when the Miller platform of the first voltage signal ends, so that the turn-off loss of the device can be reduced.

[0012] When the power semiconductor device is a discrete device such as an IGBT, a MOSFET (such as a Vertical Double-diffused Metal Oxide Semiconductor Field Effect Transistor (VDMOS) and an SGT), and the like, a packaging shell can be further included, the power semiconductor device body and the signal processing circuit are located in the packaging shell, and the gate port is arranged on the packaging shell.

[0013] The power semiconductor device can also be integrated in a DrMOS, and the gate port can be connected to a driver in the DrMOS, so that the DrMOS has lower loss and smaller size.

[0014] The power semiconductor device is mainly applied to the field of low-voltage and large-current, for example, a server using a Power Supply in a Package (PSiP) packaging technology, an Information and Communications Technology (ICT) chip, an Artificial Intelligence (AI) chip, and a smart phone, a portable android device (PAD), a smart wearable device, and a vehicle-mounted device having a low-voltage and large-current fast charging function.

[0015] In a second aspect, the embodiments of the present application provide a power supply circuit, including the device of any one of the first aspect. The power supply circuit can be a power supply circuit in a power supply using a PSiP packaging, or a power supply circuit of an ICT chip, an AI chip, and a smart phone, a portable android device (PAD), a smart wearable device, and a vehicle-mounted device having a low-voltage and large-current fast charging function.

[0016] In a third aspect, the embodiments of the present application provide an electronic device comprising the power supply circuit of any one of the second aspect. The electronic device can be a server with a PSiP package, a smartphone, a PAD, a smart wearable device, a vehicle-mounted device, etc. with a low-voltage high-current fast charging function. BRIEF DESCRIPTION OF DRAWINGS

[0017] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed in the embodiments will be briefly introduced as follows. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without creative labor.

[0018] FIG. 1 is a structural schematic diagram of an example of a power semiconductor device provided by the embodiments of the present application;

[0019] FIG. 2a is another structural schematic diagram of a power semiconductor device provided by the embodiments of the present application;

[0020] FIG. 2b is another structural schematic diagram of a power semiconductor device provided by the embodiments of the present application;

[0021] FIG. 3a is a structural schematic diagram of an example of a body in a power semiconductor device provided by the embodiments of the present application;

[0022] FIG. 3b is a structural schematic diagram of an LDMOS;

[0023] FIG. 3c is another structural schematic diagram of a body in a power semiconductor device provided by the embodiments of the present application;

[0024] FIG. 4a is another structural schematic diagram of a power semiconductor device provided by the embodiments of the present application;

[0025] FIG. 4b is another structural schematic diagram of a power semiconductor device provided by the embodiments of the present application;

[0026] FIG. 5a is a schematic diagram of an example of a power semiconductor device provided by the embodiments of the present application;

[0027] FIG. 5b is a schematic diagram of a voltage signal generated by a gate electrode in the device shown in FIG. 5a;

[0028] FIG. 6a is another schematic diagram of a power semiconductor device provided by the embodiments of the present application;

[0029] FIG. 6b is a schematic diagram of a voltage signal generated by a gate electrode in the device shown in FIG. 6a;

[0030] FIG. 7a is another schematic diagram of a power semiconductor device provided by the embodiments of the present application;

[0031] Fig. 7b is a schematic diagram of a voltage signal generated by the gate electrode in the device shown in Fig. 7a;

[0032] Fig. 8a is a schematic diagram of another example of a power semiconductor device according to an embodiment of the present application;

[0033] Fig. 8b is a schematic diagram of a voltage signal generated by the gate electrode in the device shown in Fig. 8a;

[0034] Fig. 9a is a schematic diagram of another example of a power semiconductor device according to an embodiment of the present application;

[0035] Fig. 9b is a schematic diagram of a voltage signal generated by the gate electrode in the device shown in Fig. 9a;

[0036] Fig. 10 is a schematic diagram of yet another example of a power semiconductor device according to an embodiment of the present application;

[0037] Fig. 11a is a schematic diagram of still another example of a power semiconductor device according to an embodiment of the present application;

[0038] Fig. 11b is a schematic diagram of a voltage signal generated by the gate electrode in the device shown in Fig. 11a;

[0039] Fig. 12 is a schematic diagram of an application of a power semiconductor device according to an embodiment of the present application. DETAILED DESCRIPTION

[0040] In order to better understand the technical solutions of the present application, the embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0041] Fig. 1 is a schematic diagram of an example of a power semiconductor device according to an embodiment of the present application. As shown in Fig. 1, the power semiconductor device includes a power semiconductor device body, a signal processing circuit, a gate port G, a source port S and a drain port D. The power semiconductor device body includes a first gate electrode G1, a second gate electrode G2, a source electrode and a drain electrode. There is one of each of the gate port G, the source port S and the drain port D. The gate port G is connected to the first gate electrode G1 and connected to the second gate electrode G2 through the signal processing circuit, the source port S is connected to the source electrode, and the drain port D is connected to the drain electrode. Among them, one end of the signal processing circuit connected to the gate port G is the input end, and one end connected to the second gate electrode G2 is the first output end.

[0042] The power semiconductor device body can be an N-type MOS, as shown in Fig. 2a.

[0043] The power semiconductor device body can also be a P-type MOS, as shown in Fig. 2b.

[0044] When the power semiconductor device provided by the embodiment of the present application is a MOSFET, the power semiconductor device body is a MOSFET body. One structure of the MOSFET body is shown in FIG. 3a, which includes a semiconductor substrate, a semiconductor active layer, a semiconductor body region, a source structure, a drain structure, a first gate structure and a second gate structure 12. The semiconductor active layer is located on the semiconductor substrate, and the source structure, the drain structure, the first gate structure and the second gate structure 12 are located on the semiconductor active layer.

[0045] The source structure includes a source electrode S, two source contact regions and a body contact region. The source electrode S is located on the two source contact regions and the body contact region, and the lower surface thereof is connected with the two source contact regions and the body contact region. The two source contact regions and the body contact region are located in the semiconductor body region, and the body contact region is located between the two source contact regions.

[0046] The first gate structure has two, including a trench gate structure 111 and a planar gate structure 112. The trench gate structure 111 and the planar gate structure 112 are located on both sides of the source structure, and the planar gate structure 112 is located between the source structure and the drain structure. The trench gate structure 111 longitudinally extends into the semiconductor active layer and contacts the semiconductor body region. The trench gate structure 111 includes a gate electrode G11, a trench gate dielectric and a conductive material surrounded by the trench gate dielectric. The planar gate structure 112 includes a gate electrode G12 and a planar gate dielectric. The gate electrode G11 is connected with the gate electrode G12 through a metal wire, so that the trench gate structure 111 and the planar gate structure 112 are equipotential. The second gate structure 12 includes a gate electrode G2 and a trench gate dielectric surrounding the gate electrode G2. The first gate structure and the second gate structure 12 are separated by the trench gate dielectric and are independent of each other. Among them, the gate electrode G11 and the gate electrode G12 are the first gate electrode, and the gate electrode G2 is the second gate electrode.

[0047] The drain structure includes a drain electrode D and a drain contact region, part of the drain contact region is located in the semiconductor active layer, and the other part is located between the semiconductor substrate and the semiconductor active layer.

[0048] Among them, the semiconductor substrate, the semiconductor body region and the body contact region are of a first conductive type, and the semiconductor active layer, the two source contact regions and the drain contact region are of a second conductive type. When the first conductive type is N-type, the second conductive type is P-type; when the first conductive type is P-type, the second conductive type is N-type.

[0049] When the power semiconductor device provided by the embodiments of the present application is an LDMOS, the power semiconductor device body is an LDMOS body. The LDMOS is an integrated lateral power device, which can be used in the field of smart power integrated circuits (SPiCs) in automotive electronics, flat panel display, switching power supply, motor drive, industrial control, power management, etc.

[0050] Another structure of the LDMOS body is shown in FIG. 3c, which includes a substrate, a first body region, a drift region, a second body region, a source region, a drain region, a field oxide layer, a source electrode S, a first gate electrode G1, a silicide blocking layer, a second gate electrode G2 and a drain electrode D. The first body region and the second body region are of a first conductivity type, and the source region, the drift region and the drain region are of a second conductivity type. The first body region and the drift region are located on the substrate. The second body region and the source region are located in the first body region. The first body region is tangent to the left side of the drift region, and the drain region is located in the drift region. The field oxide layer is located on the first body region and the drift region. In the field oxide layer, the source electrode S, the first gate electrode G1, the silicide blocking layer, the second gate electrode G2 and the drain electrode D are sequentially arranged. Moreover, the source electrode S is located on the second body region and the source region, the left side of the first gate electrode G1 is located on the same vertical line as the right side of the source region, the silicide blocking layer overlaps the first gate electrode G1, the second gate electrode G2 is located on the silicide blocking layer, and the drain electrode is located on the drain region. The first gate electrode G1 and the field oxide layer form a first gate structure 31, and the second gate electrode G2 and the field oxide layer form a second gate structure 32. The first gate structure 31 and the second gate structure 32 are isolated by the silicide blocking layer and are independent of each other.

[0051] The second gate electrode G2 is separated from the source field plate in the LDMOS shown in FIG. 3b. The source field plate shown in FIG. 3b is used to reduce the surface field to optimize the static characteristics of the device. Separating the source field plate as the second gate electrode and separately setting the voltage of the second gate electrode when the device is turned off or on can optimize the dynamic characteristics of the device. For example, for the NLDMOS, in the off state, by setting the second gate electrode to a negative potential, it assists the drift region to be depleted, which helps the device to achieve the expected withstand voltage at a higher drift region concentration, thereby achieving the purpose of not reducing the device withstand voltage, but increasing the on-state current and reducing the on-state resistance Ron,sp.

[0052] It can be understood that the power semiconductor device body in the embodiments of the present application is not limited to the content shown in the above embodiments, and can include more or fewer structures or parts. For example, the first gate structure can be more than two, and / or the second gate structure can also be more than one, etc.

[0053] Figure 4a is a schematic diagram of another example of a power semiconductor device according to an embodiment of the present application. As shown in Figure 4a, in this embodiment, the power semiconductor device body in the power semiconductor device is the MOSFET body shown in Figure 3a. The signal processing circuit is integrated in the semiconductor device, the gate port G is connected to the first gate electrode (gate electrodes G11 and G12) through a metal wire, and is connected to the second gate electrode (gate electrode G2) through the signal processing circuit.

[0054] Figure 4b is a schematic diagram of yet another example of a power semiconductor device according to an embodiment of the present application. As shown in Figure 4a, in this embodiment, the power semiconductor device body in the power semiconductor device is the LDMOS body shown in Figure 3c. The gate port G is connected to the first gate electrode G1 through a metal wire, and is connected to the second gate electrode G2 through the signal processing circuit.

[0055] In some embodiments, the power semiconductor device further comprises a package shell, such as the package shell 41 shown in Figure 4a, the package shell 42 shown in Figure 4b, and the like. The package shell encapsulates the power semiconductor device body and the signal processing circuit inside, and the gate port G, the source port S (the interface of the source electrode S to the outside), and the drain port D (the interface of the drain electrode D to the outside) are pins extending out of the package shell.

[0056] The power semiconductor device provided by the above embodiments enables different control of the first gate electrode and the second gate electrode by providing the signal processing circuit connected between the gate port and the second gate electrode in the device, so that the external circuit only needs to provide one gate control signal, thereby achieving the purpose of further optimizing the dynamic characteristics of the power semiconductor device and reducing the switching loss without adding additional ports.

[0057] Figure 5a is a schematic diagram of an example of a power semiconductor device according to an embodiment of the present application. In this embodiment, the power semiconductor device body is an N-type MOSFET, which includes a first gate electrode G1 and a second gate electrode G2, and the signal processing circuit is a first delay circuit. The gate port G is connected to the second gate electrode G2 through the first delay circuit, and is connected to the first gate electrode G1 through a metal wire.

[0058] When a voltage signal Vin as shown in Figure 5b is applied to the gate port G, the first gate electrode G1 generates a voltage signal V G1 under the action of Vin as shown in Figure 5b. After being processed by the first delay circuit, Vin causes the second gate electrode G2 to generate a voltage signal V G2 .

[0059] As shown in Figure 5b, V G2 is delayed from Vin by a time t0, and in the device opening stage, V G1Enter the Miller platform at time t1, and V at time t2. G1 After the Miller plateau ends, at time t3, the first gate electrode G1 is charged to the operating voltage V. H (that is, V) G1 Upgrade to V H At time t4, the device begins to turn off, and Vin and V G1 It begins to decline, at time t5 V G1 Entering the Miller platform, at time t6, V G1 End of Miller platform, at time t7 V G1 Reduced to 0 volts, V G2 Compared to V G1 The duration for the time to drop to 0 early is t8.

[0060] The power semiconductor device provided in this embodiment delays the voltage signal at the gate port through a first delay circuit, so that the second gate, during the device turn-on phase, delays the voltage signal V at the first gate electrode. G1 A positive voltage is generated upon entering the Miller plateau, which charges the drift region of the auxiliary device, i.e., it charges the internal parasitic capacitance C of the device. GD Charging accelerates the device's turn-on speed and reduces turn-on losses. Specifically, when t0 > 0 and t0 = t1, the turn-on losses are even lower. The power semiconductor device provided in this embodiment reduces switching losses and optimizes device switching characteristics without adding additional ports, making it easier to apply in integrated circuit design.

[0061] Figure 6a is another schematic diagram of the power semiconductor device provided in this application embodiment. Based on the embodiment shown in Figure 5a, the power semiconductor device provided in this embodiment further includes a first chopper circuit. The first delay circuit is connected to the second gate electrode G2 through the first chopper circuit.

[0062] When a voltage signal Vin is applied to the gate port G, under the action of the first delay circuit and the first chopper circuit, the second gate electrode G2 generates a voltage signal V as shown in Figure 6b. G2 .

[0063] As shown in Figure 6b, during the device turn-off phase, V G2 Compared to V shown in Figure 5b G2 The V shown in Figure 6b G2 It drops to 0 before t6, that is, before the first gate electrode voltage signal V. G1 When the Miller plateau is about to end, the second gate electrode is turned off, prematurely discharging the carriers modulated by the second gate electrode, assisting the depletion of the drift region, accelerating the device turn-off speed, and reducing the device turn-off loss. Specifically, when t8 = t7 - t6, or in other words, V... G2 When t6 drops to 0 volts, the device turn-off loss is lower.

[0064] Fig. 7a is a schematic diagram of another example of the power semiconductor device according to an embodiment of the present application. The power semiconductor device according to the present embodiment further comprises a level shift circuit based on the power semiconductor device according to the embodiment shown in Fig. 6a. The first chopper circuit is connected to the second gate electrode G2 through the level shift circuit.

[0065] When a voltage signal Vin is applied to the gate port G, the second gate electrode G2 generates a voltage signal V G2 as shown in Fig. 7b under the action of the first delay circuit, the first chopper circuit and the level shift circuit. Compared with the V G2 shown in Fig. 6b, the voltage signal V G2 shown in Fig. 7b is 0 volt during the period from 0 to t0 in the device opening stage, and rises from a negative voltage V L to 0 volt at the moment t7-t8 in the device closing stage, and falls to the negative voltage V L before the moment t7. The absolute value of V L is determined by the actual circuit implementation.

[0066] The power semiconductor device according to the present embodiment further makes the voltage signal generated on the second gate electrode fall to a negative voltage at the device closing stage through the action of the level shift circuit, which further assists the drift region depletion, further reduces the device closing loss, and optimizes the dynamic characteristics of the device.

[0067] Fig. 8a is a schematic diagram of another example of the power semiconductor device according to an embodiment of the present application. The power semiconductor device according to the present embodiment further comprises a second chopper circuit based on the power semiconductor device according to the embodiment shown in Fig. 7a. The level shift circuit is connected to the second gate electrode G2 through the second chopper circuit.

[0068] When a voltage signal Vin is applied to the gate port G, the second gate electrode G2 generates a voltage signal V G2 as shown in Fig. 8b under the action of the first delay circuit, the first chopper circuit, the level shift circuit and the second chopper circuit. Compared with the V G2 shown in Fig. 7b, the voltage signal V G2 shown in Fig. 8b is 0 volt during the period from 0 to t0 in the device opening stage, and rises from a negative voltage V L at the moment t7 in the device closing stage.

[0069] The power semiconductor device according to the present embodiment further makes the second gate electrode rise to 0 volt at the device closing stage through the action of the second chopper circuit, so that the lowest voltage of the second gate electrode at the next device opening stage is 0 volt, which avoids the increase of the device opening loss caused by the charging of the second gate electrode from a negative voltage at the device opening stage.

[0070] Figure 9a is another schematic diagram of a power semiconductor device according to an embodiment of the present application. The power semiconductor device according to the present embodiment is different from the embodiment shown in Figure 8a in that the level shift circuit is connected to the second gate electrode G2 through a third chopper circuit.

[0071] When a voltage signal Vin is applied to the gate port G, the second gate electrode G2 generates a voltage signal V G2 as shown in Figure 9b under the action of the first delay circuit, the first chopper circuit, the level shift circuit and the third chopper circuit. G2 Compared with V G2 shown in Figure 8b, the voltage signal V H shown in Figure 9b rises to the working voltage V G2 in the device opening stage, and then starts to drop after a time length t9, and drops to 0 volt before t3, which avoids using too many passive devices to maintain the high level of the second gate electrode, helps to reduce the size of the device, and can further assist the device drift region carrier discharge, reduce the off loss and improve the device performance. In particular, when t9>t2-t1, the effect is better.

[0072] In some embodiments, the first chopper circuit and the third chopper circuit are the same, so as to reduce the size of the internal integrated signal processing circuit of the low-loss lateral power semiconductor device provided by the present application.

[0073] In the device shown in the above embodiments, the high / low level duty cycle of the second gate timing signal V G2 can be changed by adjusting the delay circuit and the chopper circuit, so that the switching loss of the device is minimized, and the device can achieve the optimal working state in dynamic performance.

[0074] Figure 10 is another schematic diagram of a power semiconductor device according to an embodiment of the present application. The power semiconductor device according to the present embodiment is different from the above embodiments in that the gate port G is further connected to the first gate electrode G1 through a signal processing circuit. One end of the signal processing circuit connected to the first gate electrode G1 is a second output end.

[0075] Figure 11a is another schematic diagram of a power semiconductor device according to an embodiment of the present application. The power semiconductor device according to the present embodiment is different from the device shown in Figure 5a in that the signal processing circuit further includes a second delay circuit, and the gate port G is connected to the first gate electrode G1 through the second delay circuit.

[0076] When a voltage signal Vin is applied to the gate port G, the first gate electrode G1 generates a voltage signal V G1 as shown in Figure 9b under the action of the second delay circuit. As shown in Figure 9b, in the device opening stage, V G1Relative to Vin, delay to t11, start to rise from 0 volts, to t12, reach the Miller plateau, end the Miller plateau at t13, rise to the working voltage V at t14 H In the device off phase, V G1 Relative to Vin, delay to t15, start to drop from V H , reach the Miller plateau at t16, end the Miller plateau at t17, drop to 0 volts at t18, compared to the time when V G2 drops to 0 volts, it is delayed backward by a time t8, and t8>t18-t17, it can be seen that V G2 drops to 0 volts before the end of the Miller plateau, achieving the purpose of reducing the off loss of the device. G1

[0077] It can be understood that the power semiconductor device provided by the embodiments of the present application is not limited to the device provided by the above-mentioned embodiments. For a specific semiconductor device, the selection of the delay circuit, the chopping circuit and the level shift circuit can be determined according to the size of the Miller plateau and the size of the input signal delay. For example, on the basis of the device shown in FIG. 11a, a chopping circuit is further added, which can be arranged between the first delay circuit and / or the second delay circuit and the corresponding first gate electrode and / or the second gate electrode according to the actual situation, so as to achieve the purpose of reducing the switching loss.

[0078] In some embodiments, any of the above-mentioned power semiconductor devices can also be used for DrMOS. Among them, the above-mentioned power semiconductor device is integrated with a gate driver, and the gate port is connected with the gate driver of the DrMOS, so as to realize higher power supply efficiency through the DrMOS integrated with the above-mentioned power semiconductor device, and meet the demand of the processor (including microprocessor) for higher power supply current and power density in the development of artificial intelligence technology.

[0079] ​The power semiconductor device provided by the embodiments of the present application can adjust and process the signal loaded on the gate port through the signal processing circuit, so that the signal acting on the first gate electrode and the second gate electrode can be flexibly adjusted according to the requirement, thereby changing the dynamic characteristics of the lateral power device, reducing the parasitic capacitance, and achieving the purpose of reducing the switching loss. The device provided by the above embodiments can flexibly control the mutually independent first gate electrode and the second gate electrode through the signal processing circuit, thereby reducing the parasitic capacitance of the device (such as LDMOS), further accelerating the opening / closing speed of the device, and reducing the opening / closing loss of the device. For integrated circuit design, the structure of the power semiconductor device can avoid introducing a new port by the second gate structure, reduce the difficulty of integrated circuit design, thereby meeting the high-frequency and miniaturization requirements of the high-speed development of intelligent integrated power supply. Moreover, accelerating the opening / closing speed of the device can reduce the adverse effects of the trade-off problem of on-resistance and parasitic capacitance on the device, and meet the application requirements of LDMOS in the low-voltage and large-current field such as servers, DrMOS, ICT chips, AI chips, etc.

[0080] The power supply circuit provided by the embodiments of the present application includes the power semiconductor device provided by any of the above embodiments. The power supply circuit can be a power module adopting PSiP packaging, SPiC, a direct current-direct current conversion (DC-DC) module, a rectification and filtering circuit, a power conversion circuit, etc. By adopting the low-power power semiconductor device, the power supply circuit can further reduce its own power consumption, and the device has fewer ports (three ports), which is beneficial to reduce the design difficulty of the power supply circuit and reduce the size of the power supply circuit. As shown in FIG. 12, a non-isolated DC-DC module adopts an embedded chip / component package (ECP) and has the advantages of high density and high integration. By adopting the power semiconductor device provided by the above embodiments, the loss can be reduced, the circuit design difficulty can be reduced, and the size of the module can be further reduced, such as the length and width of the module can be less than 11 mm, and the height of the module can be less than 4 mm.

[0081] The electronic device provided by the embodiments of the present application includes any of the above power supply circuits. The electronic device includes a functional module and any of the above power supply circuits. The functional module can include a processor, a memory, and other electronic processing circuits for realizing the functions of the electronic device. The electronic device can be a server, a mobile phone, a portable computer, a smart wearable device, a vehicle-mounted device, or other devices that require low-voltage and large-current as energy. It can be understood that in some embodiments, the electronic device can include a housing, a fixing component, and other auxiliary parts in addition to the aforementioned functional module and power supply circuit, which are not limited here and can be different according to actual conditions or requirements. The electronic device provided by the embodiments of the present application adopts the above power supply circuit, has lower energy consumption and smaller size, and is beneficial to energy saving and space saving.

[0082] It should be apparent that the embodiments described herein are merely a few examples and not all possible embodiments. Based on the embodiments described herein, all other embodiments obtained by those of ordinary skill in the art without creative work are within the scope of the present application.

[0083] The terms used in the embodiments of the present application are merely for the purpose of describing particular embodiments and are not intended to limit the present application. The singular forms "a," "an," and "the" used in the embodiments of the present application and the appended claims are intended to include plural forms as well, unless the context clearly indicates otherwise. The term "and / or" used herein merely describes an association between associated objects, and means that there can be three relationships, for example, A and / or B can mean that A exists alone, A and B exist together, and B exists alone. In addition, the character " / " used herein generally means that the associated objects before and after are in an "or" relationship. The terms "first", "second", and "third" used herein are not necessarily used to describe a particular order or chronological order, and it should be understood that the data thus used can be interchanged under appropriate circumstances, so that the embodiments described herein can be implemented in an order other than that illustrated or described herein. For example, "first delay circuit" and "second delay circuit" can be two circuits that are the same in structure and device, or two circuits that are the same in structure and different in device, or two circuits that are different in structure and the same in device, or two circuits that are different in structure and device.

[0084] The same or similar parts among various embodiments in the specification can be referred to each other.

Claims

1. A power semiconductor device, characterized by The application relates to a power semiconductor device, which comprises a power semiconductor device body, a signal processing circuit and a gate port. The power semiconductor device body comprises a first gate structure and a second gate structure, the first gate structure comprises a first gate electrode, the second gate structure comprises a second gate electrode, the first gate electrode is connected with the gate port, and the second gate electrode is connected with the gate port through the signal processing circuit. The gate port is used for being connected with an external circuit, and the first gate electrode and the second gate electrode are used for loading a control signal provided by the external circuit, the signal processing circuit is used for processing the control signal and loading the second gate electrode, and the first gate electrode and the second gate electrode are used for controlling the state of the power semiconductor device body under the control of the control signal and reducing the switching loss of the power semiconductor device body. The signal processing circuit comprises a first delay circuit, the second gate electrode is connected with the gate port through the first delay circuit, and the first delay circuit is used for delaying the control signal and loading the second gate electrode. The first gate electrode generates a first voltage signal under the action of the control signal, and the second gate electrode generates a second voltage signal under the action of the signal loaded by the first delay circuit.

2. The device of claim 1, wherein, In the opening stage of the device, the second voltage signal rises to a high level when the first voltage signal reaches the Miller platform. The signal processing circuit further comprises a first chopper circuit, the second gate electrode is connected with the first delay circuit through the first chopper circuit, the first chopper circuit is used for chopping the signal loaded by the first delay circuit and loading the second gate electrode, and the second voltage signal is generated by the second gate electrode under the action of the signal loaded by the first chopper circuit. In the closing stage of the device, the second voltage signal falls to a low level when the first voltage signal ends the Miller platform.

3. The device of claim 2, wherein, The signal processing circuit further comprises a level shift circuit, the second gate electrode is connected with the first chopper circuit through the level shift circuit, the level shift circuit is used for performing level shift processing on the signal loaded by the first chopper circuit and loading the second gate electrode, and the second voltage signal is generated by the second gate electrode under the action of the signal loaded by the level shift circuit. The low level is a negative voltage.

4. The device of claim 3, wherein, The signal processing circuit further comprises a second chopper circuit, the second gate electrode is connected with the level shift circuit through the second chopper circuit, the second chopper circuit is used for chopping the signal loaded by the level shift circuit and loading the second gate electrode, and the second voltage signal is generated by the second gate electrode under the action of the signal loaded by the second chopper circuit. The second voltage signal rises to 0 volt after the duration of the low level reaches a preset length.

5. The device of claim 4, wherein, ​ ​ 6. The device of claim 4, wherein, The signal processing circuit further comprises a third chopper circuit, the second gate electrode is connected with the level shift circuit through the third chopper circuit, the third chopper circuit is used for chopping the signal loaded by the level shift circuit and loading on the second gate electrode, and the second voltage signal is generated by the second gate electrode under the action of the signal loaded by the third chopper circuit. The second voltage signal is reduced to 0 volt after the duration of the high level reaches a preset length.

7. The device of claim 2, wherein, The first gate electrode is connected with the gate port through the signal processing circuit, the signal processing circuit further comprises a second delay circuit, the first gate electrode is connected with the gate port through the second delay circuit, the second delay circuit is used for delaying the control signal and loading on the first gate electrode, and the first voltage signal is generated by the first gate electrode under the action of the signal loaded by the second delay circuit. In the off stage of the device, the second voltage signal is reduced to a low level when the first voltage signal ends the miller platform.

8. The device according to any one of claims 1 to 7, characterized in that The gate port is used for being connected with an external circuit through a driver.

9. A power supply circuit, characterized by comprising: The device comprises any one of the devices in claims 1 to 8.

10. An electronic device, comprising: The power supply circuit comprises the power supply circuit in claim 9.

Images