Metalized guide plate for probe card, and manufacturing method for metalized guide plate

Abstract

Disclosed in the present invention are a metalized guide plate for a probe card, and a manufacturing method for the metalized guide plate. The method comprises the following steps: providing a substrate made of an insulating material, and performing a planarization treatment on two opposite side surfaces of the substrate; machining and drilling the substrate to form probe implantation holes that penetrate the substrate; performing photolithography on each of the two opposite side surfaces of the substrate to form photoresist layers; depositing first conductive materials on each of the two opposite side surfaces of the substrate to form seed layers on inner wall surfaces of at least some of the probe implantation holes and on the two opposite side surfaces of the substrate corresponding to at least some of the probe implantation holes; electroplating second conductive materials on surfaces of the seed layers to form electroplated layers on the surfaces of the seed layers; and cleaning the substrate and removing the photoresist layers to obtain a metallized guide plate having a patterned circuit. The metalized guide plate manufactured by the manufacturing method of the present invention has relatively high current resistance, and can improve the stability of a probe card for testing wafers having high current and high power consumption. The method is stable and controllable, has a high yield and is low-risk.

Description

Metallized guide plate for probe card and manufacturing method thereof TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor wafer test probe, in particular to a kind of metallized guide plate for probe card and manufacturing method thereof. BACKGROUND

[0002] In the technical field of semiconductor wafer test probe, as the electrical contact interface connecting the wafer chip to be tested and the test machine, the probe card is one of the key elements limiting the performance of the test system. With the iteration of chip design technology, the demand for probe cards for testing wafers with high power consumption and high current is becoming more and more urgent. The probe card mainly includes a guide plate and a probe. The guide plate and the probe are the key components that affect the bearing current of the test chip. The guide plate is used to install the probe and limit the probe. The guide plate is mainly used as a template or carrier in the chip packaging process, which is used to ensure the precise alignment between the chip and the packaging material. In the design of integrated circuits in semiconductor wafers, the distance between the centers of two adjacent identical elements (such as transistors, pads, contacts, etc.) on a chip (i.e., PITCH) has a direct impact on the performance, integration, and production cost of the chip. Since PITCH is limited by technology, it cannot be reduced indefinitely, as this will significantly increase the complexity and cost of the manufacturing process. At the same time, the size of PITCH also affects the design of the probe, as the probe needs to be precisely connected to these elements on the chip. Since the probe is a metal device that directly contacts the PAD (i.e., a metal area on the chip used for testing steps during chip manufacturing and as a connection point between the chip and external circuits during final packaging) on the test wafer chip. If PITCH is too small, the thickness and width of the probe will also be limited and cannot be increased indefinitely, otherwise it may affect the contact quality of the probe and the chip, or even cause the probe to fail to correctly contact the contact point on the chip. In the actual chip testing process, the probes on the probe card will contact the chip terminals on the wafer for electrical testing. These probes are usually arranged at a very narrow pitch, such as 20-30 microns. The service life of the probe depends not only on the service life, but also on the number of times the probe contacts the chip on the wafer. Therefore, the design and manufacture of the probe need to take these factors into consideration to ensure the accuracy and reliability of the test. Therefore, there is an urgent need for a manufacturing method for a metallized guide plate for a probe card to improve the current resistance performance of the probe card and improve the stability of the wafer test with high power consumption and high current. SUMMARY

[0003] To solve the above technical problems, the purpose of the present application is to provide a manufacturing method for a metallized guide plate for a probe card and a metallized guide plate manufactured by the manufacturing method.

[0004] In one aspect, the present application provides a manufacturing method of a metallized guide plate for a probe card, comprising the following steps: (1) providing a substrate made of an insulating material, and planarizing opposite surfaces of the substrate; (2) processing the substrate to form needle implantation holes penetrating through the substrate and used for implanting probes; (3) performing photolithography on the opposite surfaces of the substrate respectively to form photoresist layers; (4) depositing a first conductive material on the opposite surfaces of the substrate respectively to form seed layers on inner walls of at least part of the needle implantation holes and on the opposite surfaces of the substrate corresponding to the at least part of the needle implantation holes; (5) electroplating a second conductive material on surfaces of the seed layers to form electroplated layers on the surfaces of the seed layers; and (6) cleaning the substrate and removing the photoresist layers to obtain the metallized guide plate with a patterned circuit.

[0005] According to one embodiment of the present application, in the step (1), the insulating material comprises one of sapphire, ceramic, silicon carbide, and silicon nitride.

[0006] According to one embodiment of the present application, in the step (1), the planarization process comprises one of chemical mechanical polishing, glass reflow, spin-on film layer, sputtering deposition, selective deposition, low pressure chemical vapor deposition, plasma enhanced chemical vapor deposition, and thermal reflow; after the planarization process is performed on the opposite surfaces of the substrate, the thickness of the substrate is 200 micrometers to 450 micrometers.

[0007] According to one embodiment of the present application, in the step (2), the needle implantation hole has a hole diameter of 20 micrometers to 100 micrometers.

[0008] According to one embodiment of the present application, in the step (3), when the opposite surfaces of the substrate are subjected to photolithography, the photoresist layer has a thickness of 15 micrometers, an exposure dose of 500 millijoules per square centimeter, and a developing time of 50 seconds.

[0009] According to one embodiment of the present application, in the step (4), at least one layer of the first conductive material or multiple layers of the first conductive material are deposited on the opposite surfaces of the substrate in sequence, the first conductive material comprises one or a combination of titanium, copper, gold, nickel, and chromium, and the seed layer comprises one of a titanium / copper / gold composite layer, a chromium / copper / gold composite layer, and a nickel / copper / gold composite layer, and the composite layer has a thickness of 20 nanometers / 100 nanometers / 100 nanometers.

[0010] According to one embodiment of the present application, in the step (5), the second conductive material comprises one of rhodium, gold, and silver, and the electroplated layer has a thickness of 2 micrometers to 5 micrometers.

[0011] According to one embodiment of the present application, in the step (6), the substrate is ultrasonically cleaned with acetone, alcohol and deionized water in sequence, and each cleaning time is not less than 15 minutes.

[0012] In another aspect, the present application also provides a metalized guide plate for a probe card, which is manufactured by the method according to any one of the above technical solutions, and comprises: a substrate made of insulating material, wherein a plurality of needle implantation holes penetrating through the substrate and used for implanting probes are formed on the substrate; and a patterned circuit comprising a conductive layer, wherein the conductive layer is formed on at least part of inner wall surfaces of the needle implantation holes and on both side surfaces of the substrate opposite to the at least part of the needle implantation holes.

[0013] According to one embodiment of the present application, the conductive layer comprises a seed layer and an electroplated layer, wherein the seed layer is made of a first conductive material, the seed layer is formed on at least part of inner wall surfaces of the needle implantation holes and on both side surfaces of the substrate opposite to the at least part of the needle implantation holes, and the electroplated layer is made of a second conductive material, and the electroplated layer is formed on a surface of the seed layer.

[0014] Compared with the prior art, the present application has the following beneficial effects:

[0015] By using the manufacturing method of the present application, the seed layer and the electroplated layer are formed on the needle implantation holes and the opposite two side surfaces of the substrate in sequence by deposition and electroplating, so that the metalized guide plate with the preset patterned circuit can be obtained, the process steps are stable and controllable, and the yield is high and the risk is low. By using the manufacturing method of the present application, the at least part of the needle implantation holes are connected together by the conductive layer to form the patterned circuit, so that the part of the needle implantation holes has high current resistance after implanting the probes, and the stability of the probe card for wafer testing with high current and high power consumption can be improved. The part of the needle implantation holes which is not passed through by the patterned circuit is isolated and independent, and the part of the needle implantation holes can be used as separate test probes after implanting the probes, so that the probe card has a wider application scenario. BRIEF DESCRIPTION OF DRAWINGS

[0016] FIGS. 1(a) to 1(b) are schematic diagrams of step one of the manufacturing method of the metalized guide plate according to one embodiment of the present application;

[0017] FIG. 2 is a schematic diagram of step two of the manufacturing method of the metalized guide plate;

[0018] FIGS. 3(a) to 3(b) are schematic diagrams of step three of the manufacturing method of the metalized guide plate;

[0019] FIGS. 4(a) to 4(b) are schematic diagrams of step four of the manufacturing method of the metalized guide plate.

[0020] [According to Rule 91 correction 08.09.2025] Fig. 5 is a schematic view of step five of the manufacturing method of the metallized guide plate;

[0021] Fig. 6 is a schematic view of step six of the manufacturing method of the metallized guide plate;

[0022] Fig. 7 is a schematic view of the planar view of the metallized guide plate according to an embodiment of the present application.

[0023] In the drawings, the following reference numerals are used:

[0024] 100, metallized guide plate;

[0025] 10, substrate; 11, needle-implanting hole; 12, photoresist layer;

[0026] 20, patterned circuit; 2, conductive layer; 21, seed layer; 22, electroplated layer. DETAILED DESCRIPTION

[0027] It is easy to understand that, according to the technical solution of the present application, a person skilled in the art can propose a plurality of alternative structures and implementation manners without changing the essential spirit of the present application. Therefore, the following detailed description and the drawings are only exemplary descriptions of the technical solution of the present application, and should not be considered as the whole or as a limitation or restriction on the technical solution of the present application.

[0028] One embodiment of the present application provides a manufacturing method of a metallized guide plate 100 for a probe card, which comprises the following steps:

[0029] (1) providing a substrate 10 composed of an insulating material, and performing planarization treatment on the opposite two side surfaces of the substrate 10;

[0030] (2) processing the substrate 10 to drill holes to form needle-implanting holes 11 penetrating through the substrate 10 and used for implanting probes;

[0031] (3) performing photoetching on the opposite two side surfaces of the substrate 10 respectively to form photoresist layers 12;

[0032] (4) depositing a first conductive material on the opposite two side surfaces of the substrate 10 respectively to form seed layers 21 on the inner walls of at least part of the needle-implanting holes 11 and the opposite two side surfaces of the substrate 10 corresponding to at least part of the needle-implanting holes 11;

[0033] (5) electroplating a second conductive material on the surface of the seed layer 21 to form an electroplated layer 22 on the surface of the seed layer 21;

[0034] (5) electroplating a second conductive material on the surface of the seed layer 21 to form an electroplated layer 22 on the surface of the seed layer 21;

[0035] (6) The substrate 10 is cleaned and the photoresist layer 12 is removed, thereby obtaining the metallized guide plate 100 with the patterned circuit 20.

[0036] The steps of the manufacturing method in the above-mentioned embodiment of the present application and the structural composition of the metallized guide plate 100 manufactured according to the manufacturing method are specifically described below according to the accompanying drawings of the specification.

[0037] According to Fig. 1(a), a substrate 10 composed of a ceramic material is provided, and the initial thickness D0 of the substrate 10 is 500 microns. In other embodiments, the substrate 10 can also be selected from other insulating materials such as sapphire, silicon carbide, silicon nitride, etc., and the initial thickness of the substrate 10 can also be selected within the range of 500 microns to 800 microns, without specific limitation.

[0038] According to Fig. 1(b), the opposite surfaces of the substrate 10 are subjected to a planarization treatment, and the process thickness D1 of the substrate 10 after the planarization treatment is 200 microns. Specifically, the opposite surfaces of the substrate 10 are subjected to a chemical mechanical polishing (CMP) treatment, and the substrate 10 is ground and polished to 200 microns. In other embodiments, other planarization treatment processes can also be used, such as glass flow, spin-on glass (SOG), sputtering deposition, selective deposition, low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), thermal reflow, etc., and the process thickness D1 of the substrate 10 after the planarization treatment can be controlled within the range of 200 microns to 450 microns, without specific limitation.

[0039] According to Fig. 2, the substrate 10 is drilled to form a needle implantation hole 11 that penetrates the substrate 10 and is used for implanting a probe. In this embodiment, a laser rotary drilling process can be used to drill the substrate 10 to form the needle implantation hole 11 with a hole diameter of 20 microns. In other embodiments, the hole diameter of the needle implantation hole 11 can be controlled within the range of 20 microns to 100 microns, without specific limitation.

[0040] According to FIG. 3(a), a photoresist is coated on one side surface of the substrate 10 and photoetching is performed to form a photoresist layer 12. The thickness of the photoresist layer 12 formed is 15 microns, the exposure dose is 500 millijoules per square centimeter, and the developing time is 50 seconds.

[0041] According to FIG. 3(b), a photoresist is coated on the other side surface of the substrate 10 opposite to the one side surface and photoetching is performed to form a photoresist layer 12. The thickness of the photoresist layer 12 formed is 15 microns, the exposure dose is 500 millijoules per square centimeter, and the developing time is 50 seconds.

[0042] According to FIG. 4(a), a seed layer 21 having a composite layer is formed by sequentially depositing titanium / copper / gold materials on the one side surface of the substrate 10 by a physical vapor deposition process (PVD). The thickness of the composite layer is 20 nanometers / 100 nanometers / 100 nanometers. In other embodiments, other deposition processes can be used to deposit on the one side surface of the substrate 10, such as a chemical vapor deposition process (CVD), an electrochemical deposition process (ECD), an atomic layer deposition process (ALD), etc., and the deposited materials are not limited to the composite layer formed by sequentially depositing titanium / copper / gold, but can also be other first conductive materials, such as one or a combination of titanium, copper, gold, nickel, and chromium, and the deposited first conductive materials are not limited to only one layer, but can also be two or more layers of alternating composite, such as a titanium / copper / gold composite layer, a chromium / copper / gold composite layer, a nickel / copper / gold composite layer, etc., and the thickness of the seed layer 21 can be controlled within a range of 100 nanometers to 250 nanometers, without limitation.

[0043] According to FIG. 4(b), a seed layer 21 having a composite layer is formed by sequentially depositing titanium / copper / gold materials on the other side surface of the substrate 10 opposite to the one side surface by a chemical vapor deposition process (CVD). The thickness of the composite layer is 20 nanometers / 100 nanometers / 100 nanometers. In other embodiments, other deposition processes can be used to deposit on the other side surface of the substrate 10 opposite to the one side surface, such as a physical vapor deposition process (PVD), an electrochemical deposition process (ECD), an atomic layer deposition process (ALD), etc., and the deposited materials are not limited to the composite layer formed by sequentially depositing titanium / copper / gold, but can also be other first conductive materials, such as one or a combination of titanium, copper, gold, nickel, and chromium, and the deposited first conductive materials are not limited to only one layer, but can also be two or more layers of alternating composite, such as a titanium / copper / gold composite layer, a chromium / copper / gold composite layer, a nickel / copper / gold composite layer, etc., and the thickness of the seed layer 21 can be controlled within a range of 100 nanometers to 250 nanometers, without limitation.

[0044] According to the embodiment shown in Fig. 5, the substrate 10 is subjected to an electroplating process to form a layer of rhodium as the electroplating layer 22 on the surface of the seed layer 21 of the substrate 10, and the thickness of the electroplating layer 22 is 2 microns. In other embodiments, other second conductive materials such as gold and silver can be used to form the electroplating layer 22 on the surface of the seed layer 21, and the thickness of the electroplating layer 22 can be controlled to be between 2 microns and 5 microns, and the specific thickness is not limited.

[0045] According to the embodiment shown in Fig. 6, the substrate 10 is subjected to ultrasonic cleaning with acetone, alcohol and deionized water in sequence, and each cleaning time is not less than 15 minutes, and the photoresist layer 12 is removed to obtain the metallized guide plate 100 with the patterned circuit 20.

[0046] The manufacturing method of the present application can form the conductive layer 2 on the pin planting holes 11 and the opposite two surfaces of the substrate 10 by deposition and electroplating in sequence, the conductive layer 2 includes the seed layer 21 and the electroplating layer 22, and the metallized guide plate 100 with the preset patterned circuit 20 can be obtained, the process steps are stable and controllable, and the yield is high and the risk is low.

[0047] According to the embodiments shown in Figs. 6 and 7, after cleaning, the cross-sectional structure of the metallized guide plate 100 shown in Fig. 6 can be obtained. The part of the pin planting holes 11 through which the patterned circuit 20 passes connects the probes together after the probes are implanted, and the part of the pin planting holes 11 not passing through the patterned circuit 20 are independent and isolated from each other, and each probe can be used as an independent test probe after the probes are implanted in the part of the pin planting holes 11.

[0048] The metallized guide plate 100 obtained by the above manufacturing method includes the substrate 10 and the patterned circuit 20. The substrate 10 is made of an insulating material, and the substrate 10 is provided with a plurality of pin planting holes 11 penetrating the substrate 10 and used for implanting probes. The patterned circuit 20 includes the conductive layer 2, and the conductive layer 2 includes the seed layer 21 and the electroplating layer 22. The seed layer 21 is made of a first conductive material, and the seed layer 21 is formed on the inner wall of at least part of the pin planting holes 11 and the opposite two surfaces of the substrate 10 corresponding to the at least part of the pin planting holes 11. The electroplating layer 22 is made of a second conductive material, and the electroplating layer 22 is formed on the surface of the seed layer 21. In other embodiments, the patterned circuit 20 can be specifically designed, for example, only a part of the pin planting holes 11 is used to lay the conductive layer 2 to form the patterned circuit 20, and the seed layer 21 and the electroplating layer 22 are formed by deposition and electroplating in sequence, and the part of the pin planting holes are connected together through the patterned circuit 20, and the specific design is not limited.

[0049] The metalized guide plate 100 manufactured by the manufacturing method has the seed layer 21 deposited in a part of the needle implanting hole and the electroplated layer 22 electroplated on the surface of the seed layer 21, so that the part of the needle implanting hole 11 is connected together through the pattern circuit 20, has higher current resistance, can improve the stability of the probe card for wafer testing of high current and high power consumption, and the part of the needle implanting hole 11 is isolated and independent, and after the probe is implanted, the part of the needle implanting hole 11 can be used as a single test probe, so that the probe card has a wider application scene.

[0050] The technical scope of the present application is not limited to the above description, and those skilled in the art can make various modifications and changes to the above embodiments without departing from the technical idea of the present application, and these modifications and changes should be within the protection scope of the present application.

Claims

1. A method of manufacturing a metallized guide plate for a probe card, characterized by, The method comprises the following steps: (1) providing a substrate made of insulating material, and planarizing the opposite surfaces of the substrate; (2) processing the substrate to form needle implantation holes penetrating through the substrate and used for implanting probes; (3) performing photolithography on the opposite surfaces of the substrate respectively to form photoresist layers; (4) depositing a first conductive material on the opposite surfaces of the substrate respectively to form seed layers on the inner walls of at least part of the needle implantation holes and on the opposite surfaces of the substrate corresponding to the at least part of the needle implantation holes; (5) electroplating a second conductive material on the surfaces of the seed layers to form electroplated layers on the surfaces of the seed layers; (6) cleaning the substrate and removing the photoresist layers to obtain a metalized guide plate with a patterned circuit. In the step (1), the insulating material comprises one of sapphire, ceramic, silicon carbide and silicon nitride.

2. The method of claim 1, wherein: In the step (1), the planarization process comprises one of chemical mechanical polishing, glass reflow, spin-on film layer, sputtering deposition, selective deposition, low pressure chemical vapor deposition, plasma enhanced chemical vapor deposition and thermal reflow; after the planarization treatment of the opposite surfaces of the substrate, the thickness of the substrate is 200-450 microns.

3. The method of claim 1, wherein: In the step (2), the aperture of the needle implantation hole is 20-100 microns.

4. The method of claim 1, wherein: In the step (3), when performing photolithography on the opposite surfaces of the substrate, the thickness of the photoresist layer is 15 microns, the exposure dose is 500 mJ / cm2, and the developing time is 50 seconds.

5. The method of claim 1, wherein: In the step (4), at least one layer of the first conductive material or multiple layers of the first conductive material are deposited on the opposite surfaces of the substrate in sequence, the first conductive material comprises one or a plurality of combinations of titanium, copper, gold, nickel and chromium, the seed layer comprises one of titanium / copper / gold composite layer, chromium / copper / gold composite layer and nickel / copper / gold composite layer, and the thickness of the composite layer is 20 nm / 100 nm / 100 nm.

6. The method of claim 1, wherein: In the step (5), the second conductive material comprises one of rhodium, gold and silver, and the thickness of the electroplated layer is 2-5 microns.

7. The method of claim 1, wherein: In the step (6), the substrate is cleaned by using acetone, alcohol and deionized water in sequence, and each cleaning time is not less than 15 minutes.

8. The method of claim 1, wherein: The method comprises:

9. A metallized guide plate for a probe card, characterized by a substrate made of insulating material, and a plurality of needle implantation holes penetrating through the substrate and used for implanting probes are formed on the substrate; a patterned circuit comprising a conductive layer, which is formed on the inner walls of at least part of the needle implantation holes and on the opposite surfaces of the substrate corresponding to the at least part of the needle implantation holes. ​ 10. The method of claim 9, wherein: The conductive layer comprises a seed layer and a plating layer, the seed layer is made of a first conductive material, the seed layer is formed on at least part of the inner wall surface of the pin hole and the opposite surface of the substrate corresponding to the at least part of the pin hole, the plating layer is made of a second conductive material, and the plating layer is formed on the surface of the seed layer.

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