Isolated DC / DC converter and method for controlling isolated DC / DC converter

Abstract

An inverter 2 is set, during a pause period of the inverter, in a switching state in which a primary-side winding of a transformer 3 is short-circuited. The initial pulse width in an inverter operation period is fixed to 0.5 times a pulse period. A positive pulse width, which is required for making the exciting current of the transformer 3 coincide with that at the start of the inverter operation period for each inverter operation period, is calculated and cumulated for each inverter operation period to calculate a cumulative value. On the basis of the cumulative value, the initial pulse polarity of the next inverter operation period is selected so that a DC magnetic flux of a transformer core is suppressed in the next inverter operation period. In an isolated DC / DC converter that performs intermittent operation using the transformer and the inverter, a desired operation characteristic is obtained by correcting the inverter output voltage.

Description

Isolated DC / DC converter and control method for isolated DC / DC converter

[0001] The present invention relates to a power transmission technology in an isolated DC / DC converter using a transformer and an inverter, and more particularly to a control method for intermittent operation in which periods of voltage output and periods of no voltage output are repeatedly performed by the inverter.

[0002] As a circuit that generates another isolated DC voltage source from a DC voltage source, an isolated DC / DC converter that utilizes the isolation of a transformer 3, as shown in Figure 1, is known. As shown in Figure 1, an inverter 2 is provided on the primary side of the transformer 3, and a rectifier 4 is provided on the secondary side of the transformer 3. The output voltage of the inverter 2 is applied to the primary side of the transformer 3, and its voltage waveform is pulsed.

[0003] As a control method for the inverter 2 that varies the power transmitted from the primary side to the secondary side, there is a method of varying the pulse width (duty cycle) of the pulse voltage, which is the inverter output voltage, and a method of performing intermittent operation by setting a period during which the output of the inverter 2 is paused while keeping the pulse width constant, thereby varying the pulse density.

[0004] Of these two methods, the method that controls pulse density has a fixed power limit for each pulse. When the ratio of inverter operation period to inverter downtime period is small, the pulse density is low, and on average, the power that can be transmitted from the primary side to the secondary side is small.

[0005] On the other hand, when the proportion of the inverter operating period is large, the pulse density is high, and on average, the power that can be transmitted from the primary side to the secondary side is large. Figure 2 shows the difference in transmitted power due to differences in pulse density. Note that the inverter output voltage will be either +V1, 0, or -V1 for the voltage V1 of the first DC voltage source 1 in Figure 1. The inverter output voltage is ±V1 during the inverter operating period and 0 during the inverter idle period.

[0006] In the configuration shown in Figure 1, if the average voltage applied to the transformer 3 is not zero, the excitation current of the transformer 3 will continue to increase or decrease, causing a magnetic bias phenomenon in which the iron core of the transformer 3 becomes magnetically saturated. To suppress this, Patent Documents 1 to 4 describe the following countermeasures.

[0007] Patent Document 1: The inverter output voltage pattern is controlled so that the inverter enters a shutdown period when the excitation current becomes zero.

[0008] Patent documents 2 and 3 describe a mechanism for measuring the voltage waveform applied to a transformer and the magnetic flux of the transformer core, and controlling the pulse width of the inverter output voltage according to the measured values.

[0009] Patent Document 4: The polarity of the inverter output voltage is reversed at each operating period.

[0010] Japanese Patent Publication No. 2017-130997, Japanese Patent Publication No. 2016-144303, Japanese Patent Publication No. Hei 5-344715, Japanese Patent Publication No. 2024-000954

[0011] In the case of Patent Document 1, the timing when the excitation current becomes zero occurs only twice per pulse cycle, making it difficult to perform high-precision control to match the inverter operation period to a desired time.

[0012] Figure 3 shows an example waveform when the inverter is controlled to enter the inverter shutdown period at the timing when the excitation current becomes zero, as in Patent Document 1. As mentioned above, there are timing constraints because the timing when the excitation current becomes zero occurs only twice per pulse cycle. If this constraint is ignored and the inverter shutdown period is entered at a timing when the excitation current is not zero, a DC current may be superimposed on the excitation current, causing magnetic bias, as shown in Figure 4.

[0013] In the cases of Patent Documents 2 and 3, additional mechanisms are required for measuring voltage and magnetic flux, and furthermore, the control becomes complex because both pulse density and pulse width must be controlled simultaneously.

[0014] Patent Document 4 describes how the inverter output voltage is switched between positive and negative signs for each operating period. When the duration of the operating period is the same for two consecutive periods, the magnetic flux of the transformer can be canceled out for each of the two operating periods. However, when the duration of the operating period differs for each period, the magnetic flux of the transformer cannot be canceled out, and residual magnetic flux may accumulate, potentially causing a magnetic bias phenomenon in which the iron core of the transformer becomes magnetically saturated.

[0015] Furthermore, variations may occur in the rise characteristics of the secondary DC voltage when switching from the inverter shutdown period to the inverter operation period, and variations may occur in the fall characteristics of the secondary DC voltage when switching from the inverter operation period to the inverter shutdown period.

[0016] For the reasons described above, a challenge in isolated DC / DC converters that perform intermittent operation using a transformer and an inverter is to correct the inverter output voltage to achieve desired operating characteristics.

[0017] The present invention was devised in view of the above-mentioned conventional problems, and one aspect thereof is an isolated DC / DC converter to which pulse density control by intermittent operation is applied, comprising: a first DC voltage source; an inverter whose DC side is connected to the first DC voltage source; a transformer whose primary winding is connected to the AC side of the inverter; a rectifier connected to the secondary winding of the transformer; and a second DC voltage source connected to the DC side of the rectifier, wherein the inverter is in a switching state in which the primary winding of the transformer is short-circuited during the inverter idle period, the initial pulse width during the inverter operation period is fixed to 0.5 times the pulse period, the positive pulse width necessary to match the excitation current of the transformer with that at the start of the inverter operation period is calculated and accumulated for each inverter operation period to calculate an integrated value, and the initial pulse polarity of the next inverter operation period is selected based on the integrated value so as to suppress the DC magnetic flux of the transformer core in the next inverter operation period.

[0018] Furthermore, in one embodiment, the inverter is characterized in that, if the cumulative value is less than -0.5 × pulse period, the first pulse polarity of the next inverter operation period is negative; if the cumulative value is -0.5 × pulse period or greater and 0.5 × pulse period or less, the first pulse polarity of the next inverter operation period is the inverse of the first pulse polarity of the current inverter operation period; and if the cumulative value is greater than 0.5 × pulse period, the first pulse polarity of the next inverter operation period is positive.

[0019] In one embodiment, the inverter comprises first and second switching elements connected in series between one end and the other end of the first DC voltage source, and third and fourth switching elements connected in series between one end and the other end of the first DC voltage source, and is a single-phase full-bridge circuit in which the connection point of the first and second switching elements and the connection point of the third and fourth switching elements are connected to the primary winding of the transformer, and the inverter shutdown period is characterized by turning the first and third switching elements ON and turning the second and fourth switching elements OFF, or turning the second and fourth switching elements ON and turning the first and third switching elements OFF.

[0020] Furthermore, in one embodiment, an isolated DC / DC converter to which pulse density control by intermittent operation is applied, comprising: a first DC voltage source; an inverter whose DC side is connected to the first DC voltage source; a transformer whose primary side winding is connected to the AC side of the inverter; a rectifier connected to the secondary side winding of the transformer; and a second DC voltage source connected to the DC side of the rectifier, wherein the inverter generates a corrected inverter output voltage command which is held for a dead time + minimum ON time from the timing when the inverter operation command switches from ON to OFF and then set to 0, or the polarity of the value is reversed at the timing when the inverter operation command switches from ON to OFF and held for a dead time + minimum ON time and then set to 0, and the inverter is controlled based on the corrected inverter output voltage command.

[0021] Furthermore, in one embodiment, the inverter generates a delayed inverter operation command by delaying the inverter operation command by a dead time + minimum ON time, generates a delayed inverter output voltage command based on the delayed inverter operation command, and corrects the delayed inverter output voltage command so that it holds a value for a period of dead time + minimum ON time from the timing when the inverter operation command switches from ON to OFF, and then becomes 0, thereby generating a corrected inverter output voltage command.

[0022] Furthermore, in one embodiment, the control unit of the inverter generates a pre-delay inverter output voltage command based on the inverter operation command, generates a delayed inverter output voltage command by delaying the pre-delay inverter output voltage command by a dead time + minimum ON time, compares the pre-delay inverter output voltage command and the delayed inverter output voltage command at the timing when the inverter operation command switches from ON to OFF, and if the pre-delay inverter output voltage command and the delayed inverter output voltage command match, the delayed inverter output voltage command becomes the corrected inverter output voltage command, and if the pre-delay inverter output voltage command and the delayed inverter output voltage command do not match, the delayed inverter output voltage command is corrected so that its polarity is reversed at the timing when the inverter operation command switches from ON to OFF, held for a dead time + minimum ON time, and then becomes 0, thereby generating the corrected inverter output voltage command.

[0023] According to the present invention, in an isolated DC / DC converter that performs intermittent operation using a transformer and an inverter, it is possible to correct the inverter output voltage to obtain desired operating characteristics.

[0024] A schematic diagram showing an example of an isolated DC / DC converter. A diagram showing the transmission power as a function of pulse density. A diagram showing an example waveform when the inverter is stopped at the timing when the excitation current is zero. A diagram showing an example waveform when the inverter is stopped at the timing when the excitation current is not zero. A diagram showing the circuit configuration of the isolated DC / DC converter of Example 1. A diagram showing an example waveform when state 3 is applied to the inverter stop period and the inverter stop period is short. A diagram showing the waveforms of the inverter output voltage and excitation current of Example 1. A diagram showing the circuit configuration of the isolated DC / DC converter of Example 2. A diagram showing an example inverter output voltage waveform when the inverter operation period is twice the length of the inverter pulse period. A diagram showing an example of the secondary DC voltage waveform under the conditions of Figure 9. A diagram showing the inverter output voltage pattern and excitation current waveform in Example 3. A diagram showing the secondary DC voltage characteristics when switching from the inverter operation period to the inverter stop period. A diagram showing an example waveform of Example 4 when the delayed inverter operation command turns ON→OFF after the minimum ON time has elapsed since the delayed inverter output voltage command entered state 1 or 2. Figure 4 shows an example waveform of Example 4 when the inverter operation command turns ON→OFF before the minimum ON time has elapsed after the inverter output voltage command before delay is in state 1 or 2. Figure 4 shows an example waveform of Example 4 when the inverter operation command turns ON→OFF while the inverter output voltage command before delay is in state 3. Figure 5 shows an example waveform of Example 5 when the inverter operation command turns ON→OFF after the minimum ON time has elapsed after the inverter output voltage command before delay is in state 1 or 2. Figure 5 shows an example waveform of Example 5 when the inverter operation command turns ON→OFF while the inverter output voltage command before delay is in state 3.

[0025] Examples 1 to 5 of the isolated DC / DC converter according to the present invention will be described in detail below with reference to Figures 5 to 18. Note that "desired operating characteristics" refer to the suppression of transformer bias in Examples 1 and 2, the suppression of transformer bias and the suppression of variations in the rise characteristics of the secondary DC voltage in Example 3, and the suppression of variations in the fall characteristics of the secondary DC voltage in Examples 4 and 5.

[0026] [Example 1] Figure 5 shows the circuit configuration of an isolated DC / DC converter to which the control method of this Example 1 is applied. First, the circuit configuration of the isolated DC / DC converter in this Example 1 will be explained based on Figure 5.

[0027] A single-phase full-bridge inverter 2 is connected to the first DC voltage source 1. Specifically, U-phase first and second switching elements S1 and S2 are connected in series between one end and the other end of the first DC voltage source 1. In addition, V-phase third and fourth switching elements S3 and S4 are connected in series between one end and the other end of the first DC voltage source 1.

[0028] The connection point of the first and second switching elements S1 and S2 is connected to one end of the primary winding of the transformer 3. The connection point of the third and fourth switching elements S3 and S4 is connected to the other end of the primary winding of the transformer 3.

[0029] A single-phase rectifier 4 is connected to the secondary winding of the transformer 3. Specifically, one end of the secondary winding of the transformer 3 is connected to the connection point of the first and second diodes D1 and D2 of the rectifier 4, and the other end of the secondary winding of the transformer 3 is connected to the connection point of the third and fourth diodes D3 and D4 of the rectifier 4.

[0030] The first and third diodes D1 and D3 are connected to one end of the second DC voltage source 5, and the second and fourth diodes D2 and D4 are connected to the other end of the second DC voltage source 5. A load 6 is connected in parallel to the second DC voltage source 5.

[0031] The inverter 2 connected to the first DC voltage source 1 is a single-phase full-bridge circuit, and the phase-to-phase voltage Vuv between the U-phase and V-phase of the single-phase full-bridge circuit is applied to the primary winding of the transformer 3. The secondary winding of the transformer 3 is converted to DC by connecting a rectifier 4. This makes it possible to generate a second DC voltage source 5 that is isolated from the first DC voltage source 1 at the input of the inverter 2.

[0032] The inverter 2 of the single-phase full-bridge circuit has four switching states (states 1 to 4) as shown in Table 1. Note that state 4 has two different switching states, but since the inverter output voltage is 0 in both switching states, they are treated as a single switching state without distinction.

[0033]

[0034] During inverter operation, the output voltage of inverter 2 is alternately switched between +V1 and -V1 by switching between state 1 and state 2. Generally, a dead time needs to be inserted during this switching, and this dead time corresponds to state 3. On the other hand, during inverter downtime, there are two methods: state 3 or state 4.

[0035] When State 3 is applied as the inverter shutdown period, the inverter 2 operates as a rectifier during the State 3 period. When switching from the inverter operation period to State 3 as the inverter shutdown period while the excitation current is not zero, the excitation current flows to the first DC voltage source 1 or the second DC voltage source 5, discharging the energy charged in the excitation inductance of the transformer 3 to the first DC voltage source 1 or the second DC voltage source 5, and the excitation current decreases.

[0036] Here, if the inverter downtime is short and the next inverter operation period occurs before the energy charged in the excitation inductance of transformer 3 is completely discharged, a DC current is superimposed on the excitation current, causing a magnetic bias, as shown in Figure 6.

[0037] When state 4 is applied as the inverter shutdown period, if the switch from the inverter operation period to the inverter shutdown period occurs while the excitation current is not zero, the excitation inductance of the transformer 3 is short-circuited by the switching element of the primary side inverter 2. As a result, ignoring circuit losses, the excitation current is maintained as in Figure 4, as in the inverter operation period.

[0038] In this embodiment 1, state 4 is applied during the inverter shutdown period to maintain the excitation current. The switching state is kept the same during the inverter operation period immediately before and after the inverter shutdown period, and the sum of the pulse widths during the inverter operation period immediately before and after the inverter shutdown period is made to match the normal pulse width during the inverter operation period.

[0039] As a result, the change in the exciting current can be suppressed within the same range as when the inverter is stopped at the timing when the exciting current becomes zero as shown in FIG. 3. In this method, restrictions during the inverter operation period as in Patent Document 1 and additional voltage and magnetic flux measurement mechanisms as in Patent Documents 2 and 3 are not required. Also, there is no need to match the time widths of two consecutive operation periods, which is a restriction in Patent Document 4.

[0040] The operation pattern derivation method according to Embodiment 1 is summarized below. A waveform example is shown in FIG. 7.

[0041] Period 1: Inverter operation period During the inverter operation period, ignoring the dead time and setting the pulse period as Tpulse, an operation is performed in which states 1 and 2 in Table 1 are alternately repeated for 0.5×Tpulse (0.5 cycle) each. As a result, the operation becomes such that the inverter output voltage is constant at a duty of 50%.

[0042] When switching from the inverter operation period to the inverter stop period, based on the switching state (state 1 or state 2) during the immediately preceding inverter operation period and the output time (Tbefore) in that state, the shortage “Tshort” of the output time with respect to 0.5 cycle is calculated and recorded by the following formula (1).

[0043]

[0044] Period 2: Inverter stop period During the inverter stop period, by setting it to state 4 in Table 1, the exciting current during the immediately preceding inverter operation period is maintained. State 4 is such that the first and third switching elements S1 and S3 are on and the second and fourth switching elements S2 and S4 are off, or the second and fourth switching elements S2 and S4 are on and the first and third switching elements S1 and S3 are off.

[0045] Period 3: Next inverter operation period The first switching state at the time of resuming the inverter operation is the same as the state during the inverter operation period immediately before the inverter stop period. After that, the operation returns to alternately repeating states 1 and 2 again. At this time, the time (pulse width) of the first switching state at the time of resuming is set to “Tshort” calculated and recorded in “Period 1: Inverter operation period”.

[0046] This results in a state where the excitation current waveform is maintained during inverter idle periods, even when the inverter output voltage is kept constant at a 50% duty cycle without intermittent operation. As a result, the excitation current can be kept within the same range as when the inverter is continuously operated, without imposing any constraints on the length of the inverter operation period, thereby suppressing magnetic bias.

[0047] As described above, according to this embodiment 1, by applying a switching state (state 4 in Table 1) that can maintain the excitation current during the inverter shutdown period, it becomes unnecessary to end the inverter operation period at the timing when the excitation current becomes 0, as described in Patent Document 1, and bias can be suppressed during any inverter operation period.

[0048] Furthermore, by calculating and recording the pulse width required for the next inverter operation period when the inverter operation period ends, the pulse width for the next inverter operation period can be adjusted without the need for information on the applied voltage or magnetic flux of the transformer 3, eliminating the need for the additional voltage and magnetic flux measurement mechanisms described in Patent Documents 2 and 3. In addition, there is no need to match the time widths of two consecutive operation periods, which is a constraint in Patent Document 4.

[0049] (Regarding the conditions under which circuit losses can be ignored) The primary side equivalent series resistance component associated with the windings and circuit element wiring of transformer 3 is ESR １ The primary winding inductance is L １ , the primary current is I １ Therefore, since the secondary side is effectively open during the period corresponding to the inverter shutdown period in state 4, the following equation (2) holds true.

[0050]

[0051] Therefore, if fluctuations in the secondary voltage are negligible, the current at t=0 immediately after the transition to the pause period is I ０ Therefore, equation (3) below holds true.

[0052]

[0053] In other words, the condition under which the above damping can be ignored is that the rest period t corresponds to the primary time constant L. １ / ESR１ needs to be sufficiently smaller. Conversely, the value obtained by dividing L １ by the pause period t is the primary-side equivalent series resistance component ESR １ Even if it is sufficiently larger than, the circuit loss can be ignored such that the attenuation can be ignored. The condition for the primary-side equivalent series resistance component ESR １ to be sufficiently small is sufficient for this condition to hold. This condition holds in normal designs.

[0054] [Example 2] The difference between this Example 2 and Example 1 is that the transformer 3, the inverter 2, and the rectifier 4 are changed from single-phase to three-phase. The circuit configuration in this Example 2 is shown in FIG. 8.

[0055] Specifically, the first and second switching elements S1 and S2 of the U phase are connected in series between one end and the other end of the first DC voltage source 1. Also, the third and fourth switching elements S3 and S4 of the V phase are connected in series between one end and the other end of the first DC voltage source 1. Also, the fifth and sixth switching elements S5 and S6 of the W phase are connected in series between one end and the other end of the first DC voltage source 1.

[0056] The connection points of the first and second switching elements S1 and S2, the connection points of the third and fourth switching elements S3 and S4, and the connection points of the fifth and sixth switching elements S5 and S6 are connected to the transformer 3.

[0057] The secondary winding of the transformer 3 is connected to the connection points of the first and second diodes D1 and D2, the connection points of the third and fourth diodes D3 and D4, and the connection points of the fifth and sixth diodes D5 and D6.

[0058] The first, third, and fifth diodes D1, D3, and D5 are connected to one end of the second DC voltage source 5, and the second, fourth, and sixth diodes D2, D4, and D6 are connected to the other end of the second DC voltage source 5. A load 6 is connected in parallel to the second DC voltage source 5.

[0059] Note that the line-to-line voltages between the U phase and the V phase, between the V phase and the W phase, and between the W phase and the U phase are denoted as Vuv, Vvw, and Vwu, respectively.

[0060] In the case of the three-phase inverter shown in Figure 8, there are eight switching states (states 1 to 8) as shown in Table 2. Note that state 8 has two possible switching states, but since the inverter output voltage is 0 in both switching states, they are treated as a single switching state without distinction. State 8 is when the first, third, and fifth switching elements S1, S3, and S5 are on and the second, fourth, and sixth switching elements S2, S4, and S6 are off, or when the second, fourth, and sixth switching elements S2, S4, and S6 are on and the first, third, and fifth switching elements S1, S3, and S5 are off.

[0061] During inverter operation, each phase of inverter 2 outputs pulses with a 50% duty cycle, with a timing difference of 1 / 3 of the pulse period between phases (phase difference of 120 degrees). As a result, states 1 through 6 in Table 2 are output sequentially for periods of 1 / 6 of the pulse period.

[0062]

[0063] Next, we will explain the operation during the inverter shutdown period.

[0064] In the single-phase full-bridge circuit of Example 1, in state 4 in Table 1, the excitation inductance of the transformer 3 is short-circuited by the switching element of the primary inverter 2.

[0065] Similarly, in the case of the three-phase inverter of this embodiment 2, in state 8 in Table 2, the excitation inductance of the transformer 3 is short-circuited by the switching element of the primary inverter 2.

[0066] Thus, similar to Example 1, by selecting state 8 in Table 2 during the inverter shutdown period, the excitation current during the inverter shutdown period can be maintained. The initial switching state upon resuming inverter operation is the same as the switching state during the inverter operation period immediately preceding the inverter shutdown period. Subsequently, states 1 through 6 are output sequentially for periods of 1 / 6 of the pulse period. At this time, the duration of the initial switching state upon resumption is set to "Tshort," which is calculated and recorded during the inverter operation period immediately preceding the inverter shutdown period.

[0067] Therefore, the excitation current waveform, when the inverter output voltage is operated with a constant duty cycle without intermittent operation, is modified by inserting an inverter downtime period during which the excitation current is maintained. As a result, without imposing constraints on the length of the inverter operation period, the fluctuation range of the excitation current can be kept the same as when the inverter is operated continuously, thereby suppressing magnetic bias.

[0068] As described above, this embodiment 2 provides the same effects and advantages as embodiment 1, even in the case of a three-phase inverter.

[0069] [Example 3] Examples 1 and 2 solve the problems described in Patent Documents 1 to 4. On the other hand, the rise characteristics of the secondary DC voltage change depending on the condition of the initial pulse width during the inverter operation period.

[0070] Figure 9 shows the inverter output voltage waveform when the inverter operating period is twice the length of the inverter pulse period, and Figure 10 shows examples of the secondary DC voltage waveform. The narrower the initial pulse width of the inverter operating period, the slower the rise time of the secondary voltage tends to be. As a result, when the purpose is to supply voltage to equipment such as ICs whose operation switches according to a voltage threshold, there is a problem in that it affects the operating characteristics of the equipment.

[0071] This embodiment 3, like embodiment 1, assumes that the transformer 3, inverter 2, and rectifier 4 are single-phase.

[0072] This embodiment 3 is similar to embodiment 1 in that the excitation current is maintained by using state 4 during the inverter shutdown period. The difference from embodiment 1 is that the initial pulse width during the inverter operation period is fixed to 0.5 times the pulse period, regardless of the conditions during the previous inverter operation period.

[0073] Since the initial pulse width during the inverter operation period is fixed at 0.5 times the pulse period, as shown in Table 3, the excitation current of transformer 3 at the end of the inverter operation period relative to the start of the inverter operation period has a positive offset if the initial pulse during the inverter operation period is positive, and a negative offset if the initial pulse during the inverter operation period is negative. Note that if the inverter operation period is an integer multiple of the pulse period, the excitation current of transformer 3 will be the same at the start and end of the inverter operation period.

[0074]

[0075] By utilizing the above characteristics and appropriately selecting the polarity of the first pulse during the inverter operation period, DC bias can be suppressed. The method for deriving the operation pattern according to this embodiment 3 is summarized below.

[0076] Period 1: Inverter Operation Period During the inverter operation period, ignoring the dead time, the pulse period is set to Tpulse, and the operation alternates between State 1 and State 2 in Table 1 for a period of 0.5 × Tpulse (0.5 periods), thereby maintaining a constant 50% duty cycle for the inverter output voltage.

[0077] The initial pulse width during the inverter operation period is set to 0.5 × Tpulse, and the voltage polarity is set to the polarity selected during the previous inverter operation period in the processing described later. The length of the inverter operation period, Tout, is measured, and the positive pulse width required to match the excitation current at the start of the inverter operation period (to eliminate the excitation current offset) is determined from the relationship between the length Tout and the pulse period Tpulse, based on Table 4. Note that if the required positive pulse width is negative, it means a negative pulse width. Also, N in Table 4 represents an integer greater than or equal to 0.

[0078] The condition N×Tpulse ≤ Tout < N×Tpulse + 0.5×Tpulse in Table 4 indicates the case where the inverter operation period ends with the same pulse polarity as the initial pulse polarity of the inverter operation period. In this case, if the initial pulse polarity of the inverter operation period is positive, the required positive pulse width is -(Tout - N×Tpulse), and if the initial pulse polarity of the inverter operation period is negative, the required positive pulse width is (Tout - N×Tpulse).

[0079] The expression N×Tpulse + 0.5×Tpulse ≤ Tout < (N+1)×Tpulse in Table 4 represents the case where the inverter operation period ends with a pulse polarity different from the pulse polarity of the initial pulse during the inverter operation period. In this case, if the initial pulse polarity of the inverter operation period is positive, the required positive pulse width is -((N+1)×Tpulse)-Tout), and if the initial pulse polarity of the inverter operation period is negative, the required positive pulse width is ((N+1)×Tpulse)-Tout).

[0080]

[0081] The cumulative value Tsum is obtained by accumulating the required positive pulse width derived above for each inverter operating period.

[0082] Period 2: Inverter shutdown period. During the inverter shutdown period, the excitation current from the previous inverter operation period is maintained by setting the inverter to state 4 in Table 1.

[0083] Period 3: Based on the range of the next inverter operation period cumulative value Tsum, the initial pulse polarity of the next inverter operation period is selected so as to suppress the current magnetic flux of the core of transformer 3 during the next inverter operation period. Specifically, the initial switching state (pulse polarity) when the inverter operation is restored is determined according to Table 5.

[0084]

[0085] In other words, if the cumulative value Tsum is less than -0.5 × pulse period, the polarity of the first pulse in the next inverter operation period will be negative. If the cumulative value Tsum is greater than or equal to -0.5 × pulse period and less than or equal to 0.5 × pulse period, the polarity of the first pulse in the next inverter operation period will be the inverse of the polarity of the first pulse in the current inverter operation period. If the cumulative value Tsum is greater than 0.5 × pulse period, the polarity of the first pulse in the next inverter operation period will be positive.

[0086] Furthermore, the initial pulse width during the inverter operation period after recovery will be 0.5 × T pulses, as in the previous instance.

[0087] Figure 11 shows the inverter output voltage pattern and excitation current waveform according to this embodiment 3. Initially, the integrated value Tsum of the required positive pulse width is 0.

[0088] During the first inverter operation period, the initial pulse polarity is positive, and the inverter operation period ends with the same pulse polarity as the initial pulse polarity (N × Tpulse ≤ Tout < N × Tpulse + 0.5 × Tpulse). Therefore, the cumulative value Tsum is -(Tout - N × Tpulse). Since the cumulative value Tsum does not exceed -0.5 × Tpulse, the initial pulse polarity in the second inverter operation period is reversed from the initial pulse polarity of the first inverter operation period and becomes negative.

[0089] In the second inverter operation period, the initial pulse polarity is negative, and the inverter operation period ends with a pulse polarity different from the initial pulse polarity (N × Tpulse + 0.5 × Tpulse ≤ Tout < (N + 1) × Tpulse). Therefore, ((N + 1) × Tpulse) - Tout is added to the cumulative value Tsum. Since the cumulative value Tsum does not exceed -0.5 × Tpulse, the initial pulse polarity in the third inverter operation period is positive, which is the inverse of the initial pulse polarity in the second inverter operation period.

[0090] In the third inverter operation period, the initial pulse polarity is positive, and since the inverter operation period ends with the same pulse polarity as the initial pulse polarity (N × Tpulse ≤ Tout < N × Tpulse + 0.5 × Tpulse), -(Tout - N × Tpulse) is added to the cumulative value Tsum. Because the cumulative value Tsum exceeds -0.5 × Tpulse, the initial pulse polarity in the fourth inverter operation period becomes negative.

[0091] In the fourth inverter operation period, the initial pulse polarity is negative, and since the inverter operation period ends with a pulse polarity different from the initial pulse polarity (N × Tpulse + 0.5 × Tpulse ≤ Tout < (N + 1) × Tpulse), ((N + 1) × Tpulse) - Tout is added to the cumulative value Tsum. Since the cumulative value Tsum exceeds -0.5 × Tpulse, the initial pulse polarity in the fifth inverter operation period becomes negative.

[0092] In the fifth inverter operation period, the initial pulse polarity is negative, and the inverter operation period ends with the same pulse polarity as the initial pulse polarity (N × Tpulse ≤ Tout < N × Tpulse + 0.5 × Tpulse), so (Tout - N × Tpulse) is added to the cumulative value Tsum.

[0093] As described above, according to this embodiment 3, by applying a switching pattern that can maintain the excitation current during the inverter shutdown period (State 4 in Table 1), it becomes unnecessary to end the inverter operation period when the excitation current becomes zero, as in Patent Document 1, and bias can be suppressed during any inverter operation period.

[0094] Furthermore, this embodiment 3 allows for the deriving and integrating of the positive pulse width necessary to eliminate the excitation current offset, and by selecting the initial pulse polarity in the next inverter operation period based on this integrated value, the excitation current in the next inverter operation period can be directed in a direction that suppresses the offset, thereby suppressing the excitation current.

[0095] Furthermore, according to this embodiment 3, since operation control can be performed without magnetic flux information of the iron core of the transformer 3, the additional magnetic flux measurement mechanism described in Patent Documents 2 and 3 becomes unnecessary.

[0096] Furthermore, since the initial pulse width during the inverter operation period is fixed, the rise characteristics of the secondary DC voltage during the inverter operation period can be matched for each inverter operation period, thereby suppressing the effects of variations in voltage rise characteristics when supplying power to ICs and other devices that have threshold-dependent characteristics.

[0097] In this embodiment 3, the range of possible excitation currents is doubled compared to embodiment 1. As a result, the magnetic flux generated in the transformer 3 can also be doubled compared to embodiment 1. Therefore, embodiment 1 is suitable when miniaturization of the transformer 3 is desired because the range of possible excitation currents is narrow. On the other hand, embodiment 3 is suitable for equipment where the effects of variations in voltage rise characteristics are to be suppressed.

[0098] [Example 4] The main circuit of this Example 4 is the same as that of Example 1. In Example 3, when performing intermittent operation in which the inverter is started and stopped, the initial pulse width of the inverter output voltage Vuv during the inverter operation period is fixed to equalize the rise characteristics of the secondary DC voltage when switching from the inverter stop period to the inverter operation period.

[0099] In Example 3, when switching from the inverter operation period to the inverter shutdown period, variations in the falling edge characteristics of the secondary DC voltage occur due to the effects of the inverter's dead time and minimum ON time.

[0100] Here, "dead time" refers to the time during which a pair of switching elements connected in series in inverter 2 are simultaneously turned off to prevent a short circuit caused by the simultaneous conduction of these elements (the simultaneous activation of the control signal). Furthermore, "minimum ON time" refers to the minimum ON time allowed for the control signal used to activate inverter 2.

[0101] The principle of variation in the falling edge characteristics of the secondary DC voltage will be explained using Figure 12. In Figure 12, the switching element state is as follows: when the inverter output voltage is +V1, it is as state 1 in Table 1; when the inverter output voltage is -V1, it is as state 2; during the zero voltage period during inverter operation, it is as state 3; and during the inverter shutdown period, it is as state 4.

[0102] (1) When the inverter operation command is turned ON ⇒ OFF after the minimum ON time has elapsed since the state 1 or 2 has been reached, as shown in (1) of Figure 12, the inverter output voltage is +V1 or -V1 until just before the switch from the inverter operation period to the inverter shutdown period, and from the switching timing the inverter output voltage becomes 0 and the secondary DC voltage begins to decrease.

[0103] (2) When the inverter operation command turns ON to OFF before the minimum ON time has elapsed after entering state 1 or 2, as shown in (2) of Figure 12, the minimum ON time has not elapsed immediately after switching from the inverter operation period to the inverter shutdown period, so inverter 2 will shut down after waiting for the minimum ON time to elapse (minimum ON time processing). As a result, the inverter output voltage becomes 0 with a delay from the switching timing and the secondary DC voltage begins to decrease.

[0104] (3) When the inverter operation command is switched ON to OFF during state 3, as shown in (3) of Figure 12, inverter 2 has already entered dead time just before switching from the inverter operation period to the inverter shutdown period, so the inverter output voltage becomes 0 from the moment it enters dead time. Therefore, the inverter output voltage becomes 0 before the switching timing and the secondary DC voltage begins to decrease.

[0105] Depending on which of the three patterns described above is met, the falling edge characteristics of the secondary DC voltage during the switch from the inverter operation period to the inverter shutdown period will differ.

[0106] Patent Document 1 suppresses magnetic saturation of the transformer core by using an inverter output voltage pattern that enters the inverter shutdown period at the timing when the excitation current becomes zero. In the above method, the timing when the excitation current becomes zero occurs only twice per pulse cycle, making it difficult to switch from the inverter operation period to the inverter shutdown period at an arbitrary timing.

[0107] In this embodiment 4, the switching element pattern is corrected so that no dead time and minimum ON time processing occur at the timing of switching from the inverter operation period to the inverter shutdown period. As a result, the secondary DC voltage command always starts to decrease from the timing of switching from the inverter operation period to the inverter shutdown period, as shown in Figure 12, "(1) After the minimum ON time has elapsed since entering state 1 or 2, the inverter operation command turns ON ⇒ OFF".

[0108] This embodiment 4 aims to suppress variations in the falling edge characteristics of the secondary DC voltage. By combining embodiment 3, which suppresses variations in the rising edge characteristics of the secondary DC voltage, with embodiment 4, which suppresses variations in the falling edge characteristics, it becomes possible to output the secondary DC voltage for the same period as the ON time of the inverter operation command. As a result, when the ON time of the inverter operation command is arbitrarily varied, the rising edge and falling edge characteristics of the secondary DC voltage can be made uniform.

[0109] This embodiment 4 describes a method for delaying the switching timing (maintaining the previous state).

[0110] As shown in Figures 13 to 15, a delayed inverter operation command is generated by delaying the inverter operation command by "dead time + minimum ON time". A delayed inverter output voltage command is generated based on the delayed inverter operation command. Specifically, the delayed inverter output voltage command is a signal that alternately outputs +V1 and -V1 during the ON period of the delayed inverter operation command. The corrected inverter output voltage command is a signal obtained by correcting this delayed inverter output voltage command. When inverter 2 is controlled based on the corrected inverter output voltage command, the inverter output voltage waveform is obtained, and the secondary DC voltage waveform decreases from the moment the inverter output voltage waveform becomes 0.

[0111] This section describes a method for correcting a delayed inverter output voltage command to a corrected inverter output voltage command. The delayed inverter output voltage command is corrected so that it holds its value for a period of time equal to the dead time + minimum ON time (until the delayed inverter operation command switches from ON to OFF) from the moment the inverter operation command switches from ON to OFF, and then becomes 0, thereby generating a corrected inverter output voltage command. For the rest of the period, the delayed inverter output voltage command and the corrected inverter output voltage command are the same. This allows the secondary DC voltage to be supplied for the same duration as the inverter operation command's operating time, without being affected by the dead time or minimum ON time.

[0112] (1) After the inverter output voltage command before delay (not shown) is in state 1 or 2, the inverter operation command is turned ON and then OFF after the minimum ON time has elapsed. As shown in Figure 13, there is no change between the inverter output voltage command after delay and the inverter output voltage command after correction. The secondary DC voltage begins to decrease from the moment the inverter operation command after delay is turned OFF (switching from the inverter operation period to the inverter shutdown period).

[0113] (2) The inverter operation command is turned ON ⇒ OFF before the minimum ON time elapses after the inverter output voltage command before delay (not shown) reaches state 1 or 2. Figure 14 shows the inverter output voltage waveform based on the inverter output voltage command after delay for reference. As shown in Figure 14, in the inverter output voltage waveform based on the inverter output voltage command after delay, the minimum ON time processing continues at the timing when the inverter operation command after delay is turned OFF. Therefore, with the inverter output voltage command after delay, it was necessary to extend the inverter operation period from the value of the inverter operation command after delay in order to ensure the minimum ON time.

[0114] The corrected inverter output voltage command is set to 0 after holding its value for the period from when the inverter operation command switches from ON to OFF until the delayed inverter operation command switches from ON to OFF. This avoids the minimum ON time mentioned above, and the secondary DC voltage begins to decrease from the moment the delayed inverter operation command turns OFF (switching from the inverter operation period to the inverter shutdown period).

[0115] Furthermore, due to the correction from the delayed inverter output voltage command to the corrected inverter output voltage command, the period of states 1 and 2 immediately before the inverter operation stops is extended by up to "dead time + minimum ON time" compared to normal, and the absolute value of the excitation current of transformer 3 also increases accordingly.

[0116] (3) The inverter output voltage command before delay (not shown) is ON ⇒ OFF while the inverter operation command is ON ⇒ OFF in state 3. Figure 15 shows the inverter output voltage waveform based on the inverter output voltage command after delay for reference. As shown in Figure 15, the inverter output voltage waveform based on the inverter output voltage command after delay becomes 0 before the inverter operation command after delay turns OFF due to the effect of dead time, and the timing at which the secondary DC voltage drops also becomes earlier than the timing at which the inverter operation command after delay turns OFF.

[0117] The corrected inverter output voltage command is set to 0 after retaining its value for the period from when the inverter operation command switches from ON to OFF until the delayed inverter operation command switches from ON to OFF. As a result, the secondary DC voltage begins to decrease from the moment the delayed inverter operation command turns OFF (the switch from the inverter operation period to the inverter shutdown period).

[0118] Furthermore, due to the correction from the delayed inverter output voltage command to the corrected inverter output voltage command, the period of states 1 and 2 immediately before the inverter operation stops is extended by up to "dead time + minimum ON time" compared to normal, and the absolute value of the excitation current of transformer 3 also increases accordingly.

[0119] As described above, according to this embodiment 4, by correcting the inverter output voltage command, it is possible to avoid dead time and minimum ON time processing when switching from the inverter operation period to the inverter shutdown period, and the secondary DC voltage can be reduced from the switching timing from the inverter operation period to the inverter shutdown period. This makes it possible to suppress variations in the falling edge characteristics of the secondary DC voltage.

[0120] [Example 5] This Example 5 describes a method for suppressing variations in the falling edge characteristics of the secondary DC voltage, similar to Example 4. This Example 5 describes a method for advancing the switching timing (immediate switching).

[0121] As shown in Figures 16 to 18, a pre-delay inverter output voltage command is generated based on the inverter operation command, and a delayed inverter output voltage command is generated by delaying the pre-delay inverter output voltage command by "dead time + minimum ON time". The delayed inverter output voltage command is corrected to generate a corrected inverter output voltage command. When inverter 2 is controlled based on the corrected inverter output voltage command, the inverter output voltage waveform is obtained, and the secondary DC voltage waveform decreases from the moment the inverter output voltage waveform becomes 0.

[0122] This section describes a method for correcting a delayed inverter output voltage command to a corrected inverter output voltage command. The delayed inverter output voltage command is generated such that it is held for a period of time equal to the dead time plus the minimum ON time from the moment the inverter operation command switches from ON to OFF, and then set to 0, or the polarity of the value is reversed at the moment the inverter operation command switches from ON to OFF, and it is held for a period equal to the dead time plus the minimum ON time, and then set to 0. During other periods, the delayed inverter output voltage command and the corrected inverter output voltage command are the same.

[0123] The following explains in detail how to correct the delayed inverter output voltage command to the corrected inverter output voltage command. A comparison is made between the pre-delay inverter output voltage command and the delayed inverter output voltage command at the moment the inverter operation command switches to OFF.

[0124] If these match, the delayed inverter output voltage command is used as the corrected inverter output voltage command. That is, the corrected inverter output voltage command holds its value for a period of dead time plus minimum ON time from the moment the inverter operation command switches from ON to OFF, and then becomes 0.

[0125] On the other hand, if a discrepancy is found in the above comparison, the delayed inverter output voltage command is corrected by immediately reversing the polarity of its value at the moment the inverter operation command switches from ON to OFF, holding it for "dead time + minimum ON time" before becoming 0, thereby generating a corrected inverter output voltage command.

[0126] This allows the secondary DC voltage to be supplied for the same duration as the inverter operation command, without being affected by dead time or minimum ON time. Figures 17 and 18 also show the inverter output voltage waveform based on the delayed inverter output voltage command for reference.

[0127] (1) After the inverter output voltage command before delay is in state 1 or 2 and the minimum ON time has elapsed, the inverter operation command is switched ON ⇒ OFF. As shown in Figure 16, at the timing when the inverter operation command is switched to OFF, the inverter output voltage command before delay generated based on the inverter operation command and the inverter output voltage command after delay coincide. Therefore, the inverter output voltage command after delay becomes the corrected inverter output voltage command. In other words, the corrected inverter output voltage command is a signal that is held for a dead time + minimum ON time from the timing when the inverter operation command switches from ON to OFF, and then becomes 0. Inverter 2 is operated based on the corrected inverter output voltage command. In this case, the secondary DC voltage starts to decrease from the timing when the inverter operation command switches from ON to OFF and the dead time + minimum ON time has elapsed (switching from the inverter operation period to the inverter rest period).

[0128] (2) The inverter operation command is turned ON ⇒ OFF before the minimum ON time has elapsed after the inverter output voltage command before the delay has reached state 1 or 2. As shown in Figure 17, at the moment the inverter operation command switches to OFF, the inverter output voltage command before the delay generated based on the inverter operation command and the inverter output voltage command after the delay become inconsistent. Therefore, the corrected inverter output voltage command immediately reverses the polarity of its value at the moment the inverter operation command switches to OFF, holds for "dead time + minimum ON time", and then becomes 0.

[0129] As a result, dead time and minimum ON time processing occur from the moment the inverter operation command is switched to OFF, and the secondary DC voltage begins to decrease from the moment these are completed (the timing of the switch from inverter operation period to inverter shutdown period).

[0130] Furthermore, due to the correction from the delayed inverter output voltage command to the corrected inverter output voltage command, the period of states 1 and 2 immediately before the inverter operation stops is shortened by up to "dead time + minimum ON time" compared to normal, and the switching frequency of the switching elements constituting inverter 2 increases.

[0131] (3) When the inverter operation command is ON ⇒ OFF while the inverter output voltage command before delay is in state 3, as shown in Figure 18, at the moment the inverter operation command is switched to OFF, the inverter output voltage command before delay generated based on the inverter operation command and the inverter output voltage command after delay become inconsistent. Therefore, the corrected inverter output voltage command is immediately set to 0 after the polarity of the value is reversed at the moment the inverter operation command is switched to OFF and is held for "dead time + minimum ON time".

[0132] As a result, dead time and minimum ON time processing occur from the moment the inverter operation command is switched to OFF, and the secondary DC voltage begins to decrease from the moment these are completed (the timing of the switch from inverter operation period to inverter shutdown period).

[0133] Furthermore, due to the correction from the delayed inverter output voltage command to the corrected inverter output voltage command, the period in states 1 and 2 immediately before the inverter operation stops is shortened by up to "dead time + minimum ON time" compared to normal, and the switching frequency of the switching elements constituting the inverter increases.

[0134] As described above, this embodiment 5 provides the same effects and advantages as embodiment 4.

[0135] Furthermore, if there is sufficient margin in the excitation current, which is determined by the characteristics of the transformer's magnetic core material, its relationship to the drive frequency, and dimensional constraints, the configuration of Example 4 is more preferable. If there is sufficient margin in the switching frequency, which is determined by the characteristics of the switching element and the allowable range of switching losses, the configuration of Example 5 is more preferable. Alternatively, one can compare the design difficulties of expanding either allowable range and select the example that corresponds to the one that is easier to modify.

[0136] Although the present invention has been described in detail only with respect to the specific examples described above, it will be obvious to those skilled in the art that a wide variety of modifications and alterations are possible within the scope of the technical concept of the present invention, and it is natural that such modifications and alterations fall within the scope of the claims.

[0137] In Example 3, the threshold value used for comparison with the integrated value was set to 0.5 times the pulse period, but other values ​​may be used. However, if the threshold value is greater than 0.5 times the pulse period, the range of possible excitation currents will be greater than when the threshold value is 0.5 times the pulse period.

[0138] 1...First DC voltage source, 2...Inverter, 3...Transformer, 4...Rectifier, 5...Second DC voltage source, 6...Load, S1-S6...First-to-sixth switching elements, D1-D6...First-to-sixth diodes

Claims

1. An isolated DC / DC converter that applies pulse density control by intermittent operation, comprising: a first DC voltage source; an inverter whose DC side is connected to the first DC voltage source; a transformer whose primary winding is connected to the AC side of the inverter; a rectifier connected to the secondary winding of the transformer; and a second DC voltage source connected to the DC side of the rectifier, wherein the inverter is in a switching state that short-circuits the primary winding of the transformer during the inverter idle period; the initial pulse width during the inverter operation period is fixed to 0.5 times the pulse period; for each inverter operation period, a positive pulse width necessary to match the excitation current of the transformer with that at the start of the inverter operation period is calculated and accumulated for each inverter operation period to calculate an integrated value; and based on the integrated value, the initial pulse polarity of the next inverter operation period is selected so as to suppress the DC magnetic flux of the transformer core in the next inverter operation period.

2. The isolated DC / DC converter according to claim 1, characterized in that, if the cumulative value is less than -0.5 × pulse period, the polarity of the first pulse in the next inverter operation period is negative; if the cumulative value is -0.5 × pulse period or greater and 0.5 × pulse period or less, the polarity of the first pulse in the next inverter operation period is the inverse of the polarity of the first pulse in the current inverter operation period; and if the cumulative value is greater than 0.5 × pulse period, the polarity of the first pulse in the next inverter operation period is positive.

3. The inverter comprises first and second switching elements connected in series between one end and the other end of the first DC voltage source, and third and fourth switching elements connected in series between one end and the other end of the first DC voltage source, and is a single-phase full-bridge circuit in which the connection point of the first and second switching elements and the connection point of the third and fourth switching elements are connected to the primary winding of the transformer, and the inverter shutdown period is characterized by turning the first and third switching elements ON and the second and fourth switching elements OFF, or turning the second and fourth switching elements ON and the first and third switching elements OFF, as described in claim 1.

4. A control method for an isolated DC / DC converter that applies pulse density control by intermittent operation, comprising: a first DC voltage source; an inverter whose DC side is connected to the first DC voltage source; a transformer whose primary winding is connected to the AC side of the inverter; a rectifier connected to the secondary winding of the transformer; and a second DC voltage source connected to the DC side of the rectifier, wherein the inverter is in a switching state that shorts the primary winding of the transformer during the inverter idle period; the initial pulse width during the inverter operation period is fixed to 0.5 times the pulse period; for each inverter operation period, a positive pulse width necessary to match the excitation current of the transformer with that at the start of the inverter operation period is calculated and accumulated for each inverter operation period to calculate an integrated value; and based on the integrated value, the initial pulse polarity of the next inverter operation period is selected so as to suppress the DC magnetic flux of the transformer core during the next inverter operation period.

5. An isolated DC / DC converter to which pulse density control by intermittent operation is applied, comprising: a first DC voltage source; an inverter whose DC side is connected to the first DC voltage source; a transformer whose primary winding is connected to the AC side of the inverter; a rectifier connected to the secondary winding of the transformer; and a second DC voltage source connected to the DC side of the rectifier, wherein the inverter generates a corrected inverter output voltage command which is held for a dead time + minimum ON time from the timing when the inverter operation command switches from ON to OFF and then set to 0, or the polarity of the value is reversed at the timing when the inverter operation command switches from ON to OFF and held for a dead time + minimum ON time and then set to 0, and controls the inverter based on the corrected inverter output voltage command.

6. The isolated DC / DC converter according to claim 5, characterized in that the inverter generates a delayed inverter operation command by delaying the inverter operation command by a dead time + minimum ON time, generates a delayed inverter output voltage command based on the delayed inverter operation command, and corrects the delayed inverter output voltage command so that it holds a value for a period of dead time + minimum ON time from the timing when the inverter operation command switches from ON to OFF, and then becomes 0, thereby generating the corrected inverter output voltage command.

7. The control unit of the inverter generates a pre-delay inverter output voltage command based on the inverter operation command; generates a delayed inverter output voltage command by delaying the pre-delay inverter output voltage command by a dead time + minimum ON time; compares the pre-delay inverter output voltage command and the delayed inverter output voltage command at the timing when the inverter operation command switches from ON to OFF; if the pre-delay inverter output voltage command and the delayed inverter output voltage command match, the delayed inverter output voltage command becomes the corrected inverter output voltage command; and if the pre-delay inverter output voltage command and the delayed inverter output voltage command do not match, corrects the delayed inverter output voltage command by reversing the polarity of its value at the timing when the inverter operation command switches from ON to OFF, holding it for a dead time + minimum ON time, and then making it 0, thereby generating the corrected inverter output voltage command, as described in claim 5.

8. A control method for an isolated DC / DC converter that applies pulse density control by intermittent operation, comprising: a first DC voltage source; an inverter whose DC side is connected to the first DC voltage source; a transformer whose primary winding is connected to the AC side of the inverter; a rectifier connected to the secondary winding of the transformer; and a second DC voltage source connected to the DC side of the rectifier, wherein the inverter generates a corrected inverter output voltage command which is held for a dead time + minimum ON time from the timing when the inverter operation command switches from ON to OFF and then set to 0, or which has its polarity reversed at the timing when the inverter operation command switches from ON to OFF and is held for a dead time + minimum ON time and then set to 0, and controls the inverter based on the corrected inverter output voltage command.

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