Circuit board and semiconductor package

Abstract

This circuit board comprises: a first insulating layer; a second insulating layer, which is disposed on the first insulating layer and is made of a material different from that of the first insulating layer; a protective layer disposed on the second insulating layer; and a wiring unit disposed between the first insulating layer and the second insulating layer, wherein: the wiring unit includes a circuit layer disposed on the first insulating layer, and a via electrode passing through at least a portion of the second insulating layer from the upper surface of the second insulating layer toward the upper surface of the circuit layer; the second insulating layer is a photocurable insulating layer; the via electrode includes a side surface having a predetermined slope with respect to the upper surface of the circuit layer; and the horizontal length to an end portion of the circuit layer from a contact portion in which the side surface of the via electrode and the upper surface of the circuit layer are in contact is 30 µm or greater.

Description

Circuit boards and semiconductor packages

[0001] The present embodiment relates to a circuit board and a semiconductor package.

[0002]

[0003] Recently, technologies related to electronic products, such as AI and servers, are progressing toward multifunctionality and high speed, and to respond to this trend, semiconductor chip manufacturing technology is also developing rapidly.

[0004] In particular, as the density of transistors and wiring within semiconductor chips increases, the number of I / O terminals on the chips is growing. To meet this trend, not only are the wiring densities, lengths, and widths of circuit boards becoming finer, but there is also a trend toward high-layer, large-area designs.

[0005] Furthermore, from the perspective of miniaturizing finished electronic products, the thickness of the applied circuit boards is also decreasing, and technologies related to multilayer circuit boards, which configure more circuit layers within a circuit board of the same thickness, are being actively researched. In addition, as the pitch of semiconductor chips narrows and the size of chips increases, chiplet technology for separating semiconductor chips by function is being researched. Moreover, technologies for connecting separated chiplets on circuit boards are being actively researched. Furthermore, by connecting semiconductor chips with different functions on circuit boards, technologies regarding the connection relationship between circuit boards and semiconductor chips are being actively researched, such as the circuit board connecting semiconductor chips to each other, which was previously considered only from the perspective of conventional semiconductor packaging.

[0006] A circuit board is a device in which circuit line patterns are arranged using a conductive material, such as copper, on an electrically insulating substrate; it is a general term for the package board immediately before mounting electronic components. To densely mount many different types of electronic components on a flat surface, the mounting positions of each component are determined, and circuit patterns connecting the components are printed and fixed onto the surface.

[0007] A circuit board includes a plurality of insulating layers arranged in a vertical direction. The plurality of insulating layers may be electrically connected by wiring portions arranged on each surface and via electrodes connecting different wiring portions. In this case, via holes for arranging via electrodes may be formed in each of the plurality of insulating layers.

[0008] For circuit boards, the bonding between the wiring and the insulation layer is an essential factor that must be considered. If the bonding at the interface between the wiring and the insulation layer is insufficient, it can lead to structural and functional failures in the reliability of the circuit board quality.

[0009]

[0010] The present invention provides a circuit board and a semiconductor package that improve structural and functional stability by improving the bonding between the insulating layer and the circuit area.

[0011]

[0012] A circuit board according to the present embodiment comprises: a first insulating layer; a second insulating layer disposed on the first insulating layer and made of a material different from that of the first insulating layer; a protective layer disposed on the second insulating layer; and a wiring portion disposed between the first insulating layer and the second insulating layer, wherein the wiring portion comprises a circuit layer disposed on the upper surface of the first insulating layer and a via electrode penetrating at least a portion of the second insulating layer from the upper surface of the second insulating layer toward the upper surface of the circuit layer, the second insulating layer is a photocurable insulating layer, and the via electrode comprises a side surface having a predetermined slope with respect to the circuit layer, and the horizontal length from the contact portion where the side surface of the via electrode contacts the upper surface of the circuit layer to the end of the circuit layer is 30 μm or more.

[0013] The horizontal length from the contact portion where the side of the via electrode and the upper surface of the circuit layer meet to the end of the circuit layer may be less than 300 μm.

[0014] The horizontal length from the end of the circuit layer to the side of the second insulating layer may be 3 µm or more.

[0015] The vertical thickness of the above circuit layer may be 6 µm or more and 22 µm or less.

[0016] It includes a second circuit layer disposed on the upper surface of the second insulating layer, and the via electrode can connect the circuit layer and the second circuit layer.

[0017] The via electrodes connecting the circuit layer and the second circuit layer are provided in multiple numbers and can be spaced apart in the horizontal direction.

[0018] The above via electrode may have a shape in which the horizontal width gradually decreases as it faces the first insulating layer.

[0019] The above circuit layer is provided in a plurality and is spaced apart horizontally from the upper surface of the first insulating layer, and the second insulating layer includes a first region disposed in the spaced region of the plurality of circuit layers, and the horizontal length of the first region may be 10 µm or more.

[0020] It may include a cavity penetrating at least a portion of the second insulating layer.

[0021] A semiconductor package according to the present embodiment comprises: a first insulating layer; a second insulating layer disposed on the first insulating layer and made of a material different from that of the first insulating layer; a protective layer disposed on the second insulating layer; an electronic element disposed in a cavity formed in the second insulating layer; and a wiring portion disposed between the first insulating layer and the second insulating layer, wherein the wiring portion comprises a circuit layer disposed on the upper surface of the first insulating layer and a via electrode penetrating at least a portion of the second insulating layer from the upper surface of the second insulating layer toward the upper surface of the circuit layer, the via electrode comprises a side surface having a predetermined slope with respect to the circuit layer, the second insulating layer is a photocurable insulating layer, and the horizontal length from the contact portion where the side surface of the via electrode contacts the upper surface of the circuit layer to the end of the circuit layer is 30 μm or more.

[0022]

[0023] Through this embodiment, by controlling the vertical length of the circuit layer, delamination can be prevented at the bonding interface with the insulating layer, thereby improving the bonding strength with the insulating layer.

[0024]

[0025] FIG. 1 is a cross-sectional view of a circuit board according to an embodiment of the present invention.

[0026] FIGS. 2 to 6 are drawings for explaining various modified examples of a circuit board according to an embodiment of the present invention.

[0027] FIG. 7 is a cross-sectional view illustrating the combined structure of an insulating layer and a wiring portion according to an embodiment of the present invention.

[0028] FIGS. 8 to 13 are drawings for explaining the bonding force with an insulating layer according to the length of a circuit layer according to an embodiment of the present invention.

[0029] FIG. 14 is a cross-sectional view illustrating a semiconductor package according to an embodiment of the present invention.

[0030]

[0031] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the attached drawings.

[0032] However, the technical concept of the present invention is not limited to some of the described embodiments but can be implemented in various different forms, and within the scope of the technical concept of the present invention, one or more of the components among the embodiments may be selectively combined or substituted.

[0033] In addition, terms used in the embodiments of the present invention (including technical and scientific terms) may be interpreted in a meaning that is generally understood by those skilled in the art to which the present invention belongs, unless explicitly and specifically defined otherwise. Terms that are commonly used, such as terms defined in advance, may be interpreted in consideration of their meaning in the context of the relevant technology.

[0034] Additionally, the terms used in the embodiments of the present invention are for describing the embodiments and are not intended to limit the present invention. In this specification, the singular form may include the plural form unless specifically stated otherwise in the text, and when described as “at least one of A and B and C (or more than one),” it may include one or more of all combinations that can be combined with A, B, and C.

[0035] In addition, terms such as first, second, A, B, (a), (b), etc. may be used when describing the components of the embodiments of the present invention.

[0036] These terms are intended merely to distinguish a component from other components and are not limited by the nature, order, sequence, etc., of the said component.

[0037] And, where it is stated that a component is 'connected', 'combined', or 'joined' to another component, this may include not only cases where the component is directly connected, combined, or joined to the other component, but also cases where it is 'connected', 'combined', or 'joined' due to another component located between the component and the other component.

[0038] Furthermore, when described as being formed or placed "above or below" each component, "above" or "below" includes not only cases where two components are in direct contact with each other, but also cases where one or more other components are formed or placed between the two components. Additionally, when expressed as "above or below," it may include the meaning of a downward direction as well as an upward direction relative to a single component.

[0039] In addition, the expression that configuration A is positioned between configuration B and configuration C must include the meaning that configuration A is positioned such that at least a portion of it overlaps with configurations B and C in the horizontal and / or vertical directions.

[0040] Expressions referring to directions include horizontal and vertical directions, and the horizontal direction includes a first horizontal direction and a second horizontal direction perpendicular to the first horizontal direction. These are referred to as the first horizontal direction (X-axis), the second horizontal direction (Y-axis), and the vertical direction (Z-axis) according to the Cartesian coordinate system, and the meaning of being superimposed along the horizontal direction must include the meaning of being superimposed along the first horizontal direction and / or superimposed along the second horizontal direction.

[0041] Furthermore, the statement that Configuration A is exposed from Configuration B should be understood as meaning that Configuration A is exposed from Configuration B, not that Configuration A is exposed from the entire product. In other words, when Configuration A is stated to be exposed from Configuration B, it should be understood to mean that Configuration A is covered by at least a portion of Configuration C.

[0042] Furthermore, when it is stated that Component A 'contacts' Component B, this may include not only cases where the component 'contacts' the other component directly, but also cases where it 'contacts' due to another component located between the component and the other component. Therefore, if Component A is to be understood only as 'directly contacting' Component B, it is described as 'directly contacting'.

[0043] In addition, when it is stated that configuration A is 'covered' by configuration B, it should be understood that configuration A is covered by configuration B, and that the part intended for the function and purpose to be resolved is covered, and unless there are special circumstances, it should not be understood that the entire configuration A is covered by configuration B.

[0044] FIG. 1 is a cross-sectional view of a circuit board according to an embodiment of the present invention, and FIG. 2 to 6 are drawings for explaining various modified examples of a circuit board according to an embodiment of the present invention.

[0045] Referring to FIG. 1, a circuit board (10) according to an embodiment of the present invention may include a plurality of insulating layers, a plurality of circuit layers, a plurality of via electrodes and a protective layer.

[0046] A circuit board (10) may include a plurality of insulating layers. The plurality of insulating layers may be arranged along a vertical direction. The plurality of insulating layers may include a first insulating layer (111), a second insulating layer (121), a third insulating layer (112), a fourth insulating layer (113), a fifth insulating layer (114), and a sixth insulating layer (122). The second insulating layer (121) may be placed on the first insulating layer (111). The third insulating layer (112) may be placed on the lower surface of the first insulating layer (111). The fourth insulating layer (113) may be placed on the lower surface of the third insulating layer (112). The fifth insulating layer (114) may be placed on the lower surface of the fourth insulating layer (113). The sixth insulating layer (122) may be placed on the lower surface of the fifth insulating layer (114). A plurality of insulating layers can be arranged sequentially along the vertical direction from the second insulating layer (121) to the sixth insulating layer (122).

[0047] The first to sixth insulating layers (111, 121, 112, 113, 113, 114, 122) may each be any insulating material, such as photocurable and / or thermosetting materials. As thermosetting insulating materials, an insulating material in which inorganic and / or organic fillers are dispersed within a resin, such as ABF (Ajinomoto Build-up Film), a product released by Ajinomoto, may be used, and a prepreg (PPG) containing glass fibers within a resin may be used. In addition, the resins described above may be, for example, epoxy resin, bismaleimide triazine resin (BT resin), phenolic resin, etc., and the inorganic and / or organic fillers may be provided with materials such as silica or plastic. When an insulating resin is used as a core, it may include a reinforcing material provided with glass fibers or aramid fibers. When the first to sixth insulating layers (111, 121, 112, 113, 113, 114, 122) are photocurable insulators, the first to sixth insulating layers (111, 121, 112, 113, 113, 114, 122) may each be a PID (Photo Imageable Dielectric).

[0048] Among the plurality of insulating layers, at least some of the insulating layers may have a material different from that of the other insulating layers. For example, the first insulating layer (111), the third insulating layer (112), the fourth insulating layer (113), and the fifth insulating layer (114) positioned in the vertical center of the circuit board (10) may each be a prepreg (PPG) containing glass fibers in a resin. The second insulating layer (121) and the sixth insulating layer (122) positioned on the upper surface of the first insulating layer (111) and the lower surface of the fifth insulating layer (114) may each be a PID (Photo Imageable Dielectric) or an ABF (Ajinomoto Build-up Film). Accordingly, the strength of the circuit board (10) can be reinforced through the first insulating layer (111), the third insulating layer (112), the fourth insulating layer (113), and the fifth insulating layer (114) arranged in the vertical inner direction, thereby minimizing bending. Additionally, the thickness of the circuit board (10) can be minimized through the second insulating layer (121) and the sixth insulating layer (122), and the wiring portion within the circuit board (10) can be arranged finely and at a high density.

[0049] The vertical thickness of each of the first insulating layer (111), the third insulating layer (112), the fourth insulating layer (113), and the fifth insulating layer (114) may be thicker than the vertical thickness of each of the second insulating layer (121) and the sixth insulating layer (122). Accordingly, the bending of the circuit board (10) can be minimized through the first insulating layer (111), the third insulating layer (112), the fourth insulating layer (113), and the fifth insulating layer (114) which are positioned in the vertical center of the circuit board (10). To ensure the integrity of signal and / or power transmission or to alleviate the bending of the circuit board (10), the number of insulating layers positioned on the upper surface of the first insulating layer (111) and the number of insulating layers positioned on the lower surface of the fifth insulating layer (114) may be the same, but are not limited thereto and may be different from each other.

[0050] The vertical thickness of each of the first insulating layer (111), the third insulating layer (112), the fourth insulating layer (113), and the fifth insulating layer (114) may be the same. The vertical thickness of each of the second insulating layer (121) and the sixth insulating layer (122) may be mutually the same.

[0051] The number of stacked insulating layers described above is exemplary, and the circuit board (10) may have more or fewer insulating layers arranged in the vertical direction. For example, as shown in FIG. 5, the fifth insulating layer (114) may be omitted, in which case the first insulating layer (111), the third insulating layer (112), and the fourth insulating layer (113) may be arranged in the vertical center of the circuit board (10), and the second insulating layer (121) and the seventh insulating layer (123), which are made of a different material from the first insulating layer (111), may be arranged on the first insulating layer (111), and the sixth insulating layer (122) and the eighth insulating layer (124), which are made of a different material from the fifth insulating layer (114), may be arranged on the lower surface of the fifth insulating layer (114).

[0052] When all insulating layers made of prepreg material are named as first insulating layers and all insulating layers made of PID or ABF material are named as second insulating layers, as shown in FIG. 2 and FIG. 5, the ratio of the number of layers stacked within the circuit board (10) may be 5:2, but as shown in FIG. 6, the ratio of the number of layers stacked within the circuit board may be 3:4. Accordingly, based on the first insulating layer, the number of second insulating layers may be 10:4 to 10:13. When insulating layers made of PID or ABF material are arranged at a ratio of 1.33 or more compared to insulating layers made of prepreg material, there is a problem that the rigidity of the circuit board (10) becomes weak. In addition, when insulating layers made of PID or ABF material are arranged at a ratio of 0.4 or less compared to insulating layers made of prepreg material, there is a problem that the cavity formation process is difficult and the thickness of the circuit board increases excessively.

[0053] The circuit board (10) may include a protective layer. The protective layer may include a first protective layer (191) disposed on the upper surface of the second insulating layer (121) and a second protective layer (196) disposed on the lower surface of the sixth insulating layer (122). When a semiconductor element is disposed on the surface of the circuit board (10) using a material such as solder, the first protective layer (191) and the second protective layer (196) can perform the function of preventing short circuits between solders due to low wettability with the solder, and can prevent the problem of external contaminants penetrating into the build-up structure and reducing reliability. The first protective layer (191) and the second protective layer (196) may each be a solder resist.

[0054] The first protective layer (191) may include a hole (192) for exposing upward a circuit layer (136) disposed on the upper surface of the second insulating layer (121). The hole (192) may have a shape in which the horizontal width narrows as it approaches the second insulating layer (121). The first protective layer (191) may include a through hole (193) that overlaps vertically with the cavity (150) to be described later. The second protective layer (196) may include a hole (197) for exposing downward a circuit layer (137) disposed on the lower surface of the sixth insulating layer (122). The hole (197) of the second protective layer (196) may have a shape in which the horizontal width narrows as it approaches the lower surface of the sixth insulating layer (122).

[0055] A circuit board (10) may include a wiring section for transmitting electrical signals and / or power to an electronic device such as a semiconductor chip. The wiring section may be disposed between a plurality of insulating layers. The wiring section may include a plurality of circuit layers and a plurality of via electrodes.

[0056] A plurality of circuit layers may each be disposed on the surface of a plurality of insulating layers. Here, the meaning of being disposed on the surface may also include the meaning that at least a portion of the plurality of circuit layers is embedded within each of the plurality of insulating layers or protective layers and exposed to the outside from the surface. A circuit layer may also be referred to as a metal layer. Furthermore, the surface of the plurality of insulating layers includes a first surface, a second surface, and a side between the first surface and the second surface. Here, the first surface of the insulating layer may be understood as the upper surface, and the second surface of the insulating layer may be understood as the lower surface. The meaning of a circuit layer being disposed on the surface is that it is disposed on at least one of the first surface, the second surface, or the side between the plurality of insulating layers. A structure may be formed in which a circuit layer is disposed on both the first surface and the second surface of some of the insulating layers, and a circuit layer is disposed on only one of the first surface or the second surface of other parts of the plurality of insulating layers.

[0057] A plurality of circuit layers may include a first circuit layer (131) disposed on the upper surface of a first insulating layer (111), a second circuit layer (136) disposed on the upper surface of a second insulating layer (121), a third circuit layer (132) disposed on the upper surface of a third insulating layer (112), a fourth circuit layer (133) disposed on the upper surface of a fourth insulating layer (113), a fifth circuit layer (134) disposed on the lower surface of the fourth insulating layer (113), a sixth circuit layer (135) disposed on the lower surface of the fifth insulating layer (114), and a seventh circuit layer (137) disposed on the lower surface of the sixth insulating layer (122). Here, the second circuit layer (136) and the seventh circuit layer (137), which are covered by at least a portion of the protective layer (191, 196), can be named the first pad portion and the second pad portion, respectively. Additionally, the circuit layer may include a pad portion for connecting to a via electrode.

[0058] A via electrode may be a metallic material disposed in a via hole formed in each of a plurality of insulating layers to connect a plurality of circuit layers facing each other in a vertical direction. Here, the via hole penetrates at least a portion of each of the plurality of insulating layers in a vertical direction, and a via electrode may be disposed within the via hole.

[0059] The via electrode may include a second via electrode (142) penetrating at least a portion of the first insulating layer (111), a first via electrode (141) penetrating at least a portion of the second insulating layer (121), a third via electrode (143) penetrating at least a portion of the third insulating layer (112), a fourth via electrode (144) penetrating at least a portion of the fourth insulating layer (113), a fifth via electrode (145) penetrating at least a portion of the fifth insulating layer (114), and a sixth via electrode (146) penetrating at least a portion of the sixth insulating layer (122).

[0060] The second via electrode (142) can electrically connect the first circuit layer (131) and the third circuit layer (132). The first via electrode (141) can electrically connect the first circuit layer (131) and the second circuit layer (136). The third via electrode (143) can electrically connect the third circuit layer (132) and the fourth circuit layer (133). The fourth via electrode (144) can electrically connect the fourth circuit layer (133) and the fifth circuit layer (134). The fifth via electrode (145) can electrically connect the fifth circuit layer (134) and the sixth circuit layer (135). The sixth via electrode (146) can electrically connect the sixth circuit layer (135) and the seventh circuit layer (137).

[0061] The second via electrode (142), the first via electrode (141), and the third via electrode (143) may each have a shape in which the horizontal width decreases as it goes downward. The fourth via electrode (144), the fifth via electrode (145), and the sixth via electrode (146) may each have a shape in which the horizontal width increases as it goes downward. That is, when the first insulating layer (111), the third insulating layer (112), the fourth insulating layer (113), and the fifth insulating layer (114) made of prepreg are all referred to as the first insulating layer, the expansion direction of the via electrodes disposed within the first insulating layer may be reversed within the first insulating layer. Accordingly, stress can be distributed in the vertical direction of the circuit board (10) by the structure of the reversed expansion direction of the via electrodes at the center of the vertical direction of the circuit board (10).

[0062] Meanwhile, in this embodiment, different circuit layers facing each other in the vertical direction are electrically connected by a single via electrode, but this is not limited thereto, and as shown in FIGS. 5 and 6, different circuit layers facing each other in the vertical direction can be electrically connected by a plurality of via electrodes. Accordingly, the efficiency of signal transmission in the vertical direction within the circuit board (10) can be increased.

[0063] The circuit board (10) may include a cavity (150). The second insulating layer (121) may include a through hole penetrating from one side to the other, and the cavity (150) may be formed by the through hole of the second insulating layer (121). The cavity (150) may be positioned at the center of the second insulating layer (121) in the horizontal direction. Through the cavity (150), a portion of the upper surface of the first insulating layer (111) may be exposed from the second insulating layer (121) in the vertical direction. The cavity (150) may form a placement area for an electronic component to be described later. In this case, a portion of the upper surface of the first insulating layer (111) may be provided as the bottom surface of the cavity (150) to form a placement surface for an electronic component.

[0064] The through hole of the second insulating layer (121), which is the formation area of ​​the cavity (150), may have a shape in which the horizontal width gradually decreases as it faces the first insulating layer (111). Accordingly, the inner wall (152) of the through hole of the second insulating layer (121) may have an inclined surface shape. The inner wall (152) of the through hole of the second insulating layer (121) may form an obtuse angle with the upper surface of the first insulating layer (111) that forms the bottom surface of the cavity (150).

[0065] As illustrated in FIG. 3, the cavity (150) may be omitted. In this case, the electronic device is placed on the first protection layer (191), and the electronic device may be electrically connected to the second circuit layer (136) through a bonding portion (not shown). At least a portion of the bonding portion may be placed in a hole (192) within the first protection layer (191).

[0066] As illustrated in FIG. 4, a plurality of insulating layers may be disposed on the first insulating layer (111). A seventh insulating layer (123) may be disposed on the second insulating layer (121). The seventh insulating layer (123) may be made of the same material as the second insulating layer (121). In this case, the cavity (150) may have a shape that penetrates the plurality of insulating layers. That is, the seventh insulating layer (123) includes a through hole that overlaps vertically with the second insulating layer (121), and the cavity (150) may be implemented by a through hole penetrating the second insulating layer (121) and a through hole penetrating the seventh insulating layer (123). Accordingly, there is an advantage in that the placement area of ​​the electronic device through the cavity (150) can be formed more widely.

[0067] In order to minimize bending of the circuit board (10), an eighth insulating layer (124) made of the same material as the sixth insulating layer (122) may be placed on the lower surface of the sixth insulating layer (122).

[0068] A circuit layer (138, 139) and a via electrode (147, 148) for electrical connection with an adjacent wiring section may be disposed in the seventh insulating layer (123) and the eighth insulating layer (124), respectively.

[0069] Below, the combined structure of the insulation layer and the wiring section will be explained.

[0070] For convenience of explanation, the combined structure of the insulating layer and the wiring portion is described based on a first circuit layer (131) disposed on a first insulating layer (111) and a first via electrode (141) penetrating at least a portion of the second insulating layer (121), but this is not limited thereto, and the combined structure of the insulating layer and the wiring portion described below can be applied to at least one insulating layer disposed within the circuit board and the wiring portion disposed therein.

[0071] The first circuit layer (131) will be described as a circuit layer, and the first via electrode (141) will be described as a via electrode.

[0072] FIG. 7 is a cross-sectional view illustrating the combined structure of an insulating layer and a wiring portion according to an embodiment of the present invention, and FIG. 8 to 13 are drawings for explaining the bonding force with the insulating layer according to the length of the circuit layer according to an embodiment of the present invention.

[0073] Referring to FIGS. 2 and 7, the via electrode (141) may include a side surface (162) having a predetermined slope with respect to the upper surface of the circuit layer (131). Depending on the shape of the via electrode (141) described above, the side surface (162) of the via electrode (141) may also have a sloped surface shape such that the horizontal distance from the side surface of the second insulating layer (121) increases as it faces the first insulating layer (111). The side surface (162) of the via electrode (141) and the upper surface of the circuit layer (130) may form an acute angle.

[0074] As illustrated in FIG. 7, the area where the side (162) of the via electrode (141) and the upper surface (168) of the circuit layer (131) come into contact can be defined as a contact portion (160). The contact portion (160) may form a part of the upper surface of the circuit layer (131). In this case, the horizontal length (b) from the contact portion (160) to the end of the circuit layer (131) may be 30 μm or more.

[0075] Referring to FIGS. 8 to 10, a circuit board according to a comparative example includes a circuit layer (330) disposed on the upper surface of an insulating layer (310) and a via electrode (320) disposed on the circuit layer (330). The circuit layer (330) includes a first region (332) extending in one direction relative to the via electrode (320) and a second region (334) extending in the other direction opposite to the one direction. Here, the horizontal length from the upper surface of the circuit layer (330) in contact with the side of the via electrode (320) to the end of the first region (332) can be defined as L1, and the horizontal length from the upper surface of the circuit layer (330) in contact with the side of the via electrode (320) to the end of the second region (334) can be defined as L2. L1 is 130 µm and L2 is 15 µm.

[0076] Referring to FIG. 9, no delamination occurred at the interface between the first region (332) and the insulating layer (310). However, referring to FIG. 10, delamination (340) occurred at the interface between the second region (334) and the insulating layer (310). Here, the delamination (340) mostly occurred on the end surface of the second region (334) facing in the horizontal direction and on the opposite surface of the insulating layer (310). Based on this, it can be confirmed that the longer the horizontal length of the circuit layer (330) extending from the connection region of the via electrode (320), the greater the bonding force with the insulating layer (310).

[0077] Meanwhile, peeling (340) occurs due to the difference in the coefficient of thermal expansion between the insulating layer and the wiring section during the formation process of the wiring section. Since the bonding strength between the insulating layer and the wiring section decreases due to peeling (340), a problem regarding the reliability of the circuit board occurs.

[0078] Referring to FIGS. 11 to 13, a circuit board according to another comparative example includes a circuit layer (430) disposed on the upper surface of an insulating layer (410) and a via electrode (420) disposed on the circuit layer (430). The circuit layer (430) includes a first region (432) extending in one direction relative to the via electrode (420) and a second region (434) extending in the other direction opposite to the one direction. Here, the horizontal length from the upper surface of the circuit layer (430) in contact with the side of the via electrode (420) to the end of the first region (432) can be defined as L3, and the horizontal length from the upper surface of the circuit layer (430) in contact with the side of the via electrode (420) to the end of the second region (434) can be defined as L4. Here, L3 is 29.4 μm and L4 is 16 μm.

[0079] Referring to FIG. 12, it can be seen that delamination (440) occurs at the bonding interface between the second region (434) and the insulating layer (410) based on the second region (434), which is a relatively short region. However, referring to FIG. 13, it can be seen that delamination hardly occurs at the bonding interface between the first region (432) and the insulating layer (410). Through this, it can be seen that when the horizontal length from the contact portion (160) to the end of the circuit layer (131) is less than 30 µm, the bonding strength between the circuit layer (131) and the insulating layer decreases due to the occurrence of a fine delamination region, but in the range of 30 µm or more, no delamination region occurs.

[0080] Accordingly, according to the present invention, by forming the horizontal length from the contact portion (160) to the end of the circuit layer (131) to 30 µm or more, the peeling phenomenon at the bonding interface between the circuit layer (131) and the first insulating layer (111) can be prevented, thereby improving the bonding strength between them.

[0081] That is, it is preferable that the horizontal length from the contact portion (160) to the end of the circuit layer (131) be 30 µm or more. Considering the recent trend of technological advancements toward large-area circuit boards (10), it is preferable that the horizontal length from the contact portion (160) to the end of the circuit layer (131) be 30 µm or more, and the horizontal length from the side of the insulating layer where the circuit layer (131) is placed to the end of the circuit layer (131) be 3 µm or more. This is to prevent the circuit layer (131) from being exposed to the outside from the side of the insulating layer, or from being damaged by moisture or other contaminants penetrating the side of the insulating layer. That is, depending on the product specifications, the horizontal length from the contact portion (160) to the end of the circuit layer (131) may be 300 µm or more, but the reliability of the circuit board (10) can be improved by arranging the circuit layer (131) from the side of the insulating layer where the circuit layer (131) is placed to have a horizontal length of 3 µm or more.

[0082] In addition, the circuit layer (131) according to the present invention is limited to the case where it is a PID (Photo Imageable Dielectric) material. That is, since the coefficient of thermal expansion (CTE) of an insulating layer made of conventional PPG or ABF material is different from that of a PID material, delamination often does not occur in the numerical range of less than 30 µm where the aforementioned delamination occurs. However, since PID has a larger coefficient of thermal expansion (CTE) and a lower content of filler compared to insulating layers such as PPG or ABF, delamination as described above may occur. Therefore, according to an embodiment of the present invention, the insulating layer is limited to a PID material, but if there is another insulating layer having characteristics similar to PID, such as a coefficient of thermal expansion, filler content, and filler size, it can be understood that the technical concept of the present invention is extended to that insulating layer.

[0083] The vertical thickness (a) of the circuit layer (131) may be 6 µm or more and 22 µm or less. If the vertical thickness of the circuit layer (131) is less than 6 µm, the bonding strength may decrease as the vertical contact area between the circuit layer (131) and the first insulating layer (111) becomes shorter. If the vertical thickness of the circuit layer (131) exceeds 22 µm, the vertical thickness of the insulating layer for the placement of the circuit layer (131) must be increased to maintain the insulation characteristics between the circuit layers, which causes the size of the circuit board (10) to increase excessively.

[0084] Based on a single insulating layer, multiple circuit layers may be provided and spaced apart in the horizontal direction. As shown in FIG. 2, multiple circuit layers (131) may also be provided and spaced apart in the horizontal direction. A first region (125) of a second insulating layer (121) may be disposed in the spaced-out area of ​​the circuit layer (131). In this case, the horizontal spacing distance between the multiple circuit layers (131) spaced apart in the horizontal direction or the horizontal length of the first region (125) may be 10 µm or more. If the spacing distance between the multiple circuit layers (131) is less than 10 µm, there may be a risk of contact between adjacent circuit layers, which could lead to an electrical short circuit. Additionally, the placement area of ​​the insulating layer placed between adjacent circuit layers may be insufficient, which could result in a problem with the bonding between the circuit layer and the insulating layer.

[0085] According to the present invention, the second insulating layer (121) is limited to being provided with a PID material. That is, by arranging the circuit layers (131) so that the horizontal spacing distance between them is 10 µm or more according to the CTE of the second insulating layer (121), the content of the filler, the size of the filler, etc., the problem of delamination between the circuit layers (131) and the second insulating layer (121) can be improved by heat cycles generated during the operation of a product including the circuit board (10) or heat generated during the process. In addition, the horizontal spacing distance between the circuit layers (131) may vary depending on the trend of the circuit board (10) becoming larger in area and the specifications of the product including the circuit board (10), but it is appropriate to arrange them considering the miniaturization and density of the circuit layers (131) for signal and / or power transmission.

[0086] Meanwhile, the horizontal distance between the side of the circuit layer (131) and the second insulating layer (121) is also formed to be 10 µm or more, so that the circuit layer (131) is not exposed to the side of the second insulating layer (121) or foreign substances are not introduced from the side of the second insulating layer (121).

[0087] As illustrated in FIG. 1, a connection pad (155) for electrical connection with an electronic device may be disposed on the bottom surface of the cavity (150). The connection pad (155) may be disposed so as to overlap horizontally with the circuit layer (131). The connection pad (155) may be disposed on the upper surface of the first insulating layer (111). An electronic device may be coupled to the connection pad (155).

[0088] The connecting pad (155) can be spaced horizontally apart from the inner wall (152) of the cavity (150). Accordingly, damage to the electronic device caused by the inner wall (152) can be minimized during the process of connecting the electronic device on the connecting pad (155). In addition, through the spaced-out area, a space can be secured for air bubbles between the adhesive member (not shown) and the electronic device to be discharged during the process of connecting the electronic device through the adhesive member (not shown) described later. The above-described embodiment is a case where the bottom surface of the cavity (150) includes at least a portion of the first insulating layer (111), but is not limited thereto. In the case where another insulating layer is placed between the first insulating layer (111) and the second insulating layer (121), the width of the connecting pad (155) can be made larger than the width of the through hole of the second insulating layer (121) so that a spaced-out area is not provided, so that a recess does not occur on the surface of the other insulating layer.

[0089] An adhesive member (not shown) may be added between the connection pad (155) and the electronic component. The electronic component may be joined to the connection pad (155) through the adhesive member. A Die Attach Film (DAF) may be used as the adhesive member. Although not shown, a portion of the adhesive member may be positioned to cover at least a portion of the side of the electronic component to improve fixing force. At this time, the vertical length of the adhesive member positioned on a portion of the side of the electronic component is positioned to be smaller than the thickness of the second insulating layer (102), thereby controlling the frictional force between the adhesive member and the electronic component, and thus preventing the position of the electronic component from shifting when the electronic component is placed. Additionally, although not shown, another adhesive member (not shown) may be placed on the upper and / or lower side of the adhesive member to prevent the position of the electronic component from shifting. In this case, the side of the electronic device may come into contact with an adhesive member and another adhesive member (not shown), and the fixing force between the electronic device and the circuit board can be improved to be more robust.

[0090] A via electrode for heat dissipation may be disposed within the cavity (150). In this case, the connection pad (155) may be exposed on the circuit board (10) and heat dissipation may be achieved, and the via electrode may not be electrically connected to the circuit board (10) and / or electronic components. Accordingly, a configuration such as the aforementioned adhesive member may be omitted.

[0091] A molding member (not shown) is disposed within the cavity (150) so that the bonding state of the electronic component within the cavity (150) can be firmly maintained. The upper surface of the molding member may be exposed onto the first protective layer (191), but alternatively, the first protective layer (191) may be disposed to cover up to the upper surface of the molding member. The molding member may be an insulating layer.

[0092] When an electronic component is placed within a cavity (150), an additional electronic component that is electrically connected to the electronic component may be placed on the circuit board (10). In this case, the electronic component and the additional electronic component may be electrically connected by via electrodes. In this case, the via electrode placed within the cavity (150) may be distinguished from the via electrode (141) penetrating the second insulating layer (121) described above. The via electrode within the cavity (150) may have a shape that penetrates at least a portion of the molding member. The horizontal width of the via electrode within the cavity (150) may be greater than the horizontal width of the via electrode (141) penetrating the second insulating layer (121). The vertical thickness of the via electrode placed within the cavity (150) may be greater than the vertical thickness of the via electrode (141) penetrating the second insulating layer (121). Accordingly, heat generated from the operation of the electronic device can be easily discharged to the outside through the via electrode penetrating the cavity (150).

[0093] As illustrated in FIG. 7, the via electrode (141) may be positioned to penetrate at least a portion of the circuit layer (131) from the upper surface toward the lower surface. Accordingly, a groove (164) with at least a portion concave shape may be positioned on the upper surface of the circuit layer (131). A protrusion (166) may be positioned at the bottom of the via electrode (141) that protrudes downward toward the first insulating layer (111) rather than the upper surface of the circuit layer (131), and the protrusion (166) may be positioned so that at least a portion overlaps horizontally with the circuit layer (131). Accordingly, the bonding force between the circuit layer (131) and the via electrode (141) can be increased.

[0094] However, this is not limited thereto, and the lower surface of the via electrode (141) may be implemented as a flat surface corresponding to the upper surface of the circuit layer (131), so that the lower surface of the via electrode (141) and the upper surface of the circuit layer (131) may be arranged to form the same plane.

[0095] A seed layer (180) may be disposed between the via electrode (141) and the upper surface of the circuit layer (131). The seed layer (180) is for forming the via electrode (141) and may be disposed parallel to the upper surface of the circuit layer (131). When forming the via electrode (141), a mask corresponding to the placement area of ​​the via electrode (141) is disposed on the circuit layer (131), so that the via electrode (141) through the seed layer (180) can be realized.

[0096] FIG. 14 is a cross-sectional view illustrating a semiconductor package according to an embodiment of the present invention.

[0097] Referring to FIG. 14, the semiconductor package may include an electronic element (1000) disposed within a cavity (150). As described above, the electronic element (1000) may be electrically connected to a wiring portion within a circuit board (10) through a connection pad (155) disposed on the bottom surface of the cavity (150).

[0098] In the foregoing, although all components constituting an embodiment of the present invention have been described as being combined or operating in combination, the present invention is not necessarily limited to such embodiments. That is, within the scope of the purpose of the present invention, all components may be selectively combined in one or more ways to operate. Furthermore, terms such as "include," "constitute," or "have" described above, unless specifically stated otherwise, mean that the relevant component may be inherent; thus, they should be interpreted as allowing for the inclusion of additional components rather than excluding other components. All terms, including technical or scientific terms, have the same meaning as generally understood by those skilled in the art to which the present invention pertains, unless otherwise defined. Terms commonly used, such as those defined in advance, should be interpreted in accordance with their meaning in the context of the relevant technology and should not be interpreted in an ideal or overly formal sense unless explicitly defined in the present invention.

[0099] The foregoing description is merely an illustrative explanation of the technical concept of the present invention, and those skilled in the art to which the present invention pertains will be able to make various modifications and variations within the scope of the essential characteristics of the present invention. Accordingly, the embodiments disclosed in the present invention are intended to explain, not limit, the technical concept of the present invention, and the scope of the technical concept of the present invention is not limited by such embodiments. The scope of protection of the present invention shall be interpreted by the claims below, and all technical concepts within an equivalent scope shall be interpreted as being included within the scope of rights of the present invention.

[0100] Meanwhile, when a circuit board having the features of the invention described above is used in IT devices or home appliances such as smartphones, server computers, and TVs, it can stably perform functions such as signal transmission or power supply. For example, when a circuit board having the features of the invention performs a semiconductor package function, it can safely protect the semiconductor chip from external moisture or contaminants, and can resolve issues such as leakage current, electrical short circuits between terminals, or electrical open circuits of terminals supplying power to the semiconductor chip. In addition, when it is responsible for signal transmission, it can resolve noise issues. Through this, the circuit board having the features of the invention described above enables the stable operation of IT devices or home appliances, thereby allowing the entire product and the circuit board to which the invention is applied to achieve functional integration or technical interoperability.

[0101] When a circuit board having the features of the invention described above is used in a transportation device such as a vehicle, it can resolve the problem of signal distortion transmitted to the transportation device, or safely protect a semiconductor chip controlling the transportation device from the outside, and further improve the stability of the transportation device by resolving problems such as leakage current, electrical short circuits between terminals, or electrical open circuits of terminals supplying power to the semiconductor chip. Accordingly, the transportation device and the circuit board to which the present invention is applied can achieve functional integration or technical interoperability with each other.

Claims

1. First insulating layer; A second insulating layer disposed on the first insulating layer and made of a material different from the first insulating layer; A protective layer disposed on the second insulating layer; and It includes a wiring portion disposed between the first insulating layer and the second insulating layer, and The wiring portion comprises a circuit layer disposed on the upper surface of the first insulating layer and a via electrode penetrating at least a portion of the second insulating layer from the upper surface of the second insulating layer toward the upper surface of the circuit layer. The above second insulating layer is a photocurable insulating layer, and The above via electrode includes a side surface having a predetermined slope with respect to the circuit layer, and A circuit board having a horizontal length of 30 μm or more from the contact portion where the side of the via electrode and the upper surface of the circuit layer meet to the end of the circuit layer.

2. In Paragraph 1, A circuit board in which the horizontal length from the contact portion where the side of the via electrode and the upper surface of the circuit layer meet to the end of the circuit layer is less than 300 μm.

3. In Paragraph 1, A circuit board in which the horizontal length from the end of the circuit layer to the side of the second insulating layer is 3 µm or more.

4. In Paragraph 1, A circuit board having a vertical thickness of the circuit layer of the above circuit layer of 6 µm or more and 22 µm or less.

5. In Paragraph 1, It includes a second circuit layer disposed on the upper surface of the second insulating layer, and The above via electrode is a circuit board connecting the above circuit layer and the above second circuit layer.

6. In Paragraph 5, A circuit board spaced apart in the horizontal direction, wherein the via electrodes connecting the circuit layer and the second circuit layer are provided in plurality.

7. In Paragraph 1, The above via electrode is a circuit board having a shape in which the horizontal width gradually decreases as it faces the first insulating layer.

8. In Paragraph 1, The above circuit layer is provided in multiple numbers and is spaced apart horizontally from the upper surface of the first insulating layer, The second insulating layer includes a first region disposed in a spaced-apart region of the plurality of circuit layers, and A circuit board in which the horizontal length of the first region is 10 µm or more.

9. In Paragraph 1, A circuit board comprising a cavity penetrating at least a portion of the second insulating layer.

10. First insulating layer; A second insulating layer disposed on the first insulating layer and made of a material different from the first insulating layer; A protective layer disposed on the second insulating layer above; An electronic device disposed within a cavity formed in the second insulating layer; and It includes a wiring portion disposed between the first insulating layer and the second insulating layer, and The wiring portion comprises a circuit layer disposed on the upper surface of the first insulating layer and a via electrode penetrating at least a portion of the second insulating layer from the upper surface of the second insulating layer toward the upper surface of the circuit layer. The above via electrode includes a side surface having a predetermined slope with respect to the circuit layer, and The above second insulating layer is a photocurable insulating layer, and A semiconductor package in which the horizontal length from the contact portion where the side of the via electrode and the upper surface of the circuit layer meet to the end of the circuit layer is 30 μm or more.

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